TWI299500B - Memory row decoder - Google Patents

Description

1299500 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a memory row decoder (Decoder), and more particularly to a gate-induced drain leakage with a small gate (Gate induced drain) Leakage; GIDL) Current memory column decoder. [Prior Art] _ Gate induced a non-polar leakage (hereinafter referred to as GIDL), which is related to the current in the off state. As CMOS devices continue to shrink in size, the gate-induced bungee leakage creates severe limitations. GIDL is caused by a strong electric field between the gate and the drain, and when the thickness of the gate oxide layer is reduced, the magnitude of the GIDL current is increased by a number. When it is desired to increase the degree of integration of the semiconductor device, it is necessary to reduce the thickness of the gate oxidation between the gate and the substrate, and the GIDL thus becomes a MOS electric a-body orientation; an important problem in the development of the sub-micron field. Figure 1 is a plot of the source-to-drain current JSD of a PMQS transistor and the source-pole vs. gate relative voltage VSG for illustration (hdL effect. As shown in the figure 'When the source and gate are opposite voltages When the VSG falls below the threshold voltage Vt, the path between the source and the drain has only a sub-threshold current. When the VSG continues to drop to -VA, the two under-critical currents also decrease. The VA is between approximately -IV and -3V depending on the manufacturing technique and process. However, when the VSG falls below the -VA, a leakage current, the so-called GIDL current, is generated. The GIDL current will also rise sharply as the VSG decreases. It is noted that this illustration and the H series are for the PM0S transistor, but can be easily analogized to

Client s Docket No. :94-048 TT9s Docket No:0492-A40702.TW/f7ChingYen/2006-04.25 1299500 NMOS transistor. The method is to replace the source-to-drain current ISD with the drain-to-source current IDS, and to replace the source-gate relative voltage VS(} with the gate-to-source relative voltage VGS. Figure 2 is a conventional memory. A circuit diagram of the body decoder 200, wherein the memory column decoder 200 is coupled to a word line in a memory to selectively open the word line. As shown in the figure, the memory The body-defining 200 series includes an enhanced pM〇s transistor mepl, and the source-to-drain circuit is coupled between a signal terminal 21 and an output terminal 23. The output terminal 23 is coupled to The word line WL. The substrate 22 of the reinforced PMOS transistor mepl is coupled to a node 24 to receive a fixed voltage VPP. A first enhanced NMOS transistor meni and a second enhanced NMOS transistor men2 The source-to-drain path is connected in parallel between the output terminal 23 and a node 25, wherein the node 25 receives a fixed voltage VNN that is negative with respect to VPP. The first enhanced NMOS transistor menl and The substrates 26 and 27 of the second enhancement type NMOS transistor men2 are also connected to the voltage VNN. A first partial decoded signal bMWL is applied to the gates of the enhanced PMOS transistor mepl and the first enhanced NMOS transistor menl. A second partial decoded signal WLDV is applied to the signal terminal 21. A reset signal WLRST (usually The second phase of the decoded signal WLDV is applied to the gate of the second enhancement type S[MOS transistor men2 for selectively reducing the word line WL to VNN under special input conditions. The circuit shown in Figure 2 is used to activate the selected word line WL. When the first part of the decoded signal bMWL is low and the second part

Client's Docket No.:94-048 TT^ Docket No:0492-A40702-TW/^ChingYen/2006-04-25 1299500 When the decoding signal WLDV is high (and the reset signal WLRST is low), a high voltage ( That is, VPP) is applied to the word line WL to activate the word line WL, thereby turning on the memory cell transistor to which the gate is connected to the word line WL. Thus, the memory column decoder 200 is said to operate in a "select" mode. When the first partial decoded signal bMWL is at a high level and the second partial decoded signal WLDV is at a low level (and the reset signal WLRST is at a high level), a low voltage (i.e., VNN) is applied to the word line WL. Since the memory cell transistor whose gate is connected to the word line WL is thus turned off, the memory bank decoder 200 is said to operate in a "non-selected" mode. Thus, the memory bank decoder 200 can be used to apply a startup voltage (i.e., Vpp) to the word line WL' or to apply a disable voltage (i.e., vnN) to the word line WL. Referring to Fig. 2, when the memory column decoder 2 is operating in the non-selected mode, the source and gate relative voltage of the enhanced PMOS transistor mepi is (VNN-VPP). When designing for memory, the vnn level is chosen to be lower than the bulk voltage of the transistor outside the memory (Bulk v〇ltage), so that the secondary critical current flowing when the transistor is turned off can be minimized. However, this leads to (VNN-VPP) being more negative. Due to the GIDL effect, the subcritical current flowing when the transistor is turned off increases, which in turn leads to more power loss. In view of this, it is important to provide a memory column decoder having a smaller GIDL current to reduce power loss. SUMMARY OF THE INVENTION The present invention provides a method that is smaller when operating in a non-selected mode.

Client's Docket No.: 94-048 TT5s Docket No: 0492.A40702.TW/f/ChingYen/2006-04^25 1299500 The GIDL current is lower and the power consumption is lower. The present invention provides a memory column decoder comprising a first-mode NMOS transistor having a first source/turn and a pole, a second source wide and a pole coupled to a first partial decoded signal, and a The gate is coupled to a sub-decode signal, a first enhancement type pM〇S transistor having a first source/drain, a second source/drain coupled to the second portion of the decoded signal, and a The gate is coupled to the first source/and the pole of the first depletion NMOS transistor, and the first enhancement type NMOS transistor has a first source/drain = connected to the first enhanced PMOS a first source/drain of the crystal, a second source drain coupled to a first reference voltage, and a gate coupled to the first partial decoded signal, and a second enhanced NMOS transistor having a The first source/drain is connected to the first source/drain of the first PM〇s transistor, a second source/drain is coupled to the first reference voltage, and a gate is coupled to the A reset signal. The first source/no pole of the first enhanced PMOS crystal is used as an output of the memory column decoder to be coupled to a memory word line. Since the word line is deactivated when the memory column decoder operates in the non-selected mode, the closed-electrode of the first-enhanced PMOS transistor can be lowered. Therefore, the first-enhanced type? The (7) sinking energy of Congdian crystal is reduced. The memory column decodes (4) this loss is less power and has better power efficiency. [Embodiment] FIG. 3 shows a memory column decoder proposed by the present invention.

Client's Docket No_ :94-048 TT^s Docket N〇:0492.A40702-TW/^ChingYeii/2006-04.25 1299500 One of the circuit diagrams. As shown in the figure, the memory column decoder 3 includes an enhanced PMOS transistor mepl, and the source-to-pole path is coupled between a signal terminal 31 and an output terminal 33. The wheel end 33 is externally coupled to a word line WL. The substrate 32 of the reinforced PMOS transistor mepl is connected to a node 34 to receive a second reference voltage VPP. A depleted NMOS transistor mdn1 has a source-to-drain path coupled between the gate 38 of the enhanced PMOS transistor and a signal terminal 39. The substrate 40 of the depleted NMOS transistor mdn1 is coupled to a node 41 for receiving a first reference voltage VNN, the gate of which is coupled to the signal terminal 31. A source-to-drain path of a first enhancement mode NMOS transistor menl and a second enhancement mode NMOS transistor men2 is connected in parallel between the light connection to the output terminal 3 3 of the sub-line WL and a node 35 Where the node 35 accepts the first reference voltage VNN. The first enhancement type NMOS transistor menl and the base materials 36 and 37 of the second enhancement type NMOS transistor men2 are connected to the first reference voltage VNN. A first partial decoded signal bMWL is applied to the signal terminal 39, and a second partial decoded signal WLDV is applied to the signal terminal 31. A reset signal WLRST (usually an inverted signal of the second partial decoded signal WLDV) is applied to the gate of the second enhanced NMOS transistor men2 for selectively enabling the word line under special input conditions. WL drops to VNN. As can be seen from the figure, the difference between the memory column decoder 300 and the memory column decoder 200 of FIG. 2 is only to increase the depletion type NM〇s transistor mdnl, and the difference can be in the memory column decoder. When operating in the non-selected mode, the voltage of the gate 38 of the enhanced PMOS transistor mepl is lowered.

Client's Docket No.: 94-048 TT^ Docket No:0492-A40702-TW/f^ChingYen/2006-04-25 10 1299500 Thus, the GIDL current of the enhanced PMOS transistor mepl is lowered, and the details will be detailed below. Figure 4 shows an example of the first and second partial decoded signals bMWL and WLDV, the reset signal WLRST, the voltage level VPG of the signal terminal 38, and the voltage level VWL of the output terminal 3 3 (or the word line WL). Waveform diagram. In the period PUS1 or pus2, the first partial decoding signal bMWL is at a high level (level VPP), the second partial decoding signal WLDV is at a low level (level VNN), and the reset signal WLRST is at a high level (bit) Quasi VINT). Referring back to FIG. 3, for the depleted NM0S2 transistor mdnl, since bMWL is higher than WLDV, a transient current flows from the signal terminal 39 to the gate 38, and the transient current will be enhanced PMOS transistor mepl The gate 38 is charged. At the same time, the enhanced PMOS transistor mepl is turned off due to the negative voltage of the source relative to the gate. In addition, the high-level bMWL and WLRST turn on the enhanced NMOS transistors menl and men2, respectively, so that the voltage VWL at the output terminal 33 is pulled down to > VNN. Since the word line WL is applied with the low voltage VNN, the memory cell transistor whose gate is connected to the word line WL is thus turned off. The memory bank decoder is then said to operate in a "non-selected" mode during the period Pusl or Pus2. The transient current is continuously flowing to the gate 38 of the enhancement PMOS transistor mepl to be charged to (VNN-Vtnd) to turn off the depletion NMOS transistor mdnl, wherein the symbol ytn (j is a depletion type nm〇S The threshold voltage at which the crystal mdnl is turned off. After that, the enhanced PMqS transistor mepl is maintained in a closed state, and the voltage of the source is stable relative to the gate.

Client's Docket No. :94-048 TT^s Docket No:0492-A40702-TW/f/ChingYen/2006-04-25 11 1299500 at [VNN-(VNN_Vtnd)]=Vtnd 〇Picture 5 shows the 2nd and Figure 3: Enhanced pM〇s transistor (5) The source-to-drain current ISD and the source-to-gate voltage VS(} relationship, to illustrate that the memory column decoders 2〇〇 and 3(10) operate in non- The GIDL effect is selected when the mode is selected. When the memory column decoder 3 is operating in the non-selected mode, the source of the enhanced PMOS transistor mepl is Vtnd relative to the gate voltage VSG, as indicated by the inverted symbol γα. When the memory column decoding 200 operates in the non-selected mode, the source relative gate voltage VSG of the enhanced pM〇s transistor is (VNN-VPP), as shown by the symbol "B". Since Vtnd is ( VNN-VPP) is positive, so the GIDL current of the memory column decoder 300 is smaller than the GIDL current of the memory column decoder 200. Therefore, the memory column decoder 300 consumes less memory than the memory column decoder 2 The power has better power efficiency. Preferably, the threshold voltage Vtnd of the depleted NMOS transistor is selected to be about -VA, The current of the enhanced PMOS transistor mepl in the off state can reach a minimum value. When in the period Ps, the first partial decoding signal bMWL is converted to a low level (level VNN), and the second partial decoding signal WLDV is turned to a high level. The quasi-level (VPP) and the reset signal WLRST are turned to the low level (level VNN). The first portion of the low-level decoded signal bMWL whose reset signal WLRST turns off the enhanced NMOS transistors menl and men2. Since the first partial decoding signal bMWL is at a low level and the second partial decoding signal WLDV is at a high level, the depleted NMOS transistor mdnl is turned on, which pulls the voltage VPG of the gate 38 down to VNN.

Client's Docket No. :94-048 TT5s Docket No:0492-A40702-TW/^ChingYen/2006-04-25 1299500 Thereby the enhanced PMOS transistor mepl is turned on. As a result, the input voltage VWL is pulled up to Vpp. Since the word line WL is applied with a high voltage vpp, it is activated to supply power to the memory cell crystal whose gate is connected to the word line WL. The memory column decoder 300 is then referred to as the "select" mode during this period ps. Although the present invention has been disclosed in the above preferred embodiments, the present invention is not intended to limit the present invention, and any one skilled in the art can make some modifications and refinements without departing from the dreams and scope of the present invention. Inventive: The scope is subject to the definition of the scope of the patent application. > 'Bright [schematic description] The relationship between the pole and the gate relative voltage VSG; Figure 2 is a circuit diagram of a conventional memory column decoder. Figure 3 shows the memory proposed by the present invention An example of several important signals in Figure 3 shows that the enhanced pM〇~ pole-to The relationship between the gate voltages. (5) Rainbow <

Client's Docket Ν〇····94-048 TT^ Docket No:0492-A40702-TW/^ChingYen/2006-04-25 1299500 [Main component symbol description] 200~Traditional memory column decoder 21~Signal terminal 22~ Substrate 23 to output terminal 24 to node 25 to node 2 6 to substrate 27 to substrate 300 to memory bank decoder 31 to signal terminal 3 2 to substrate 3 3 to output terminal 34 to node 3 5 to Node 3 6~substrate 37~substrate 38~gate 39~signal end 40~substrate 41~node bM WL~first part decoded signal WL~word line WLDV~second part decoded signal WLRST~reset

Client’s Docket Ν〇·:94-048 TT5s Docket No:0492-A40702-TW/f/ChiiigYen/2006-04-25

Claims (1)

1299500 X. Patent application scope: 1· A memory column decoder, comprising: - a flute-deficient NM0S transistor having a first-source/drain' connection to a first partial decoding signal, And - the gate is coupled to a second partial decoded signal; a first enhanced touch s-type transistor having a -first source/no pole, a source-source level _ connected to the second portion of the unsaved number, and a idle pole connected to the first vacant NMOS transistor a first source/drain pole. A first enhancement type NMOS transistor having a first source/depolarization wheel connected to the first source/no pole of the first enhancement type p Μ 电s transistor, two= The drain is connected to the -first reference voltage, and the gate _ to the third portion, the sub-decode signal; and a second enhancement NMOS transistor having a first connection to the first PMOS transistor a first source/drain, a second source/汲 is coupled to the first reference voltage, and a gate is coupled to the reset source pole, wherein the first source of the first enhancement PMOS transistor is/ Bungee system: is the output of the memory column decoder, coupled to one of the ticks ~= line. The memory column decoder of the first aspect of the invention, wherein the substrate of the first enhanced PMOS transistor is coupled to a first: reference voltage, wherein the second reference The voltage level is substantially equal to the high voltage level of the second partial decoded signal, and wherein the first depletion type nm〇s transistor, the first and second enhanced NMOS transistors are coupled to each other Connected to the first reference voltage. Client’s Docket Ν〇·:94-048 TT^ Docket No:0492-A40702-TW/FChingYen/2006-04-25 15