TWI399561B - Test Method for Nonlinear Error of High - speed Digital Analogy Converter - Google Patents

Description

Test method for nonlinear error of high speed digital analog converter

A digital analog converter test method, especially a test method for nonlinear error of a high speed digital analog converter.

High-speed digital analog converters have been widely used in consumer electronics and communication technologies. Please refer to "Figure 1". The traditional digital analog converter 1 test method usually requires a precision analog signal measurement circuit 3 at the output terminal 2. The measurement circuit 3 must contain analog-like digital bits. The sample hold circuit 4 is provided. The performance of the sample-and-hold circuit 4 will directly affect the accuracy of the measurement result, wherein the accuracy and stability of the sample-and-hold circuit 4 are difficult to design, whether the high-speed or high-resolution sample-and-hold circuit 4 is designed. Not easy to achieve.

In addition, the signal to be tested can be converted into special test features to facilitate our analysis. The converted size value can be expressed as a pulse signal frequency or a duty ratio, and the digital count signal can be used to measure the analog signal. However, these techniques require the construction of a high-speed circuit in the chip to accommodate high-speed digital analog converters, which greatly increases the design difficulty and increases the design problem.

Therefore, the main purpose of the present invention is to develop a new digital analog converter test architecture based on down-clock sampling technology, which converts the analog signal of the digital analog converter into a series of low-speed pulse streams, and then The width of this pulse signal finds the nonlinearity error of the digital analog converter.

Based on the above object, the steps of the present invention comprise obtaining the high speed digital analog converter The digital analog conversion converts the output signal, and then provides a low frequency carrier signal, and then provides a comparator for inputting the digital analog conversion output signal and the low frequency carrier signal to the comparator to obtain a low speed pulse signal. Then, the fluctuation of the pulse width of the low-speed pulse wave signal is measured by a logic analyzer, and finally the nonlinear error of the digital analog converter is obtained from the variation of the pulse width.

Accordingly, the present invention does not require the use of high speed circuitry, but can use a general logic analyzer to estimate the nonlinearity of the digital analog converter and improve the ability of automated test equipment (ATE) to test high speed digital analog converters.

In order to give your members a better understanding and recognition of the features, objects and effects of the present invention, the preferred embodiments are illustrated with the following description: see Figure 2 and Figure 3, For the sampling technique theory of the present invention, it is assumed that f ( ωt ) is the output waveform of the digital analog converter 10 and has a period T . We take three sampling points p ₁ to p ₃ , which are respectively arranged in three cycles for individual sampling. It is necessary to take out three sampling points in one cycle and sample them in three cycles respectively. Defining a first sampling point is assumed and the signal voltage magnitude difference between the second time point sample value △ V _i and △ W _i, there is a relationship between _{△ W i = W i - T} . Therefore, the nonlinear error of the circuit to be tested, f ( ωt ) / dt , can represent the difference value of the sample point signal size as the pulse width signal, that is, the variation of the pulse width, that is, Δ W _i .

The sampling circuit used in the present invention is as shown in FIG. 3, and as shown in FIG. 3, f ( ωt ) is a digital analog conversion conversion output signal of the digital analog converter 10, which can pass through a low pass. filter out high frequency noise 11, f (ω't) slightly lower frequency to another carrier of the low frequency signal 31, which may be by a carrier generator 30 generates, according to the present invention will be f (ωt) and f (ω ' t ) The two signals are sent to the comparator 20 for comparison, and a pulse signal s ( t ) is obtained, and the pulse signal s ( t ) is stored in a register 40 to obtain a low-speed pulse wave signal w ( t The low speed pulse signal w ( t ) reflects the linearity error value of the output of the digital analog converter 10. Therefore, logic analyzer measurement (not shown) can be used to observe the low-speed pulse signal w ( t ) instead of measuring the high-speed analog signal, so that under this method, high-speed or high-resolution is not required. Signal measurement circuit.

Further, since W _i is the difference corresponding to the two sampling points, the comparator offset error (offset error) of the 20 naturally will be offset away. Because the test method is in the low-speed sampling mode, only one sampling point is taken per cycle, so the operating frequency of the circuit is very low, which is quite easy to implement, and the final test characteristic value is the pulse width of the digital signal, so it is transmitted to the chip. The external process is less prone to distortion, and the oscilloscope equipment on the existing automatic test equipment has good time domain sampling capability, so the measurement pulse width of the signal can reach a relatively high precision. If we consider the influence of noise on the pulse width value during the modulation process, we can reduce the noise effect by taking an average pulse width value by extending the period of the test method to make the same position repeat sampling.

Further, the present invention can use a triangular wave as the low frequency carrier signal 31, or a sine wave can also be used. Please refer to Figure 4-1, Figure 4-2, Figure 4-3 and Figure 5 for the first use of triangular waves. Defining the period T _{da of the} low frequency carrier signal 31 period T _C and the signal to be tested 12 (ie, the digital analog conversion modulation output signal), the relationship is T _C = T _da + Δ T , Δ T is the signal to be tested 12 and the low frequency carrier The difference between the signal period 31. The relationship between the slope of the low frequency carrier signal 31 and the signal to be tested 12 can be expressed as:

Where T _da = 2 × (2 ⁿ -1) × t _da ; T _c = 2 × (2 ⁿ -1) × t _da + △ T

Therefore, the pulse width will be expressed as "Figure 5":

Suppose that the circuit under test (ie digital analog converter 10) is an n- bit component, only N = 2 ⁿ -1 quantization interval, so there should be N test pulse widths W _i , respectively sampled from N +1 the signal periods, must push the relationship between the test signal and the low frequency carrier signal 12 cycles of 31 difference values △ T, the number of bits n circuit under test 12 and the test signal T _da period in order to determine how much the The low frequency carrier signal 31 of the frequency is modulated. Suppose N sample points needs to be spent (N +0.5) cycles to obtain feature values W _i, whereas i = 1,2,3 ...., N.

Please refer to "Figure 6", so the operating frequency of the low frequency carrier signal 31 must be defined. In this case, the total sampling time can be expressed as Σ T .

And Σ T must meet the following relationship:

Therefore, we can know from the above formula that the low frequency carrier signal 31 frequency f _c can be expressed as:

Next, please refer to "Figure 7-1" and "Figure 7-2", which is the relationship between the test pulse width and the nonlinear error of the circuit to be tested. First, it is assumed that there is a nonlinear error in a certain quantization interval of the circuit to be tested, which causes the slope of the signal to be tested to vary by Δ w in the slope of a certain segment. As shown in Figure 7-1. Extend "Figure 7-1" to "Figure 7-2". The error signal of this error change can be expressed by the following formula:

It can be seen from the above formula that W _j represents a pulse wave modulation signal. From this result, the nonlinearity error can be derived by using the pulse width obtained by comparing the low frequency carrier signal 31 with the signal 12 to be measured.

Please refer to the figure shown in Figure 8 for the use of sine wave as low frequency carrier signal 32. In the actual test environment, the precise and adjustable triangular wave generator is difficult to implement, and the sine wave signal is generated as low frequency. The carrier signal 32 is much easier than the generation of a triangular wave signal. However, the way of using the sine wave as the low frequency carrier signal 32 is not an intuitive linearization modulation method, so the correlation between the signal 12 to be tested and the test characteristic value after modulation must be derived.

First, the sinusoidal low frequency carrier signal 32 is considered to be a combination of many pieces of piecewise linearity, since the sampling point has a certain number, in other words, the signal difference value between any two sampling points is small. It is assumed that the voltage signals between any two sampling points are linear, but the linear relationship of the sampling points in the different interval is also different, and the variation of the peak and valley slope of the sinusoidal signal is too large to be used as the low frequency carrier signal 32, Therefore, the sinusoidal signal V _c must be slightly larger than the signal to be tested V _da to ensure that the sampling points where the two signals cross are not present near the peaks and troughs of the low frequency carrier signal 32.

Therefore, the formula must be re-represented as:

Please refer to Figure 9 again. In the above equation, m _c [ i ] can be further expressed as:

Next, please refer to FIG. 10 and FIG. 11 , and the test pulse width W _{i should be} expressed in a similar form, and the difference value Δ T between the period of the signal 12 to be tested and the low-frequency carrier signal 32 is derived. The frequency of the carrier signal that determines the modulation.

Since the sampling point has a certain amount, in other words, the sampling difference between any two points is small, assuming that the voltage between the adjacent two points is linear, but the linear relationship of the sampling points in the different interval is different, therefore , to slightly modify the formula (1):

Please refer to Figure 12-1 and Figure 12-2. Similarly, formula (2) is also modified. As shown in Figure 12-1, assume that there is a certain quantization in the circuit under test. There is a nonlinear error in the interval, which causes the slope of the signal 12 to be measured to vary by Δ w . The slope of the change is corrected as follows:

The present invention derives the relationship between the nonlinearity error of the output signal of the digital to analog converter 10 and the pulse width modulation. In order to reduce the estimation error, the sampling point can be intuitively increased. This method can be easily realized by changing the operating frequency of the low frequency carrier signal 32. For example, an 8-bit digital analog converter 10 has 255 quantization levels. It is assumed that 1020 sampling points are required, that is, each quantization level is sampled four times on average, but we From these 1020 sampling points, we tried to estimate the original 255 quantization heights.

Please refer to "Figure 3", "Figure 13-1" and "Figure 13-2", if the digital analog converter 10 is ideal and the number of points sampled is the same. In this example, the m _f slope estimate can be derived from the average of the slopes between two adjacent points, m _i , i =1,...,4. Unfortunately, the quantized height of the digital analog converter 10 is not ideal, so each sampling point is not the same. As shown in Figure 13-2. As can be seen from this figure, it is not difficult to find a turning point between the third and fourth sampling points that is the slope, that is, m ₄ . Therefore, when we calculate m _{f 1} and m _{f 2} , we must consider m ₄ into the average value. Therefore, the differential nonlinearity error (DNL) can be estimated by the following equation When m ₅ > m ₃ > m ₄ .

In addition, another situation must be considered, which also causes the circuit under test to estimate the nonlinearity error. If the condition is m ₅ > m ₄ > m ₃ as shown in Figure 13-2, the meaning is that the third sampling point is very close to the quantitative height slope turning point. In other words, the slope of m ₃ will be much smaller than m ₄ . Therefore, the slope of m ₄ cannot be averaged in m _{f 1} because m ₃ and m _{4 are} almost the slope of m ₄ , so we must make some corrections to estimate the differential nonlinearity: When m ₅ > m ₄ > m ₃ .

Please refer to "Figure 14". To explain the estimation of differential nonlinearity error (DNL), assume that there are N sampling points, and "Figure 14" is the slope distribution map between each adjacent sampling point. First, you must first find the position of all the slope maxima in "Figure 14" as the starting point of each code, and then calculate the average of the slopes associated with the maximum of these slopes.

For example, since m _{5 j} > m _{3 j} > m _{4 j} can be known from the previous section versus . In another case, m _{5 k} > m _{4 k} > m _{3 k} , we will get versus

Therefore, for the n-bits digital-to-digital converter 10 to take N sampling points, the differential nonlinearity error (DNL) estimation is normalized as follows: Since ( m _i ; i =1 to N ) find the maximum slope value at m _Max [ k ]={ m _mk }, k =1,2...,2 ⁿ -1 due to ( k =1 to 2 ⁿ -1) first case

another situation

The integral nonlinearity error (INL) can be represented by the addition of differential nonlinearity errors (DNL):

When calculating the integral nonlinearity error, it can be intuitively expressed using the above equation, and the integral nonlinearity error can be easily calculated. However, when calculating the differential nonlinearity error, the systematic error existing in the differential nonlinear error is also calculated into the integral nonlinear error.

Therefore, in order to solve this problem, we must find out the source of the systematic error and make a difference between the systematic error and the actual integral nonlinear error. There is a systematic error in the process of pulse width modulation (PWM). This is because when estimating the differential nonlinearity error, the sine wave carrier is caused by the combination of the linear slopes of many segments, but it is not the slope of the segment linearity, but a series of continuous curves. Therefore, when estimating the differential nonlinearity error, there will be some small amount of error between the estimated differential nonlinear error and the actual differential nonlinearity error. In addition, the amount of variation in this systematic error is periodic, which occurs cyclically with the frequency of the digital analog converter output signal. For this reason, when estimating the integral nonlinearity error, it will be described by the following formula: , ε ( ωk ) is expressed as the systematic error of the differential nonlinearity, and

From the signal point of view, the integral nonlinear error signal can be combined as a differential nonlinear error integral, and the system error is also included. Because the digital analog converter output signal period is a fairly large value, the frequency of the known systematic error is much smaller than the differential nonlinear error signal. Therefore, the system error can be removed, so that the estimation of the integral nonlinear error is more accurate. Here, the system error of the low frequency is filtered out by a simple high-pass filter (HPF), so The formula of nonlinear error is slightly corrected:

As mentioned above, a set of test methods is proposed for the non-ideal effects of high speed digital analog converters. This method is based on the technique of down-sampling to implement a pulse width modulation signal. The nonlinear error of the circuit to be tested is converted into a variation of the pulse width. The advantage of using this method is that it does not require high speed or high resolution instruments to capture analog signals.

The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the embodiments of the present invention. That is, the equal change and repair done in accordance with the scope of patent application of the present invention Decorations are covered by the scope of the invention.

1‧‧‧Digital Analog Converter

2‧‧‧output

3‧‧‧Measurement circuit

4‧‧‧Sampling and holding circuit

10‧‧‧Digital Analog Converter

11‧‧‧Low-pass filter

12‧‧‧Signal to be tested

20‧‧‧ comparator

30‧‧‧Carrier generator

31‧‧‧Low-frequency carrier signal

32‧‧‧Low-frequency carrier signal

40‧‧‧ register

FIG. 1 is a test environment diagram of a conventional digital analog converter.

2 is a basic conceptual diagram of a down-conversion sampling technique of the present invention.

FIG. 3 is a schematic diagram of a frequency down sampling technology architecture and signal of the present invention.

Figure 4-1 is a schematic diagram of a low frequency carrier signal using a triangular wave according to the present invention.

4-2 is a schematic diagram of crossover of a signal to be tested and a triangular carrier according to the present invention.

Figure 4-3 is a partial enlarged view of Figure 4-1 of the present invention.

Figure 5 is a schematic view of the test features of the present invention.

FIG. 6 is a diagram showing the difference between the signal to be tested and the low frequency carrier signal period according to the present invention.

Figure 7-1 is a graph showing the relationship between the nonlinear error and the test pulse width according to the present invention.

Figure 7-2 is a partially enlarged view of Figure 7-1 of the present invention.

FIG. 8 is a schematic diagram of a low frequency carrier signal using a sine wave according to the present invention.

FIG. 9 is a diagram showing amplitude relationship between a signal to be tested and a low frequency carrier signal according to the present invention.

Figure 10 is a schematic view of the test features of the present invention.

Figure 11 is a diagram showing the difference between the signal to be tested and the sinusoidal carrier cycle of the present invention.

Figure 12-1 shows the relationship between the nonlinear error of the circuit under test and the width of the test pulse.

Figure 12-2 is a partial enlarged view of Figure 12-1 of the present invention.

Figure 13-1 is a schematic diagram of four sampling points of an ideal quantized height according to the present invention.

Figure 13-2 is a schematic diagram of the actual quantized height of four sampling points of the present invention.

Figure 14 is a diagram showing the slope distribution of adjacent sampling points of the present invention.

10‧‧‧Digital Analog Converter

11‧‧‧Low-pass filter

20‧‧‧ comparator

30‧‧‧Carrier generator

31‧‧‧Low-frequency carrier signal

40‧‧‧ register

Claims (3)

A method for testing a nonlinear error of a high-speed digital analog converter, comprising: obtaining a digital analog conversion conversion output signal of the high speed digital analog converter; providing a low frequency carrier signal, the frequency of the low frequency carrier signal being slightly lower than a digital analog conversion Modulating the output signal; providing a comparator for inputting the digital analog conversion output signal and the low frequency carrier signal to the comparator to obtain a low speed pulse wave signal; measuring the low speed pulse wave signal by a logic analyzer The variation of the pulse width; the nonlinear error of the digital analog converter is known from the variation of the pulse width. The method for testing a nonlinear error of a high speed digital analog converter as described in claim 1 wherein the low frequency carrier signal is a triangular wave. The method for testing a nonlinear error of a high speed digital analog converter as described in claim 1, wherein the low frequency carrier signal is a sine wave.