JP5342486B2 - Test circuit for A / D converter - Google Patents

Description

  The present invention relates to an A / D converter test circuit and a test method.

  In a semiconductor integrated circuit that performs feedback control of an analog signal, replacement from analog control to digital control using an A / D converter is progressing. As a method for testing this A / D converter, several methods have been devised (see FIG. 4).

  In the integrated circuit 70 shown in FIG. 4A, both the A / D converter 20 and the D / A converter 72 are mounted on the same substrate. The output of the A / D converter 20 is connected to the input of the D / A converter 72, and both A / D and D / A converters are tested simultaneously (see Patent Documents 1 and 2). A test may be performed by connecting the input of the D / A converter 72 to the output of the A / D converter 20. Reference numeral 71 denotes a selector, and reference numeral 21 denotes a circuit that uses the digital data converted by the A / D converter 20.

  The integrated circuit 80 shown in FIG. 4B is configured such that N-bit digital data converted and generated by the A / D converter 20 can be externally output by a pin, and the digital data output from this pin is output to a tester. Alternatively, the quality is determined by sampling with BOST (Built-out Self-Test) (see Patent Document 3).

  An integrated circuit 90 shown in FIG. 4C includes a test circuit 91 and an internal memory 92. The digital signal converted and generated by the A / D converter 20 is recorded in the internal memory 92. Data is read and tested (see Patent Document 4).

JP-A-5-297061 JP 2007-178387 A JP 58-20031 A JP 2001-358586 A

  However, the test methods described in Patent Documents 1 and 2 can be applied only to an integrated circuit in which both the A / D converter 20 and the D / A converter 72 are mounted. For this reason, it cannot be used for testing an integrated circuit in which only the A / D converter 20 is mounted.

  The test method described in Patent Document 3 requires pins (output terminals) with the number of bits (N) on the substrate. Small devices such as LED drivers and power supply devices that perform feedback control of analog signals have limitations on the package and device size, so there is a limit to the number of external terminals provided, and in some cases, as many pins as necessary to perform the test. Can not be provided. In addition, since the configuration is such that digital data is sampled by an external tester, it takes time to process the data in the tester, which increases the test time, and noise is generated due to the operation of the output buffer. There is also a problem that the S / N ratio decreases due to the test.

  The test method described in Patent Document 4 has a configuration in which digital data after generation of conversion is once recorded in an internal memory, and the data is read from this memory at the time of testing. For this reason, a large-capacity memory is required in the first place. In LED drivers, power supply devices, and the like, such a large-capacity memory is often not originally mounted. In such a case, this method cannot be employed.

  Further, since the test is performed by reading out the digital data from the memory, the test time is increased by the time required for the operation of reading out the data from the memory. When the internal CPU determines using the read data, it is necessary to incorporate a large-scale logic such as a microcomputer, which is difficult to mount on a small device.

  In view of the above problems, the present invention provides a test circuit capable of testing an A / D converter mounted on a small board without a D / A converter and a large-capacity memory with a small number of pins and its It aims to provide a method.

A test circuit for an A / D converter according to the present invention includes:
A test circuit for an A / D converter that converts an analog signal to be converted into a series of basic digital data, and is configured on the same substrate as the A / D converter,
A maximum value detection circuit to which the basic digital data is input, a minimum value detection circuit, and a variance value calculation circuit;
The maximum value detection circuit, the minimum value detection circuit, and the variance value calculation circuit are each reset to a predetermined initial value before starting input of the analog signal to the A / D converter,
The maximum value detection circuit sequentially compares the size of the held data and the input data while the basic digital data is input, and updates the held data to the input data when the input data is larger than the held data,
The minimum value detection circuit sequentially compares the held data and the input data while the basic digital data is input, and updates the held data to the input data when the input data is smaller than the held data,
The variance value calculation circuit performs a variance value calculation of the basic digital data and holds the data,
After completion of the input of the basic digital data, the held data of the maximum value detection circuit, the minimum value detection circuit, and the variance value calculation circuit are externally set as the maximum value, the minimum value, and the variance value of the basic digital data, respectively. It is characterized by being configured to be capable of output.

  According to the test circuit of the present invention, the minimum value, the maximum value, and the variance value of a series of basic digital data obtained by converting the input analog signal are obtained. Since this value is output to the outside, it can be output externally as serial data and does not require a large number of pins.

  When the input analog signal is a small amplitude signal such as a DC signal, the voltage level does not greatly deviate from the average value, which means that the variance value is suppressed within a certain range. To do. Therefore, if the dispersion value of the digital data obtained by digitally converting the small amplitude signal is within the target range, it can be determined that the A / D conversion has been correctly performed.

  On the other hand, when the input analog signal is a large amplitude signal having a large amplitude (for example, a signal close to the amplitude of the full swing signal that oscillates between the lower limit voltage and the upper limit voltage that can be converted by the A / D converter), the voltage The level fluctuation is large, that is, the Peak-to-Peak value is large. Therefore, even if noise is superimposed at the time of conversion to digital data, the noise level relative to the original voltage level is small, so that only the lower bits affect the converted digital signal, and there is no effect on the upper bits. .

  Therefore, in a large amplitude signal, the Peak-to-Peak value is detected from the maximum value and the minimum value after conversion into digital data, and if this value is within the target range, the A / D is correctly It is possible to determine that the conversion has been completed.

  The present invention makes it possible to test an A / D converter by evaluating the variance value and the Peak-to-Peak value of a series of the basic digital data after conversion in this way. And, by making the configuration necessary for that purpose (minimum value, maximum value, variance value) can be output externally, it is possible to test the A / D converter while reducing the number of pins. is there.

  In addition to the above configuration, an average value calculation circuit for calculating an average value of the series of basic digital data can be provided.

In the present invention, it is preferable that the dispersion value calculation circuit has the following configuration. That is,
The variance value calculation circuit includes:
A difference absolute value calculation circuit for calculating a difference absolute value between the digital data output from the A / D converter and the reference data set in the reference setting circuit;
A square circuit that applies a square process to the digital data output from the absolute difference calculation circuit;
An average value calculation circuit for dispersion that calculates an average value of a series of squared data output from the square circuit;
The average value calculation circuit for dispersion is
In the state where the average value of the basic digital data obtained by A / D-converting the analog signal by the A / D converter is set as the reference data, the same analog signal is converted to A / D by the A / D converter. While the converted basic digital data is input to the difference absolute value calculation circuit, the held data is updated by calculating an average value of the squared data output from the square circuit, and the difference absolute value calculation After the input of the basic digital data to the circuit is completed, the held data can be output to the outside as a variance value of the basic digital data.

As a method for measuring the dispersion value, a method of measuring the dispersion value using the V value obtained by V = (a−b ² ) by sequentially measuring the average a of the square value of the digital data and the average b of the digital data itself. Is also possible. However, in this case, when the number of bits of the digital data from the A / D converter 20 is n, an n × n-bit multiplier, an n-bit average value measuring circuit for obtaining a b value, and an a value are obtained. Therefore, a 2n-bit average value calculation circuit and a 2n-bit subtractor for difference calculation are required.

  On the other hand, like the present invention, after calculating the average value from the digital data once, the digital data is input again, and the average of the square value of the difference from the average value is calculated, whereby the variance value V Can be realized by an n × n-bit multiplier, a 2n-bit average value calculation circuit, and an n-bit subtracter. Therefore, the circuit scale can be reduced by a certain level as compared with the former method.

  In the latter method, since the variance value is calculated based on the average value once calculated, it is necessary that the average value of the digital data does not fluctuate when obtaining the variance value. In the present invention, the influence of the fluctuation of the average value is eliminated by inputting the digital data converted from the same analog signal twice.

Further, in addition to the above feature, the variance value calculation circuit determines whether or not a predetermined number of upper bits are all 0s in the digital data output from the difference absolute value calculation circuit. A square pre-processing circuit that outputs the remaining lower bits with the upper bits missing in the case,
It is preferable that the square circuit performs a square process on the digital data output from the square preprocessing circuit.

  In the above configuration, the variance value is calculated by performing a square process using a square circuit. Here, in the squaring circuit, when the number of bits of data to be squared (multiplied) increases, the scale of the circuit for performing the squared (multiplication) processing increases.

  In the present invention, as described above, the circuit design corresponding to the number of bits when the multiplier circuit (square circuit) converts the small amplitude signal into digital data by calculating the variance only for the small amplitude signal. It is said. In the square pre-processing circuit, a digit removal process is performed in order to reduce the scale of the square circuit. Since it is digital data obtained by A / D converting a small amplitude signal, the change in the value after conversion is small, and a predetermined number of upper bits are expected to be zero. That is, after determining that a predetermined number of upper bits are 0 in the square pre-processing circuit, the number of bits of digital data to be multiplied is reduced by deleting the upper bits.

  On the other hand, in order to calculate a variance value for digital data obtained by A / D converting a large amplitude signal, a multi-bit × multi-bit multiplication process is required, which increases the scale of the square circuit. For this reason, in the case of a large amplitude signal, if the minimum value and the maximum value are exclusively detected, the evaluation is performed using the Peak-to-Peak value derived from these values. In the case of a large-amplitude signal, the influence of noise becomes relatively small, so that it is possible to evaluate the A / D converter by measuring the Peak-to-Peak value and calculating using it.

  The average value calculation circuit and the above-mentioned dispersion average value calculation circuit can also be used as the same circuit. In this case, a selector is provided immediately before the average value calculation circuit, and digital data output from the A / D converter is input to the average value calculation circuit, or digital data that is squared by the square circuit is input. It may be configured to select.

  In measuring the dispersion value, first, an analog signal for test is input to the A / D converter, and the average value of the converted digital data is calculated. After this average value is once set as a reference value, the same analog signal is input again to the A / D converter, and the converted digital data is input to the dispersion value calculation circuit (difference absolute value calculation circuit thereof). . In the difference absolute value calculation circuit, the difference absolute value between the series of basic digital data and the average value measured in advance is calculated. When the analog signal is a small-amplitude signal, the magnitude of this difference absolute value is small. Therefore, when the predetermined number of upper bits are continuous with zeros, the average of the square processing of only the lower bits from which these bits are omitted There is no problem even if the value is calculated as the variance value.

  In the above configuration, each value such as the maximum value, the minimum value, the average value, or the variance value may be output to an external tester, and evaluation using these values may be performed in the tester. The configuration may be such that the above is executed inside the test circuit.

  In the latter case, an evaluation unit including an arithmetic circuit that performs four arithmetic operations, a comparator, and a data holding circuit is provided in the test circuit. The evaluation unit is configured such that a reference value can be set from the outside, and the reference value (ideal Peak-to-Peak value, ideal average value, ideal variance value, etc.) can be written to the data holding circuit. . Then, a Peak-to-Peak value is derived from the maximum value and the minimum value calculated by the above method, and it is evaluated whether the deviation from the ideal Peak-to-Peak value is within a predetermined range. Similarly, for the average value and the variance value, it is evaluated whether the deviation from the ideal average value or the ideal variance value is within a predetermined range. And it is set as the structure which outputs only these evaluation results outside. Thereby, even the evaluation of the A / D converter can be performed inside the test circuit. Note that the test circuit may include a square root circuit, a bit shift circuit, and other necessary arithmetic circuits in addition to the four arithmetic operation circuits.

  For the maximum value detection circuit or minimum value detection circuit, an analog signal that monotonously increases or decreases is used by adding a function to update data only when the difference between the input data and the retained data is less than or equal to a predetermined value. A / D converter can be tested.

  For example, the maximum value detection circuit sequentially compares the size of the held data and the input data while the basic digital data is input, and the difference between the input data and the held data is larger than the held data at the time of input. A signal that continuously increases monotonically from a lower limit voltage to an upper limit voltage that can be converted by the A / D converter as the analog signal in a state in which the held data is updated to input data only when it is equal to or less than a predetermined value. Is input to the A / D converter, and the maximum value of the basic digital data output from the A / D converter is detected by the maximum value detection circuit. If the maximum value corresponds to the upper limit voltage, it can be determined that the A / D converter can output all code values.

  Similarly, while the basic digital data is input, the minimum value detection circuit sequentially compares the size of the held data and the input data, is smaller than the held data at the time of input, and the input data and the held data The analog signal is continuously monotonically from the upper limit voltage to the lower limit voltage that can be converted by the A / D converter in a state in which the held data is updated to input data only when the difference is equal to or less than a predetermined value. By inputting a decreasing signal to the A / D converter and causing the minimum value detection circuit to detect the minimum value of the basic digital data output from the A / D converter, the minimum value detection circuit If the output minimum value corresponds to the lower limit voltage, it can be determined that the A / D converter can output all code values.

Furthermore, a DC voltage obtained by adding the lower limit voltage to a value obtained by multiplying the input amplitude corresponding to 1 bit obtained by dividing the width of the upper limit voltage and the lower limit voltage that can be converted by the A / D converter, with the corresponding code value is obtained. Input as an analog signal, with the corresponding code value set as the reference value, the dispersion value is calculated by the dispersion circuit and output,
Thereafter, the corresponding code value is incremented by 1 and the variance value is calculated in the same manner and output to the tester, thereby detecting a location where the variance value varies significantly between the corresponding codes, and performing a linearity test. Can do.

  The test circuit of the A / D converter according to the present invention is configured to calculate a minimum value, a maximum value, and a dispersion value of a series of digital data obtained by converting an input analog signal, and to output these values to the outside. Therefore, since it can be externally output as serial data, a large number of pins are not required. Furthermore, the configuration does not require a D / A converter or a large-capacity memory.

  Therefore, the test circuit of the present invention can be mounted on a small substrate, and by mounting such a test circuit, it is possible to realize a small integrated circuit having a test function of the A / D converter. Become.

The block diagram which shows schematic structure of the integrated circuit provided with the test circuit of this invention The block diagram which shows schematic structure of the test circuit of this invention Another block diagram showing a schematic configuration of the test circuit of the present invention Diagram for explaining the conventional test method

  Embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected about the component same as FIG.

  FIG. 1 is a block diagram showing a schematic configuration of an integrated circuit including a test circuit of the present invention. The integrated circuit 10 is configured so that digital data converted and generated by the A / D converter 20 (corresponding to “basic digital data”) can be output to the integrated circuit 21 and the test circuit 1 of the present invention. Since the test circuit 1 is configured to output digital data serially, the integrated circuit 10 does not need to have N pins as shown in FIG.

  FIG. 2 shows the configuration of the test circuit of the present invention. The test circuit 1 includes a maximum value detection circuit 2, a minimum value detection circuit 3, an average value calculation circuit 4, a variance value calculation circuit 5, and a reference setting circuit 6. The variance value calculation circuit 5 includes a difference absolute value calculation circuit 8, a square circuit 12, an average value calculation circuit 13, and a square preprocessing circuit 15.

  The maximum value detection circuit 2, the minimum value detection circuit 3, the average value calculation circuit 4, the reference setting circuit 6, and the average value calculation circuit 13 are each configured to be capable of holding at least one data. Further, the maximum value detection circuit 2 and the minimum value detection circuit 3 have a comparator, and the average value calculation circuits 4 and 13 have a counter, an addition circuit, and a division circuit.

  When testing the A / D converter 20, a test analog signal (test signal) input to the A / D converter 20 has a small amplitude and a signal close to DC (small amplitude signal). In general, a signal having a sufficiently large amplitude (large amplitude signal) is used.

  First, a case where a small amplitude signal is used as a test signal will be described. A small-amplitude signal used as a test signal is referred to as VTs.

  When the test signal VTs is input to the A / D converter 20, a change in the value of digital data obtained by performing conversion processing on the test signal VTs is small. Therefore, if noise is superimposed at the time of conversion, even if the noise component is small, it may affect the upper bits of the converted digital signal depending on the case. In this case, the input test signal cannot be correctly converted into digital data.

  By the way, when a DC signal is employed as the test signal, the voltage level always shows a constant value. Even if the signal is not completely a DC signal, the signal voltage level does not deviate greatly from the voltage average value if the signal has a small amplitude. That is, it can be expected that the dispersion value of the small amplitude signal does not exceed a certain level, and this also applies to the converted digital data.

  Based on this, when a small amplitude signal is used as a test signal, the variance of the converted digital data obtained by the A / D converter 20 is measured, and whether or not this variance value is within a predetermined range is determined. By judging, the A / D converter 20 is evaluated.

  First, when starting a new test, the data stored in the maximum value detection circuit 2, the minimum value detection circuit 3, the average value calculation circuit 4, the reference setting circuit 6, and the average value calculation circuit 13 are initialized (initial setting). ) For example, in the maximum value detection circuit 2 and the reference setting circuit 6, the retained data is set to the minimum value at which each bit is 0, and in the minimum value detection circuit 3, the retained data is set to the maximum value at which each bit is 1. To do. In the average value calculation circuits 4 and 13, the stored data and the counter are set to the minimum value at which each bit becomes 0.

  When the test signal VTs is input to the A / D converter 20, digital conversion is performed according to the voltage value sampled at a predetermined sampling interval τ.

  First, the digital value Ds (t1) obtained by performing digital conversion on the voltage value VTs (t1) indicated at the time t1 is sent to the maximum value detection circuit 2, the minimum value detection circuit 3, and the average value calculation circuit 4. Send it out.

  The maximum value detection circuit 2 compares the data held immediately before and the newly sent data, and holds the data having the larger value. Conversely, the minimum value detection circuit 3 holds data having a smaller value.

  The average value calculation circuit 4 calculates the average value of the digital data values sent. As an example, every time data is sent, the counter value is counted by one, and the newly sent data is added to the accumulated value held immediately before, and this is held as a new accumulated value. . Then, after all data has been acquired, the accumulated value held is divided by the counter value.

  In the case of the above method, since the accumulated value must be held until the final data is acquired, the number of bits of the value to be held becomes very large. Therefore, as another method, the accumulated value is divided by the counter value for each predetermined counter value, the value after division is set as a new accumulated value, and the counter value is cleared to 1. Then, after the final data is acquired, the average value is obtained by dividing the obtained accumulated value by the counter value. If the number of data acquisitions is a multiple of a predetermined counter value, the counter value = 1, so that the cumulative value at the final point is the average value.

  Further, in the above method, by setting the “predetermined counter value” to a power of 2, it can be realized by bit shift instead of the division operation of the counter value.

  The above arithmetic processing is sequentially performed on the digital value Ds (t2) output from the A / D converter 20 at time t2, the signal value Ds (t3) output at time t3,. When the processing for the digital value Ds (tE) output at the final sampling time tE is completed, the maximum value DsM after the digital conversion processing of the test signal VTs is stored in the minimum value detection circuit 3 in the maximum value detection circuit 2. The minimum value Dsm after the digital conversion processing of the test signal VTs is held, and the average value Dsa after the digital conversion processing of the test signal VTs is held in the average value calculation circuit 4, respectively.

  Then, the maximum value DsM, the minimum value Dsm, and the average value Dsa are output to the tester. When these data are output, they are serially sent out as one data string in which the values at the respective bit positions are sequentially arranged from the most significant bit to the least significant bit. Of course, the order of arrangement may be reversed (the direction from the least significant bit to the most significant bit).

  Next, the average value Dsa is input as serial data from the tester to the reference setting circuit 6 and set as a reference value. Then, the same test signal VTs is input to the A / D converter 20 again. As before, the A / D converter 20 performs digital conversion processing according to the voltage value sampled at a predetermined sampling interval τ, and this time, the digital value after conversion processing is converted to the variance value calculation circuit 5 ( More specifically, it is sent to the absolute difference calculation circuit 8).

  The difference absolute value calculation circuit 8 first calculates a difference value between the digital value sent from the A / D converter 20 and the value set in the reference setting circuit 6 (that is, the average value Dsa) in the subtractor 9, The absolute value circuit 11 calculates the absolute value and outputs it to the square pre-processing circuit 15.

  The square preprocessing circuit 15 includes an upper bit zero determination circuit 16 and an upper bit digit dropping circuit 17. The high-order bit zero determination circuit 16 is a circuit that determines whether or not all high-order (NM) bits are 0 among the digital values (N-bit values) sent from the differential absolute value calculation circuit 8. If the high-order bit zero determination circuit 16 determines that all the high-order (NM) bits of the digital value sent from the difference absolute value calculation circuit 8 are 0, the high-order bit carry-down circuit 17 M) Bits are discarded, and only the lower M bits of digital data are sent to the squaring circuit 12. On the other hand, if even one of the upper (NM) bits has “1”, the upper bit zero determination circuit 16 outputs a FAIL signal to the tester and stops the subsequent processing.

  The square circuit 12 performs a square process on the digital data dropped to M bits by the square pre-processing circuit 15 and sends the digital data to the average value calculation circuit 13. The average value calculation circuit 13 calculates the average value of the digital data (corresponding to “data after the square process”) sent from the square circuit 12 by the same method as the average value calculation circuit 4.

  The above arithmetic processing is sequentially performed on the digital value Ds (t2) output from the A / D converter 20 at time t2, the signal value Ds (t3) output at time t3,. When the above processing for the digital value Ds (tE) is completed without the upper bit zero determination circuit 16 outputting the FAIL signal until the final sampling time tE, the average value calculation circuit 13 receives the test signal VTs. The variance value for the data after the digital conversion processing is held as 2M bit data. The average value calculation circuit 13 outputs this value to the tester. At the time of output, it is output to the tester as a serial data string in the same manner as in the case of the maximum value or the minimum value.

  When the small amplitude signal VTs is used as the test signal, as described above, since the fluctuation of the amplitude is small in the first place, it is expected that the dispersion value also remains below a certain level. Since the variance value is defined as the average value of the square of the error from the average value of each value (here, the digitally converted value at each time), the fact that this variance value remains below a certain level means that This means that the error from the average digital value at each time also remains below a certain level. Therefore, the difference absolute value between the digital value Ds (t) at each time t and the average value Dsa set in the reference setting circuit 6 remains below a certain level. Can be expected. In other words, when the value of the upper few bits including the most significant bit is not “0” (“1”), the test signal VTs is no longer correctly D / It can be determined that A conversion processing has not been performed. This is remarkable when the test signal VTs is a DC signal.

  The square circuit 12 is a circuit that multiplies input digital data, and generates data having a length twice the number of bits of the input data. For this reason, if the number of bits of input data is large, the circuit scale also increases. Therefore, if the input N-bit digital data is squared as it is, an N-bit × N-bit operation is performed, and the circuit scale becomes large. However, in the present invention, the upper (N−M) bits are dropped in advance, so that the digital data of M bits smaller than N bits is limited to the square process (M bits × M bits arithmetic process). The scale of the circuit 12 can be reduced. In addition, since the test signal VTs is a small amplitude signal and the values of the higher order (NM) bits that have lost digits are all “0”, the dispersion value obtained even when such a loss processing is performed. There is no effect.

  In the present embodiment, when the A / D converter 20 is tested using the test signal VTs having a small amplitude, the minimum value, the maximum value, the average value, and the variance value are measured and transmitted to the tester. However, since it is assumed that the evaluation is performed based on the variance value, the data regarding the minimum value and the maximum value is not necessarily required. In this embodiment, since the minimum value and the maximum value can be calculated in parallel with the calculation of the average value by the average value calculation circuit 4, these are calculated as evaluation elements.

  Next, a case where a large amplitude signal is used as a test signal will be described. A large-amplitude signal used as a test signal is referred to as a code VTL.

  When the test signal VTL is input to the A / D converter 20, the number of bits of the digital data DL (t) obtained by performing conversion processing on the test signal VTL is large. Therefore, unlike the small-amplitude test signal VTs, even if noise is superimposed at the time of conversion, the converted digital signal is affected only by the lower bits and has no effect on the upper bits.

  On the other hand, in the case of the large amplitude test signal VTL, since the fluctuation of the digital data DL (t) is larger than that of the small amplitude test signal VTs, the variance value is expected to be large. Therefore, unlike the small-amplitude test signal VTs, it is impossible to judge that the digital conversion process is not performed correctly unless the higher-order bits are all 0. Therefore, the squaring preprocessing circuit 15 performs the digit loss process. I can't do it. However, if an attempt is made to obtain the variance without using this square pre-processing circuit 15, multi-bit × multi-bit multiplication must be performed by the square circuit 12, which increases the circuit scale.

  That is, in the case of the test signal VTL having a large amplitude, unlike the test signal VTs having a small amplitude, the necessity for measuring dispersion is low. Rather, the circuit scale of the squaring circuit 12 required for the measurement is small. Since it becomes very large, we do not dare to evaluate by variance value. Instead, the digital conversion is evaluated based on the distance between the maximum digital data DLM and the minimum digital data DLm (that is, the peak-to-peak value of the digital data) of the test signal VTL. In other words, the evaluation is performed based on a value obtained by converting the signal strength of the test signal VTs into digital data.

  Since the amplitude of the test signal VTL is sufficiently large in the first place, a large Peak-to-Peak value that is the difference between the maximum value and the minimum value is expected. Since the magnitude of the noise is somewhat smaller than the magnitude of the amplitude of the test signal VTL, even if some noise is superimposed, the Peak-to-Peak value is not affected. Therefore, if the digital Peak-to-Peak value is within a predetermined range, it can be determined that the digital conversion has been correctly performed.

  The calculation method of the maximum value and the minimum value is the same as in the case of the test signal VTs having a small amplitude, and the description is omitted. Further, in addition to the maximum value and the minimum value, data related to the average value may be output to the tester.

  In the case of performing a test using the large amplitude signal VTL, it is described that “the evaluation based on the variance value is not performed”. This is because the peak value is output to the tester after the maximum value, the minimum value, and the average value are output to the tester. If it is recognized that the signal is a large amplitude signal based on the -to-Peak value, it can be realized by no longer setting the reference value to the reference setting circuit 6. In other words, when the tester evaluates the peak-to-peak value from the maximum and minimum data and recognizes that the test signal is a small amplitude signal, the test setting is averaged with respect to the reference setting circuit 6. The value may be set as a reference value, and the test signal may be input again.

  As a test method, a method of using both the small amplitude signal VTs and the large amplitude signal VTL and evaluating the A / D converter 20 based on the respective results can be considered. For example, digital conversion processing is performed on both signals, and the A / D converter 20 is evaluated based on the S / N ratio obtained from these values. Hereinafter, an example method will be described.

  First, a predetermined voltage signal (for example, a sine signal of a reference frequency) is used as the large amplitude signal VTL, and the digital data relating to the maximum value, the minimum value, and the average value is calculated and output to the tester by the above method. Then, it is confirmed whether the difference between the maximum value and the minimum value (that is, Peak-to-Peak value) and the average value satisfy initial conditions. You may evaluate using the intermediate value of said Peak-to-Peak.

  Next, a predetermined voltage signal (for example, DC signal) is used as the small amplitude signal VTs. First, digital data relating to the maximum value, the minimum value, and the average value are calculated and output to the tester, and then the average value is used as a reference value. By setting the value and inputting VTs again, the variance value is calculated and output to the tester. At this time, if a predetermined (NM) bit does not satisfy all zeros by the upper bit zero determination circuit 16, a FAIL value is returned to the tester.

  Next, the square root of the mean square value in the sampling period τ of the sin signal with the amplitude of the peak-to-peak value when the large amplitude signal VTL is used as the test signal, and the square root of the calculated variance value The ratio is calculated (or multiplied by a correction coefficient as necessary) to obtain the S / N ratio. It is determined whether the S / N ratio is a value within a predetermined range. When a signal other than a sin signal or a cos signal is used as the test signal VTL, the ratio between the maximum amplitude of the test signal VTL and the measured value of Peak-to-Peak is calculated. A value obtained by integrating the value obtained by multiplying the square of the signal VTL over the sampling period τ may be used.

  Here, if necessary, the correction coefficient is multiplied when calculating the Peak-to-Peak (maximum value detection circuit 2, minimum value detection circuit 3) and when calculating the variance. Since the circuits used (average value calculation circuit 4, variance value calculation circuit 5) are different, and simply calculating the ratio of values obtained using these different circuits, an error may occur. ) Is performed for the purpose of suppressing. The correction coefficient may be a value derived in advance.

  The following method can be considered as a method for deriving the correction coefficient. First, the last amplitude value at which the upper bit zero determination circuit 16 does not operate, that is, the upper (NM) bits are all 0, and if the amplitude is expanded more than that, “1” is included in the bits. An amplitude value is determined, a Peak-to-Peak value and a variance value are calculated under the amplitude value, and a correction coefficient is determined based on these ratios. Since this value is a last-minute value at which no digits are lost, it can be said that the error between the two is the smallest test voltage, and such a ratio can be used as a correction coefficient.

  As another method, a peak-to-peak value is measured by inputting a DC voltage to the A / D converter 20. The Peak-to-Peak value obtained here indicates the Peak-to-Peak value derived from the superimposed noise component. Thereafter, the S / N ratio is derived using a value obtained by subtracting the Peak-to-Peak value derived from the noise component measured previously from the Peak-to-Peak value when the large amplitude signal VTL is used as the test signal. Thereby, S / N ratio is computable in the state which suppressed the influence of the noise superimposed on DC voltage.

  Instead of using the mean square value in the sampling period τ, the mean value of Peak-to-Peak is multiplied by the voltage value at each sampling time (t1, t2,..., TE) and squared. An average value may be used.

  In addition to S / N ratio measurement, LPF attenuation measurement and crosstalk measurement can be performed using both the small amplitude signal VTs and the large amplitude signal VTL, as described above. Detailed explanation is omitted.

  Another test of the A / D converter 20 is to check whether digital data not corresponding to the input test signal is being output. In performing this test, the maximum value detection circuit 2 is provided with a subtracter together with a comparator so that the newly input digital value is larger than the digital value held at the present time, and the difference between the two is a predetermined value. The input value is updated as new retained data only when the value is less than (for example, “1”). On the other hand, if the input data is less than or equal to the value of the retained data, or if there is a difference between the two data that is greater than the predetermined size, a signal to that effect is output and the processing is terminated. Thereby, for example, when an analog signal (for example, a ramp waveform) that monotonously increases is input as a test signal, the data output from the maximum value detection circuit 2 after the completion of the test signal input indicates the upper limit value of the analog signal as A / D If it is confirmed that the digital value is obtained by the conversion, it is possible to check whether or not the converted digital data also increases monotonously and continuously.

  A monotonically decreasing analog signal can be tested by the same method. That is, the minimum value detection circuit 3 is provided with a subtracter together with a comparator, and the newly input digital value is smaller than the digital value held at the present time, and the difference between the two is a predetermined magnitude (for example, “1” ]) Update the input value as new retained data only if: On the other hand, if the input data is equal to or greater than the value of the retained data or if there is a difference between the two data larger than the predetermined size, a signal to that effect is output and the processing is terminated.

  In particular, by setting the predetermined size to “1”, it can be checked whether or not all corresponding digital values (codes) are output.

  As another test, a test related to the linearity of the input signal and the output signal is assumed. When performing this test, after measuring the lower limit voltage and the upper limit voltage of the input range, the two are divided and the amplitude corresponding to 1 bit (LSB) of the A / D converter 20 is calculated. Then, an analog signal obtained by adding a value obtained by multiplying the voltage of 1LSB by the code value to the lower limit voltage of the input range is input as a test voltage, and the variance value is obtained by the variance value calculation circuit 5 and output to the tester. At this time, the code value is set as a reference value. This process is calculated while changing each code value by 1 to examine whether or not there is a code having a large variance value. It can be detected that the linearity is poor in the code value indicating a large variance value compared to the others.

  According to this method, since it is only necessary to compare the respective variance values, there is an effect that it is not necessary to perform special arithmetic processing on the tester side.

  As a method of measuring the lower limit voltage of the input range, a method of setting the upper limit voltage at which the maximum value detection circuit 2 outputs “0”, a lower limit voltage immediately before the minimum value detection circuit 3 stops outputting “0”. In addition to the method described above, a method of setting the lower limit voltage using the average value of these two can be used. The reverse voltage may be used for the upper limit voltage.

[Another embodiment]
In the following, another embodiment will be described.

  <1> In the above embodiment, the test circuit 1 of the present invention generates data necessary for performing a test, serially outputs the data to the tester, and the test result can be recognized only when the tester performs a predetermined calculation. The configuration. On the other hand, a configuration (BIST: Built-in Self-Test) capable of recognizing up to the test result inside the test circuit may be used.

  More specifically, an evaluation unit capable of setting a reference value from the outside is provided. The evaluation unit includes a comparator, an arithmetic circuit that performs simple four arithmetic operations, and a data holding circuit. Each reference value (that is, ideal peak-to-peak value, ideal average value, ideal variance value, etc.) is written to the data holding circuit from the outside.

  Data of the maximum value and the minimum value obtained by the maximum value detection circuit 2 and the minimum value detection circuit 3 is output to the evaluation unit, and calculation is performed in the evaluation unit to obtain a Peak-to-Peak measurement value. Then, a divergence between the measured value and the ideal Peak-to-Peak value is calculated, and a result indicating whether or not the divergence remains within a predetermined range is output to the outside.

  Similarly, the variance value and the average value obtained by the variance value calculation circuit 5 and the average value calculation circuit 4 are compared with the ideal variance value and the ideal average value held in the data holding circuit in the evaluation unit. The deviation is calculated, and the result of whether or not this deviation remains within a predetermined range is output to the outside.

  In this configuration, compared to when testing outside the test circuit, a holding circuit for holding the ideal peak-to-peak value, ideal variance value, ideal average value, and an arithmetic unit for calculating the deviation, An integrated circuit that originally requires a comparator but incorporates a microcomputer or the like can be handled without adding a new component. In addition, when evaluating Peak-to-Peak values, variance values, average values, etc., it is possible to minimize the circuit scale of the holding circuit by writing the ideal value to the holding circuit before each evaluation. it can. It should be noted that, in actuality, a configuration capable of holding at least data of the maximum number of bits (2N) that can be taken by the ideal variance value may be used.

  <2> In the above embodiment, the test circuit 1 of the present invention is configured to provide the average value calculation circuit 13 different from the average value calculation circuit 4 in the variance value calculation circuit 5, but these average value calculation circuits May be shared (FIG. 3).

  The test circuit 1A shown in FIG. 3 has a configuration in which a selector 18 is provided instead of the average value calculation circuit 4 and the output data of the squaring circuit 12 is output to the selector 18. The output data of the A / D converter 20 is also output to the selector 18. The selector 18 selects one of the input data and outputs it to the average value calculation circuit 13.

  In this case, when the test of the A / D converter 20 is performed using the test signal VTs having a small amplitude, first, the selector 18 selects the output data of the A / D converter 20, and the time t (t = t1, Digital data Ds (t) output at t2,..., tE) is output to the average value calculation circuit 13, and the average value calculation circuit 13 calculates the average value Dsa. After outputting this average value Dsa to the tester, it is written in the reference setting circuit 6 as a set value. Next, the selector 18 selects the output data of the square circuit 12 and outputs the data sequentially output from the square circuit 12 to the average value calculation circuit 13, and the average value calculation circuit 13 calculates the average value (that is, this is the variance value). Equivalent to With this configuration, the average value calculation circuits 4 and 13 can be shared.

  In this case, the average value calculation circuit 13 needs to calculate an average value for the N-bit data output from the A / D converter 20 and the 2M-bit data output from the squaring circuit 12. That is, it is necessary to design the average value calculation circuit 13 according to the larger number of bits of N and 2M. At this time, for example, N = 2M is set, and the number of bits is set to the maximum number of bits that can be calculated by the average value calculation circuit 13, thereby maximizing both reduction of the circuit scale and ensuring of calculation accuracy. be able to.

  <3> In the above embodiment, the average value calculated by the average value calculation circuit 4 is once output to the tester, and then the average value is written to the reference setting circuit 6 from the tester. The calculation result may be directly output to the reference setting circuit 6.

  <4> In the above embodiment, the upper bit zero determination circuit 16 outputs a FAIL signal to the tester and stops the subsequent processing if even one of the upper (NM) bits is “1”. It was. On the other hand, a counter that counts the number of times “1” exists in even one of the upper (NM) bits is provided, and the lower M bits of digital data are stored until the value indicated by the counter exceeds a predetermined value. It is good also as a structure which continues the process sent out to the squaring circuit 12. FIG.

  <5> In the above embodiment, the circuit scale is reduced by reducing the number of bits to be squared using the square preprocessing circuit 15, but if the number of bits of digital data is not significantly large, The output data of the difference absolute value calculation circuit may be directly input to the square circuit 12.

  <6> In the above embodiment, the dispersion value was measured by calculating the average value of values obtained by squaring the difference from the average value of each digital data. Incidentally, a certain correlation is recognized between the average value for the difference from the average value of each digital data and the variance value. For this reason, when the circuit scale is inevitably large and cannot be mounted on the IC, as a second best measure, the square circuit 12 is eliminated, and the average value calculation circuit 13 outputs the output data of the (square) preprocessing circuit 15. An average value may be calculated, and the A / D converter 20 may be evaluated based on a variance value estimated from this value.

  In this case, the value obtained by the average value calculation circuit 13 is not a “dispersion value”, but merely a value serving as a basis for estimating the dispersion value. That is, the test circuit of this embodiment does not include the “dispersion value calculation circuit 5” that calculates the “dispersion value”, but includes a “dispersion estimation value calculation circuit” that calculates a base value for estimating the dispersion value. Prepare. This variance estimated value calculation circuit is composed of elements obtained by removing the square circuit 12 from the variance value calculation circuit 5.

1: Test circuit of the present invention 2: Maximum value detection circuit 3: Minimum value detection circuit 4: Average value calculation circuit 5: Variance calculation circuit 6: Reference setting circuit 8: Difference absolute value calculation circuit 9: Subtractor 10: Book Integrated circuit equipped with test circuit of invention 11: Absolute value circuit 12: Square circuit 13: Average value calculation circuit 15: Pre-square calculation circuit 16: High-order bit zero decision circuit 17: High-order bit carry-down circuit 18: Selector 20: A / D converter 21: Integrated circuit using digital data 70: Integrated circuit with conventional test function 71: Selector 72: D / A converter 80: Integrated circuit with conventional test function 90: Conventional circuit Integrated circuit with test function 91: Test circuit 92: RAM

Claims (10)

A test circuit for an A / D converter that converts an analog signal to be converted into a series of basic digital data, and is configured on the same substrate as the A / D converter,
A maximum value detection circuit to which the basic digital data is input, a minimum value detection circuit, and a variance value calculation circuit;
The maximum value detection circuit sequentially compares the size of the held data and the input data while the basic digital data is input, and updates the held data to the input data when the input data is larger than the held data,
The minimum value detection circuit sequentially compares the held data and the input data while the basic digital data is input, and updates the held data to the input data when the input data is smaller than the held data,
The variance value calculation circuit performs a variance value calculation of the basic digital data and holds the data,
After completion of the input of the basic digital data, the held data of the maximum value detection circuit, the minimum value detection circuit, and the variance value calculation circuit are externally set as the maximum value, the minimum value, and the variance value of the basic digital data, respectively. A test circuit for an A / D converter, wherein the test circuit is configured to be capable of outputting to the A / D converter. An average value calculation circuit to which the basic digital data is input;
The average value calculation circuit updates the held data by sequentially calculating the average value while the basic digital data is input, and after completing the input of the basic digital data, the average value calculation circuit calculates the average value of the basic digital data. The test circuit for an A / D converter according to claim 1, wherein the test circuit is configured to be output to the outside. The variance value calculation circuit includes:
A difference absolute value calculation circuit for calculating a difference absolute value between the digital data output from the A / D converter and the reference data set in the reference setting circuit;
A square circuit that applies a square process to the digital data output from the absolute difference calculation circuit;
An average value calculation circuit for dispersion that calculates an average value of a series of squared data output from the square circuit;
The average value calculation circuit for dispersion is
In the state where the average value of the basic digital data obtained by A / D-converting the analog signal by the A / D converter is set as the reference data, the same analog signal is converted to A / D by the A / D converter. While the converted basic digital data is input to the difference absolute value calculation circuit, the held data is updated by calculating an average value of the squared data output from the square circuit, and the difference absolute value calculation 3. The test circuit for an A / D converter according to claim 2, wherein after the input of the basic digital data to the circuit is completed, the held data can be output to the outside as a variance value of the basic digital data. . The variance value calculation circuit includes:
A difference absolute value calculation circuit for calculating a difference absolute value between the digital data output from the A / D converter and the reference data set in the reference setting circuit;
A square circuit that applies a square process to the digital data output from the absolute difference calculation circuit;
A selector that selects and outputs either output data of the A / D converter or output data of the squaring circuit;
An average value calculating circuit for calculating an average value of a series of digital data input from the selector;
The average value calculation circuit includes:
When the output data of the A / D converter is selected by the selector, an average value is obtained while the basic digital data obtained by A / D converting the analog signal by the A / D converter is input. The calculation is performed to update the holding data, and after the input of the basic digital data is completed, the holding data can be output as an average value of the basic digital data, and
When the output data of the square circuit is selected by the selector, the same analog signal is A / D converted by the A / D converter in a state where the average value of the basic digital data is set as the reference data. While the converted basic digital data is input to the difference absolute value calculation circuit, the average data of the series of squared data sequentially output from the square circuit is calculated to update the held data, and the difference is updated. 2. The A / D conversion according to claim 1, wherein after the input of the basic digital data to the absolute value calculation circuit is completed, the held data can be output to the outside as a variance value of the basic digital data. Test circuit for dexterity. The variance value calculation circuit determines whether or not a predetermined number of upper bits are all 0s in the digital data output from the difference absolute value calculation circuit. A square pre-processing circuit that outputs the remaining lower bits,
The test circuit for an A / D converter according to claim 3, wherein the square circuit performs a square process on the digital data output from the square pre-processing circuit. The variance value calculation circuit determines whether or not a predetermined number of upper bits are all 0s in the digital data output from the difference absolute value calculation circuit. A square pre-processing circuit that outputs the remaining lower bits,
5. The A / D converter test circuit according to claim 4, wherein the square circuit performs a square process on the digital data output from the square pre-processing circuit.   7. The A / D converter test circuit according to claim 6, wherein the predetermined number of upper bits is ½ of the maximum number of bits of digital data output from the A / D converter.   The A / D converter test according to any one of claims 3 to 7, wherein the reference setting circuit is configured to be able to count up and / or count down a reference value to be set. circuit.   The maximum value detection circuit sequentially compares the stored data and the input data while the basic digital data is input, and is larger than the stored data at the time of input, and the difference between the input data and the stored data is a predetermined value. 9. The A / D converter test circuit according to claim 1, wherein the A / D converter test circuit has a limiting function of updating the stored data to input data only in the following cases.   The minimum value detection circuit sequentially compares the stored data and the input data while the basic digital data is input. The minimum value detection circuit is smaller than the stored data at the time of input, and the difference between the input data and the stored data is predetermined. 10. The A / D converter test circuit according to claim 1, further comprising a limiting function of updating the stored data to input data only when the value is equal to or less than the value. 11.

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