WO2012165940A1 - A method of measuring non-linearity specification of an analog-to-digital converter (adc) - Google Patents
A method of measuring non-linearity specification of an analog-to-digital converter (adc) Download PDFInfo
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- WO2012165940A1 WO2012165940A1 PCT/MY2012/000115 MY2012000115W WO2012165940A1 WO 2012165940 A1 WO2012165940 A1 WO 2012165940A1 MY 2012000115 W MY2012000115 W MY 2012000115W WO 2012165940 A1 WO2012165940 A1 WO 2012165940A1
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- analog
- digital converter
- linearity
- input
- adc
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
- H03M1/109—Measuring or testing for dc performance, i.e. static testing
Definitions
- the present invention relates to a method of measuring non-linearity specification of an analog-to-digital converter (ADC).
- Static parameters are an important component of an analog to digital converter (ADC) specification. These parameters measure the ADCs non-linearity when the input is a very low frequency signal (near DC). Examples of these parameters are differential non- linearity (DNL) and integral non-linearity (INL). DNL is a deviation of a code width from the ideal one measured in least significant bit (LSB) while INL is the deviation of an ADC's transfer function from its ideal transfer function as shown in Figure 1 and 2.
- DNL differential non- linearity
- INL integral non-linearity
- a histogram method (also known as code density test) is a standard way to measure the INL and DNL of an A/D converter as described in IEEE Standard for Terminology and Test Methods for Analog-To-Digital Converters, IEEE Std. 1241-2000, Dec. 2000.
- the objective of the histogram test methodology is to measure the width of all the codes and calculate the DNL and INL specifications from the code width measurements.
- the data increases by a factor of two for each bit added to the converter's resolution.
- a method of measuring non-linearity specification of an analog-to-digital converter (ADC) by measuring deviation of observed output code distribution from an ideal distribution by providing a custom piecewise linear ramp input waveform to the analog to digital convertor and providing a reference input and a clock input to the analog to digital convertor includes the steps of generating a plurality of analog to digital converter output codes based on the custom ramp input waveform, storing a plurality of output codes, analyzing the plurality of output codes, reporting maximum differential non-linearity values for each output code and identifying the maximum value of differential non-linearity based on a plot of analog input versus differential non-linearity values for each output code generated from the input ramp waveform.
- Figure 1 shows a graphical representation of a Differential Non-linearity of an Analog Digital Converter
- Figure 2 shows a graphical representation of an Integral non-linearity of an Analog Digital Converter
- Figure 3 shows a flowchart that illustrates a test stimulus in histogram testing of an Analog Digital Converter in the preferred embodiment of the invention
- Figure 4 shows a schematic of a binary weighted charge redistribution DAC block
- Figure 5 shows a schematic of a 3 bit unitary weighted (thermometer coded) DAC block
- Figure 6 shows a graphical representation of a DNL plot for binary weighted DAC of successive approximation analog to digital converter in the preferred embodiment of the invention
- Figure 7 shows a graphical representation of a DNL plot for unitary weighted DAC of SA- ADCin the preferred embodiment of the invention
- Figure 8 shows a block diagram of a hardware setup for histogram testing of ADC in the preferred embodiment of the invention
- Figure 9 shows a graphical representation of a sample piecewise ramp used for accelerated DNL testin the preferred embodiment of the invention
- Figure 10 shows a flowchart of a method of measuring non-linearity of specifications of an analog-to-digital converter (ADC) in the preferred embodiment of the invention.
- ADC analog-to-digital converter
- Figure 11 shows a flowchart of specific measurement setup for testing a successive approximation analog to digital converter circuitry for differential non-linearity errors in the preferred embodiment of the invention.
- the present invention relates to a method of measuring non-linearity specification of an analog-to-digital converter (ADC).
- ADC analog-to-digital converter
- Figure 10 is a flowchart that illustrates a method of measuring non-linearity specification of an analog-to-digital converter (ADC) for measuring deviation of observed output code distribution from an ideal distribution by providing a custom piecewise linear ramp input waveform to the analog to digital convertor and providing a reference input and a clock input to the analog to digital convertor.
- ADC analog-to-digital converter
- the method includes the steps of generating a plurality of analog to digital converter output codes based on the custom ramp input waveform, storing a plurality of output codes, analyzing the plurality of output codes, reporting maximum differential non-linearity values for each output code and identifying the maximum value of differential non-linearity based on a plot of analog input versus differential non-linearity values for each output code generated from the input ramp waveform.
- a model for determination of differential non-linearity (DNL) errors of a successive approximation analog to digital converter which incorporates circuit non-idealities in the successive approximation analog to digital converter is generated to be used with the method.
- the model includes information of the digital to analog converter (DAC) sub- circuit topology used as part of a successive approximation analog to digital converter (SA-ADC), wherein this model embeds statistical mismatch variation information (standard deviation) of basic elements such as capacitors and resistors which make up the digital to analog converter (DAC) sub-circuit.
- DAC digital to analog converter
- the method measures maximum values of DNL happening at a specific code range defined by DAC topology wherein the method measures the DNL specifications of SA- ADC faster than conventionally known histogram methods.
- the method is used in measuring the ADCs non-linearity when input is at a very low frequency.
- a low-frequency test stimulus is applied to the ADC and a histogram of the output digital codes is obtained as shown in Figure 3.
- the histogram of the output digital codes shows a number of times each digital code word appears at the ADC output (number of hits).
- the test stimulus is a low frequency triangular ramp or a sinusoidal signal.
- Ideal output code histogram for a triangular ramp test stimulus is a flat distribution with equal hits per code.
- Ideal output code histogram for a sinusoidal test stimulus is a bathtub distribution. The deviation of the observed output code distribution from the ideal distribution is a measure of the non-linearity in the device. DNL of the ADC under test can be measured by counting the number of hits for each code and comparing them against the ideal number of hits for that code.
- Figure 4 and 5 show a binary weighted charge redistribution DAC block and a 3 bit unitary weighted (thermometer coded) DAC block respectively.
- the number of samples that are required for histogram testing depends on the resolution of the analog to digital converter (ADC) and the level of accuracy desired in the DNL measurement. As the resolution of the ADC increases, the number of samples required to achieve the desired accuracy in the code width measurement increases by a factor of two for each bit added to the converter's resolution. This results in a large test time for measuring all the code widths to calculate the integral nonlinear (INL) and DNL specifications.
- ADC analog to digital converter
- INL integral nonlinear
- the present invention reduces the time taken for conducting these measurements.
- the method measures the DNL specifications of SA-ADC faster than conventionally known methods.
- the method is based on the fact that, the maximum values of DNL, happens at specific code range defined by the digital to analog (DAC) topology inherent in the designed ADC.
- DAC digital to analog
- the method identifies specific code widths that have the highest impact on the static specifications of the designed SA-ADC.
- a piecewise linear test stimulus (see Figure 8) is then generated to measure these specific code widths using a specific measurement setup for histogram testing (see Figure 9).
- a function generator for providing programmable custom analog input waveforms to the analog to digital convenor, pulse generator circuit for providing pulse waveforms to the clock input of the analog to digital converter, a voltage regulator for providing a constant and stable voltage to the reference input of the analog to digital converter, a logic analyzer to store a plurality of output codes of the analog to digital converter generated by the analog input waveformsand an output data analysis tool adapted to identify differential non-linearity values corresponding to the output codes obtained as seen in Figure 11.
- This invention is adapted for use for measuring the ADCs non-linearity when input is at a very low frequency.
- the disclosed invention is suitable, but not restricted to, for use in ADCs.
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Abstract
A method of measuring non-linearity specification of an analog-to-digital converter (ADC) is provided, characterized in that, measuring of deviation of observed output code distribution from an ideal distribution by providing a custom piecewise linear ramp input waveform to the analog to digital converter and providing a reference input and a clock input to the analog to digital converter, the method includes the steps of generating a plurality of analog to digital converter output codes based on the custom ramp input waveform, storing a plurality of output codes, analyzing the plurality of output codes, reporting maximum differential non- linearity values for each output code and identifying the maximum value of differential non- linearity based on a plot of analog input versus differential non-linearity values for each output code generated from the input ramp waveform.
Description
A METHOD OF MEASURING NON-LINEARITY SPECIFICATION OF AN ANALOG-TO- DIGITAL CONVERTER (ADC)
FIELD OF INVENTION
The present invention relates to a method of measuring non-linearity specification of an analog-to-digital converter (ADC). BACKGROUND OF INVENTION
Static parameters are an important component of an analog to digital converter (ADC) specification. These parameters measure the ADCs non-linearity when the input is a very low frequency signal (near DC). Examples of these parameters are differential non- linearity (DNL) and integral non-linearity (INL). DNL is a deviation of a code width from the ideal one measured in least significant bit (LSB) while INL is the deviation of an ADC's transfer function from its ideal transfer function as shown in Figure 1 and 2.
A histogram method (also known as code density test) is a standard way to measure the INL and DNL of an A/D converter as described in IEEE Standard for Terminology and Test Methods for Analog-To-Digital Converters, IEEE Std. 1241-2000, Dec. 2000. The objective of the histogram test methodology is to measure the width of all the codes and calculate the DNL and INL specifications from the code width measurements. However, due to the large number of samples required to achieve the desired accuracy in the code width measurement, the data increases by a factor of two for each bit added to the converter's resolution. This results in a large test time for measuring all the code widths to calculate the integral and differential nonlinearity (INL) and DNL specifications
Therefore, there is a need for a solution that achieves this desired accuracy in measurement in INL and DNL specifications in a speedier manner.
SUMMARY OF INVENTION
Accordingly, there is provided a method of measuring non-linearity specification of an analog-to-digital converter (ADC) by measuring deviation of observed output code distribution from an ideal distribution by providing a custom piecewise linear ramp input waveform to the analog to digital convertor and providing a reference input and a clock input to the analog to digital convertor, the method includes the steps of generating a plurality of analog to digital converter output codes based on the custom ramp input waveform, storing a plurality of output codes, analyzing the plurality of output codes, reporting maximum differential non-linearity values for each output code and identifying the maximum value of differential non-linearity based on a plot of analog input versus differential non-linearity values for each output code generated from the input ramp waveform.
The present invention consists of several novel features and a combination of parts hereinafter fully described and illustrated in the accompanying description and drawings, it being understood that various changes in the details may be made without departing from the scope of the invention or sacrificing any of the advantages of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, wherein:
Figure 1 shows a graphical representation of a Differential Non-linearity of an Analog Digital Converter;
Figure 2 shows a graphical representation of an Integral non-linearity of an Analog Digital Converter;
Figure 3 shows a flowchart that illustrates a test stimulus in histogram testing of an Analog Digital Converter in the preferred embodiment of the invention;
Figure 4 shows a schematic of a binary weighted charge redistribution DAC block;
Figure 5 shows a schematic of a 3 bit unitary weighted (thermometer coded) DAC block; Figure 6 shows a graphical representation of a DNL plot for binary weighted DAC of successive approximation analog to digital converter in the preferred embodiment of the invention;
Figure 7 shows a graphical representation of a DNL plot for unitary weighted DAC of SA- ADCin the preferred embodiment of the invention; Figure 8 shows a block diagram of a hardware setup for histogram testing of ADC in the preferred embodiment of the invention;
Figure 9 shows a graphical representation of a sample piecewise ramp used for accelerated DNL testin the preferred embodiment of the invention;
Figure 10 shows a flowchart of a method of measuring non-linearity of specifications of an analog-to-digital converter (ADC) in the preferred embodiment of the invention; and
Figure 11 shows a flowchart of specific measurement setup for testing a successive approximation analog to digital converter circuitry for differential non-linearity errors in the preferred embodiment of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention relates to a method of measuring non-linearity specification of an analog-to-digital converter (ADC). Hereinafter, this specification will describe the present invention according to the preferred embodiment of the present invention. However, it is to be understood that limiting the description to the preferred embodiment of the invention is merely to facilitate discussion of the present invention and it is envisioned that those skilled in the art may devise various modifications and equivalents without departing from the scope of the appended claims.
The following detailed description of the preferred embodiment will now be described in accordance with the attached drawings, either individually or in combination. Figure 10 is a flowchart that illustrates a method of measuring non-linearity specification of an analog-to-digital converter (ADC) for measuring deviation of observed output code distribution from an ideal distribution by providing a custom piecewise linear ramp input waveform to the analog to digital convertor and providing a reference input and a clock input to the analog to digital convertor. The method includes the steps of generating a plurality of analog to digital converter output codes based on the custom ramp input waveform, storing a plurality of output codes, analyzing the plurality of output codes, reporting maximum differential non-linearity values for each output code and identifying the maximum value of differential non-linearity based on a plot of analog input versus differential non-linearity values for each output code generated from the input ramp waveform.
A model for determination of differential non-linearity (DNL) errors of a successive approximation analog to digital converter which incorporates circuit non-idealities in the successive approximation analog to digital converter is generated to be used with the method. The model includes information of the digital to analog converter (DAC) sub- circuit topology used as part of a successive approximation analog to digital converter (SA-ADC), wherein this model embeds statistical mismatch variation information (standard deviation) of basic elements such as capacitors and resistors which make up the digital to analog converter (DAC) sub-circuit.
The method measures maximum values of DNL happening at a specific code range defined by DAC topology wherein the method measures the DNL specifications of SA- ADC faster than conventionally known histogram methods. The method is used in measuring the ADCs non-linearity when input is at a very low frequency.
A low-frequency test stimulus is applied to the ADC and a histogram of the output digital codes is obtained as shown in Figure 3. The histogram of the output digital codes shows a number of times each digital code word appears at the ADC output (number of hits). Generally, the test stimulus is a low frequency triangular ramp or a sinusoidal signal. Ideal output code histogram for a triangular ramp test stimulus is a flat distribution with equal hits per code. Ideal output code histogram for a sinusoidal test stimulus is a bathtub distribution. The deviation of the observed output code distribution from the ideal distribution is a measure of the non-linearity in the device. DNL of the ADC under test can be measured by counting the number of hits for each code and comparing them against the ideal number of hits for that code.
Figure 4 and 5 show a binary weighted charge redistribution DAC block and a 3 bit unitary weighted (thermometer coded) DAC block respectively.
The number of samples that are required for histogram testing depends on the resolution of the analog to digital converter (ADC) and the level of accuracy desired in the DNL measurement. As the resolution of the ADC increases, the number of samples required to achieve the desired accuracy in the code width measurement increases by a factor of two for each bit added to the converter's resolution. This results in a large test time for measuring all the code widths to calculate the integral nonlinear (INL) and DNL specifications.
The present invention reduces the time taken for conducting these measurements.
The method measures the DNL specifications of SA-ADC faster than conventionally known methods. The method is based on the fact that, the maximum values of DNL, happens at specific code range defined by the digital to analog (DAC) topology inherent in the designed ADC. By running multiple simulations using behavioral models of the SA- AD, as seen in Figure 6 and 7, an estimation of the code ranges where the worst DNL happens can be predicted in advance. Therefore, by measuring a subset of total code widths that have large DNL values, all the code widths can be estimated accurately.
The method identifies specific code widths that have the highest impact on the static specifications of the designed SA-ADC. A piecewise linear test stimulus (see Figure 8) is then generated to measure these specific code widths using a specific measurement setup for histogram testing (see Figure 9).
For testing a successive approximation analog to digital converter circuitry for differential non-linearity errors a combination of known components are used. A function generator for providing programmable custom analog input waveforms to the analog to digital convenor, pulse generator circuit for providing pulse waveforms to the clock input of the analog to digital converter, a voltage regulator for providing a constant and stable voltage
to the reference input of the analog to digital converter, a logic analyzer to store a plurality of output codes of the analog to digital converter generated by the analog input waveformsand an output data analysis tool adapted to identify differential non-linearity values corresponding to the output codes obtained as seen in Figure 11.
This invention is adapted for use for measuring the ADCs non-linearity when input is at a very low frequency. The disclosed invention is suitable, but not restricted to, for use in ADCs.
Claims
A method of measuring non-linearity specification of an analog-to-digital converter (ADC), characterized in that, measuring of deviation of observed output code distribution from an ideal distribution by providing a custom piecewise linear ramp input waveform to the analog to digital converter and providing a reference input and a clock input to the analog to digital converter, the method includes the steps of:
i. generating a plurality of analog to digital converter output codes based on the custom ramp input waveform;
ii. storing a plurality of output codes;
iii. analyzing the plurality of output codes;
iv. reporting maximum differential non-linearity values for each output code; and
v. identifying the maximum value of differential non-linearity based on a plot of analog input versus differential non-linearity values for each output code generated from the input ramp waveform.
The method as claimed in claim 1 , wherein a model for determination of differential non-linearity (DNL) errors of a successive approximation analog to digital converter which incorporates circuit non-idealities in the successive approximation analog to digital converter is generated.
The method as claimed in claim 2, wherein the model includes information of the digital to analog converter (DAC) sub-circuit topology used as part of a successive approximation analog to digital converter (SA-ADC), wherein this model embeds statistical mismatch variation information (standard deviation) of basic elements such as capacitors and resistors which make up the digital to analog converter (DAC) sub- circuit.
4. The method as claimed in claim 1 , wherein the method measures maximum values of DNL happening at a specific code range defined by DAC topology.
5. The method as claimed in claim 1 , wherein the method measures the DNL specifications of SA-ADC faster than conventionally known histogram methods.
6. The method as claimed in claim 1 , wherein the method is used in measuring the ADCs non-linearity when input is at a very low frequency.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023285477A1 (en) * | 2021-07-13 | 2023-01-19 | Nordic Semiconductor Asa | Adc non-linearity testing |
| CN115882858A (en) * | 2023-03-03 | 2023-03-31 | 南京派格测控科技有限公司 | Method and device for measuring differential nonlinearity of analog-to-digital conversion chip and electronic equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6211804B1 (en) * | 1998-05-04 | 2001-04-03 | Photobit Corporation | Using single lookup table to correct differential non-linearity errors in an array of A/D converters |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6211804B1 (en) * | 1998-05-04 | 2001-04-03 | Photobit Corporation | Using single lookup table to correct differential non-linearity errors in an array of A/D converters |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023285477A1 (en) * | 2021-07-13 | 2023-01-19 | Nordic Semiconductor Asa | Adc non-linearity testing |
| CN115882858A (en) * | 2023-03-03 | 2023-03-31 | 南京派格测控科技有限公司 | Method and device for measuring differential nonlinearity of analog-to-digital conversion chip and electronic equipment |
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