TWI397980B - 使用介電外殼以加強半導體元件之可靠性 - Google Patents

使用介電外殼以加強半導體元件之可靠性 Download PDF

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TWI397980B
TWI397980B TW098126770A TW98126770A TWI397980B TW I397980 B TWI397980 B TW I397980B TW 098126770 A TW098126770 A TW 098126770A TW 98126770 A TW98126770 A TW 98126770A TW I397980 B TWI397980 B TW I397980B
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solder
layer
openings
dielectric
dielectric material
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TW201027691A (en
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Stuart Lichtenthal
Anthony P Curtis
Guy F Burgess
Michael E Johnson
John J H Reche
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Flipchip Int Llc
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Description

使用介電外殼以加強半導體元件之可靠性 【相關申請】
本發明係請求美國臨時申請案61/087,109(2008年8月7日申請)的優先權，在此將其整體內容併入以做為參考。
本發明是關於加強半導體元件可靠性的方法。特別地，本發明是關於使用介電外殼(encasement)以加強半導體元件的可靠性。
在使用電子裝置及消費者偶而意外摔落(造成機械衝擊)電子裝置(如手機，但不以此為限)時，所發生之加熱及冷卻(分別引起膨脹及收縮)的正常循環期間，焊接接點可能斷裂。焊接接點斷裂將導致電子裝置的功能故障。因此熱循環測試和墜落測試是檢定半導體元件技術之可靠性的標準程序。
各種底部填充(underfill)和再鈍化應用已發展多年。先前技術之晶圓級晶片尺寸封裝(WLCSP)再鈍化應用涉及將介電層施加至圖案化凸塊下冶金(under bump metallurgy；UBM)層上。在這些應用中，由於再鈍化層係施加在凸塊下冶金(UBM)上方，故密封特徵結構 (feature)是形成在凸塊下冶金(UBM)墊邊緣附近。此外，底部填充於工業上之應用一般侷限於晶粒級(die level)處理方法。先前技術已揭露晶圓級底部填充。但晶圓級底部填充處理和其產生的最終結構無疑不同於本發明揭示之製程、方法、系統、設備和結構。
習知技藝之缺陷仍然存在，故本發明係針對解決該些缺陷。
本發明是關於使用介電外殼以加強半導體元件之可靠性的方法和裝置。在一或多個實施例中，使用介電外殼以加強半導體元件之可靠性的方法包含：施加光致成像型永久性介電材料層至半導體元件之頂表面；以及圖案化該光致成像型永久性介電材料層而於各個特徵結構上具有一開口。
在一或多個實施例中，光致成像型永久性介電材料層為液態介電質。在替代實施例中，光致成像型永久性介電材料層為乾膜疊層。在一些實施例中，光致成像型永久性介電材料層的厚度為1-300微米。較厚的介電層提供了額外的機械強度。
在一些實施例中，半導體元件包括一包含矽(Si)的基板層。在一或多個實施例中，半導體元件的特徵結構(feature)包括焊料焊墊、晶粒道(die street)和測試 特徵結構，但不以此為限。在至少一實施例中，光致成像型永久性介電材料層與凸塊下冶金(UBM)部分重疊至少1微米。
在一或多個實施例中，方法更包含將助焊材料分配或模版印刷(stencil print)至永久性介電材料開口內、以及施加不含助焊劑之焊料至助焊材料的頂表面。在至少一實施例中，焊料為至少一焊料球(solder sphere)及/或焊膏(solder paste)。在一或多個實施例中，方法更包含加熱半導體元件達適於焊料回流的回流溫度，使得焊料符合於永久性介電材料開口的側壁而形成保護性封接(protective seal)。
在一些實施例中，使用介電外殼以加強半導體元件之可靠性的方法包含：施加光致成像型永久性介電材料層至半導體元件之頂表面；圖案化該光致成像型永久性介電材料層而於各個特徵結構上具有一開口；分配含助焊劑之焊料至永久性介電材料開口內；以及加熱該半導體元件達適於焊料回流的回流溫度，使得焊料符合於永久性介電材料開口的側壁而形成保護性封接。
在一或多個實施例中，使用介電外殼以加強半導體元件之可靠性的裝置包含：基板層、至少一輸入/輸出(I/O)墊、鈍化層、至少一凸塊下冶金(UBM)、光致成像型永久性介電材料層、助焊材料、以及至少一不含助焊劑之焊料球。
在一些實施例中，至少一輸入/輸出(I/O)墊位於基板層 的頂表面上。又，鈍化層位於基板層的頂表面上，且位於各個輸入/輸出(I/O)墊的部分頂表面上。此外，至少一凸塊下冶金(UBM)位於各個輸入/輸出(I/O)墊的頂表面上。光致成像型永久性介電材料層位於基板層的頂表面上，且位於至少一凸塊下冶金(UBM)的頂表面上。光致成像型永久性介電材料層係經圖案化而具有位於各個特徵結構上方的開口。助焊材料位於永久性介電材料開口內。此外，至少一不含助焊劑之焊料球位於助焊材料的頂表面上。半導體元件係經加熱達適於至少一焊料球回流的回流溫度，使得至少一焊料球符合於永久性介電材料開口的側壁而形成一保護性封接。
在一或多個實施例中，使用介電外殼以加強半導體元件之可靠性的裝置包含：基板層、至少一輸入/輸出(I/O)墊、鈍化層、至少一凸塊下冶金(UBM)、光致成像型永久性介電材料層、以及至少一含助焊劑之焊料球。
在至少一實施例中，至少一輸入/輸出(I/O)墊位於基板層的頂表面上。此外，鈍化層位於基板層的頂表面上，且位於各個輸入/輸出(I/O)墊的部分頂表面上。又，至少一凸塊下冶金(UBM)位於各個輸入/輸出(I/O)墊的頂表面上。此外，光致成像型永久性介電材料層位於基板層的頂表面上，且位於至少一凸塊下冶金(UBM)的頂表面上。光致成像型永久性介電材料層係經圖案化而在各個特徵結構上具有一開口。至少一含助焊劑之焊料球位於永久性介電材料開口內。半導體元件經加熱達適於至少 一焊料球回流的回流溫度，使得至少一焊料球符合於永久性介電材料開口的側壁而形成保護性封接。
在此所述之方法和設備提出用以加強半導體元件(或，晶圓級晶片尺寸封裝；wafer level chip scale package(WLCSP))可靠性的操作系統。明確地說，此系統利用介電外殼來加強半導體元件的可靠性。
本發明是關於改善半導體元件可靠性的性能，其為委託代工製造商(OEM)所需求的，例如手機製造商，但不以此為限。特別地，目前半導體元件技術亟需改善連接晶片與基板的焊接接點(solder joint)之可靠性。
在使用電子裝置及消費者偶而意外摔落(造成機械衝擊)電子裝置(如手機，但不以此為限)時，所發生之加熱及冷卻(分別引起膨脹及收縮)的正常循環期間，焊接接點可能斷裂。焊接接點斷裂將導致電子裝置的功能故障。因此熱循環測試和墜落測試是檢定半導體元件技術之可靠性的標準程序。
焊料與下方電路/敷金屬(metallization)間的封接(seal)需改良，以免於後續電子裝置處理及/或使用電子裝置期間可能受到腐蝕劑的影響。本發明之系統採用回流製程之冷卻階段不會與焊料分離的材料或材料混合物，藉以在焊接接點處形成封接。
本發明教示之製程、方法、系統、設備和結構藉由減少熱膨脹、收縮和機械衝擊對電子裝置的影響，進而提高半導體元件性能的可靠性。此外，本發明揭示之製程、方法、系統、設備和結構能更有效密封及保護下方結構，以免遭到腐蝕或污染(其會導致裝置提早失效或故障)。本發明教示之製程、方法、系統、設備和結構可改善半導體元件之機械和熱可靠性，並加強避免元件的下方結構遭到腐蝕。
各種底部填充(underfill)和再鈍化應用已發展多年。先前技術之晶圓級晶片尺寸封裝(WLCSP)再鈍化應用涉及將介電層施加至圖案化凸塊下冶金(under bump metallurgy；UBM)層上。在這些應用中，由於再鈍化層係施加在凸塊下冶金(UBM)上方，故密封特徵結構(feature)是形成在凸塊下冶金(UBM)墊邊緣附近。此外，底部填充於工業上之應用一般侷限於晶粒級(die level)處理方法。先前技術已揭露晶圓級底部填充。但晶圓級底部填充處理和其產生的最終結構無疑不同於本發明揭示之製程、方法、系統、設備和結構。
本發明教示之設備、系統、方法、製程、和結構可被使用類似WLCSP封裝且需最大熱循環和機械韌性的公司採用。特別地，此類公司包括需此封裝設計標準的委託代工(OEM)製造商、和任何涉及製造晶片尺寸封裝(CSP)或任何相仿封裝類型的公司，但不以此為限。判斷本發明技術是否可用來製造半導體元件的一方法包含將 元件拆解成x個區段、以及使用高倍率光學顯微鏡或掃描式電子顯微鏡(SEM)檢視最終元件結構。然應注意也可採行其他方法。
以下之描述及數種細節係提供對該系統之更為透徹的說明。熟諳此技藝者將理解所述系統不一定需按下列細節才能實踐。在其他例子中，並未詳述熟知的特徵結構，以免不必要地對該系統造成混淆。
第1至5圖一同繪示使用介電外殼來製造具有加強之可靠性的半導體元件之步驟。第1圖為根據本發明至少一實施例之半導體元件100的示意圖。在此圖中，半導體元件100包括基板層110、輸入/輸出(I/O)墊130、鈍化層120和凸塊下冶金(UBM)140。在一或多個實施例中，各種半導體材料可用於基板層110，包括矽(Si)，但不以此為限。
在第1圖中，輸入/輸出(I/O)墊130位於基板層110的頂表面上。在一或多個實施例中，所述元件採用至少一輸入/輸出(I/O)墊130。又在此圖中，鈍化層120位於基板層110的頂表面上且位於輸入/輸出(I/O)墊130的部分頂表面上。此圖亦顯示凸塊下冶金(UBM)140位於輸入/輸出(I/O)墊130的頂表面上。在至少一實施例中，凸塊下冶金(UBM)140包括用來容設焊料球510的凹部(參見第5圖)。
第2圖繪示使用介電外殼來製造具有加強之可靠性的半導體元件100之第一步驟200。第2圖顯示半導體元 件100另具有光致成像型永久性(photoimageable permanent)介電材料210施加在半導體元件100的頂表面上。在此圖中，厚的光致成像型永久性介電材料之毯覆塗層210係施加在半導體元件100的頂表面上。厚毯覆塗層210完全覆蓋住凸塊下冶金140的頂表面和半導體元件100之鈍化層120的頂表面。
在一或多個實施例中，光致成像型永久性介電層210為液態介電質或乾膜疊層(laminate)。在至少一實施例中，介電層210中的介電材料為光可界定型(photodefineable)或雷射可剝蝕型(laser ablatable)。在一些實施例中，光致成像型永久性介電層210的厚度為1-300微米(μm)。較厚的光致成像型永久性介電層210提供半導體元件100額外的機械強度。
第3圖繪示使用介電外殼來製造具加強之可靠性的半導體元件100之第二步驟300。第3圖顯示光致成像型永久性介電材料層210經圖案化而在半導體元件100的單一特徵結構上具有一開口310。在此圖中，單一特徵結構為凸塊下冶金(UBM)140。在一些實施例中，光致成像型永久性介電層210係經圖案化，使得光致成像型永久性介電材料210與凸塊下冶金(UBM)140部分重疊至少1微米。在替代實施例中，光致成像型永久性介電層210經圖案化而在特徵結構上具有開口310，該特徵結構包括焊料焊墊、晶粒道(die street)和測試特徵結構，但不以此為限。
第4圖繪示使用介電外殼來製造具有加強之可靠性的半導體元件100之第三步驟400。第4圖另顯示助焊材料(fluxing material)410分配至半導體元件100的永久性介電材料開口310內，或是模版印刷(stencil print)至永久性介電材料開口310上。此圖繪示助焊材料410分配到至少一永久性介電材料開口310內，或是模版印刷至永久性介電材料開口310上。
第5圖繪示使用介電外殼來製造具有加強之可靠性的半導體元件100之第四步驟500。特別地，第5圖另顯示不含助焊劑(flux)之焊料球510放置在助焊材料410的頂表面上。在此步驟中，不含助焊劑之焊料球510係落至或施加至已分配在半導體元件100之永久性介電材料開口310內的助焊材料410上。在替代實施例中，除了使用焊料球510之外(或是取代使用焊料球510)，係使用焊膏(solder paste)。
在替代實施例中，所述方法及/或元件採用含助焊劑之焊料球510。在這些實施例中，不需使用助焊材料410。故對這些實施例來說，含助焊劑之焊料球510直接分配至半導體元件100的永久性介電材料開口310內
將焊料球510施加至半導體元件100後，加熱半導體元件100達適於焊料球510之回流的回流溫度。回流製程期間，焊料510填充並符合於永久性介電開口310的側壁而形成保護性封接(protective seal)520以抵擋腐蝕劑。
第6圖為掃描式電子顯微鏡(SEM)圖像，其顯示圖案化後的光致成像型永久性介電層210。在此圖中，所示之光致成像型永久性介電材料210係經圖案化而於凸塊下冶金(UBM)140上方形成開口310。第7圖為SEM圖像，其顯示回流後之半導體元件100的最終結構。特別地，此圖繪示具有圖案化之光致成像型永久性介電層210的半導體元件100，該光致成像型永久性介電層210具有位於凸塊下冶金(UBM)140上方的開口。又，在此圖中，所示之焊料球510係施加至半導體元件100的凸塊下冶金(UBM)140。外殼結構的高度可以改變，並可以如凸塊直徑的75%一般高。
在一或多個實施例中，所揭示之半導體元件增設較厚的光致成像型介電材料層可建立較高的有效聚合物層，而容許連續緩衝層抵抗熱膨脹應力和機械衝擊，並避免遭到腐蝕元素破壞。當採行所述方法時，可輕易控制永久性介電材料層的厚度及依應用需求改變。圍繞焊料球的有效外殼高度很重要，因應用晶圓之底部填充的先前技術顯示，隨著底部填充高度與凸塊比率(underfill height-to-bump ratio)提高，熱循環壽命亦隨之增加。先前技術亦發現，隨著底部填充高度與凸塊比率提高，機械衝擊抗力也隨之增強。
在一些實施例中，調整光致成像型永久性介電層的高度以符合特殊設計的需求。特別地，光致成像型永久性介電層的高度可依設計所採取的焊料球種類和尺寸而調 整。在至少一實施例中，進行回流製程而形成連續保護再鈍化層之後，焊料(或部分其他類型的助焊底部填充材料)係完全填滿或密封住安置焊料球的開口。此晶圓級晶片尺寸封裝(WLCSP)外殼方式具備極多功能，且可用於標準濺射金屬和電鍍銅(Cu)應用、以及無電電鍍鎳(Ni)/金(Au)與無電電鍍Ni/鈀(Pd)/Au凸塊下冶金(UBM)選擇中。由於所述方法為晶圓級應用，故其比目前晶粒級底部填充法更具吸引力。
在其他實施例中，打開光致成像型永久性介電材料層，並分配聚合物環圈(collar)助焊劑至該開口內。此法將製造一改質之毯覆層。就這些替代實施例而言，毯覆塗層材料不必然為光致成像型。但毯覆塗層材料必須可當作助焊劑，且能接合焊料與凸塊下冶金(UBM)。
雖然本發明已以特定實施例和方法揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。許多其他實施例只有細節上的不同。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體元件
110‧‧‧基板層
120‧‧‧鈍化層
130‧‧‧I/O墊
140‧‧‧凸塊下冶金(UBM)
200、300、400、500‧‧‧步驟
210‧‧‧介電材料/塗層/層
310‧‧‧開口
410‧‧‧助焊材料
510‧‧‧焊料球/焊料
520‧‧‧封接
本發明之上述和其他特徵、態樣與優點在參閱詳細說明、後附申請專利範圍和所附圖式後，將變得更明顯易懂，其中：
第1圖為根據本發明至少一實施例之半導體元件的截面圖。
第2圖為根據本發明至少一實施例之類似第1圖的截面圖，除了其另顯示光致成像型永久性介電材料施加在半導體元件的頂表面。
第3圖為根據本發明至少一實施例之類似第2圖的截面圖，除了其另顯示光致成像型永久性介電材料層經圖案化而具有開口於單一特徵結構上。
第4圖為根據本發明至少一實施例之類似第3圖的截面圖，除了其另顯示助焊材料分配至永久性介電材料開口內或是模版印刷至永久性介電材料開口上第5圖為根據本發明至少一實施例之類似第4圖的截面圖，除了其另顯示焊料球放置在助焊材料的頂表面。
第6圖為根據本發明至少一實施例之掃描式電子顯微鏡(SEM)圖像，其顯示圖案化後的光致成像型永久性介電層。
第7圖為根據本發明至少一實施例之SEM圖像，其顯示回流後的最終半導體元件結構。
110‧‧‧基板層
120‧‧‧鈍化層
130‧‧‧I/O墊
140‧‧‧凸塊下冶金/UBM
210‧‧‧介電材料/塗層/層
500‧‧‧步驟
510‧‧‧焊料球/焊料
520‧‧‧封接

Claims (22)

  1. 一種用於使用介電外殼(encasement)的一半導體元件之方法，該半導體元件包含一基板層、覆蓋該基板層的一鈍化層、及複數個凸塊下冶金(under bump metallurgy；UBM)，該方法包含以下步驟：形成覆蓋該鈍化層的一光致成像型永久性(photoimageable permanent)介電層；圖案化該介電層，以在該介電層上形成複數個開口，各個開口放置在該等UBM之分別一者上，且各個開口具有一側壁；添加一助焊(fluxing)材料至該複數個開口之各者內；施加一焊料至該等開口之各者中的該助焊材料的一分別頂表面上；以及加熱該半導體元件達適於該焊料回流的一回流溫度，使得該焊料符合於各個開口的該分別側壁。
  2. 如申請專利範圍第1項所述之方法，其中形成該介電層之步驟包含以下步驟：使用一液態介電質。
  3. 如申請專利範圍第1項所述之方法，其中形成該介電層之步驟包含以下步驟：使用一乾膜疊層(laminate)。
  4. 如申請專利範圍第1項所述之方法，其中該介電層具 有1-300微米(μm)的一厚度。
  5. 如申請專利範圍第1項所述之方法，其中該半導體元件進一步包含一輸入/輸出墊，該輸入/輸出墊放置於該基板層上在該等UBM之一者的下方。
  6. 如申請專利範圍第1項所述之方法，其中在該圖案化步驟之後，該介電層以至少1微米覆蓋該等UBM之各者。
  7. 如申請專利範圍第1項所述之方法，其中該基板層包含矽(Si)。
  8. 如申請專利範圍第1項所述之方法，其中該焊料為至少一焊料球(solder sphere)。
  9. 如申請專利範圍第1項所述之方法，其中該焊料為一焊膏(solder paste)。
  10. 如申請專利範圍第1項所述之方法，其中在該加熱步驟之後，該焊料形成一保護性封接。
  11. 如申請專利範圍第1項所述之方法，其中在該加熱步驟之後，該焊料完全填滿該等開口之各者。
  12. 如申請專利範圍第1項所述之方法，其中該焊料係複數個焊料球，且在該加熱步驟之後，各個焊料球之一外表面向外橫向延伸超過其分別開口的一邊緣。
  13. 如申請專利範圍第1項所述之方法，其中該焊料不含助焊劑。
  14. 如申請專利範圍第1項所述之方法，其中該添加助焊材料之步驟包含以下步驟：分配或是模版印刷(stencil print)該助焊材料。
  15. 如申請專利範圍第1項所述之方法，其中該複數個UBM的各個UBM在該鈍化層的一頂表面上延伸，且該加熱該半導體元件之步驟進一步造成該焊料完全覆蓋各個開口的該分別側壁。
  16. 一種用於使用介電外殼的一半導體元件之方法，該半導體元件包含一基板層、覆蓋該基板層的一鈍化層、及複數個凸塊下冶金(UBM)，該方法包含以下步驟：施加一光致成像型永久性介電材料層覆蓋該鈍化層；圖案化該光致成像型永久性介電材料層，以得到複數個開口，各個開口暴露一分別輸入/輸出墊的一部分；施加含有助焊劑之焊料至該複數個開口之各者內； 以及加熱該半導體元件達適於該焊料回流的一回流溫度，使得該焊料符合於該等開口之各者的一側壁。
  17. 如申請專利範圍第16項所述之方法，其中該光致成像型永久性介電材料層為一液態介電質。
  18. 如申請專利範圍第16項所述之方法，其中該光致成像型永久性介電材料層為一乾膜疊層。
  19. 如申請專利範圍第16項所述之方法，其中該光致成像型永久性介電材料層具有1-300微米的一厚度。
  20. 如申請專利範圍第16項所述之方法，其中在該加熱步驟之後，該焊料形成一保護性封接。
  21. 如申請專利範圍第16項所述之方法，其中該焊料係複數個焊料球，且在該加熱步驟之後，各個焊料球之一外表面向外橫向延伸超過其分別開口的一邊緣。
  22. 如申請專利範圍第16項所述之方法，其中該複數個UBM的各個UBM在該鈍化層的一頂表面上延伸，且該加熱該半導體元件之步驟進一步造成該焊料完全填充該等開口之各者。
TW098126770A 2008-08-07 2009-08-10 使用介電外殼以加強半導體元件之可靠性 TWI397980B (zh)

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