TWI395308B - Fabrication method of package substrate - Google Patents

Description

Method of manufacturing package substrate

The invention relates to a method for manufacturing a package substrate, in particular to a method for manufacturing a package substrate in which a circuit is buried in a substrate.

With the rapid development of the electronics industry, electronic products have gradually entered the trend of multi-functional, high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization for more active and passive components and line loading, the semiconductor package substrate has gradually evolved from a two-layer package substrate into a multi-layer package substrate ( Multi-layer board), which uses Interlayer connection to expand the layout area available on the semiconductor package substrate in a limited space, thereby cooperating with the high circuit density integrated circuit. The thickness of the package substrate is reduced to accommodate a greater number of lines and electronic components at the same substrate unit area.

In order to meet the computing needs of high-performance chips such as microprocessors, chipsets, graphics chips, and special application integrated circuits (ASICs), semiconductor package substrates with wires also need to improve their transfer of chip signals, improve bandwidth, and control impedance. Other features to accommodate the development of high I/O number packages. However, in order to meet the development direction of semiconductor packages, such as thinness, shortness, versatility, high speed, high line density, and high frequency, the package substrate has been developed toward fine lines and small apertures. The existing semiconductor package substrate process has been reduced from the conventional 100 micron line size to the current 30 micron or less, including line width and line spacing, which continue to face smaller lines. Precision is developed.

Therefore, in order to improve the wiring precision of the semiconductor package substrate, the industry has developed a build-up technology, that is, a multilayer dielectric layer is alternately stacked on the surface of a core circuit board by a circuit build-up technology. a circuit layer, and a conductive via is provided in the dielectric layer for electrically connecting the upper and lower layers; wherein the circuit build-up process is the key to affecting the circuit density of the semiconductor package substrate, according to the current technology, The industry mostly uses the semi-additive process (SAP) to make the line build-up, and the industry has developed a method of embedding the line in the demand for higher precision and fine lines.

1A to 1G, which are schematic diagrams of a conventional package substrate; as shown in FIG. 1A, a core board 10 is provided, at least one surface having a plurality of conductive traces 102 and an electrical connection pad 101; As shown in FIG. 1B, a first dielectric layer 11 is formed on the core board 10, the conductive traces 102, and the electrical connection pads 101; as shown in FIG. 1C, a plurality of slots are formed on the first dielectric layer 11. Forming a blind via 110 in the first dielectric layer of each of the trenches 111, correspondingly exposing the plurality of electrical connection pads 101; as shown in FIG. 1D, the first dielectric layer 11 is slotted A conductive layer 13 is formed on the sidewall of the 111, the hole wall of the blind via 110, and the electrical connection pad 101. As shown in FIG. 1E, a metal layer 14 is formed on the conductive layer 13, and the metal layer 14 is filled. a first conductive via 141 is formed in the blind via 110; as shown in FIG. 1F, the metal layer 14 is thinned to form a first wiring layer 142; as shown in FIG. 1G, the first dielectric layer is formed 11 and the first circuit layer 142 are formed with a build-up structure 16 including at least a second dielectric layer 160, a second circuit layer 162 disposed in the second dielectric layer 160, and a plurality of the second dielectric layer 160 and electrically connected to the first circuit layer 142 and the second a second conductive via 161 of the circuit layer 162, the outermost line of the build-up structure 16 has a plurality of electrical contact pads 163, and then a solder resist layer 17 is formed on the surface of the build-up structure 16, and the solder resist layer A plurality of solder mask openings 170 are formed in the 17 to correspondingly expose the respective electrical contact pads 163.

It can be seen from the above that in the conventional method for manufacturing a package substrate, a groove and a blind hole are formed directly on the dielectric layer, and volatile matter generated in the process is easily splashed and remains on the surface of the dielectric layer, which is difficult to remove; and when the conductive layer is removed It is easy to have palladium (Pd remains on the dielectric layer, and special palladium treatment is required to prevent the palladium from causing copper migration to cause short circuit; in addition, the dielectric layer is susceptible to surface scratch damage during substrate manufacturing.

Therefore, in view of the above problems, it has become a problem to be solved at present to avoid the problem that the surface of the conventional dielectric layer is likely to remain volatile or palladium, and the surface of the dielectric layer is easily damaged.

In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a method for fabricating a package substrate, so as to avoid easy residual volatiles or conductive layers on the surface of the dielectric layer of the prior art, and to avoid damage to the surface of the dielectric layer. problem.

To achieve the above object, the present invention provides a method for manufacturing a package substrate, comprising: providing a core board having at least one surface having a plurality of conductive traces and electrical connection pads; and the core board, the conductive traces, and the electrical connection pads form a first dielectric layer; a release layer is formed on the first dielectric layer; a plurality of patterned opening regions are formed on the release layer; and formed on the first dielectric layer corresponding to each of the patterned opening regions Slotting, and forming a plurality of blind holes in a portion of the slots to respectively expose the electrical connection pads; forming a first circuit layer in each of the slots, and forming a first conductive layer in the blind holes a blind hole electrically connecting each of the electrical connection pads and the first circuit layer; and removing the release layer.

According to the above method for manufacturing a package substrate, the method for manufacturing the first circuit layer comprises: exposing the release layer, the patterned opening region and the corresponding grooved surface, the hole wall of the blind hole, and the blind hole; a conductive layer is formed on the electrical connection pad; a metal layer is formed on the conductive layer, and the metal layer is filled in each of the slots and the blind holes; and a thinning process is performed to remove the formed on the release layer a metal layer to form the first conductive blind via in the blind via, and the first trace layer is formed in the trench.

According to the above method for manufacturing a package substrate, a build-up structure is formed on the first dielectric layer and the first circuit layer, and the build-up structure includes at least one second dielectric layer disposed on the second dielectric a second circuit layer on the layer, and a plurality of second conductive blind holes disposed in the second dielectric layer and electrically connected to the first and second circuit layers, and an outermost second line of the build-up structure The layer has a plurality of electrical contact pads, and a solder resist layer is formed on the outermost surface of the buildup structure, and the solder resist layer is formed with a plurality of solder mask openings to correspondingly expose the respective electrical contact pads.

According to the above method, wherein the release layer is made of a metal material and formed by physical deposition or chemical deposition, and the release layer is removed by chemical etching; or the release layer is a polymer film. And to fit or The coating method is formed, and the release layer is removed by physical peeling.

According to the above, the patterning opening area and the groove forming method are laser ablation; the blind hole is manufactured by laser burning.

The invention discloses a method for fabricating another package substrate, comprising: providing a core plate; forming a first dielectric layer on the core plate; forming a release layer on the first dielectric layer; forming on the release layer a plurality of patterned opening regions; forming a groove on the first dielectric layer corresponding to each of the patterned opening regions; forming a first circuit layer in each of the grooves, having a plurality of conductive traces and electrical connections a mat; and removing the release layer.

According to the above method for manufacturing a package substrate, the first circuit layer is formed by: forming a conductive layer on the release layer, the patterned opening region and the corresponding grooved surface; forming on the conductive layer a metal layer is filled, and the metal layer is filled in each of the grooves; and a thinning process is performed to remove the metal layer formed on the release layer, thereby forming the first wiring layer in the groove.

According to the above method, a build-up structure is formed on the first dielectric layer and the first circuit layer, and includes at least a second dielectric layer, a second circuit layer disposed on the second dielectric layer, And a plurality of second conductive blind vias disposed in the second dielectric layer and electrically connected to the electrical connection pads and the second circuit layer, and the outermost second circuit layer of the buildup structure has a plurality of electrical contact pads And a solder resist layer is formed on the outermost surface of the build-up structure, and the solder resist layer has a plurality of solder mask openings to correspondingly expose the electrical contact pads.

According to the above method, the release layer is made of metal, and is formed by physical deposition or chemical deposition, and the method of removing the release layer is made. Etching; or the release layer is a polymer film, and is formed by lamination or coating, and the release layer is removed by physical tearing.

According to the above, the patterning opening area and the groove forming method are laser burning.

Compared with the prior art, the package substrate of the present invention is mainly formed by forming a release layer on the dielectric layer, and removing the release layer after forming the circuit layer on the dielectric layer. The problem that the surface of the dielectric layer of the prior art is likely to remain volatile or palladium is avoided, and the surface of the dielectric layer is easily damaged.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

[First Embodiment]

Referring to Figures 2A through 2H, a method of fabricating the first embodiment of the package substrate of the present invention is provided.

As shown in FIG. 2A, a core board 20 is provided, at least one surface having a plurality of conductive traces 202 and electrical connection pads 201, and the core board 20 may have conductive vias connecting the two corresponding surface conductive traces 202 (Fig. Not shown).

As shown in FIG. 2B, a first dielectric layer 21 is formed on the core board 20, the conductive traces 202, and the electrical connection pads 201.

As shown in FIG. 2C, a release layer 22 is formed on the first dielectric layer 21.

As shown in FIG. 2D, a plurality of patterns are formed on the release layer 22. a plurality of blind holes 211 are formed in the first dielectric layer 21 corresponding to each of the patterned opening regions 220, and a plurality of blind holes 210 are formed in the plurality of the openings 211 to correspondingly expose the electrical regions. In the embodiment, the patterning opening area 220 and the opening 211 are formed by laser burning, and the blind hole 210 is made by laser burning.

As shown in FIG. 2E, the surface of the release layer 22, the patterned opening region 220 and the corresponding slot 211, the hole wall of the blind hole 210, and the electrical connection pad 201 exposed by the blind hole 210 are formed. Conductive layer 23.

As shown in FIG. 2F, a metal layer 24 is formed on the conductive layer 23, and the metal layer 24 is formed in each of the slits 211 and the blind holes 210.

As shown in FIG. 2G, a thinning process is performed to remove the metal layer 24 formed on the release layer 22, thereby forming the first conductive via 241 in the blind via 210, and in the trench 211 Forming the first circuit layer 242 and removing the release layer 22; the release layer 22 is, for example, a metal material, and is formed by physical deposition or chemical deposition, and the release layer 22 is removed. Chemically etched; the release layer 22 is, for example, a polymeric film, and is formed by lamination or coating, and the release layer 22 is removed by physical tearing.

As shown in FIG. 2H, a build-up structure 27 is formed on the first dielectric layer 21 and the first circuit layer 242. The build-up structure 27 includes at least one second dielectric layer 270 disposed on the second a second circuit layer 272 in the dielectric layer 270, and a plurality of second conductive vias 271 disposed in the second dielectric layer 270 and electrically connected to the first circuit layer 242 and the second circuit layer 272. The outermost second circuit layer 272 of the layer structure 27 has a plurality of electrical contacts The pad 273 is further formed with a solder resist layer 28 on the outermost surface of the build-up structure 27, and the solder resist layer 28 is formed with a plurality of solder resist openings 280 to correspondingly expose the respective electrical contact pads 273.

[Second embodiment]

Referring to Figures 3A through 3H, there is provided a method of fabricating a second embodiment of the package substrate of the present invention.

As shown in FIG. 3A, a core board 20 is provided.

As shown in FIG. 3B, a first dielectric layer 21 is formed on the core board 20.

As shown in FIG. 3C, a release layer 22 is formed on the first dielectric layer 21.

As shown in FIG. 3D, a plurality of patterned opening regions 220 are formed on the release layer 22, and a slit 211 is formed on the first dielectric layer 21 corresponding to each of the patterned opening regions 220. The method for fabricating the patterned opening region 220 and the slit 211 is laser ablation.

As shown in FIG. 3E, a conductive layer 23 is formed on the surface of the release layer 22, the patterned opening region 220, and the corresponding groove 211.

As shown in FIG. 3F, a metal layer 24 is formed on the conductive layer 23, and the metal layer 24 is filled in each of the slits 211.

As shown in FIG. 3G, a thinning process is performed to remove the metal layer 24 formed on the release layer 22, thereby forming the first wiring layer 242 in the trench 211, having a plurality of conductive traces 242a and The pad 242b is electrically connected and the release layer 22 is removed.

As shown in FIG. 3H, the first dielectric layer 21 and the first circuit layer A build-up structure 27 is formed on the 242, the build-up structure 27 includes at least a second dielectric layer 270, a second circuit layer 272 disposed in the second dielectric layer 270, and a plurality of second dielectric layers The electrical layer 270 is electrically connected to the electrical connection pad 242b of the first circuit layer 242 and the second conductive via 271 of the second circuit layer 272, and the outermost second circuit layer 272 of the buildup structure 27 has a plurality of The electrical contact pad 273 is further provided with a solder resist layer 28 on the outermost surface of the build-up structure 27, and the solder resist layer 28 is formed with a plurality of solder resist openings 280 to correspondingly expose the respective electrical contact pads 273. .

In the foregoing embodiment, conductive vias (not shown) penetrating through the core plate and the first dielectric layer 21 formed on the opposite surfaces thereof may be formed before the formation of the build-up structure 27 to connect the lines on both sides.

Therefore, the method for fabricating the package substrate of the present invention is mainly to form a release layer on the dielectric layer, and to remove the release layer after the formation of the circuit layer on the dielectric layer, so that conventional methods can be avoided. The surface of the technical intermediate layer is prone to residual volatiles or conductive layers, and the surface of the dielectric layer is easily damaged.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10,20‧‧‧ core board

101,201‧‧‧Electrical connection pads

102,202‧‧‧ conductive traces

11,21‧‧‧First dielectric layer

22‧‧‧ release layer

110,210‧‧‧blind hole

111,211‧‧‧ slotting

13,23‧‧‧ Conductive layer

14,24‧‧‧metal layer

141,241‧‧‧First conductive blind hole

142, 242‧‧‧ first line layer

16,27‧‧‧Additional structure

160, 270‧‧‧ second dielectric layer

162,272‧‧‧second circuit layer

161,271‧‧‧Second conductive blind hole

163,273‧‧‧Electrical contact pads

17,28‧‧‧ solder mask

170,280‧‧‧ solder mask opening

220‧‧‧ patterned open area

1A to 1G are schematic cross-sectional views showing a method of manufacturing a conventional package substrate; 2A to 2H are schematic cross-sectional views showing the manufacturing method of the first embodiment of the package substrate of the present invention; and Figs. 3A to 3H are schematic cross-sectional views showing the manufacturing method of the second embodiment of the package substrate of the present invention.

201‧‧‧Electrical connection pads

202‧‧‧conductive traces

21‧‧‧First dielectric layer

210‧‧‧Blind hole

211‧‧‧ slotting

23‧‧‧ Conductive layer

241‧‧‧First conductive blind hole

242‧‧‧First line layer

Claims (19)

A method for manufacturing a package substrate, comprising: providing a core plate having at least one surface having a plurality of conductive traces and an electrical connection pad; forming a first dielectric layer on the core plate, the conductive traces and the electrical connection pads; Forming a release layer on the first dielectric layer; forming a plurality of patterned opening regions on the release layer; forming a groove on the first dielectric layer corresponding to each of the patterned opening regions, and forming a portion Forming a plurality of blind holes in the slot to respectively expose the electrical connection pads; forming a first circuit layer in each of the slots, and forming a first conductive blind hole in the blind hole to electrically connect To each of the electrical connection pads and the first circuit layer; and removing the release layer. The method for manufacturing a package substrate according to claim 1, wherein the release layer is made of a metal material and formed by physical deposition or chemical deposition. The method for manufacturing a package substrate according to claim 2, wherein the method of removing the release layer is chemical etching. The method of manufacturing a package substrate according to claim 1, wherein the release layer is a polymer film and is formed by lamination or coating. For example, the method for manufacturing a package substrate according to item 4 of the patent application, wherein The way of removing the release layer is to physically tear off. The method for manufacturing a package substrate according to claim 1, wherein the patterning opening area and the groove forming method are laser burning. The method for manufacturing a package substrate according to claim 1, wherein the method for manufacturing the blind hole is laser ablation. The method for manufacturing a package substrate according to the first aspect of the invention, wherein the method for manufacturing the first circuit layer comprises: the release layer, the patterned opening region, the corresponding grooved surface, the hole wall of the blind hole, And forming a conductive layer on the electrical connection pad exposed by the blind hole; forming a metal layer on the conductive layer, and filling the metal layer in each of the groove and the blind hole; and performing a thinning process to remove the formed a metal layer on the release layer, thereby forming the first conductive blind via in the blind via, and forming the first trace layer in the trench. The method for manufacturing a package substrate according to claim 1, further comprising forming a build-up structure on the first dielectric layer and the first circuit layer, the build-up structure comprising at least one second dielectric layer disposed on the a second circuit layer on the second dielectric layer, and a plurality of second conductive blind holes disposed in the second dielectric layer and electrically connected to the first and second circuit layers, and the outermost layer of the build-up structure The second circuit layer has a plurality of electrical contact pads. The method for manufacturing a package substrate according to claim 9 is characterized in that a solder resist layer is formed on the outermost surface of the buildup structure, and the solder resist layer is formed with a plurality of solder resist openings to correspondingly expose the electrical properties. Contact pad. A method for manufacturing a package substrate, comprising: providing a core plate; forming a first dielectric layer on the core plate; forming a release layer on the first dielectric layer; forming a plurality of patterns on the release layer An opening region; forming a slot on the first dielectric layer corresponding to each of the patterned opening regions; forming a first circuit layer in each of the slots, having a plurality of conductive traces and electrical connection pads; In addition to the release layer. The method for manufacturing a package substrate according to claim 11, wherein the release layer is made of a metal material and formed by physical deposition or chemical deposition. The method of manufacturing a package substrate according to claim 12, wherein the release layer is removed by chemical etching. The method of manufacturing a package substrate according to claim 11, wherein the release layer is a polymer film and is formed by lamination or coating. The method of manufacturing a package substrate according to claim 14, wherein the release layer is physically peeled off. The method for manufacturing a package substrate according to claim 11, wherein the patterning opening area and the groove forming method are laser burning. The method for manufacturing a package substrate according to claim 11 , wherein the method for manufacturing the first circuit layer comprises: Forming a conductive layer on the release layer, the patterned opening region, and the corresponding grooved surface; forming a metal layer on the conductive layer, and filling the metal layer in each of the grooves; and performing a thinning process The metal layer formed on the release layer is removed to form the first wiring layer in the trench. The method for manufacturing a package substrate according to claim 11, further comprising forming a build-up structure on the first dielectric layer and the first circuit layer, the build-up structure comprising at least one second dielectric layer disposed on the a second circuit layer on the second dielectric layer, and a plurality of second conductive blind holes disposed in the second dielectric layer and electrically connected to the electrical connection pad and the second circuit layer, and the buildup structure is the most The outer second circuit layer has a plurality of electrical contact pads. The method for manufacturing a package substrate according to claim 18, further comprising forming a solder resist layer on an outermost surface of the buildup structure, and the solder resist layer has a plurality of solder mask opening to correspondingly expose the electrical contact pad .