TWI393352B - Digital/analog converter and driving apparatus using the same and image data converting method thereof - Google Patents

Description

Digital analog converter, using the same and its image data conversion method

The present invention relates to a digital analog converter, and more particularly to a digital analog converter for use in a light emitting diode display.

Light Emitting Diode (LED) is small, power-saving and durable, and as the process matures, the price drops. Recently, products using light-emitting diodes as light sources are becoming more and more popular. In addition, the light-emitting diode has a low operating voltage (only 1.5-3V), can actively emit light and has a certain brightness, and the brightness can be adjusted by voltage or current, and has the characteristics of impact resistance, vibration resistance and long life (100,000 hours). Light-emitting diodes are widely used in a variety of terminal equipment, from automotive headlights, traffic lights, text displays, billboards and large-screen video displays, to general and architectural lighting and LCD backlighting.

The driving circuit of the light-emitting diode usually uses the pulse width modulation (PWM) signal to adjust the brightness of the light-emitting diode, which is also a gray scale value. The driving circuit determines the on-time of the light-emitting diode according to the duty cycle in the PWM signal, thereby determining the grayscale value of the display. However, due to the problem of insufficient image update rate in the conventional PWM signal, this may cause image flicker. In order to overcome the phenomenon of flickering, the prior art disperses the duty cycle of the grayscale of the image to reduce the harmonic signal energy in the visible range of the human eye, but the excessive dispersion will cause image signal distortion.

The invention provides an adaptive control digital analog converter and a driving device thereof, which can be applied to a driving circuit of a light emitting diode display, and the digital analog converter divides the duty cycle according to the gray scale of the image data into Different sub-work cycles to increase the image update rate while avoiding the problem of distortion loss.

The invention provides a method for converting image data, which divides the working period into different sub-working periods according to the gray scale of the image data to provide an image update rate, and at the same time avoids the problem of distortion loss.

In view of the above, the present invention provides a digital analog converter and a driving device using the same, the driving device comprising a digital analog converter and a driving circuit for driving the LED display panel. The digital analog converter includes a gray-scale decision circuit and a pulse segmentation unit, wherein the gray-scale decision circuit outputs a determination signal according to the value of the image data, and the determination signal is used to indicate that the value of the image data is located in a first numerical interval. Or a second numerical interval, wherein the value of the second numerical interval is greater than the value of the first numerical interval, and the value of the image data corresponds to a working period. The pulse segmentation unit is coupled to the grayscale decision circuit to receive the determination signal. When the value of the image data is in the first numerical interval, the pulse segmentation unit divides the work cycle corresponding to the image data into a maximum of N sub-work cycles. To generate a segmented pulse wave signal. When the value of the image data is in the second numerical interval, the pulse segmentation unit divides the working period corresponding to the image data into M sub-working periods at most to generate the segmented pulse wave signal, where M and N are positive integers and M Greater than N.

In an embodiment of the invention, the sum of the N sub-working cycles or the M sub-working cycles is substantially equal to the duty cycle.

In an embodiment of the invention, the pulse segmentation unit includes a sequence counter, an output adjustment circuit, and a digital comparator. The sequence counter is used to output a reference signal, and the number of bits of the reference signal is the same as the number of bits of the image data. The output adjustment circuit is coupled to the sequence counter and the gray scale decision circuit, and adjusts the bit sequence of the reference signal according to the determination signal to generate a segment reference signal. The digital comparator is coupled to the output adjustment circuit for comparing the segment reference signal and the image data to generate a segmented pulse wave signal. Wherein, when the value of the image data is in the first numerical interval, the segment reference signal corresponds to a first bit sequence. When the value of the image data is in the second numerical interval, the segment reference signal corresponds to a second bit sequence.

The output adjustment circuit includes a plurality of selection circuits coupled to the reference signals output by the gray scale decision circuit and the sequence counter. The selection units adjust the bit order of the reference signals according to the determination signal to generate a segment reference signal. The first input end of each of the selection circuits corresponds to the first bit order, and the second input end of each of the selection circuits corresponds to the second bit order.

From another point of view, the present invention provides a method for converting image data, which is suitable for a driving device of a display. The conversion method includes the following steps: First, a judgment signal is output according to the value of an image data, and the determination signal is used to represent The value of the image data is located in a first value interval or a second value interval, wherein the value of the second value interval is greater than the value of the first value interval, and the value of the image data corresponds to a duty cycle. When the value of the image data is in the first numerical interval, the working period corresponding to the image data is separated into N sub-working periods at most to generate a segmented pulse wave signal; when the value of the image data is in the second numerical interval, the image is imaged The working period corresponding to the data is divided into M sub-working periods at most to generate a segmented pulse wave signal, where M and N are positive integers and M is greater than N. The sum of the N sub-work cycles or the M sub-work cycles is substantially equal to the work cycle.

Based on the above, the present invention proposes an adaptively controlled digital analog converter that can use different bit order reference signals for comparison based on the value of the image data (grayscale) to produce a different number of sub-periods. In the case of high grayscale, the duty cycle is divided into a relatively large number of sub-work cycles to increase the update rate of the picture. At low gray levels, the duty cycle is divided into a relatively small number of sub-work cycles to avoid Waveform distortion.

The above described features and advantages of the present invention will be more apparent from the following description.

First embodiment

Please refer to FIG. 1. FIG. 1 is a functional block diagram of a driving device of a display according to an embodiment of the present invention. The display device 100 includes a driving device 100 and a display panel 150. The driving device 100 is coupled to the display panel 150 to drive the display panel 150 according to the image data ID. The display panel 150 is, for example, a display composed of light emitting diode elements. The driving device 100 includes a digital analog converter 105 and a driving circuit 140, wherein the digital analog converter 105 further includes a pulse segmentation unit 120 and a grayscale decision circuit 130. The pulse segmentation unit 120 includes a sequence counter 122, an output adjustment circuit 124, and a digital comparator 126. The grayscale decision circuit 130 and the sequence counter 122 are coupled to the output adjustment circuit 124. The output of the output adjustment circuit 124 is coupled to the digital comparator 126. The output of the digital comparator 126 is coupled to the drive circuit 140.

The gray scale decision circuit 130 receives the image data ID, and outputs a judgment signal SET according to the value of the image data ID, and the judgment signal SET is used to indicate the numerical interval in which the value of the image data ID is located. Taking two numerical intervals as an example, the gray-scale decision circuit 130 determines that the image data ID is located in the first numerical interval with a small gray scale according to the gray scale of the image (for example, an 8-bit gray scale, for example, 0) ~127) or a second numerical interval with a higher grayscale (taking an 8-bit grayscale as an example, for example, 128~255), and then outputting a judgment signal SET. The determination signal SET can be used to indicate that the image data ID is located in the first value interval or the second value interval, and the value of the second value interval is greater than the value in the first value interval. The image data ID is a digital signal (for example, 8-bit image data), and the value corresponds to one duty cycle of a pulse width adjustment signal, and can also be regarded as gray scale.

The pulse segmentation unit 120 divides the work cycle corresponding to the image data ID into multiple sub-work cycles according to the determination signal SET, and the sum of the sub-work cycles is equal to the work cycle corresponding to the image data ID, that is, the overall work. The period is unchanged. The pulse segmentation unit 120 spreads the sub-work cycles at different locations throughout the signal period to produce a segmented pulse signal PDM. Taking the above two numerical intervals as an example, when the value of the image data ID is located in the first numerical interval, the pulse segmentation unit divides the working period corresponding to the image data ID into N sub-working cycles at most to generate the segmented pulse wave signal. PDM. When the value of the image data ID is located in the second numerical interval, the pulse segmentation unit 120 divides the duty cycle corresponding to the image data ID into M sub-working cycles to generate a segmented pulse wave signal, where M and N are positive integers. And M is greater than N.

In other words, the pulse segmentation unit 120 adjusts the number of sub-working cycles according to the grayscale corresponding to the image data ID. When the gray level corresponding to the image data ID is high, the duty cycle is replaced by more sub-work cycles. When the gray level corresponding to the image data ID is low, the duty cycle is replaced by a small sub-work cycle. Thereby, in the image with lower gray scale, the problem of signal distortion loss caused by the waveform being divided into excessive sub-work cycles can be reduced; in the image with higher gray scale, more children can be used Work cycle to increase the image update rate to avoid flickering.

Next, the internal architecture of the pulse segmentation unit 120 is further explained. The sequence counter 122 outputs a reference signal BS in numerical order, and the number of bits of the reference signal BS is the same as the number of bits of the image data ID. The sequence counter 122 can sequentially adjust the reference signal BS from a low value to a high value or sequentially adjust the reference signal BS from a high value to a low value. In the present embodiment, the sequence counter 122 sequentially adjusts the reference signal BS from a low value to a high value for use by the output adjustment circuit 124. In the conventional technique, the digital comparator 126 directly compares the image data ID with the reference signal BS to generate a pulse width modulation signal. In this embodiment, in order to divide the duty cycle into multiple sub-working periods, the reference signal BS first adjusts the sequence of numerical changes of the reference signal BS via the output adjustment circuit 124 to generate a segment reference signal DBS, and then supplies the digital signal to the digital signal. The comparator 126 is used. In this embodiment, the output adjustment circuit 124 can adjust the bit configuration manner of the reference signal BS according to the determination signal SET (for example, swapping the second bit and the third bit) to output the segment reference signal DBS having different bit order. .

In this embodiment, when the value of the image data ID is in the first numerical interval, the segment reference signal DBS corresponds to the first bit sequence, and when the value of the image data ID is in the second numerical interval, the segment reference signal DBS Corresponds to the second bit order. After comparison by the digital comparator 126, the segment reference signals DBS of different bit orders can differentiate the duty cycle of the image material ID into a different number of sub-work cycles to generate segmented pulse wave signals PDM having different update rates. Therefore, the segmented pulse wave signal PDM can also be referred to as an Adaptive Pulse Density Modulation signal, and the pulse wave density of the sub-period can be adjusted via the bit order of the segment reference signal DBS.

Taking a four-bit image data ID and a four-bit reference signal BS as an example, please refer to FIG. 2 at the same time, and FIG. 2 illustrates a four-bit output adjustment circuit according to the first embodiment of the present invention. The output adjustment circuit 224 includes selection circuits 210, 220, 230, 240 having two inputs ("1" and "2") for receiving respective bits of the reference signal BS, The selection terminal "3" is coupled to the determination signal SET, and the input terminal ("1" or "2") can be switched as an output according to the determination signal SET. The selection circuits 210, 220, 230, 240 are, for example, multiplexers. The bit order of the reference signal BS is represented by C[3]C[2]C[1]C[0], where C[3] is the Most Significant Bits (MSB) and C[0] is the lowest. Least Significant Bits (LSB). The bit sequence of the reference signal BS outputted by the sequence counter 122 is as shown in FIG. 3(a), and FIG. 3(a) to FIG. 3(c) show the reference signal BS and the segment reference signal according to the first embodiment of the present invention. The bit order of DBS. The sequence counter 122 sequentially increments the value of its reference signal BS, as shown in the top-down order of FIG. 3(a), wherein the "decimal" field indicates the value of the reference signal BS, and the "binary" field is The binary mode represents the reference signal BS.

If the output adjustment circuit 124 directly outputs the reference signal BS to the digital comparator 126, the segmented pulse wave signal PDM output by the digital comparator 126 after comparing the reference signal BS with the video signal ID will have only a single duty cycle. Taking the value of the image signal ID equal to 8 as an example, the waveform of the segmented pulse wave signal PDM is shown in FIG. 4( a ), and FIGS. 4( a ) to 4 ( c ) illustrate the segmentation of the first embodiment of the present invention. Waveform of pulse wave signal PDM. In FIG. 4(a), the segmented pulse wave signal PDM is a single-stage pulse wave modulation signal having a half cycle duty cycle, which is the same as a general pulse wave modulation signal waveform, which corresponds to an image. The value of the signal ID is equal to the condition of 8.

In this embodiment, the input terminal "1" of the selection circuit 210, 220, 230, 240 is coupled to the bit sequentially in the order of C[1]C[2]C[3]C[0]. The first bit sequence in the embodiment; the input terminal "2" is coupled to the bit sequentially in the order of C[0]C[2]C[1]C[3], which is the second in the embodiment. Bit order. The output sequence of the segment reference signal DBS having the first bit order is as shown in FIG. 3(b), and the numerical output order is 0, 1, 8, 9, 4, 5, 12, 13, 2, 3, 10 11, 11, 6, 14, 15 and binary representations are shown in Figure 3(b). The output sequence of the segment reference signal DBS having the second bit order is as shown in FIG. 3(c), and the numerical output order is 0, 8, 2, 10, 4, 12, 6, 14, 1, 9, 3 11, 11, 5, 13, 7, and 15, the representation of the binary is shown in Figure 3 (c). In the present embodiment, 0 to 8 are taken as the first numerical interval, and 9-15 is taken as the second numerical interval as an example. Therefore, when the value of the image data ID is 0-8, the selection circuits 210, 220, 230, 240 select the input terminal "1" as the output; when the value of the image data ID is 9-15, the selection circuits 210, 220 230, 240 will select the input "2" as the output.

Taking the value of the image data ID equal to 8 as an example, the selection circuit 210, 220, 230, 240 selects the input terminal "1" as the output. At this time, the waveform of the segment reference signal DBS received by the digital comparator 126 is as shown in FIG. As shown in (b), the segmented pulse wave signal PDM outputted is as shown in Fig. 4(b). In FIG. 4(b), the segmented pulse signal PDM has four sub-working periods 421 to 424, and the sum of the four sub-working periods 421 to 424 is equal to half a period, which is the duty cycle 410 in FIG. 4(a). equal. Therefore, the effect of gray scale of 8 can also be achieved, but the image update rate can be improved to avoid flickering.

Taking the value of the image data ID equal to 9 as an example, the selection circuit 210, 220, 230, 240 selects the input terminal "2" as the output. At this time, the waveform of the segment reference signal DBS received by the digital comparator 126 is as shown in FIG. As shown in (c), the segmented pulse wave signal PDM outputted is as shown in Fig. 4(c). In Figure 4(c), the segmented pulse signal PDM divides the duty cycle into 7 segments, resulting in 7 sub-periods 432~438. The sum of the 7 sub-periods 432~438 is 9/16 of the entire cycle ( 9/16), equal to the image data ID value equal to 9 corresponding work cycle. Therefore, the effect of gray scale of 9 can also be achieved, but the image update rate is further increased to avoid flickering.

As can be seen from the above, in this embodiment, the segment reference signal DBS of different bit order is selected according to the value of the image data ID to be compared with the image data ID. By using the segment reference signal DBS having different bit order, when the value of the image data ID is low, the work cycle is divided into a relatively small number of sub-work cycles using the segment reference signal DBS having the first bit order. . When the value of the image data ID is high, the work cycle is divided into a relatively large number of sub-work cycles using the segment reference signal DBS having the second bit order. The height and low judgment of the image data ID can be determined according to the design requirements. For example, when the image data ID is 4 bits, the first value interval can be set to 0 to 8, and the second value interval can be set to 9 to 15. When the image data ID is 8 bits, the first numerical interval may be set to 0 to 127, and the second numerical interval may be set to 128 to 255. The present invention does not limit the setting manner of the numerical interval, as long as the second numerical interval is The value is greater than the first value interval.

Then, according to the numerical interval in which the image data ID is located, the segment reference signal DBS of different bit order is used to compare with the image data ID. In such a way of distinguishing, when the brightness is low, it is possible to avoid the waveform distortion caused by the division into too many sub-periods, and the brightness is decreased. In the case of high brightness, the sub-work period of the plurality of numbers can be utilized to improve the update rate and avoid the picture. flicker.

The correspondence between the individual bit order and the numerical interval is determined according to the maximum number of sub-work cycles that can be distinguished by the bit order. Taking the first bit order and the second bit order as an example, as shown in FIG. 4(b) and FIG. 4(c), the first bit order is in the first numerical interval (0~8), and at most The duty cycle is divided into 4 sub-working cycles (ie, N is equal to 4), and the second bit sequence is in the second numerical interval (9~15), and the working cycle can be divided into up to 7 sub-working cycles (ie, M is equal to 7). . In addition, if the first numerical interval is adjusted to (0~7), the second numerical interval is adjusted to (8~15), and as shown in Fig. 4(c), when the image data ID is equal to 8, the segmentation reference is used. When the signal DBS is equal to 8, it will be converted to logic low, and then 8 separate sub-periods can be obtained, so M will be equal to 8. Therefore, in such numerical interval setting, the first bit order and the second bit order are still applicable, and a relatively large sub-period can be obtained for a numerical interval having a large value.

Since the sub-work cycle of the energy is occupied for most of the period during high brightness, this will cause the illusion that the waveform is not split, which is actually the effect of the sub-work cycles being connected to each other. Conversely, at low brightness, the work cycle of the image data ID cannot be divided into multiple sub-work cycles. For example, if the value of the image data ID is equal to 1, only a single sub-work cycle can be generated. Therefore, the number of sub-work cycles varies with the value of the image data ID, so the bit order is set by the maximum number that can be divided in the corresponding value interval. In addition, through the appropriate bit order setting, the sub-work cycle can be evenly distributed throughout the cycle, as shown in Fig. 4(b) and Fig. 4(c), which can further improve the picture quality and avoid the problem of flicker.

Furthermore, the order of the first bit order and the second bit order is not limited to the arrangement in FIG. 3(b) and FIG. 3(c), and the user may refer to different documents or design requirements and adopt different The order of the bits (ie the order in which the values are output). It should be noted that both the first bit order and the second bit order must include all values. For example, the 4-bit segment reference signal DBS needs to include values from 0 to 15, and the 8-bit segment reference. The signal DBS needs to include values from 0 to 255, and each value can only appear once in the same cycle. Then, according to the maximum number of divisions corresponding to the individual bit order, the corresponding numerical interval is determined. The order in which the number of divisions is smaller corresponds to the numerical interval in which the numerical value is smaller.

In addition, it should be noted that the segment reference signal DBS may be divided into more bit sequences according to the value of the image data ID, for example, three or six types, and the embodiment is not limited. The segment reference signal DBS having a different bit order can be generated by increasing the number of inputs of the selection circuits 210, 220, 230, 240. The selection circuits 210, 220, 230, 240 having three inputs are used in three sequences, and the selection circuits 210, 220, 230, 240 having six inputs are used in six sequences. Similarly, the number of numerical intervals is not limited to two, and can be set according to design requirements, and the embodiment is not limited. After the disclosure of the present invention, those skilled in the art should readily infer the implementation thereof, and will not be described herein.

Second embodiment

A method for converting image data can be summarized from FIG. 1 to FIG. 4 above, which is suitable for a driving device of a light-emitting diode display. Please refer to FIG. 5 for the digital analog conversion method. FIG. 5 is a flow chart showing a method for converting image data according to a second embodiment of the present invention. First, an image data is received (step S510), and the value of the image data corresponds to a duty cycle. Then, it is determined that the value of the image data is in the first value interval or the second value interval (step S520), wherein the value of the second value interval is greater than the value of the first value interval. When the value of the image data is in the first numerical interval, the working period corresponding to the image data is divided into N sub-working periods at most to generate a segmented pulse wave signal (step S530). When the value of the image data is in the second numerical interval, the working period corresponding to the image data is divided into M sub-working periods at most to generate a segmented pulse wave signal, where M and N are positive integers and M is greater than N. The sum of the N sub-work cycles or the M sub-work cycles is equal to the work cycle. For the remaining implementation details of the method, please refer to the description of the first embodiment above, and no further description is provided herein.

In summary, the present invention first detects the value of the image data, and then selects the reference signals of different numerical order according to the value of the image data for comparison to divide the duty cycle into different sub-working periods. Therefore, when the brightness is low, the work cycle is prevented from being excessively divided and distorted, and in the case of high brightness, the image update rate can be improved to avoid the problem of flickering of the screen.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Drive unit

101. . . monitor

105. . . Digital analog converter

120. . . Pulse segmentation unit

122. . . Sequence counter

124. . . Output adjustment circuit

126. . . Digital comparator

130. . . Order decision circuit

140. . . Drive circuit

150. . . Display panel

210, 220, 230, 240. . . Selection circuit

410. . . Working period

421~424, 432~438. . . Sub-work cycle

ID. . . video material

SET. . . Judgment signal

PDM. . . Segmented pulse signal

SET. . . Judgment signal

BS. . . Reference signal

DBS. . . Segmented reference signal

C[3]C[2]C[1]C[0]. . . Bit of reference signal BS

S510~S540. . . Flow chart step

1 is a functional block diagram of a driving device of a display according to an embodiment of the present invention.

2 is a diagram showing a four-bit output adjustment circuit of the first embodiment of the present invention.

3(a) to 3(c) illustrate the bit order of the reference signal BS and the segment reference signal DBS of the first embodiment of the present invention.

4(a) to 4(c) are diagrams showing waveforms of the segmented pulse wave signal PDM according to the first embodiment of the present invention.

FIG. 5 is a flow chart showing a method for converting image data according to a second embodiment of the present invention.

100. . . Drive unit

101. . . monitor

105. . . Digital analog converter

120. . . Pulse segmentation unit

122. . . Sequence counter

124. . . Output adjustment circuit

126. . . Digital comparator

130. . . Order decision circuit

140. . . Drive circuit

150. . . Display panel

ID. . . video material

SET. . . Judgment signal

PDM. . . Segmented pulse signal

SET. . . Judgment signal

BS. . . Reference signal

DBS. . . Segmented reference signal

Claims (14)

A digital analog converter is suitable for a driving device of a display. The digital analog converter comprises: a gray scale decision circuit, which outputs a judgment signal according to a value of an image data, wherein the judgment signal is used to indicate that the value of the image data is located a first value interval or a second value interval, wherein the value of the second value interval is greater than the value of the first value interval, the value of the image data corresponds to a duty cycle; and a pulse segmentation unit coupled The gray-scale decision circuit receives the determination signal, and when the value of the image data is located in the first numerical interval, the pulse segmentation unit divides the work cycle corresponding to the image data into a maximum of N sub-period cycles. Generating a segmented pulse wave signal. When the value of the image data is located in the second numerical interval, the pulse segmentation unit divides the work cycle corresponding to the image data into M sub-working cycles at most to generate the segment. Pulse signal, where M and N are positive integers and M is greater than N. The digital analog converter of claim 1, wherein the sum of the N sub-working cycles or the M sub-working cycles is substantially equal to the duty cycle. The digital analog converter of claim 1, wherein the pulse segmentation unit comprises: a sequence counter for outputting a reference signal, the number of bits of the reference signal and the number of bits of the image data. The output adjustment circuit is coupled to the sequence counter and the gray scale decision circuit, and adjusts a bit sequence of the reference signal according to the determination signal to generate a segment reference signal; and a digital comparator coupled to the An output adjustment circuit, configured to compare the segment reference signal and the image data to generate the segmented pulse wave signal; wherein, when the value of the image data is located in the first numerical interval, the segment reference signal corresponds to a first In a meta-order, when the value of the image data is in the second numerical interval, the segment reference signal corresponds to a second bit sequence. The digital analog converter of claim 3, wherein the output adjustment circuit comprises: a plurality of selection circuits coupled to the gray scale decision circuit and the reference signal output by the sequence counter, the selection units Adjusting a bit sequence of the reference signal according to the determining signal to generate the segment reference signal; wherein, a first input end of each of the selecting circuits corresponds to the first bit order, and one of the selecting circuits is a second input The end corresponds to the second bit order. The digital analog converter of claim 1, wherein the pulse segmentation unit adjusts a bit sequence of a reference signal according to the determination signal to generate a segment reference signal, the reference signal and the image data. The number of bits is the same, wherein when the value of the image data is in the first value interval, the segment reference signal corresponds to a first bit sequence, and when the value of the image data is in the second value interval, the The segmentation reference signal corresponds to a second bit sequence, and the pulse segmentation unit compares the segmentation reference signal with the image data to generate the segmented pulse wave signal. A driving device for a display, comprising: a digital analog converter, comprising: a gray scale decision circuit, outputting a determining signal according to a value of an image data, wherein the determining signal is used to indicate that the value of the image data is in a first numerical interval Or a second value interval, wherein the value of the second value interval is greater than the value of the first value interval, the value of the image data corresponds to a duty cycle; and a pulse segmentation unit coupled to the gray scale decision The circuit is configured to receive the determination signal. When the value of the image data is located in the first numerical interval, the pulse segmentation unit divides the working period corresponding to the image data into N sub-working periods at most to generate a segment pulse. a wave signal, when the value of the image data is located in the second numerical interval, the pulse segmentation unit divides the working period corresponding to the image data into M sub-working cycles at most to generate the segmented pulse wave signal, wherein M, N is a positive integer and M is greater than N; and a driving circuit coupled to the digital analog converter, driving a display panel according to the segmented pulse wave signal The driving device of claim 6, wherein the sum of the N sub-working periods or the M sub-working periods is substantially equal to the working period. The driving device of claim 6, wherein the display panel is a light emitting diode display panel. The driving device of claim 6, wherein the pulse segmentation unit comprises: a sequence counter for sequentially outputting a reference signal, the number of bits of the reference signal and the number of bits of the image data. The output adjustment circuit is coupled to the sequence counter and the gray scale decision circuit, and adjusts a bit sequence of the reference signal according to the determination signal to generate a segment reference signal; and a digital comparator coupled to the An output adjustment circuit, configured to compare the segment reference signal and the image data to generate the segmented pulse wave signal; wherein, when the value of the image data is located in the first numerical interval, the segment reference signal corresponds to a first In a meta-order, when the value of the image data is in the second numerical interval, the segment reference signal corresponds to a second bit sequence. The driving device of claim 9, wherein the output adjustment circuit comprises: a plurality of selection circuits coupled to the gray scale decision circuit and the reference signal output by the sequence counter, the selection units according to the Determining a signal to adjust a bit sequence of the reference signal to generate the segment reference signal; wherein, a first input end of each of the selection circuits corresponds to the first bit order, and a second input end of each of the selection circuits corresponds to In the second bit order. The driving device of claim 6, wherein the pulse segmentation unit adjusts a bit sequence of a reference signal according to the determination signal to generate a segment reference signal, the reference signal and a bit of the image data. The same number of elements, wherein when the value of the image data is in the first value interval, the segment reference signal corresponds to a first bit sequence, and when the value of the image data is in the second value interval, the segment The reference signal corresponds to a second bit sequence, and the pulse segmentation unit compares the segment reference signal with the image data to generate the segmented pulse wave signal. A method for converting image data, which is suitable for a driving device of a display, the conversion method: outputting a determining signal according to a value of an image data, wherein the determining signal is used to indicate that the value of the image data is in a first numerical interval or a first a numerical interval, wherein a value of the second numerical interval is greater than a value of the first numerical interval, the value of the image data corresponds to a duty cycle; and when the value of the image data is in the first numerical interval, the image is The working period corresponding to the data is divided into N sub-working periods at most to generate a segmented pulse wave signal. When the value of the image data is located in the second numerical interval, the working period corresponding to the image data is divided into a maximum of M sub-working cycles to generate the segmented pulse wave signal, where M, N are positive integers and M is greater than N. The method for converting image data according to claim 12, wherein the sum of the N sub-work cycles or the M sub-work cycles is substantially equal to the work cycle. The method for converting image data according to claim 12, further comprising: sequentially outputting a reference signal, the number of bits of the reference signal being the same as the number of bits of the image data; adjusting the reference according to the determining signal The bit sequence of the signal is used to generate a segment reference signal. When the value of the image data is located in the first value interval, the segment reference signal corresponds to a first bit sequence, and when the value of the image data is located in the first In the case of two numerical intervals, the segment reference signal corresponds to a second bit sequence; and the segment reference signal and the image data are compared to generate the segmented pulse wave signal.