TWI393246B - Electrostatic protection device - Google Patents

Abstract

An electrostatic protection device is connected between a power supply line and a ground line. The power supply line is used for providing a supply voltage. The electrostatic protection device includes a voltage dividing circuit, a reference voltage circuit, a comparison circuit, and a switching circuit. The voltage dividing circuit is used for sampling the supply voltage from the power supply line, so as to generate a sampling voltage. The reference voltage circuit is used for receiving the supply voltage from the power supply line, so as to generate a reference voltage. The comparison circuit is used for comparing the sampling voltage with the reference voltage, and outputting a first voltage level signal to the switching circuit if the sampling voltage is larger than the reference voltage. The switching circuit is turned on according to the first voltage level signal, then the power supply line is connected to the ground line. The comparison circuit also is used for outputting a second voltage level signal to the switching circuit if the sampling voltage is smaller than the reference voltage. The switching circuit is turned off according to the first voltage level signal, then the electrical connection between the power supply line and the ground line is cut off.

Description

Electrostatic protection device

The present invention relates to the field of integrated circuits, and in particular to an electrostatic protection device.

It is well known that the high voltage generated instantaneously by Electrostatic Discharge (ESD) can cause damage to the internal circuits of the integrated circuit. In order to avoid the damage caused by the static electricity, an electrostatic protection circuit is generally provided in the integrated circuit design. The electrostatic protection circuit includes a power line, a ground line, a switch unit and a detecting unit for connecting a power line for supplying a power supply voltage to the internal circuit, and the switch unit is connected between the power line and the ground. When there is static electricity on the power line, the detecting unit generates a control signal to the switch circuit to control the switch circuit to conduct, and the electrostatic voltage on the power line is absorbed to the ground line, thereby effectively preventing the electrostatic voltage from causing a voltage shock to the internal circuit.

However, due to electromagnetic interference or the like, a noise voltage having a voltage value larger than the supply voltage is generated on the power supply line. Generally, the noise voltage is relatively small with respect to the electrostatic voltage. For example, when the power supply voltage is 10V, the noise voltage generated on the power line usually does not exceed 20V, and the electrostatic voltage usually has hundreds of volts, thousands of volts, or even tens of thousands. volt. Since the above noise voltage may also trigger the detecting unit to generate a control signal, the switching circuit is turned on, causing the power line to be grounded, and the internal circuit of the integrated circuit cannot obtain the power supply voltage, thereby making the integrated circuit unable to be in the absence of static electricity. normal work.

In view of this, it is necessary to provide an electrostatic protection device that prevents static electricity and shields noise voltage.

An electrostatic protection device is connected between a power supply line for supplying a supply voltage and a ground. The electrostatic protection device comprises a voltage dividing circuit, a reference voltage circuit, a comparison circuit and a switching circuit, wherein the voltage dividing circuit is configured to divide a voltage supplied from the power line to generate a sampling voltage, and the reference voltage circuit is configured to receive the power a voltage supplied by the line to generate a reference voltage, the comparison circuit is configured to compare the sampling voltage with a reference voltage, and output a first level signal to the switching circuit when the sampling voltage is greater than the reference voltage, the switching circuit is according to the first The level signal is turned on to connect the power line to the ground line, and the comparison circuit outputs a second level signal to the switch circuit when the sampling voltage is less than the reference voltage, and the switch circuit is turned off according to the second level signal to cut off the power supply. Electrical connection between the line and the ground.

The electrostatic protection device is configured to provide a comparison circuit and a reference voltage circuit. When the sampling voltage is greater than the reference voltage, that is, when there is an electrostatic voltage on the power line, the comparison circuit controls the switch circuit to be connected to connect the power line to the ground line, thereby enabling the electrostatic voltage Absorbed by grounding. When there is a noise voltage on the power line, the reference voltage generated by the reference voltage circuit will be greater than the sampling voltage, and the comparison circuit controls the switch circuit to be turned off to cut off the electrical connection between the power line and the ground line, thereby realizing the noise. Shielding of voltage.

FIG. 1 is a functional block diagram of a static protection device 100 according to a preferred embodiment. The electrostatic protection device 100 includes a voltage dividing circuit 10, a reference voltage circuit 20, a comparison circuit 30, and a switching circuit 40. In the present embodiment, the electrostatic protection device 100 is applied to an integrated circuit.

Dividing circuit 10 for supplying power voltage V _DD of the power supply line V _DD supplied sampled to produce a sampled voltage, the voltage value of the sampled voltage with changes in the supply voltage V _DD varies.

A reference voltage circuit 20 for receiving supply voltage V _DD power supply line V _DD supplied to the reference voltage and generating a constant reference voltage. In the present embodiment, the reference voltage circuit 20 includes a resistor and a complex MOS field effect transistor. By adjusting the resistance of the resistor and the channel length and channel width of the MOS field effect transistor, the reference voltage generated by the reference voltage circuit 20 is preset to be larger than the sampling generated by the voltage divider circuit 10 for dividing the noise voltage. Voltage.

The comparison circuit 30 is configured to receive the reference voltage generated by the reference voltage circuit 20 for electrical operation. The comparison circuit 30 is further configured to receive the sampled voltage and the reference voltage and compare the sampled voltage with a reference voltage. When the sampling voltage is greater than the reference voltage, i.e., there is static electricity on the power line V _DD , the comparison circuit 30 generates a first level signal to the switching circuit 40. When the sampling voltage is less than or equal to the reference voltage, the comparison circuit 30 generates a second level signal to the switching circuit 40. In this embodiment, the first level signal is a high level voltage signal, and the second level signal is a low level voltage signal.

The switch circuit 40 is connected between the power line V _DD and the ground line V _SS for conducting according to the first level signal to absorb the electrostatic voltage present on the power line V _DD to the ground line V _SS . The switch circuit 40 is further configured to turn off according to the second level signal to cut off the electrical connection between the power line V _DD and the ground line V _SS . If there is a noise voltage on the power line V _DD , the switching circuit 40 is turned off because the reference voltage generated by the reference voltage circuit 20 is preset to be larger than the sampling voltage generated by the voltage dividing circuit 10 to divide the noise voltage. In the state, the power line V _{DD is} not grounded, and it can still supply the supply voltage V _DD , thus effectively avoiding the influence of the noise voltage on the circuit.

As shown in FIG. 2, it is a detailed circuit diagram of the electrostatic protection device 100. The voltage dividing circuit 10 includes a sampling voltage terminal V _Smp for outputting a sampling voltage, a first NMOS (Negative Channel Metal Oxide Semiconductor) field effect transistor 12, and a first PMOS (Positive Channel Metal Oxide Semiconductor) field effect transistor 14 . The second PMOS field effect transistor 15 and the third PMOS field effect transistor 16. The source of the first NMOS field effect transistor 12 is connected to the ground line V _SS , and the gate and the drain are connected in common to the sampling voltage terminal V _Smp . The drain of the first PMOS field effect transistor 14 is connected to the sampling voltage terminal V _Smp , the gate is connected to the ground line V _SS , and the source is connected to the drain of the second PMOS field effect transistor 15 . The gate of the second PMOS field effect transistor 15 is connected to the ground line V _SS , the source is respectively connected to the drain and the gate of the third PMOS field effect transistor 16 , and the source and the power source of the third PMOS field effect transistor 16 . Line V _{DD is} connected.

The reference voltage circuit 20 includes a second NMOS field effect transistor 22, a third NMOS field effect transistor 24, a fourth NMOS field effect transistor 25, a fifth NMOS field effect transistor 26, and a fourth PMOS field effect transistor 27. The fifth PMOS field effect transistor 28, the resistor R1, the reference voltage terminal V _B of the output reference voltage, and the reference voltage terminal V _{Ref of the} output reference voltage. The source of the second NMOS field effect transistor 22 is connected to the ground line V _SS via a resistor R1, and the gate is connected to the gate of the third NMOS field effect transistor 24 and the reference voltage terminal V _Ref , and the drain and the fourth NMOS are connected. The sources of the field effect transistor 25 are connected. The gate of the third NMOS field effect transistor 24 is connected to the reference voltage terminal V _Ref , the source is connected to the ground line V _SS , and the drain is connected to the source of the fifth NMOS field effect transistor 26 . The drain of the fourth NMOS field effect transistor 25 is connected to the drain of the fourth PMOS field effect transistor 27, and the gate is connected to the gate of the fifth NMOS field effect transistor 26. The gate of the fifth NMOS field effect transistor 26 is connected to the drain of the fifth PMOS field effect transistor 28, and the gate of the fourth PMOS field effect transistor 27 is connected to the drain thereof, the source and the power line. V _{DD is} connected. The gate of the fifth PMOS field effect transistor 28 is connected to the gate of the fourth PMOS field effect transistor 27 and the reference voltage terminal V _{B ,} respectively, and the source is connected to the power supply line V _DD .

The comparison circuit 30 includes a sixth NMOS field effect transistor 32, a seventh NMOS field effect transistor 34, an eighth NMOS field effect transistor 35, a sixth PMOS field effect transistor 36, a seventh PMOS field effect transistor 37, Eight PMOS field effect transistors 38 and a ninth PMOS field effect transistor 39. The source of the sixth NMOS field effect transistor 36 is connected to the ground line V _SS , and the gate is connected to the drain. The source of the seventh NMOS field effect transistor 34 is connected to the ground line V _SS , and the gate is connected to the gate of the sixth NMOS field effect transistor 32. The source of the eighth NMOS field effect transistor 35 is connected to the ground line V _SS , the gate is connected to the drain of the seventh NMOS field effect transistor 34 , and the drain is connected to the drain of the ninth PMOS field effect transistor 39 . . The gate of the sixth PMOS field effect transistor 36 is connected to the reference voltage terminal V _Ref , the drain is connected to the drain of the sixth NMOS field effect transistor 32 , and the source is connected to the source of the seventh PMOS field effect transistor 37 . . The gate of the seventh PMOS field effect transistor 37 is connected to the sampling voltage terminal V _Smp , and the drain is connected to the drain of the seventh PMOS field effect transistor 37 . The gate of the eighth PMOS field effect transistor 38 is connected to the reference voltage terminal V _B , the source is connected to the power supply line V _DD , and the drain is connected to the source of the sixth NMOS field effect transistor 36 . The gate of the ninth PMOS field effect transistor 39 is connected to the reference voltage terminal V _B , and the source is connected to the power supply line V _DD . The end of the ninth PMOS field effect transistor 39 connected to the drain of the eighth NMOS field effect transistor 35 is connected to the switching circuit 40.

Switching circuit 40 includes a tenth NMOS field effect transistor 42. The gate of the tenth NMOS field effect transistor 42 is connected between the drain of the eighth NMOS field effect transistor 35 and the drain of the ninth PMOS field effect transistor 39, and the drain of the NMOS field effect transistor 42 Connect the power line V _DD and the source to the ground wire V _SS .

The working principle of the electrostatic protection device 100 is as follows: for the voltage dividing circuit 10, the gate of the first NMOS field effect transistor 12 is connected to the drain, that is, V _GS = V _DS , V _DS (saturation) = V _GS -V _T =V _DS -V _T , since V _DS >V _DS (saturation)=V _DS -V _T , ensuring that the first NMOS field effect transistor 12 operates in a saturation region, thus the first NMOS field effect transistor 12 The drain current I _d = kW ₁ /2L ₁ * (V _GS1 - V _T ) ² = kW ₁ /2L ₁ * (V _DS1 - V _T ) ² , the sampling voltage V _Smp is:

Where V _T is the threshold voltage, k is the transconductance coefficient, and L ₁ and W ₁ are the channel length and the channel width of the first NMOS field effect transistor 12, respectively, and the above parameters are constant, and I _d is the drain current. In Equation 1-1, the sampling voltage V _Smp under the condition of λ = 0, where λ is the channel length adjustment coefficient.

Since the first NMOS field effect transistor 12, the first PMOS field effect transistor 14, the second PMOS field effect transistor 15, and the third PMOS field effect transistor 16 are connected in series, the first NMOS field effect transistor 12 The first PMOS field effect transistor 14, the second PMOS field effect transistor 15 and the third PMOS field effect transistor 16 have the same drain current, both of which are _Id .

The gate of the third PMOS field effect transistor 16 is connected to the drain to ensure that the third PMOS field effect transistor 16 operates in the saturation region. Under the condition of λ=0, the PMOS of the third PMOS field effect transistor 16 The pole current I _d is:

I _d = kW ₂ /2L ₂ *(V _GS2 -V _T ) ² = kW ₂ /2L ₂ *(V _DS2 -V _T ) ² 1-2

Wherein L ₂ and W ₂ are the channel length and the channel width of the third PMOS field effect transistor 16, respectively, and the formula 1-2 is substituted into the formula 1-1.

When there is a noise voltage on the power line V _DD that is greater than the supply voltage V _DD , the drain-source voltage V _{DS2 of the} third PMOS field effect transistor 16 increases, thereby causing the sampling voltage V _{Smp to} increase. Since the noise voltage V _Noise generated by the power line V _DD is generally not too large, it is assumed that V _Noise has a maximum value V _Nmax , and correspondingly the sampling voltage generated by the voltage dividing circuit 10 to divide the noise voltage V _Noise V _Smp will also reach its maximum value V _Smax .

When static electricity is present on the power line V _DD , the electrostatic voltage is large, and therefore the sampling voltage V _Smp generated by the voltage dividing circuit 10 to divide the electrostatic voltage is much larger than V _Smax .

In the reference voltage circuit 20, since the MOS field effect transistors 27 and 28 constitute a current mirror, the drain currents flowing through the MOS field effect transistors 27 and 28 are equal, and both are I ₂ . The MOS field effect transistors 22, 24 and the resistor R1 form a loop. The gate-source voltage V _GS5 of the MOS field effect transistor ₂₂ has the following relationship with the gate-source voltage V _GS6 of the MOS field effect transistor 24: V _GS6 =V _GS5 +I ₂ *R1, ie

Therefore, the drain current I ₂ = 2 / (K * R1 ² ) * (L ₆ / W _{6 -} L ₅ / W ₅ ), the reference voltage V _Ref is:

Wherein, V _T is a threshold voltage, k is a transconductance coefficient, L ₅ and W ₅ are respectively a channel length and a channel width of the MOS field effect transistor 22, and L ₆ and W ₆ are respectively MOS field effect transistors 24 The channel length and channel width are all constant. Therefore, the reference voltage V _Ref is a fixed voltage value that does not change with the change in the voltage V _DD supplied from the power supply line V _DD .

The resistance value of the resistor R1, the channel length L _{5 of the} MOS field effect transistor 22, the channel width W _{5 ,} and the channel length L _{6 of the} MOS field effect transistor 24 and the channel width W ₆ may be changed in advance. The adjustment of the reference voltage V _Ref is achieved such that the reference voltage V _{Ref is} greater than the maximum value V _{Smax of the} sampling voltage V _Smp , ie V _Ref >V _Smax . In addition, the reference voltage V _B generated by the reference voltage circuit 20 is a low level voltage.

For the comparison circuit 30, when the power supply line V _DD generates a noise voltage, since the sampling voltage V _{Smp is} smaller than the reference voltage V _Ref , that is, V _Ref >V _Smax , the seventh PMOS field effect transistor 37 is turned on, so that the eighth NMOS field The gate of the effect transistor 35 is a high level voltage, the eighth NMOS field effect transistor 35 is turned on, the gate of the NMOS field effect transistor 42 in the switching unit 40 is a low level voltage, and the NMOS field effect transistor 42 is turned off, thereby power supply The line V _{DD is} not grounded, it still provides the supply voltage V _DD , thus ensuring that the integrated circuit can operate normally without static electricity.

When the electrostatic voltage is present in the power line V _DD , since the electrostatic voltage is usually large, the sampling voltage V _{Smp is} greater than the reference voltage V _Ref , so the seventh PMOS field effect transistor 37 is _turned off, so that the eighth NMOS field effect transistor 35 The gate is grounded by the drain and source of the seventh NMOS field effect transistor 34, is a low level voltage, the eighth NMOS field effect transistor 35 is turned off, and the gate of the NMOS field effect transistor 42 in the switching unit 40 is borrowed. The drain and the source of the ninth PMOS field effect transistor are connected to the power supply line V _DD , the gate of the NMOS field effect transistor 42 is a high level voltage, the NMOS field effect transistor 42 is turned on, and the power line V _DD is grounded, the power source The electrostatic voltage present on line V _DD is absorbed by the ground. It can prevent damage to the integrated circuit caused by static electricity.

3 and 4 are circuit diagrams of the voltage dividing circuit 72 of the second preferred embodiment and the voltage dividing circuit 74 of the third preferred embodiment, respectively. The voltage dividing circuit 72 includes a first NMOS field effect transistor 12, a ninth NMOS field effect transistor 54, a second PMOS field effect transistor 15, a third PMOS field effect transistor 16, and a sampling voltage terminal V _Smp . The voltage dividing circuit 72 is different from the voltage dividing circuit 10 of FIG. 2 in that the voltage dividing circuit 72 replaces the first PMOS field effect transistor 14 in the voltage dividing circuit 10 with the ninth NMOS field effect transistor 54. The gate of the ninth NMOS field effect transistor 54 is connected to the power supply line V _DD , the source is connected to the drain of the first NMOS field effect transistor 12, and the drain is connected to the drain of the second PMOS field effect transistor 15 while sampling. The voltage terminal V _{Smp is} connected between the drain of the ninth NMOS field effect transistor 54 and the drain of the second PMOS field effect transistor 15.

The voltage dividing circuit 74 includes a first NMOS field effect transistor 12, a first PMOS field effect transistor 14, a second PMOS field effect transistor 15, a third PMOS field effect transistor 16, and a sampling voltage terminal V _Smp . The voltage dividing circuit 74 is different from the voltage dividing circuit 10 of FIG. 2 in that the sampling voltage terminal V _{Smp is} connected between the source of the second PMOS field effect transistor 15 and the drain of the third PMOS field effect transistor 16 . .

The voltage dividing circuits 72, 74 function the same as the voltage dividing circuit 10 of FIG. 2, and both generate a sampling voltage V _{Smp whose} voltage value changes with the change of the power supply voltage V _DD supplied from the power supply line V _DD . . The operating principles of the voltage dividing circuits 72, 74 and the voltage dividing circuit 10 are substantially the same and will not be described again.

5 and 6 are circuit diagrams of the reference voltage circuit 82 of the second preferred embodiment and the reference voltage circuit 84 of the third preferred embodiment. The reference voltage circuit 82 includes a second NMOS field effect transistor 22, a third NMOS field effect transistor 24, a fourth NMOS field effect transistor 25, a fifth NMOS field effect transistor 26, and a fourth PMOS field effect transistor 27, The fifth PMOS field effect transistor 28, the tenth PMOS field effect transistor 62, the eleventh PMOS field effect transistor 64, the resistor R1, the reference voltage terminal _VB, and the reference voltage terminal _{VRef of the} output reference voltage. The reference voltage circuit 82 differs from the reference voltage circuit 20 of FIG. 2 in that the reference voltage circuit 82 adds two PMOS field effect transistors 62, 64, the gate of the PMOS field effect transistor 62 and the PMOS field effect transistor 64. The gates are connected, the source of the PMOS field effect transistor 62 is connected to the drain of the fourth PMOS field effect transistor 27, and the drain is connected to the drain of the fourth NMOS field effect transistor 25. The gate of the PMOS field effect transistor 62 is connected to the drain.

The reference voltage circuit 84 includes a second NMOS field effect transistor 22, a third NMOS field effect transistor 24, a fourth NMOS field effect transistor 25, a fifth NMOS field effect transistor 26, and a fourth PMOS field effect transistor 27. The fifth PMOS field effect transistor 28, the resistor R1, the reference voltage terminal V _B and the reference voltage terminal V _{Ref of the} output reference voltage. The reference voltage circuit 84 is different from the reference voltage circuit 20 of FIG. 2 in that the reference voltage terminal V _{Ref of the} reference voltage circuit 84 is connected to the gate of the fourth NMOS field effect transistor 25 and the fifth NMOS field effect transistor 26 . Between the gates.

The reference voltage circuits 82, 84 function the same as the reference voltage circuit 20 of FIG. 2, both generating a reference voltage V _B and a constant reference voltage V _Ref . The operating principles of the reference voltage circuits 82, 84 and the reference voltage circuit 20 are substantially the same and will not be described again.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above descriptions are only preferred embodiments of the present invention, and those skilled in the art will be able to include equivalent modifications or variations in the spirit of the present invention.

100. . . Electrostatic protection device

10, 72, 74. . . Voltage dividing circuit

20, 82, 84. . . Reference voltage circuit

30. . . Comparison circuit

40. . . Switch circuit

V _DD . . . power cable

V _SS . . . Ground wire

12, 22, 24, 25, 26, 32, 34, 35, 42, 54. . . NMOS field effect transistor

14, 15, 16, 27, 28, 36, 37, 38, 39, 62, 64. . . PMOS field effect transistor

R1. . . resistance

V _B . . . Reference voltage

V _Ref . . . The reference voltage

V _Smp . . . Sampling voltage

I _d , I ₂ . . . Current

1 is a functional block diagram of an electrostatic protection device according to a preferred embodiment.

2 is a detailed circuit diagram of the electrostatic protection device of FIG. 1.

3 is a circuit diagram of a second preferred embodiment of the voltage dividing circuit of FIG. 2.

4 is a circuit diagram of a third preferred embodiment of the voltage dividing circuit of FIG. 2.

Figure 5 is a circuit diagram of a second preferred embodiment of the reference voltage circuit of Figure 2.

Figure 6 is a circuit diagram of a third preferred embodiment of the reference voltage circuit of Figure 2.

100. . . Electrostatic protection device

10. . . Voltage dividing circuit

20. . . Reference voltage circuit

30. . . Comparison circuit

40. . . Switch circuit

V _DD . . . power cable

V _SS . . . Ground wire

Claims (14)

An electrostatic protection device is connected between a power supply line for supplying a power supply voltage and a ground line, wherein the electrostatic protection device comprises a voltage dividing circuit, a reference voltage circuit, a comparison circuit and a switching circuit, and the voltage dividing transistor The circuit is configured to divide a voltage provided by the power line to generate a sampling voltage, the reference voltage circuit is configured to receive a voltage provided by the power line to generate a reference voltage, and the comparison circuit is configured to compare the sampling voltage with the reference voltage And outputting the first level signal to the switch circuit when the sampling voltage is greater than the reference voltage, the switch circuit is connected according to the first level signal to connect the power line to the ground line, and the comparison circuit is also when the sampling voltage is less than the reference voltage The second level signal is output to the switch circuit, and the switch circuit is turned off according to the second level signal to cut off the electrical connection between the power line and the ground. The electrostatic protection device of claim 1, wherein the reference voltage circuit is further configured to receive a voltage provided by the power line to generate a reference voltage, and the comparison circuit receives the reference voltage and operates electrically. The electrostatic protection device of claim 1, wherein the first level signal is a high level voltage signal, and the second level signal is a low level voltage signal. The electrostatic protection device of claim 1, wherein the reference voltage is greater than a sampling voltage generated by a voltage divider of the noise voltage supplied by the voltage dividing circuit to the power line. The electrostatic protection device of claim 1, wherein the reference voltage circuit comprises a resistor and a plurality of MOS field effect transistors, wherein the resistance of the resistor and the channel length and the trench of the MOS field effect transistor are adjusted. The width of the track, the preset reference voltage is greater than the sampling voltage generated by the voltage divider of the voltage supply circuit provided by the voltage dividing circuit. The electrostatic protection device of claim 1, wherein the switch circuit comprises an NMOS field effect transistor, the gate of the NMOS field effect transistor is connected to the comparison circuit, the drain is connected to the power line, and the source is connected to the ground. line. The electrostatic protection device of claim 1, wherein the voltage dividing circuit comprises a sampling voltage terminal for outputting a sampling voltage, a first NMOS field effect transistor, a first PMOS field effect transistor, and a second PMOS. a field effect transistor and a third PMOS field effect transistor, wherein a source of the first NMOS field effect transistor is connected to a ground, and a gate and a drain are commonly connected to a sampling voltage end, the first PMOS field effect transistor The gate is connected to the ground, the drain is connected to the drain of the first NMOS field effect transistor, the source is connected to the drain of the second PMOS field effect transistor, and the gate of the second PMOS field effect transistor is connected to the ground. The source is respectively connected to the drain and the gate of the third PMOS field effect transistor, and the source of the third PMOS field effect transistor is connected to the power line, and the sampling voltage terminal is connected to the comparison circuit. The electrostatic protection device of claim 7, wherein the reference voltage circuit comprises a second NMOS field effect transistor, a third NMOS field effect transistor, a fourth NMOS field effect transistor, and a fifth NMOS field effect device. a crystal, a fourth PMOS field effect transistor, a fifth PMOS field effect transistor, a resistor, a reference voltage terminal for outputting a reference voltage, and a reference voltage terminal for outputting a reference voltage, a source of the second NMOS field effect transistor The pole is connected to the ground by a resistor, the gate is connected to the gate of the third NMOS field effect transistor, and the drain is connected to the source of the fourth NMOS field effect transistor, and the gate of the third NMOS field effect transistor The reference voltage terminal is connected, the source is connected to the ground, the drain is connected to the source of the fifth NMOS field effect transistor, and the drain of the fourth NMOS field effect transistor is connected to the drain of the fourth PMOS field effect transistor. The gate is connected to the gate of the fifth NMOS field effect transistor, the gate of the fifth NMOS field effect transistor is connected to the drain, and the drain is connected to the drain of the fifth PMOS field effect transistor, and the fourth PMOS field Effect transistor's gate and drain The source is connected to the power line, and the gate of the fifth PMOS field effect transistor is respectively connected to the gate and the reference voltage end of the fourth PMOS field effect transistor, and the source is connected to the power line, and the reference voltage terminal and the reference are connected. The voltage terminals are all connected to the comparison circuit. The electrostatic protection device of claim 8, wherein the resistance of the resistor, the channel length and the channel width of the second NMOS field effect transistor, and the channel of the third NMOS field effect transistor are adjusted in advance. The length and the channel width are used to change the magnitude of the reference voltage value. The electrostatic protection device of claim 8, wherein the comparison circuit comprises a sixth NMOS field effect transistor, a seventh NMOS field effect transistor, an eighth NMOS field effect transistor, and a sixth PMOS field effect transistor. a seventh PMOS field effect transistor, an eighth PMOS field effect transistor, and a ninth PMOS field effect transistor. The source of the sixth NMOS field effect transistor is connected to the ground, and the gate is connected to the drain. The source of the NMOS field effect transistor is connected to the ground, the gate is connected to the gate of the sixth NMOS field effect transistor, the source of the eighth NMOS field effect transistor is connected to the ground, and the gate and the seventh The drain of the NMOS field effect transistor is connected, the gate of the sixth PMOS field effect transistor is connected to the reference voltage terminal, the drain is connected to the drain of the sixth NMOS field effect transistor, and the source and the seventh PMOS field effect are connected. The source of the transistor is connected, the gate of the seventh PMOS field effect transistor is connected to the sampling voltage terminal, and the drain is connected to the drain of the seventh NMOS field effect transistor, and the gate of the eighth PMOS field effect transistor Connected to the reference voltage terminal, the source is connected to the power line, The drain is connected to the source of the sixth NMOS field effect transistor, the gate of the ninth PMOS field effect transistor is connected to the reference voltage terminal, the source is connected to the power line, and the drain of the ninth PMOS field effect transistor is One end of the eighth NMOS field effect transistor connected to the drain is connected to the switching circuit. The electrostatic protection device of claim 1, wherein the voltage dividing circuit comprises a first NMOS field effect transistor, a ninth NMOS field effect transistor, a second PMOS field effect transistor, and a third PMOS field effect. a transistor and a sampling voltage terminal for outputting a sampling voltage, a source of the first NMOS field effect transistor is connected to a ground, a gate is connected to a drain, and a gate and a power line of the ninth NMOS field effect transistor Connected, the source is connected to the drain of the first NMOS field effect transistor, the drain is connected to the sampling voltage terminal, the gate of the second PMOS field effect transistor is connected to the ground, and the drain is connected to the ninth NMOS field effect. The drain of the crystal is connected, the source is connected to the drain of the third PMOS field effect transistor, the gate of the third PMOS field effect transistor is connected to the drain, and the source is connected to the power line, and the sampling voltage terminal is compared with The circuits are connected. The electrostatic protection device of claim 1, wherein the voltage dividing circuit comprises a sampling voltage terminal for outputting a sampling voltage, a first NMOS field effect transistor, a first PMOS field effect transistor, and a second PMOS. a field effect transistor and a third PMOS field effect transistor, the source of the first NMOS field effect transistor is connected to the ground, the gate is connected to the drain, and the gate of the first PMOS field effect transistor is connected to the ground The drain is connected to the drain of the first NMOS field effect transistor, the source is connected to the drain of the second PMOS field effect transistor, and the gate of the second PMOS field effect transistor is connected to the ground, the source and the The drains of the three PMOS field effect transistors are connected. The gate and the drain of the third PMOS field effect transistor are connected to the sampling voltage terminal, the source is connected to the power line, and the sampling voltage terminal is connected to the comparison circuit. The electrostatic protection device of claim 2, wherein the reference voltage circuit comprises a second NMOS field effect transistor, a third NMOS field effect transistor, a fourth NMOS field effect transistor, and a fifth NMOS field effect device. Crystal, fourth PMOS field effect transistor, fifth PMOS field effect transistor, tenth PMOS field effect transistor, eleventh PMOS field effect transistor, resistor, reference voltage terminal for outputting reference voltage, and for output a reference voltage terminal of the reference voltage, a source of the second NMOS field effect transistor is connected to the ground through a resistor, a gate is connected to a gate of the third NMOS field effect transistor, and the drain is connected to the fourth NMOS field effect transistor The source is connected to the source, the source of the third NMOS field effect transistor is connected to the ground, the gate and the drain are connected to the source of the fifth NMOS field effect transistor, and the gate of the fourth NMOS field effect transistor Cooperating with the gate of the fifth NMOS field effect transistor and the reference voltage terminal, the drain of the fourth NMOS field effect transistor is connected to the drain of the tenth PMOS field effect transistor, the tenth PMOS field effect transistor The gate is connected to the drain The source is connected to the drain of the fourth PMOS field effect transistor, and the gate of the eleventh PMOS field effect transistor is connected to the gate of the tenth PMOS field effect transistor, and the drain and the fifth NMOS field effect The drain of the crystal is connected, and the source is connected to the drain of the fifth PMOS field effect transistor. The gate and the drain of the fourth PMOS field effect transistor are connected to the reference voltage terminal, and the source is connected to the power line. The gate of the fifth PMOS field effect transistor is connected to the gate of the fourth PMOS field effect transistor, the source is connected to the power line, and the reference voltage terminal and the reference voltage terminal are connected to the comparison circuit. The electrostatic protection device of claim 2, wherein the reference voltage circuit comprises a second NMOS field effect transistor, a third NMOS field effect transistor, a fourth NMOS field effect transistor, and a fifth NMOS field effect device. a crystal, a fourth PMOS field effect transistor, a fifth PMOS field effect transistor, a resistor, a reference voltage terminal for outputting a reference voltage, and a reference voltage terminal for outputting a reference voltage, a source of the second NMOS field effect transistor The pole is connected to the ground by a resistor, the gate is connected to the gate of the third NMOS field effect transistor, the drain is connected to the source of the fourth NMOS field effect transistor, and the source of the third NMOS field effect transistor is connected. a ground line, the gate is connected to the drain, the drain of the fourth NMOS field effect transistor is connected to the drain of the fourth PMOS field effect transistor, and the gate is connected to the gate of the fifth NMOS field effect transistor. The gate of the fifth NMOS field effect transistor is connected to the reference voltage terminal, the drain is connected to the drain of the fifth PMOS field effect transistor, and the source is connected to the drain of the third NMOS field effect transistor, the fourth PMOS Gate and 场 of field effect transistor Commonly connected to the reference voltage terminal, the source is connected to the power line, the gate of the fifth PMOS field effect transistor is connected to the gate of the fourth PMOS field effect transistor, the source is connected to the power line, and the reference voltage terminal The reference voltage terminals are all connected to the comparison circuit.