CN101964518A - Electrostatic protection device - Google Patents

Abstract

The invention discloses an electrostatic protection device, which is connected between power lines for supplying voltage and earth wires. The electrostatic protection device comprises a voltage division circuit, a reference voltage circuit, a comparison circuit and a switching circuit, wherein the voltage division circuit is used for carrying out voltage division on the voltage supplied by the power lines so as to generate sampling voltages; the reference voltage circuit is used for receiving the voltage supplied by the power lines so as to generate reference voltages; the comparison circuit is used for comparing the sampling voltages with the reference voltages, and outputting a first level signal to the switching circuit when the sampling voltages are greater than the reference voltages, then the switching circuit switches on the electrical connection between the power lines and the earth wires according to the first level signal; moreover, the comparison circuit is also used for outputting a second level signal to the switching circuit when the sampling voltages are less than the reference voltages, then the switching circuit switches off the electrical connection between the power lines and the earth wires according to the second level signal.

Description

Electrostatic protection device

Technical field

The present invention relates to integrated circuit fields, particularly a kind of electrostatic protection device.

Background technology

As everyone knows, the high pressure that produces cause damage can for the internal circuit of integrated circuit static discharge (ESD, Electrostatic Discharge) moment.Damage for fear of this static brings generally in integrated circuit (IC) design, all can be provided with electrostatic discharge protective circuit.This electrostatic discharge protective circuit comprises and is used for power line, ground wire, the switch element of supply power voltage being provided and being connected the detecting unit of power line to above-mentioned internal circuit that this switch element is connected between power line and the ground wire.When having static on the power line, this detecting unit promptly produces control signal and gives switching circuit, with the control switch circuit turn-on, the guiding ground wire of the electrostatic potential on the power line is absorbed, thereby prevent that effectively electrostatic potential from causing voltge surge to internal circuit.

Yet, produce the magnitude of voltage noise voltage (Noise Voltage) bigger on the power line than supply power voltage owing to reasons such as electromagnetic interference can make.Usually, this noise voltage is less with respect to electrostatic potential, and for example, when supply power voltage is 10V, the noise voltage that produces on the power line can not surpass 20V usually, and electrostatic potential has hundreds of volts, thousands of volt even tens thousand of volt usually.Because above-mentioned noise voltage also may trigger detecting unit and produce control signal, make the switching circuit conducting, cause power line to be grounded, the internal circuit of integrated circuit just can not obtain supply power voltage, thereby makes integrated circuit cisco unity malfunction under the situation of no static.

Summary of the invention

In view of this, be necessary to provide a kind of electrostatic protection device that prevents static and shielding noise voltage.

A kind of electrostatic protection device is connected in and is used to provide between the power line and ground wire of supply power voltage, and it comprises bleeder circuit, reference voltage circuit, comparison circuit and switching circuit.The voltage that bleeder circuit is used for power line is provided carries out dividing potential drop, to produce sampling voltage.Reference voltage circuit is used to receive the voltage that power line provides, to produce reference voltage.Comparison circuit is used for sampling voltage and reference voltage are compared, and exports first level signal during greater than reference voltage in sampling voltage and give switching circuit, switching circuit according to this first level signal conducting so that power line is connected with ground wire.Comparison circuit is also exported second level signal during less than reference voltage in sampling voltage and is given switching circuit, and switching circuit turn-offs electric connection to cut off the electricity supply between line and the ground wire according to this second level signal.

Above-mentioned electrostatic protection device; by comparison circuit and reference voltage circuit are set, when sampling voltage greater than reference voltage, when promptly having electrostatic potential on the power line; comparison circuit is the control switch circuit turn-on so that power line is connected with ground wire, thereby electrostatic potential ground connection can be absorbed.When having noise voltage on the power line, the reference voltage that reference voltage circuit produces will be greater than sampling voltage, and comparison circuit is that the control switch circuit turn-offs the electric connection to cut off the electricity supply between line and the ground wire, thereby can realize the shielding to noise voltage.

Description of drawings

Fig. 1 is the functional block diagram of the electrostatic protection device of a better embodiment.

Fig. 2 is the detailed circuit diagram of first better embodiment of electrostatic protection device among Fig. 1, and this electrostatic protection device comprises bleeder circuit and reference voltage circuit.

Fig. 3 is the circuit diagram of second better embodiment of bleeder circuit among Fig. 2.

Fig. 4 is the circuit diagram of the 3rd better embodiment of bleeder circuit among Fig. 2.

Fig. 5 is the circuit diagram of second better embodiment of reference voltage circuit among Fig. 2.

Fig. 6 is the circuit diagram of the 3rd better embodiment of reference voltage circuit among Fig. 2.

Embodiment

Be illustrated in figure 1 as the functional block diagram of the electrostatic protection device 100 of a better embodiment.This electrostatic protection device 100 comprises bleeder circuit 10, reference voltage circuit 20, comparison circuit 30 and switching circuit 40.In the present embodiment, electrostatic protection device 100 is applied in the integrated circuit.

Bleeder circuit 10 is used for power line V _DDThe supply power voltage V that provides _DDTake a sample, to produce a sampling voltage, the magnitude of voltage of this sampling voltage is along with supply power voltage V _DDVariation and change.

Reference voltage circuit 20 is used to receive power line V _DDThe supply power voltage V that provides _DD, to produce a reference voltage and a constant reference voltage.In the present embodiment, this reference voltage circuit 20 comprises resistance and a plurality of metal-oxide-semiconductor.The resistance by regulating this resistance and the channel length and the channel width of metal-oxide-semiconductor preestablish the sampling voltage that reference voltage that reference voltage circuit 20 produces is produced greater than 10 pairs of these noise voltage dividing potential drops of bleeder circuit.

Comparison circuit 30 is used to receive the reference voltage of reference voltage circuit 20 generations to work on power.Comparison circuit 30 also is used to receive sampling voltage and reference voltage, and sampling voltage and reference voltage are compared.When sampling voltage greater than reference voltage, i.e. power line V _DDOn when having static, comparison circuit 30 produces first level signal and gives switching circuit 40.When sampling voltage was less than or equal to reference voltage, comparison circuit 30 produced second level signal and gives switching circuit 40.In the present embodiment, first level signal is the high level voltage signal, and second level signal is the low level voltage signal.

Switching circuit 40 is connected in power line V _DDWith ground wire V _SSBetween, it is used for according to the first level signal conducting, with power line V _DDThe electrostatic potential guiding ground wire V of last existence _SSAnd absorb.This switching circuit 40 also is used for turn-offing according to second level signal, with the line V that cuts off the electricity supply _DDWith ground wire V _SSBetween electric connection.If power line V _DDOn have noise voltage owing to preestablished the sampling voltage that reference voltage that reference voltage circuit 20 produces is produced greater than 10 pairs of these noise voltage dividing potential drops of bleeder circuit, this switching circuit 40 just is in off state, this power line V _DDBe not grounded, it still can provide supply power voltage V _DD, thereby avoided the influence of noise voltage effectively to circuit.

As shown in Figure 2, it is the detailed circuit diagram of first better embodiment of electrostatic protection device 100.Bleeder circuit 10 comprises the sampling voltage end V that is used to export sampling voltage _Smp, a NMOS (Negative Channel Metal Oxide Semiconductor) pipe the 12, the one PMOS (PositiveChannel Metal Oxide Semiconductor) pipe the 14, the 2nd PMOS pipe the 15 and the 3rd PMOS pipe 16.The source electrode and the ground wire V of the one NMOS pipe 12 _SSConnect the common and sampling voltage end V of grid and drain electrode _SmpLink to each other.The drain electrode and the sampling voltage end V of the one PMOS pipe 14 _SmpConnect, grid connects ground wire V _SS, source electrode links to each other with the drain electrode of the 2nd PMOS pipe 15.The grid of the 2nd PMOS pipe 15 connects ground wire V _SS, source electrode links to each other with the drain and gate of the 3rd PMOS pipe 16 respectively, the source electrode and the power line V of the 3rd PMOS pipe 16 _DDLink to each other.

Reference voltage circuit 20 comprises the reference voltage end V of the 2nd NMOS pipe the 22, the 3rd NMOS pipe the 24, the 4th NMOS pipe the 25, the 5th NMOS pipe the 26, the 4th PMOS pipe the 27, the 5th PMOS pipe 28, resistance R 1, output reference voltage _BAnd the reference voltage terminal V of output reference voltage _RefThe source electrode of the 2nd NMOS pipe 22 connects ground wire V by resistance R 1 _SS, the grid and the reference voltage terminal V of grid and the 3rd NMOS pipe 24 _RefLink to each other, drain electrode links to each other with the source electrode of the 4th NMOS pipe 25.The grid and the reference voltage terminal V of the 3rd NMOS pipe 24 _RefLink to each other, source electrode connects ground wire V _SS, drain electrode links to each other with the source electrode of the 5th NMOS pipe 26.The drain electrode of the 4th NMOS pipe 25 links to each other with the drain electrode of the 4th PMOS pipe 27, and grid links to each other with the grid of the 5th NMOS pipe 26.The grid of the 5th NMOS pipe 26 links to each other with the drain electrode of its drain electrode with the 5th PMOS pipe 28, and the grid of the 4th PMOS pipe 27 links to each other source electrode and power line V with its drain electrode _DDLink to each other.The grid of the 5th PMOS pipe 28 is managed 27 grid and reference voltage end V respectively with the 4th PMOS _BLink to each other source electrode and power line V _DDLink to each other.

Comparison circuit 30 comprises the 6th NMOS pipe the 32, the 7th NMOS pipe the 34, the 8th NMOS pipe the 35, the 6th PMOS pipe the 36, the 7th PMOS pipe the 37, the 8th PMOS pipe the 38 and the 9th PMOS pipe 39.The source electrode of the 6th NMOS pipe 36 connects ground wire V _SS, grid links to each other with drain electrode.The source electrode and the ground wire V of the 7th NMOS pipe 34 _SSLink to each other, grid links to each other with the grid of the 6th NMOS pipe 32.The source electrode and the ground wire V of the 8th NMOS pipe 35 _SSLink to each other, grid links to each other with the drain electrode of the 7th NMOS pipe 34, and drain electrode links to each other with the drain electrode of the 9th PMOS pipe 39.The grid and the reference voltage terminal V of the 6th PMOS pipe 36 _RefLink to each other, drain electrode links to each other with the drain electrode of the 6th NMOS pipe 32, and source electrode links to each other with the source electrode of the 7th PMOS pipe 37.The grid and the sampling voltage end V of the 7th PMOS pipe 37 _SmpLink to each other, drain electrode links to each other with the drain electrode of the 7th PMOS pipe 37.The grid and the reference voltage end V of the 8th PMOS pipe 38 _BLink to each other, source electrode connects power line V _DD, drain electrode links to each other with the source electrode of the 6th NMOS pipe 36.The grid and the reference voltage end V of the 9th PMOS pipe 39 _BLink to each other, source electrode connects power line V _DDThe drain electrode of the 9th PMOS pipe 39 is connected switching circuit 40 with the end that the drain electrode of the 8th NMOS pipe 35 links to each other.

Switching circuit 40 comprises the tenth NMOS pipe 42.Between the drain electrode that the grid of the tenth NMOS pipe 42 is connected in the 8th NMOS pipe 35 and the drain electrode of the 9th PMOS pipe 39, the drain electrode connection power line V of this NMOS pipe 42 _DD, source electrode connects ground wire V _SS

The operation principle of this electrostatic protection device 100 is as follows:

Grid and drain electrode for bleeder circuit 10, the one NMOS pipe 12 link together, i.e. V _GS=V _DS, V _DS(saturated)=V _GS-V _T=V _DS-V _T, because V _DS＞V _DS(saturated)=V _DS-V _T, guarantee that NMOS pipe 12 works in the saturation region, therefore the drain current of NMOS pipe 12

Sampling voltage V _SmpFor:

$V_{\mathrm{Smp}}=V_{\mathrm{<figure-callout\; id="1"\; label="DS"\; filenames="H2009101582526E0000021.png,H2009101582526E0000031.png"\; state="\{\{state\}\}">DS</figure-callout>}1}={\mathrm{<figure-callout\; id="1"\; label="V\; GS"\; filenames="H2009101582526E0000021.png,H2009101582526E0000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{GS}}=V_T+\sqrt{\frac{{2I}_d\&times;{\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="H2009101582526E0000021.png,H2009101582526E0000031.png"\; state="\{\{state\}\}">L</figure-callout>}}_1}{{\mathrm{KW}}_1}}---1-1$

V wherein _TBe threshold voltage, k is the mutual conductance coefficient, L ₁, W ₁Be respectively the channel length and the channel width of NMOS pipe 12, above-mentioned parameter is constant, I _dBe drain current.Among the formula 1-1, be the sampling voltage V under λ=0 condition _Smp, wherein λ is the channel length regulation coefficient.

Because NMOS pipe the 12, the one PMOS pipe the 14, the 2nd PMOS pipe the 15 and the 3rd PMOS pipe 16 is connected in series, therefore NMOS pipe the 12, the one PMOS pipe the 14, the 2nd PMOS pipe 15 all equates with the drain current of the 3rd PMOS pipe 16, is I _d

The grid and the drain electrode of the 3rd PMOS pipe 16 link together, and guarantee that the 3rd PMOS pipe 16 works in the saturation region, under the condition of λ=0, and the drain current I of the 3rd PMOS pipe 16 _dFor:

$I_d=\frac{{\mathrm{KW}}_2}{{2L}_2}\&times;{(V_{\mathrm{GS}2}-V_T)}^2=\frac{{\mathrm{KW}}_2}{{2L}_2}\&times;{(V_{\mathrm{DS}2}-V_T)}^2---1-2$

L wherein ₂, W ₂Be respectively the channel length and the channel width of the 3rd PMOS pipe 16, will get among the formula 1-2 substitution formula 1-1

$V_{\mathrm{Smp}}=V_{\mathrm{DS}2}+\sqrt{\frac{L_1}{{\mathrm{<figure-callout\; id="1"\; label="W"\; filenames="H2009101582526E0000021.png,H2009101582526E0000031.png"\; state="\{\{state\}\}">W</figure-callout>}}_1}/\frac{L_2}{W_2}}$

As power line V _DDOn exist magnitude of voltage greater than supply power voltage V _DDNoise voltage the time, the drain-source voltage V of the 3rd PMOS pipe 16 _DS2Can increase, thereby cause sampling voltage V _SmpIncrease.Because power line V _DDThe noise voltage V that produces _NoiseUsually all not too large, suppose V _NoiseHas a maximum V _Nmax, 10 pairs of these noise voltages of bleeder circuit V correspondingly _NoiseThe sampling voltage V that dividing potential drop produced _SmpAlso can reach its maximum V _Smax

As power line V _DDOn when having static, this electrostatic potential is very big, so 10 pairs of these electrostatic potentials of bleeder circuit carry out the sampling voltage V that dividing potential drop produced _SmpCan be much larger than V _Smax

For reference voltage circuit 20, because metal-oxide- semiconductor 27,28 constitutes current mirror, the drain current that therefore flows through metal-oxide- semiconductor 27,28 equates, is I ₂Metal-oxide- semiconductor 22,24 and resistance R 1 constitute a loop, the gate source voltage V of metal-oxide-semiconductor 22 _GS5Gate source voltage V with metal-oxide-semiconductor 24 _GS6Just like ShiShimonoseki be: V _GS6=V _GS5+ I ₂* R1, promptly

$V_T=\sqrt{\frac{{2I}_2\&times;L_6}{{\mathrm{KW}}_6}}=V_T+\sqrt{\frac{{2I}_2\&times;L_5}{{\mathrm{KW}}_5}}+I_2\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="H2009101582526E0000021.png,H2009101582526E0000031.png"\; state="\{\{state\}\}">R</figure-callout>}1$

Therefore, drain current

Reference voltage V _RefFor:

$V_{\mathrm{Ref}}=V_{\mathrm{GS}6}=V_T+\sqrt{\frac{4}{K^2\&times;{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="H2009101582526E0000021.png,H2009101582526E0000031.png"\; state="\{\{state\}\}">R</figure-callout>}1}^2}\&times;(\frac{{L_6}^2}{{W_6}^2}-\frac{L_5\&times;L_6}{W_5\&times;W_6})}$

Wherein, V _TBe threshold voltage, k is the mutual conductance coefficient, L ₅, W ₅Be respectively the channel length and the channel width of metal-oxide-semiconductor 22, L ₆, W ₆Be respectively the channel length and the channel width of metal-oxide-semiconductor 24, above-mentioned parameter is constant.Therefore, reference voltage V _RefBe a fixed voltage value, it is not with power line V _DDThe voltage V that provides _DDVariation and change.

Can be in advance by the resistance that changes resistance R 1, the channel length L of metal-oxide-semiconductor 22 ₅, channel width W ₅And the channel length L of metal-oxide-semiconductor 24 ₆, channel width W ₆, to realize to reference voltage V _RefAdjusting, and make reference voltage V _RefGreater than sampling voltage V _SmpMaximum V _Smax, i.e. V _Ref＞V _SmaxIn addition, the reference voltage V of reference voltage circuit 20 generations _BBe low level voltage.

For comparison circuit 30, as power line V _DDWhen producing noise voltage, because sampling voltage V _SmpLess than reference voltage V _Ref, i.e. V _Ref＞V _Smax, therefore the 7th PMOS manages 37 conductings, makes that the grid of the 8th NMOS pipe 35 is a high level voltage, and the 8th NMOS manages 35 conductings, and the grid of NMOS pipe 42 is a low level voltage in the switch element 40, and NMOS pipe 42 ends, thereby power line V _DDBe not grounded, it still can provide supply power voltage V _DDBut, thereby guaranteed integrated circuit operate as normal under the situation of no static.

As power line V _DDWhen having electrostatic potential because electrostatic potential is bigger usually, this moment sampling voltage V _SmpGreater than reference voltage V _RefTherefore the 7th PMOS pipe 37 ends, and makes the grid of the 8th NMOS pipe 35 pass through the drain electrode and the source ground of the 7th NMOS pipe 34, is low level voltage, the 8th NMOS pipe 35 ends, and the grid of NMOS pipe 42 is connected power line V by the drain electrode of the 9th PMOS pipe in the switch element 40 with source electrode _DD, the grid of NMOS pipe 42 is a high level voltage, NMOS manages 42 conductings, power line V _DDBe grounded power line V _DDThe electrostatic potential of last existence is led ground and is absorbed.Can avoid static that integrated circuit is caused damage.

Fig. 3 and Fig. 4 are respectively the circuit diagram of the bleeder circuit 74 of the bleeder circuit 72 of second better embodiment and the 3rd better embodiment.Bleeder circuit 72 comprises NMOS pipe the 12, the 9th NMOS pipe the 54, the 2nd PMOS pipe the 15, the 3rd PMOS pipe 16 and sampling voltage end V _SmpThe difference of bleeder circuit 10 is among this bleeder circuit 72 and Fig. 2, and bleeder circuit 72 connects power line V with the grids that the pipe of the PMOS in the bleeder circuit 10 14 replaces with the 9th NMOS pipe 54, the nine NMOS pipe 54 _DD, source electrode connects the drain electrode of NMOS pipe 12, and drain electrode connects the drain electrode of the 2nd PMOS pipe 15, simultaneously sampling voltage end V _SmpThe drain electrode that is connected in the 9th NMOS pipe 54 and the 2nd PMOS manage between 15 the drain electrode.

Bleeder circuit 74 comprises NMOS pipe the 12, the one PMOS pipe the 14, the 2nd PMOS pipe the 15, the 3rd PMOS pipe 16 and sampling voltage end V _SmpThe difference of bleeder circuit 10 is among bleeder circuit 74 and Fig. 2: sampling voltage end V _SmpThe source electrode that is connected in the 2nd PMOS pipe 15 and the 3rd PMOS manage between 16 the drain electrode.

Bleeder circuit 72,74 is identical with bleeder circuit 10 roles among Fig. 2, all is to produce a magnitude of voltage along with power line V _DDThe supply power voltage V that provides _DDChange and the sampling voltage V that changes _SmpThe operation principle of bleeder circuit 72,74 and bleeder circuit 10 is roughly the same, repeats no more.

Fig. 5 and Fig. 6 are respectively the circuit diagram of the reference voltage circuit 84 of the reference voltage circuit 82 of second better embodiment and the 3rd better embodiment.Reference voltage circuit 82 comprises the 2nd NMOS pipe the 22, the 3rd NMOS pipe the 24, the 4th NMOS pipe the 25, the 5th NMOS pipe the 26, the 4th PMOS pipe the 27, the 5th PMOS pipe the 28, the tenth PMOS pipe 62, the 11 PMOS pipe 64, resistance R 1, reference voltage end V _BReference voltage terminal V with output reference voltage _RefThe difference of reference voltage circuit 20 is among this reference voltage circuit 82 and Fig. 2: reference voltage circuit 82 has increased by two PMOS pipes 62,64, the grid of PMOS pipe 62 links to each other with the grid of PMOS pipe 64, the source electrode of PMOS pipe 62 links to each other with the drain electrode of the 4th PMOS pipe 27, and drain electrode links to each other with the drain electrode of the 4th NMOS pipe 25.The grid of this PMOS pipe 62 links to each other with drain electrode.

Reference voltage circuit 84 comprises the 2nd NMOS pipe the 22, the 3rd NMOS pipe the 24, the 4th NMOS pipe the 25, the 5th NMOS pipe the 26, the 4th PMOS pipe the 27, the 5th PMOS pipe 28, resistance R 1, reference voltage end V _BReference voltage terminal V with output reference voltage _RefThe difference of reference voltage circuit 20 is among this reference voltage circuit 84 and Fig. 2: the reference voltage terminal V of reference voltage circuit 84 _RefThe grid that is connected in the 4th NMOS pipe 25 and the 5th NMOS manage between 26 the grid.

Reference voltage circuit 82,84 is identical with reference voltage circuit 20 roles among Fig. 2, all is to produce reference voltage V _BWith a constant reference voltage V _RefThe operation principle of reference voltage circuit 82,84 and reference voltage circuit 20 is roughly the same, repeats no more.

Those skilled in the art will be appreciated that; above execution mode only is to be used for illustrating the present invention; and be not to be used as limitation of the invention; as long as within connotation scope of the present invention, appropriate change and the variation that above embodiment did all dropped within the scope of protection of present invention.

Claims (12)

1. electrostatic protection device; it is connected in and is used to provide between the power line and ground wire of supply power voltage; it is characterized in that: this electrostatic protection device comprises bleeder circuit; reference voltage circuit; comparison circuit and switching circuit; the voltage that this bleeder circuit is used for power line is provided carries out dividing potential drop; to produce sampling voltage; this reference voltage circuit is used to receive the supply power voltage that power line provides; to produce reference voltage; this comparison circuit is used for sampling voltage and reference voltage are compared; and export first level signal during greater than reference voltage in sampling voltage and give switching circuit; this switching circuit according to this first level signal conducting so that power line is connected with ground wire; this comparison circuit is also exported second level signal during less than reference voltage in sampling voltage and is given switching circuit, and this switching circuit turn-offs electric connection to cut off the electricity supply between line and the ground wire according to this second level signal.

2. electrostatic protection device as claimed in claim 1 is characterized in that: this reference voltage circuit also is used to receive the supply power voltage that power line provides, and to produce reference voltage, this comparison circuit receives this reference voltage to work on power.

3. electrostatic protection device as claimed in claim 1 is characterized in that: this first level signal is the high level voltage signal, and this second level signal is the low level voltage signal.

4. electrostatic protection device as claimed in claim 1; it is characterized in that: this reference voltage circuit comprises resistance and a plurality of metal-oxide-semiconductor, and the reference voltage that this reference voltage circuit produces carries out the sampling voltage that dividing potential drop produced greater than bleeder circuit to the noise voltage that produces on the power line.

5. electrostatic protection device as claimed in claim 1 is characterized in that: this switching circuit comprises NMOS pipe, and the grid of this NMOS pipe links to each other with comparison circuit, and drain electrode connects power line, and source electrode connects ground wire.

6. electrostatic protection device as claimed in claim 1; it is characterized in that: this bleeder circuit comprises the sampling voltage end that is used to export sampling voltage; the one NMOS pipe; the one PMOS pipe; the 2nd PMOS pipe and the 3rd PMOS pipe; the source electrode of the one NMOS pipe is connected with ground wire; grid links to each other with the sampling voltage end jointly with drain electrode; the grid of the one PMOS pipe connects ground wire; drain electrode is connected with the drain electrode of a NMOS pipe; source electrode links to each other with the drain electrode of a PMOS pipe; the grid of the 2nd PMOS pipe connects ground wire; source electrode links to each other with the drain and gate of the 3rd PMOS pipe respectively, and the source electrode of the 3rd PMOS pipe links to each other with power line, and this sampling voltage end is connected with comparison circuit.

7. electrostatic protection device as claimed in claim 6; it is characterized in that: this reference voltage circuit comprises the 2nd NMOS pipe; the 3rd NMOS pipe; the 4th NMOS pipe; the 5th NMOS pipe; the 4th PMOS pipe; the 5th PMOS pipe; resistance; be used for the reference voltage end of output reference voltage and be used for the reference voltage terminal of output reference voltage; the source electrode of the 2nd NMOS pipe connects ground wire by resistance; grid links to each other with the grid of the 3rd NMOS pipe; drain electrode links to each other with the source electrode of the 4th NMOS pipe; the grid of the 3rd NMOS pipe links to each other with reference voltage terminal; source electrode connects ground wire; drain electrode links to each other with the source electrode of the 5th NMOS pipe; the drain electrode of the 4th NMOS pipe links to each other with the drain electrode of the 4th PMOS pipe; grid links to each other with the grid of the 5th NMOS pipe; the grid of the 5th NMOS pipe links to each other with drain electrode; drain electrode links to each other with the drain electrode of the 5th PMOS pipe; the grid of the 4th PMOS pipe links to each other with drain electrode; source electrode links to each other with power line; the grid of the 5th PMOS pipe links to each other with reference voltage end with the grid of the 4th PMOS pipe respectively; source electrode links to each other with power line, and this reference voltage end and reference voltage terminal all are connected with comparison circuit.

8. electrostatic protection device as claimed in claim 6; it is characterized in that: this comparison circuit comprises the 6th NMOS pipe; the 7th NMOS pipe; the 8th NMOS pipe; the 6th PMOS pipe; the 7th PMOS pipe; the 8th PMOS pipe and the 9th PMOS pipe; the source electrode of the 6th NMOS pipe connects ground wire; grid links to each other with drain electrode; the source electrode of the 7th NMOS pipe links to each other with ground wire; grid links to each other with the grid of the 6th NMOS pipe; the source electrode of the 8th NMOS pipe links to each other with ground wire; grid links to each other with the drain electrode of the 7th NMOS pipe; the grid of the 6th PMOS pipe links to each other with reference voltage terminal; drain electrode links to each other with the drain electrode of the 6th NMOS pipe; source electrode links to each other with the source electrode of the 7th PMOS pipe; the grid of the 7th PMOS pipe links to each other with the sampling voltage end; drain electrode links to each other with the drain electrode of the 7th NMOS pipe; the grid of the 8th PMOS pipe links to each other with reference voltage end; source electrode connects power line; drain electrode links to each other with the source electrode of the 6th NMOS pipe; the grid of the 9th PMOS pipe links to each other with reference voltage end; source electrode connects power line, and the drain electrode of the 9th PMOS pipe is connected switching circuit with the end that the drain electrode of the 8th NMOS pipe links to each other.

9. electrostatic protection device as claimed in claim 1; it is characterized in that: this bleeder circuit comprises NMOS pipe; the 9th NMOS pipe; the 2nd PMOS pipe; the 3rd PMOS manages and is used to export the sampling voltage end of sampling voltage; the source electrode of the one NMOS pipe is connected with ground wire; grid links to each other with drain electrode; the grid of the 9th NMOS pipe links to each other with power line; source electrode is connected with the drain electrode of a NMOS pipe; drain electrode is connected with the sampling voltage end; the grid of the 2nd PMOS pipe links to each other with ground wire; drain electrode is connected with the drain electrode of the 9th NMOS pipe; source electrode is connected with the drain electrode of the 3rd PMOS pipe; the grid of the 3rd PMOS pipe is connected with drain electrode; source electrode links to each other with power line, and this sampling voltage end links to each other with comparison circuit.

10. electrostatic protection device as claimed in claim 1; it is characterized in that: this bleeder circuit comprises the sampling voltage end that is used to export sampling voltage; the one NMOS pipe; the one PMOS pipe; the one PMOS pipe and the 3rd PMOS pipe; the source electrode of the one NMOS pipe is connected with ground wire; grid links to each other with drain electrode; the grid of the one PMOS pipe connects ground wire; drain electrode is connected with the drain electrode of a NMOS pipe; source electrode links to each other with the drain electrode of the 2nd PMOS pipe; the grid of the 2nd PMOS pipe connects ground wire; source electrode links to each other with the drain electrode of the 3rd PMOS pipe; the grid of the 3rd PMOS pipe links to each other with the sampling voltage end jointly with drain electrode; source electrode links to each other with power line, and this sampling voltage end links to each other with comparison circuit.

11. electrostatic protection device as claimed in claim 2; it is characterized in that: this reference voltage circuit comprises the 2nd NMOS pipe; the 3rd NMOS pipe; the 4th NMOS pipe; the 5th NMOS pipe; the 4th PMOS pipe; the 5th PMOS pipe; the tenth PMOS pipe; the 11 PMOS pipe; resistance; be used for the reference voltage end of output reference voltage and be used for the reference voltage terminal of output reference voltage; the source electrode of the 2nd NMOS pipe connects ground wire by resistance; grid links to each other with the grid of the 3rd NMOS pipe; drain electrode links to each other with the source electrode of the 4th NMOS pipe; the source electrode of the 3rd NMOS pipe connects ground wire; grid links to each other with the source electrode of the 5th NMOS pipe jointly with drain electrode; the grid of the 4th NMOS pipe links to each other with reference voltage terminal jointly with the grid of the 5th NMOS pipe; the drain electrode of the 4th NMOS pipe links to each other with the drain electrode of the tenth PMOS pipe; the grid of the tenth PMOS pipe links to each other with drain electrode; source electrode links to each other with the drain electrode of the 4th PMOS pipe; the grid of the 11 PMOS pipe links to each other with the grid of the tenth PMOS pipe; drain electrode links to each other with the drain electrode of the 5th NMOS pipe; source electrode links to each other with the drain electrode of the 5th PMOS pipe; the grid of the 4th PMOS pipe links to each other with reference voltage end jointly with drain electrode; source electrode links to each other with power line; the grid of the 5th PMOS pipe links to each other with the grid of the 4th PMOS pipe; source electrode links to each other with power line, and this reference voltage end and reference voltage terminal all link to each other with comparison circuit.

12. electrostatic protection device as claimed in claim 2; it is characterized in that: this reference voltage circuit comprises the 2nd NMOS pipe; the 3rd NMOS pipe; the 4th NMOS pipe; the 5th NMOS pipe; the 4th PMOS pipe; the 5th PMOS pipe; resistance; be used for the reference voltage end of output reference voltage and be used for the reference voltage terminal of output reference voltage; the source electrode of the 2nd NMOS pipe connects ground wire by resistance; grid links to each other with the grid of the 3rd NMOS pipe; drain electrode links to each other with the source electrode of the 4th NMOS pipe; the source electrode of the 3rd NMOS pipe connects ground wire; grid links to each other with drain electrode; the drain electrode of the 4th NMOS pipe links to each other with the drain electrode of the 4th PMOS pipe; grid links to each other with the grid of the 5th NMOS pipe; the grid of the 5th NMOS pipe links to each other with reference voltage terminal; drain electrode links to each other with the drain electrode of the 5th PMOS pipe; source electrode is connected with the drain electrode of the 3rd NMOS pipe; the grid of the 4th PMOS pipe links to each other with reference voltage end jointly with drain electrode; source electrode links to each other with power line; the grid of the 5th PMOS pipe links to each other with the grid of the 4th PMOS pipe; source electrode links to each other with power line, and this reference voltage end and reference voltage terminal all link to each other with comparison circuit.

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