TWI389456B - Input data recovery circuit for asynchronous serial data transmission - Google Patents

Description

Input data recovery circuit applied to asynchronous serial data transmission

The invention relates to an input data recovery circuit, in particular to an asynchronous data serial input data recovery circuit applied in a receiving end integrated circuit.

When using non-synchronous serial bus to transmit data, the biggest problem is to consider the frequency error between the transmitting and receiving sides. Since the transmitting end and the receiving end are not like the parallel synchronous bus, they have the same clock signal. If there is a slight error in the frequency between the transmitting and receiving sides, the error may accumulate indefinitely and cause an error.

The first figure is a simplified circuit diagram of a related art of the present invention. The related art has been filed on August 29, 1997 by the same inventor of the present invention, and the application number is 097133073. The related art mainly generates an input data signal Dr through a pulse generator 120, and sequentially generates first to nth pulse signals (Vp1 to Vpn) to a switch group 130. Then, the switching state of the switch group 130 is controlled by the switching state of the input data signal Dr and the triggering of the lower edge of the pulse signal, thereby outputting a final pulse signal Vp.

The switching control switching process of the switch group 130 in the first figure is as shown in the second figure. The flow in the second figure ensures that only one switch of the controlled switch group 130 is turned on and the other switches are turned off at the same time, mainly By determining whether the input data signal Dr is switched or not, and the falling edge of the final pulse signal Vp is triggered, it is determined which switch is turned on.

The third figure (a) is the data switching detector circuit diagram in the first figure; the third picture (b) is the mutual exclusion or gate (XOR) truth table (True table); the third picture (c) is the data Switch the detector's input and output waveforms. The input data signal Dr generates an internal signal Va after being delayed by a half cycle by the half cycle delay buffer 111. The input data signal Dr and the internal signal Va are respectively input into a mutual input or the input terminal of the gate 112, and an output is output. Signal Vdsd. That is, when the input data signal Dr is switched between the "0" state and the "1" state, the output signal Vdsd with a half period of "1" is generated, indicating that the switching of the input data signal Dr is detected.

The fourth diagram (a) is a circuit diagram of the first group of logic circuits of the pulse generator in the first figure; and the fourth diagram (b) is a schematic diagram of the input and output waveforms of the first group of logic circuits. Similar to the operation of the data switching detector 110 described in the preceding paragraph, the input data signal Dr generates an internal signal V1b after a half cycle delay of the half cycle delay buffer 121, and the internal signal V1b is further buffered via another half cycle. After the delay period of 122, an internal signal V1c is generated, and the two internal signals V1b and V1c are input with a mutual exclusion gate 123 and then output a first pulse signal Vp1. That is, after the input data signal Dr is switched between the "0" state and the "1" state, the first pulse signal Vp1 having a half period of "1" is generated after a half cycle time.

According to the derivation manner of the first pulse signal Vp1, the internal signal V1c outputted by the buffer 122 is input to the half cycle delay buffer of the next logic circuit of the pulse generator, and so on. The second pulse signal Vp2 to the nth pulse signal Vpn are derived.

The fifth figure is illustrated by taking the first pulse signal Vp1 to the fourth pulse signal Vp4 as an example. The pulse signals (Vp1 to Vp4) are delayed by one cycle from each other, and the switching control flow chart of the second figure is used to control the plurality of switches SW1 to SWn in the switch group 130 (in the fifth figure, only SW1 to SW4 are taken as an example). And the slash portion represents "1", the switch is turned on), and the final pulse signal Vp that finally becomes the flip-flop 140 is obtained, and the final pulse signal Vp is used to trigger the input of the flip-flop 140. Entering the data signal Dr, an output (storage) signal Dout shown in the fifth figure is obtained, which is also the final output of the data recovery circuit.

The sixth figure is a schematic diagram of integrating the on-state of the switch and the waveform of the pulse signal in the fifth figure. The shaded portion represents the switch being turned on, and the complex pulse signal (Vp1 to Vp4) represents the input pulse signal at the input of the switch (SW1 to SW4). Taking the waveform of SW1 (&Vp1) as an example, "↑" in the waveform represents the rising edge of the first pulse signal Vp1 in the middle of the position, and the number represents the first pulse signal generated by the input data signal Dr. Similarly, Vp2 to Vp4 in SW2 (&Vp2) to SW4 (&Vp4) each represent the second to fourth pulse signals generated by the input data signal Dr.

In order to correctly capture the data, the rising edge of the final pulse signal Vp must fall in the input data signal Dr, assuming that the maximum number of bits that the data does not change continuously is n:

Then (n-1)‧T<(n-1/2)‧(2‧Td05)<n‧T→(n-1)‧T<(n-1/2)‧(T+ΔT)<n ‧T→(-1/2)‧T/(n-1/2)<ΔT<(1/2)‧T/(n-1/2)

(where ΔT=2‧Td05-T, Td05 is the delay time of the half-cycle delay buffer, and T is the input data period)

This condition limits ΔT (the error of the double half-cycle delay buffer delay time and the input data bit time) not to be too large, so as to avoid the pulse from erroneously capturing the input data signal Dr bit and causing an error. This ΔT is also a value in the related art limiting factor to be described in the following paragraph.

In addition to the above-mentioned ΔT, which is a factor that must be controlled by many methods, the related art has a limiting factor, that is, the pulse falling edge to the switch turn-on (off) time Tf2s (The delay time of pulse falling-edge to switch turn-on /turn-off). If ΔT>0 and Tf2s is too short, as shown in FIG. 7 , after the first pulse signal Vp1 falls within the period in which the input data signal Dr is “0”, the previous first switch SW1 turns on. The second switch SW2 is turned on, and the second switch SW2 is turned on to cause the tail end of the second pulse signal Vp2 generated when the previous data (the input data signal Dr is "1") is captured, so that a more grab is generated. A pulse of data that causes data to be crawled incorrectly. Therefore, there should be a limit of Tf2s greater than ΔT in this related technology application.

The main purpose of the present invention is to provide a data recovery circuit for asynchronous serial data transmission, which is to turn off the pulse signal tail generated by the previous data when the switch is switched by the conduction of the double-layer switch. The error caused.

In order to achieve the above object, the present invention mainly provides two secondary switch groups and one main switch group after the pulse generator, and controls the conduction of the two switch groups by state switching of the input data signals and triggering of the pulse signals, respectively. In order to more accurately output the pulse signal generated by the pulse generator.

The effect obtained by the present invention in comparison with the related art is that the time from the pulse falling edge to the switch conduction (off) time in the related art must be greater than the limit of ΔT, so that the pulse falling edge to the switch conduction (off) time is only greater than zero. Since the actual circuit delay time is not negative, the pulse falling edge to the switch conduction (off) time is greater than zero, so that the circuit of the present invention does not generate one more pulse due to design negligence under the same operating conditions. Signal.

The eighth figure is a circuit diagram of the input data recovery circuit of the present invention. As shown in the figure, the input data recovery circuit of the present invention has two input terminals and an output terminal. The two input terminals respectively receive an input data signal Dr and a delay control signal, and the output terminal outputs a data output (storage). Signal Dout. The circuit is mainly composed of a data switching detector 810, a pulse generator 820, a high-pass switch group 831, a low-pass switch group 832, a main switch group 840, a flip-flop 850 and a switch control circuit. 860 composition. After receiving the input data signal Dr and the delay control signal through the two input ends of the pulse generator 820, the plurality of output terminals of the pulse generator 820 sequentially generate a plurality of high pulse signals (Vp1H to VpnH). And the plurality of low pulse signals (Vp1L to VpnL) are output to the input ends of the corresponding plurality of high pass switches (SW1H to SWnH) and the plurality of low pass switches (SW1L to SWnL) of the two secondary switch groups 831 and 832. Then, a data switching detector 810 detects the state switching of the input data signal Dr, and controls the conduction of the two secondary switch groups 831, 832 through the triggering of the switch control circuit 860 and the pulse signal.

The high-pass switch group 831 is configured to collectively integrate the output ends of all the high-pass switches (SW1H-SWnH) into a high-pass output terminal, and is connected to the high-pass input terminal of one of the main switch groups 840; The low-pass switch group 832 integrates the output ends of all the low-pass switches (SW1L-SWnL) into a low-pass output connected to a low-pass main switch SHL of the main switch group 840. Through the input. After the two secondary switch groups 831 and 832 are sequentially turned on, the complex pulse signals (Vp1H to VpnH, Vp1L to VpnL) generated by the pulse generator 820 are outputted to the main switch group 840, thereby inputting the main switch. One of the groups 840 inputs a high pulse signal VpH and an input low pulse signal VpL. Finally, a final pulse signal Vp is output by the conduction of the main switch group 840.

The final pulse signal Vp generated after the main switch group 840 is turned on is used to input a clock input end of the flip-flop 850, and trigger input of the input data signal of one of the data input ends of the flip-flop 850. Dr, and thereby correctly generate the output (storage) signal Dout. At the same time, the final pulse signal Vp is also connected to the input end of the switch control circuit, thereby triggering the conduction of the two secondary switch groups 831, 832.

The two secondary switch groups 831, 832 and the main switch group 840 in the eighth figure are the switch control switching flowchart of the secondary switch group of the ninth diagram (a), and the main switch of the ninth diagram (b) The group's switch controls the flow shown in the flow chart to control its turn-on and turn-off. As shown in FIG. 9( a ), the switching process of the two secondary switch groups 831 and 832 is similar to that in the second figure, except that the high-pass switch group 831 and the low-pass switch are simultaneously turned on and off at the same time. The secondary switch in group 832. When the input data signal Dr is switched (0 is switched to 1 or 1 to 0), the trigger of the final pulse signal Vp is not required, that is, the first secondary switch (SW1H, SW1L) is turned on. And if the input data signal Dr maintains the same state, that is, when there is no switching action, that is, triggered by the falling edge of the final pulse signal Vp, the second secondary switch (SW2H, SW2L) is sequentially switched to the nth time. The switches (SWnH, SWnL) are turned on.

The ninth figure (b) is a switch control switching flowchart of the main switch group, and the main switch group 840 must have only one switch (the high-pass main switch SWH or the low-pass main switch SWL) turned on at the same time, when the input data When the signal Dr is "1", the high-pass main switch SWH is turned on; and when the input data signal Dr is "0", the low-pass main switch SWL is turned on. It can be seen that the main switch group 840 is directly controlled by the state of the input data signal Dr.

The circuit diagram, the truth table and the waveform of the input and output waveforms of the data switching detector in the eighth figure are the same as those in the third figure (a) to the third figure (c). The data switching detector 810 is composed of a half cycle delay buffer 811 and a mutually exclusive or gate 812. The input terminals of the half-cycle delay buffer 811 receive the input data signal Dr and the delay control signal respectively, and generate an internal signal after a delay of half a cycle. The input data signal Dr and the internal signal are respectively input to the input terminals of the mutex or gate 812, and an output signal Vdsd is generated. That is, when the input data signal Dr is switched between the "0" state and the "1" state, the output signal Vdsd with a half period of "1" is generated, indicating that the state switching of the input data signal Dr is detected. Finally, the output signal Vdsd is outputted to the switch control circuit 860, and then connected to the plurality of control terminals of the two secondary switch groups 831, 832 via the switch control circuit 860, thereby controlling the turn-on or turn-off of the switch groups 831 and 832.

Figure 10 (a) is a circuit diagram of a first set of logic circuits in the pulse generator. The pulse generator 820 is mainly composed of a complex array logic circuit, so as to receive the input data signal Dr, sequentially generate the first A pulse signal (Vp1H, Vp1L) to the nth pulse signal (VpnH, VpnL). The first set of logic circuits are mainly used to generate a first high pulse signal Vp1H and a first low pulse signal Vp1L, and are transmitted to the corresponding first high pass switch SW1H of the high pass switch group 831, and the low The first low pass switch SW1L in the switch group 832 is passed. The first high pulse signal Vp1H means that when the input data signal Dr changes from "0" to "1", a pulse with a period of "1" is generated after a half cycle time (for example, the tenth figure (c) The time point at which the rising edge of the first high pulse signal Vp1H is generated is in the first cycle time after the input data signal Dr is switched to the high potential (Dr=1), so it is referred to herein as A high pulse signal Vp1H. Similarly, the time point at which the rising edge of the first low pulse signal Vp1L is generated is in the first cycle time after the input data signal Dr is switched to the low potential (Dr=0), so it is referred to herein as the first low. Pulse signal Vp1L.

Each set of logic circuits in the pulse generator 820 is mainly composed of two half-cycle delay buffers 821, 822, and two gates 823 and 824 having a positive phase input terminal, an inverting input terminal, and an inverting input terminal. composition. The first half cycle delay buffer 821 is coupled to the positive phase input of the first AND gate 823 and the inverting input of the second AND gate 824; and the second half cycle delay buffer 822 is coupled to the non-inverting input of the second AND gate 824 and to the inverting input of the first AND gate 823. As shown in the figure, one input end of the first half-cycle buffer 821 of the first group of logic circuits receives the input data signal Dr, and one input end of the second half-cycle buffer 822 is connected to the first One half cycle delays the output of the buffer 821, and the other input of the two half cycle delay buffers 821, 822 receives the delay control signal.

Figure 10 (b) is the truth table of the first set of logic circuits in the tenth figure (a), and the tenth figure (c) is the input and output waveform of the first group of logic circuits in the tenth figure (a) schematic diagram. In the figure (c), the input data signal Dr is delayed by a half cycle after the first half cycle delay buffer 821 to generate an internal signal V1d, and the internal signal V1d is further delayed by the second half cycle delay buffer 822. Another internal signal V1e is generated after a half cycle. After the two internal signals V1d and V1e are input to the two gates 823 and 824 having the truth table characteristic shown in the figure (b), the first high pulse signal Vp1H shown in the tenth figure (c) is generated. And outputting the first low pulse signal Vp1L. It can be seen from the tenth figure (c) that the first high pulse signal with a half period of "1" is generated only after the input data signal Dr changes from "0" to "1" and after a half cycle time. Vp1H; and only when the input data signal Dr changes from "1" to "0", and the half cycle time elapses, the first low pulse signal Vp1L with a half period of "1" is generated.

Starting from the second set of logic circuits, the input of one of the first half-cycle delay buffers is connected to the output of the second half-cycle delay buffer of the previous set of logic circuits, thereby receiving the previous one. The second half cycle of the group logic circuit delays the internal signal output by the buffer. Then, through the connection of the other two half cycle delay buffers and the two gates, a second high pulse signal Vp2H and a second low pulse signal Vp2L are output. Finally, it is possible to output all high pulse signals (Vp1H to VpnH) and low pulse signals (Vp1L to VpnL).

The eleventh figure shows the waveform integration of pulse signal and switch switching. The time point of all pulse signals (Vp1H~VpnH, Vp1L~VpnL, VpH, VpL and Vp) can be derived from the figure, and all switches (SW1H~SWnH, SW1L to SWnL, SWH, and SWL) cooperate with the relative relationship of the switch control switching flowcharts of the ninth diagrams (a) and (b). In the eleventh figure, each of the four groups is taken as an example (SW1H to SW4H, SW1L to SW4L, Vp1H to Vp4H, and Vp1L to Vp4L), which is convenient for explanation, but is not limited thereto.

The waveform SW1H(&Vp1H) is used as an example: the diagonal portion of the waveform represents that the first high-pass switch SW1H is turned on, and Vp1H is the input pulse signal of the input of the first high-pass switch SW1H; in the waveform, "↑" represents the middle of the position. The rising edge of the first high pulse signal Vp1H; the number represents the first pulse generated by the input data signal Dr, and the "H" indicates that it is a high pulse signal. Taking the waveform SWH (&VpH) as an example: the diagonal portion of the waveform represents that the high-pass main switch SWH is turned on, and the VpH is the input high-pulse signal input to the input of the high-pass main switch SWH.

Next, the relationship between the pulse signal of the present invention and the two secondary switch groups 831, 832 and the main switch group 840 is analyzed as shown in FIG. As shown in the figure, the input data signal Dr starts with four consecutive bit times of "1", which sequentially generates first to fourth high pulse signals (Vp1H to Vp4H), and the high pulse signals (Vp1H~) Vp4H) sequentially passes through the first to fourth high-pass switches (SW1H to SW4H) to become an input high-pulse signal VpH at the input end of the high-pass main switch SWH. Therefore, the input high pulse signal VpH has four consecutive pulses in the four bit times, and the input high pulse signal VpH passes through the high pass main switch SWH to become the last pulse input of the flip flop 850. The final pulse signal Vp at the end. That is to say, the final pulse signal Vp has four consecutive pulses in the four bit times. Finally, by using the four pulses, the input data signal Dr of the data input end of the flip-flop 850 is input to the four bit times, and the temporary storage (output) is sequentially triggered to the output of the flip-flop 850. At the end, the output (storage) signal Dout of the flip-flop 850 is generated, and the output (storage) signal Dout is also the final output result of the data recovery circuit of the present invention.

Similarly, when the input data signal Dr is switched to a continuous four bit time of “0”, the first to fourth low pulse signals (Vp1L to Vp4L) are sequentially generated, and the low pulse signals (Vp1L) are sequentially generated. ～Vp4L) sequentially passes through the first to fourth low-pass switches (SW1L to SW4L) to become an input low-pulse signal VpL at the input end of the low-pass main switch SWL, so the input low-pulse signal VpL is in the fourth There will be four consecutive pulses in the bit time, and the input low pulse signal VpL will pass through the low pass main switch SWL to become the final pulse signal Vp which finally triggers the clock input of the flip flop 850. Finally, the input data signal Dr of the data input end of the flip-flop 850 is input to the four-bit pulse signal Vp, and the temporary storage (output) is sequentially triggered to the positive The output of the counter 850 generates the output (storage) signal Dout of the flip-flop.

The twelfth figure shows that when the circuit of the present invention occurs as shown in the seventh figure, it does not generate a pulse that is not due to ΔT > 0 and the pulse falling edge to the switch on (off) time Tf2s is too short. . As shown in the figure, the first primary switch SW1H/SW1L is switched on to the second due to the pulse falling edge of the final pulse signal Vp (or the first low pulse signal Vp1L). The secondary switches SW2H/SW2L are turned on, but the corresponding period is when the low-pass main switch SWL is turned on (and the high-pass main switch SWH is turned off), so the last data (when the input data signal Dr is 1) is generated. Although the pulse tail of the second high pulse signal Vp2H passes through the second high pass switch SW2H, but does not pass the high pass main switch SWH, the present invention does not generate a pulse that may not cause a data error. .

In the circuit of the present invention, the falling edge of the final pulse signal Vp is used to trigger the change of the conduction state of the two secondary switch groups 831, 832, and the input data signal is triggered from the rising edge of the final pulse signal Vp. Dr to the falling edge triggers the two secondary switch groups 831, 832, and pauses for a half cycle time. However, as described above, the circuit of the present invention does not generate a pulse that is not necessary because ΔT>0 and the Tf2s is too short. Therefore, the switching diagram of the switch shown in FIG. 9 in the present invention can be further changed. Figure 13 (a) is a flow chart of switching of another embodiment of the present invention. That is, the trigger time for changing the on-state of the two secondary switch groups 831, 832 is advanced by half a cycle. When the input data signal Dr is triggered by using the rising edge of the final pulse signal Vp, the rising edge is used to trigger the second The secondary switch groups 831, 832 change in the on state. In this way, the "pulse falling edge to switch conduction (off) time" Tf2s can be changed to "pulse rising edge to switch conduction (off) time" Tr2s (The delay time of pulse rising-edge to switch turn-on/ Turn-off). And after research, it is found that if the Tr2s is greater than T/2, the final pulse signal Vp width (time when the pulse is "1") is equal to T/2; if the Tr2s is less than T/2, the final pulse signal is The Vp width is equal to the Tr2s. As long as the width (T/2 or Tr2s) of the final pulse signal Vp is wide enough to trigger the input data signal Dr input to the flip-flop 850 to the output of the flip-flop 850, such a pulse is used. There will be no problems on it.

In the flow shown in FIG. 13(a), the triggering of the change of the on-state state of the two secondary switch groups 831, 832 can be advanced by half a cycle, in such a manner that the data recovery circuit of the present invention can be more used in the input data. Signal Dr is a faster application. The thirteenth figure (b) is a switch control switching flowchart of the main switch group according to another embodiment of the present invention. It can be seen from the figure that the main switch group 840 is still directly switched by the input data signal Dr. control.

The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. That is, the equivalent changes and modifications made by the scope of the patent application of the present invention are covered by the scope of the invention.

<Related technology>

110. . . Data switching detector

120. . . Pulse generator

121. . . Half cycle delay buffer

123. . . Mutual exclusion or gate (XOR)

130. . . Switch group

140. . . Positive and negative

150. . . Switch control circuit

Dr. . . Input data signal

Dout. . . Positive and negative output (storage) signal

SW1~SWn. . . First to nth switch

Tf2s. . . Pulse falling edge to switch turn-on (off) time

V1a～V1c. . . Internal signal

Vp1~Vpn. . . First to nth pulse signals

Vdsd. . . Data switching detector output signal

Vp. . . Final pulse signal

<present invention>

810. . . Data switching detector

820. . . Pulse generator

811. . . Half cycle delay buffer

812. . . Mutual exclusion or gate

823. . . With an inverting input and gate

831. . . Qualcomm secondary switch group

832. . . Low pass switch group

840. . . Main switch group

850. . . Positive and negative

860. . . Switch control circuit

Dr. . . Input data signal

Dout. . . Positive and negative output (storage) signal

SW1H~SWnH. . . First to nth high pass switches

SW1L~SWnL. . . First to nth low pass switches

SWH. . . Qualcomm main switch

SWL. . . Low pass main switch

Tf2s. . . Pulse falling edge to switch turn-on (off) time

Tr2s. . . Pulse rising edge to switch conduction (off) time

V1d, V1e. . . Internal signal

Vdsd. . . Data switching detector output signal

Vp1H~VpnH. . . First to nth high pulse signals

Vp1L~VpnL. . . First to nth low pulse signals

VpH. . . Qualcomm main switch input high pulse signal

VpL. . . Low-pass main switch input low pulse signal

Vp. . . Final pulse signal

The first figure is a simplified circuit diagram of a related art of the present invention.

The second figure is a flowchart of switching control switching of the switch group in the first figure.

The third figure (a) is a circuit diagram of the data switching detector in the first figure.

The third figure (b) is the truth table of the exclusive or gate.

The third figure (c) is a schematic diagram of the input and output waveforms of the data switching detector.

The fourth diagram (a) is a circuit diagram of the first set of logic circuits of the pulse generator in the first figure.

The fourth figure (b) is a schematic diagram of the input and output waveforms of the first group of logic circuits.

The fifth figure is a waveform diagram of the input data signal matched with each pulse node and each switch conduction state and data output.

The sixth figure is a schematic diagram of the waveform integration of the switch on state and the pulse signal in the fifth figure.

The seventh figure is a schematic diagram of ΔT>0 and Tf2s being too short to cause a pulse of the final pulse signal Vp.

The eighth figure is a circuit diagram of the input data recovery circuit of the present invention.

The ninth diagram (a) is a flowchart of switching control switching of the secondary switch group.

The ninth diagram (b) is a flowchart of switching control switching of the main switch group.

Figure 10 (a) is a circuit diagram of the first set of logic circuits in the pulse generator.

The tenth figure (b) is the truth table of the first group of logic circuits in the tenth figure (a).

The tenth figure (c) is a schematic diagram of the input and output waveforms of the first group of logic circuits in the tenth figure (a).

The eleventh figure is a schematic diagram of the waveform integration of the pulse signal and the switch switching.

The twelfth figure is a schematic diagram of the fact that ΔT>0 and Tf2s are too short, and the final pulse signal Vp is not pulsed.

Figure 13 (a) is a flow chart showing the switching control of the secondary switch group of another embodiment of the present invention.

Figure 13 (b) is a flow chart showing the switching control of the main switch group of another embodiment of the present invention.

Dr. . . Input data signal

Dout. . . Positive and negative output (storage) signal

810. . . Data switching detector

820. . . Pulse generator

811, 821, 822. . . Half cycle delay buffer

812. . . Mutual exclusion or gate

823, 824. . . With an inverting input and gate

831. . . Qualcomm secondary switch group

832. . . Low pass switch group

840. . . Main switch group

850. . . Positive and negative

860. . . Switch control circuit

Claims (7)

An input data recovery circuit for asynchronous serial data transmission has two input ends and one output end, the two input ends respectively receive an input data signal and a delay control signal, and the output end outputs a data output (storage The signal input circuit includes: a data switching detector having two input ends and an output end, the two input terminals respectively receiving the input data signal and the delay control signal; and a pulse generator having two inputs And the plurality of output terminals, the two input terminals respectively receive the input data signal and the delay control signal, and sequentially output the pulse signal by the plurality of output terminals, wherein the pulse signal comprises a high pulse signal and a low pulse signal; a high-pass switch group having a plurality of input terminals, a high-pass output terminal, and a plurality of control terminals respectively connected to the plurality of output terminals of the corresponding pulse generator, thereby receiving the pulse generator output The high pulse signal; a low pass switch group having a plurality of inputs, a low pass output, and a plurality of control terminals, the plurality of input terminals Connected to the plurality of output terminals of the corresponding pulse generator to receive the low pulse signal output by the pulse generator; a main switch group consisting of a high pass main switch and a low pass main switch, having one a high-pass input terminal, a low-pass input terminal, an output terminal and two control terminals, wherein the high-pass input terminal is connected to the high-pass output terminal of the high-pass switch group, and receives a high-input pulse signal outputted by the high-pass switch group The low-pass input is connected to the low-pass output of the low-pass switch group. Receiving one of the output low pulse signals after being turned on by the low pass switch group, and outputting a final pulse signal through the output end of the main switch group; a switch control circuit having a first input end and a second An input end, a third input end and a plurality of output ends, the first input end is connected to the output end of the data switching detector, the second input end receives the input data signal, and the third input end is connected The output end of the main switch group receives the final pulse signal outputted by the main switch group, and the plurality of output terminals are respectively connected to the main switch group and all control terminals of the second switch group; The flip-flop has a data input end and a clock input end, and the data input end receives the input data signal, and the clock input end is connected to the output end of the main switch group, and receives the output of the main switch group. The final pulse signal is used to trigger the input of the input data signal, and output the data output (storage) signal through one of the output terminals of the flip-flop. For example, the input data recovery circuit of the first application of the patent scope includes: a half cycle delay buffer having two input ends and an output terminal, the two input terminals respectively receiving the input data signal and the a delay control signal; and a mutual exclusion gate having a first input terminal, a second input terminal and an output terminal, the first input terminal receiving the input data signal, and the second input terminal connecting the half cycle delay buffer The output of the device is coupled to the first input of the switch control circuit. For example, the input data recovery circuit of claim 1 of the patent scope, wherein the pulse generator is composed of a complex array logic circuit, each set of the logic The circuit includes: a first half cycle delay buffer and a second half cycle delay buffer connected in series with each other and having a first input terminal, a second input terminal and an output terminal, the second half cycle delay The first input end of the buffer is connected to the output end of the first half cycle delay buffer, and the second input end of the second half cycle delay buffer receives the delay control signal; a gate and a second gate respectively having a positive phase input terminal and an inverting input terminal, wherein the positive phase input terminal of the first gate is connected to the output terminal of the first delay buffer, The inverting input terminal of the first AND gate is connected to the output end of the second delay buffer, the output end of the first AND gate outputs the high pulse signal, and the inverting input terminal of the second AND gate Connected to the output of the first delay buffer, the non-inverting input of the second AND gate is connected to the output of the second delay buffer, and the output of the second AND gate outputs the low pulse a signal; wherein the first half of the first set of the logic circuit The first input end of the delay buffer receives the input data signal, and the first input end of the first half cycle delay buffer of each of the other logic circuits is connected to the first set of the logic circuit The output of the two half cycle delay buffer. For example, in the input data recovery circuit of claim 1, wherein the high-pass switch group includes: a plurality of high-pass switches, each of the high-pass switches having an input terminal, a control terminal, and an output terminal, the input The terminal is connected to the output end of the corresponding pulse generator, so as to receive the high pulse signal output by the pulse generator, and the control terminal inputs the corresponding open The output control signal of the control circuit is turned off, and the outputs of all the high-pass switches are collectively formed into the high-pass output terminal, and connected to the high-pass input terminal of the main switch group, thereby outputting the input high-pulse signal. For example, the input data recovery circuit of claim 4, wherein the low-pass switch group includes: a plurality of low-pass switches, each of the low-pass switches having an input terminal, a control terminal, and an output terminal The input terminal is connected to the output end of the corresponding pulse generator to receive the low pulse signal output by the pulse generator, and the control terminal inputs the corresponding output control signal of the switch control circuit, and all The output terminals of the low-pass switch are collectively assembled into the low-pass output terminal, and are connected to the low-pass input terminal of the main switch group, thereby outputting the input low-pulse signal. For example, in the input data recovery circuit of the first aspect of the patent application, wherein the switch control circuit is configured according to the pulse wave falling edge trigger of the final pulse signal and the data switching detector output control, so that the high pass switch group, the The low pass switch group and the main switch group are turned on or off. For example, in the input data recovery circuit of claim 1, wherein the switch control circuit is triggered by the pulse rising edge of the final pulse signal and the output of the data switching detector, so that the high-pass switch group The low pass switch group and the main switch group are turned on or off.