TWI388977B - Microprocessors, intergarated circuits and methods for selectively biasing substrates - Google Patents

Description

Microprocessor, integrated circuit and selective substrate bias method

The present invention relates generally to providing substrate biasing to a microprocessor die to reduce sub-threshold leakage, and more particularly to selectively providing a substrate bias to a microprocessor. The device and method of the functional block are used to reduce power consumption and minimize noise of the device base in the functional block.

Complementary Metal-Oxide Semiconductor (hereinafter referred to as CMOS) circuit is denser than other types of integrated circuits (hereinafter referred to as IC) and consumes less power. Therefore, CMOS technology has been used. It becomes the dominant style of digital circuit design in integrated circuits. The CMOS circuit is composed of an n-channel metal-oxide-semiconductor (hereinafter referred to as NMOS) and a p-channel metal-oxide-semiconductor (hereinafter referred to as PMOS). Between MOSFET and PMOS, there is a threshold voltage (this refers to the voltage of the gate to the source), depending on the scale, material, and process. Due to the continuous development of integrated circuit design and manufacturing technology, the operating voltage and device size are also reduced. The 65 micrometer (nm) process is an advanced lithographic process for a large number of CMOS semiconductor processes and is more beneficial for very large scale integrated circuits (VLSI). Manufacturing, such as microprocessors. As device size and voltage levels decrease, the channel length and oxide thickness of each device also decreases. Manufacturers have switched to gate materials with lower threshold voltages to increase sub-threshold leakage current. When the gate-to-source voltage is lower than the threshold voltage of the CMOS device, the sub-critical leakage current flows between the drain and the source. A substrate interface of each CMOS of a plurality of conventional circuits (or a well region or a bulk tie/connection) is coupled to a corresponding one of the power lines (eg, the PMOS substrate contacts are coupled to the core voltage VDD, and the NMOS substrate is connected The point is coupled to the reference voltage VSS). In such conventional structures, the subcritical leakage current can account for about 30% or more of the total power consumption in a dynamic environment (e.g., during normal operation).

It is often desirable for integrated circuits to operate in a low power mode (such as sleep mode or hibernation mode) and to minimize power consumption. During the low power mode, a bias generator or charge pump biases the substrate of the device at a different voltage level than the supplied power. The bias generator can be provided on the wafer or off chip. In another case, the bias generator boosts the voltage of the PMOS base contact to a voltage higher than the voltage VDD and lowers the voltage of the NMOS base contact to a voltage lower than the reference voltage VSS. Such a substrate bias is significantly reduced by the sub-critical voltage leakage current in the low power mode, thereby preserving the total amount of power. However, large integrated devices, such as microprocessors, do not often require the entire device to operate in a low power mode. When some components of the microprocessor are not in use, it is necessary to reduce the subcritical leakage of this component. Flow, this is an urgent problem to be solved in the prior art.

In view of this, a microprocessor according to an embodiment includes: a first power supply node, a functional block, a first substrate bias wire, a first charging node, a first selection circuit, and a substrate bias circuit. The first power supply node provides a first core voltage. The functional block has a plurality of power modes including one or more semiconductor devices coupled to the first substrate bias wires wound from the functional blocks and the first substrate bias wires coupled to the substrate contacts of the at least one semiconductor device. a first selection circuit, configured to couple the first substrate bias wire to the first charging node when the functional block is in the low power mode, and clamp the first base bias wire to the first power supply node when the functional block is in the full power mode . The substrate biasing circuit charges the first charging node to a first substrate bias voltage relative to a first offset voltage of the first core voltage when the functional block is in the low power mode.

The first selection circuit may include a semiconductor device coupled between the first power supply node and the first substrate bias wire or the first selection circuit selectively enabling the first substrate bias wire and the first charging node Semiconductor device. The control device of the substrate bias circuit can control the first selection circuit. The first selection circuit can include a level shifting circuit for controlling the semiconductor device to ensure that each semiconductor device is non-conductive. The functional block can include additional clamping means for clamping the first substrate biasing wire. The level shifting circuit and the buffer can control the clamping device. The functional block can include a second substrate biasing wire, wherein the microprocessor can include a second charging node and a second selection circuit. The substrate bias circuit can include a bias generator, and the bias generator will A charging node is charged such that the first charging node has a positive voltage offset relative to the first core voltage, and when the functional block is in the low power mode, the bias generator charges the second charging node to cause the second charging The node has a negative voltage offset with respect to the second core voltage.

An integrated circuit according to an embodiment of the present invention includes a substrate, a functional block, a first substrate bias wire and a second substrate bias wire, a supply semiconductor supply core voltage and a reference voltage, and a substrate bias circuit.

A method of selecting a substrate bias voltage for a semiconductor device of a functional block of a microchip according to an embodiment, wherein the microprocessor chip includes a substrate bias wire wound around a functional block for reducing a semiconductor device At least one critical leakage current. The method includes: when the functional block is in the first power state, clamping the voltage of the substrate bias wire to the core voltage, and when the functional block is in the second power state, the base bias wire is not clamped and the substrate bias wire is driven to the substrate bias Pressure.

The method includes enabling a clamping device coupled between the substrate biasing wire and the first core voltage. The above method can include driving the gate of the semiconductor device to one of a second core voltage and a substrate bias. The above method can include shifting the level of the coincidence signal to switch between the substrate bias and the second core voltage, and providing a level shift enable signal to the gate of the semiconductor. The step of driving the substrate biasing conductor includes charging the charging node to an offset voltage relative to one of the first core voltages, and coupling the substrate biasing conductor to the charging node.

The above objects, features and advantages of the present invention will become more apparent and obvious. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment will be described below in detail with reference to the accompanying drawings.

Example:

Those skilled in the art can create and use the present invention from the following description, depending on its actual application and needs. However, those skilled in the art can change the preferred embodiment to apply to other embodiments. Therefore, the objectives of the present invention are not limited to the embodiments shown, but are also intended to cover the broad scope and novel features

The inventors considered the need to reduce the sub-critical leakage current of the functional blocks of the microprocessor when the functional block was shut down or in the low power mode, thus developing a micro with a selected substrate bias. The processor reduces the sub-critical leakage current in the functional block and is described in Figures 1 through 6 below.

1 is a schematic diagram showing an embodiment of an integrated circuit 100 including a CMOS device integrated on a P-type substrate 101 and a substrate bias circuit 102 integrated on the integrated circuit 100 according to an embodiment. . Although the specific structure shown is a twin well process, other types of processes (such as N-well, P-well, and 3-story wells) can still be considered ( Triple well), etc. N-type well regions 103, 105 and 107 are formed in P-type substrate 101, and second N-type well region 105 is deep N-well region. Isolated P-type well An isolated P-well region 109 is formed in the deep N-well region 105. The first N-type well region 103 is used to fabricate the P-type channel device 111, and the isolated P-type well region 109 is used to fabricate the N-type channel device 113. Those familiar with this art know the third The N-type well region 107 can be applied to other devices. Although FIG. 1 shows only two devices 111 and 113, those skilled in the art will appreciate that any number of additional devices can be applied to the P-type substrate 101.

Pairs of P-type diffusion regions (P+) 115 and 117 and N-type diffusion regions (N+) 119 form a P-type channel device 111 in the N-type well region 103. The P-type channel device 111 further includes an over-type of the gate insulator layer 121 over the N-type well region 103 of the P-type diffusion regions 115 and 117. The P-type diffusion region (P+) 115 is formed as a 汲 extreme, labeled "D"; the P-type diffusion region (P+) 117 is formed as a source terminal, labeled "S"; and the gate insulating layer 121 is formed as a gate terminal, labeled It is "G". The gate terminal G and the drain terminal D of the P-channel device 111 are coupled to corresponding signals (not shown) of the integrated circuit 100 according to the special function of the device. The source terminal S of the P-channel device 111 is coupled to a core voltage VDD. In an embodiment, the core voltage VDD is provided by a first power supply node. The N-type diffusion region 119 is formed as a well region or a bulk connection, labeled "B." A substrate bias rail 104 is coupled to the N-type diffusion region 119 to provide a substrate bias voltage VBNA to the P-channel device 111. For the N-type channel device 113, pairs of N-type diffusion regions (N+) 123 and 125 and a P-type diffusion region (P+) 127 are formed in the isolated P-type well region 109 of the N-channel device 113. A gate insulating layer 129 is formed on the P-type well region 109 covering the N-type diffusion regions 123 and 125. The N-type diffusion region 125 is formed as the 汲 terminal D; the N-type diffusion region 123 is formed as the source terminal S; and the gate insulating layer 129 is formed as the gate terminal G. The gate terminal G of the N-type channel device 113 and the 汲 terminal D, A corresponding signal (not shown) coupled to the integrated circuit 100 is coupled according to a particular function of the device. The source terminal S of the N-channel device 113 is coupled to another core voltage VSS, and is referred to as a core reference voltage VSS in order to be distinguished from the core voltage VDD described above. The above reference voltage VSS is a ground signal in the embodiment. In an embodiment, the reference voltage VSS is provided by a second power supply node. The P-type diffusion region 127 is formed as a well region or a substrate contact B. The substrate bias wire 106 is coupled to the P-type diffusion region 127 to provide a substrate bias voltage VBPA to the N-channel device 113.

The core voltage VDD and the reference voltage VSS can be supplied to the entire integrated circuit through a conductor or a conductive line or the like (for example, a conductive via, a conductive node, a conductive wire, a conductive bus bar and a bus bar signal known to those skilled in the art) or Wafer. The substrate biasing wires 104 and 106 can also be implemented through a conductor or a conductive line or the like.

The substrate bias circuit 102 includes a bias generator 112 that outputs a substrate bias voltage VBNA and a substrate bias voltage VBPA to the substrate bias wires 104 and 106, respectively. Although the bias generator 112 is implemented with a charge pump located in the integrated circuit 100 in the embodiment, it is still contemplated to be implemented with other types of voltage generators. The bias generator 112 is controlled by a control signal BCTL provided by the control device 114. The control device 114 has an output terminal for providing a clamp enable signal ENP to an input of a P-type level shifter (LSP) 116, and the P-type level shift circuit 116 has an output provided. Corresponding clamp displacement enable signal PEN to the gate of the P-channel clamp device PC1. The source of the P-channel clamp device PC1 is coupled to the core voltage VDD and its drain is coupled to the substrate to the substrate bias Line 104. The control device 114 has another output terminal, and provides an input terminal of another clamp enable signal ENN to an N-type level shifter (LSN) circuit 118. The N-type level shift circuit 118 has a The output terminal provides a corresponding clamp displacement enable signal NEN to the gate of the N-channel clamp device NC1. The source of the N-channel clamp device NC1 is coupled to the reference voltage VSS and its drain is coupled to the substrate to the substrate biasing conductor 106. The control device 114 switches the clamp enable signals ENP and ENN between the reference voltage VSS of the integrated circuit 100 and the core voltage VDD. The P-type level shifting circuit 116 shifts the voltage range of the clamped shift enable signal PEN to operate between the reference voltage VSS and the substrate bias voltage VBNA and the N-type level shifting circuit 118 shifts the clamped shift enable signal NEN The voltage range is operated between the substrate bias voltage VBPA and the core voltage VDD. Generally, when the control device 114 asserts the clamp enable signal ENP to a low level, the P-type level shift circuit 116 sets the clamp shift enable signal PEN to a low level to turn on the P-channel clamp device PC1. The substrate biases the wire 104 to the core voltage VDD. When the control device 114 sets the clamp enable signal ENP signal to a high level, the P-type level shift circuit 116 sets the clamp shift enable signal PEN to a high level, so that the P-channel clamp device PC1 will not conduct. However, when the control device 114 sets the clamp enable signal ENN to a high level, the N-type level shift circuit 118 sets the clamp shift enable signal NEN to a high level to be turned on, so that the N-channel clamp device NC1 will Turning on to clamp the substrate bias wire 106 to the reference voltage VSS. When the control device 114 sets the clamp enable signal ENN to a low level, the N-channel clamp device NC1 will not conduct.

When the integrated circuit 100 needs to be switched to the normal operating mode for normal operation, the control device 114 will control the bias generator 112 to drive the substrate bias voltage VBNA to the voltage level of the core voltage VDD, and drive the substrate bias voltage VBPA to The voltage level of the reference voltage VSS. Therefore, during the normal operation mode, the bias generator 112 drives the substrate B of the P-channel device 111 to be the core voltage VDD and the substrate B driving the N-channel device 113 to be the reference voltage VSS. At the same time, since the control device 114 sets the clamp enable signal ENP to a low level (so the corresponding clamp shift enable signal PEN is also a low level) due to operation in the normal operation mode, the P-channel clamp device PC1 is turned on. Setting the clamp biasing wire 104 to the core voltage VDD and the control device 114 to set the clamp enable signal ENN to a high level (so the corresponding clamped shift enable signal NEN is also at a high level) will cause the N-channel clamp device NC1 is turned on to clamp the substrate bias wire 106 to the reference voltage VSS. Although only the P-channel clamp device PC1 for the substrate biasing conductor 104 and the N-channel clamping device NC1 for the substrate biasing conductor 106 are shown, any number of clamping devices can be used along each other. The base bias wires are distributed along the length of the wires 104 and 106.

In the normal mode of operation, substrate bias wires 104 and 106 are routed to each device integrated into P-type substrate 101 (including N-channel device 113 and P-channel device 111), substrate bias VBNA and VBPA It is necessary to maintain the same with the substrate bias wire 104 and the substrate bias wire 106, respectively. Generally, the larger size P-type substrate 101 has larger substrate biasing wires 104 and 106 than the larger integrated devices. The substrate bias wires 104 and 106 can be solid conductors (physical) The impedance of the conductor causes a voltage drop that increases along the length of the wire away from the bias generator 112. If one of the N-channel device 113 and the P-channel device 111 is located relatively far from the bias generator 112, the voltage levels of the substrate bias voltage VBNA and the substrate bias voltage VBPA will be respectively related to the core voltage VDD and the reference voltage. There are significant differences in VSS and have a negative impact on the execution of operational mechanisms. Moreover, the substrate biasing wires 104 and 106 easily transmit noise generated by capacitive coupling or the like, which affects operation and reduces performance.

During the normal mode of operation of an embodiment, the number and position of the clamping devices are based on the predetermined minimum voltage level of the respective substrate bias wires relative to the corresponding core voltage VDD and reference voltage VSS. In this manner, when the clamping device is enabled, the voltage of the substrate biasing conductor 104 is clamped to a core voltage VDD having a predetermined minimum voltage level, and the voltage of the substrate biasing conductor 106 is clamped to have a predetermined minimum voltage level. Reference voltage VSS. The clamping mechanism described above reduces noise generated by capacitive coupling effects and minimizes voltage variations across the substrate biasing wires 104 and 106. In one embodiment, after the substrate bias wires 104 and 106 are clamped to the core voltage VDD and the reference voltage VSS, if less noise is required and power is maintained, the bias generator 112 can be shut down or Switch to low power mode.

When the integrated circuit 100 is required to operate in the low power mode, the control device 114 sets the clamp enable signal ENP to a high level and the clamp enable signal ENN to a low level to not turn on the clamp devices PC1 and NC1. It should be noted that the integrated circuit 100 may have multiple operating states or operating modes, the above multiple The operational state or mode of operation includes one or more low power modes or low power states. The low power mode described above is that at least a portion of the integrated circuit 100 is in a low power condition or is off. In the low power mode, the control device 114 also controls the bias generator 112 and drives the substrate bias voltage VBNA above the core voltage VDD with a first substrate bias offset voltage and is offset by a second substrate. The voltage drives the substrate bias voltage VBPA to be lower than the reference voltage VSS. According to the actual structure, the first substrate offset voltage and the second substrate offset voltage may be the same or different voltages. That is, in the low power mode, the substrate bias voltage VBNA has a positive voltage offset with respect to the core voltage VDD, and the substrate bias voltage VBPA has a negative voltage offset with respect to the reference voltage VSS. Therefore, in the low power mode, the substrate voltage of the P-channel device 111 is driven to a voltage higher than the core voltage VDD, and the substrate voltage of the N-channel device 113 is driven to a voltage lower than the reference voltage VSS, so that the above two The subcritical leakage current of the device is minimized.

The operation mechanism of the P-type level shifting circuit 116 shifting the voltage of the clamped shift enable signal PEN to the substrate bias voltage VBNA will be further described below when the clamp enable signal ENP is set to the core voltage VDD. During the low power mode of the mechanism, the clamp enable signal ENP will be switched between the reference voltage VSS and the core voltage VDD, and the clamp shift enable signal PEN is switched between the reference voltage VSS and the substrate bias voltage VBNA. The substrate bias voltage VBNA is driven above the core voltage VDD. When the bias generator 112 drives the substrate bias voltage VBNA higher than the core voltage VDD, the P-type level shifting circuit 116 will ensure that the P-channel clamp device PC1 is low. In power mode, it is not conductive at all. More specifically, when the bias generator 112 drives the substrate bias voltage VBNA higher than the core voltage VDD, the control device 114 sets the clamp enable signal ENP to the core voltage VDD and clamps the P-channel. Device PC1 is not conducting. If the clamp enable signal ENP is directly supplied to the gate of the P-channel clamp device PC1, the gate potential of the P-channel clamp device will be only at the core voltage VDD and the potential of the drain will be higher than the core voltage. VDD may cause the P-channel clamp PC1 to be partially turned on. However, the P-type level shifting circuit 116 drives the voltage level of the clamp shift enable signal PEN to the base bias voltage VBNA, so the gate and the drain of the P-channel clamp device PC1 are both higher than the core voltage VDD. The substrate biases the voltage level of VBNA to ensure that the P-channel clamp PC1 is completely non-conducting.

In a similar manner to the above, when the clamp enable signal ENN is set to the reference voltage VSS, the N-type level shifting circuit 118 will shift the voltage of the shift enable signal NEN to the substrate bias voltage VBPA. Therefore, in the low power mode, the clamp enable signal ENN is switched between the reference voltage VSS and the core voltage VDD, and the clamp shift enable signal PEN is switched between the substrate bias voltage VBPA and the core voltage VDD to drive the substrate bias. VBPA is lower than the reference voltage VSS. When the bias generator 112 drives the substrate bias voltage VBPA below the reference voltage VSS, the N-type level shifting circuit 118 will ensure that the N-channel clamp device NC1 is completely non-conducting in the low power mode. More specifically, when the bias voltage generator 112 drives the substrate bias voltage VBNA to be lower than the reference voltage VSS, the control device 114 sets the level of the clamp enable signal ENN to the reference voltage VSS to not turn on the N-channel clamp device NC1. . If the clamp enable signal ENN is directly supplied to the gate of the N-channel clamp device NC1, the potential of the gate of the N-channel clamp device NC1 will be only at the reference voltage VSS and the potential of the drain will be lower than the reference voltage. VSS may cause the N-channel clamp device NC1 to be partially turned on. However, the voltage level of the clamp shift enable signal NEN to the substrate bias voltage VBPA is driven by the N-type level shift circuit 118, so the potentials of the gate and the drain of the N-type level shift circuit 118 are lower than the reference. The voltage of the substrate of the voltage VSS is biased to the voltage level of VBPA to ensure that the N-channel clamp device NC1 is not conducting.

When switching from the low power mode to the normal operating mode is required, the control device 114 drops the control bias generator 112 to drive the substrate bias voltage VBNA back to the core voltage VDD, and pulls the drive substrate bias voltage VBPA back to the reference voltage VSS. Next, the control device 114 drives the clamp enable signal ENP to a low level and the clamp enable signal ENN to a high level to turn on the P-channel clamp device PC1 and the N-channel clamp device NC1.

2 is a block diagram showing a substrate bias circuit 202 and a die integrated into the microprocessor 200 to minimize sub-critical leakage currents in the functional block 208 on the microprocessor 200, in accordance with an embodiment. The device and composition of the substrate biasing circuit 202 operate in a manner similar to the substrate biasing circuit 102. The bias generator 112 can be replaced by an approximately functional bias generator 212 having an output that provides a charging voltage level NCHG and a charging voltage level PCHG, respectively, placed on the conductive signal lines 203 and 205. Conductive signal lines 203 and 205 will be routed by substrate bias circuit 202 to functional block 208 of microprocessor 200. The following will be The energy block 208 is in a low power mode, and the voltages of the charging voltage level NCHG and the charging voltage level PCHG are selectively applied to drive the substrate bias voltage VBNA and the substrate bias voltage VBPA on the substrate bias wires 204 and 206, respectively. Do further description. The substrate bias wires 204 and 206 wound in the functional block 208 will provide a substrate bias voltage VBNA and a substrate bias voltage VBPA to the P-channel device and the N-channel device integrated into the microprocessor of the functional block. The conventional P-channel device P1 shown in functional block 208 has a substrate contact coupled to a substrate biasing conductor 204 that approximates the P-channel device 111. Similarly, the N-type channel device N1 shown in the functional block 208 has a substrate contact coupled to the substrate biasing conductor 206, which approximates the N-channel device 113. Although only one P-type channel device P1 and one N-type channel device N1 are shown, in the above similar method, any number of devices (P-channel device and N-channel device) in the distribution function block 208 are There are corresponding substrate contacts connected to applicable substrate bias wires 204 and 206.

Control device 214, similar to control device 114, replaces control device 114, which provides clamp enable signals ENP and ENN and control signal BCTL that are similar to control device 114. The mechanism of operation is similar to that of the control device 114 of the integrated circuit 100 previously shown. The clamp enable signals ENN and ENP are transmitted from the substrate bias circuit 202 to the functional block 208 using corresponding conductive signal lines. Control signal BCTL is used to control bias generator 212. The voltage from the charging voltage level NCHG and the charging voltage level PCHG is applied to the driving substrate bias voltage VBNA and the substrate bias voltage VBPA, and the bias generator sends the charging voltage level NCHG and the charging voltage. The method of leveling the PCHG voltage approximates the method in which the bias generator 112 of the integrated circuit 100 previously shown sends the substrate bias voltage VBNA and the substrate bias voltage VBPA.

The microprocessor 200 has a plurality of operational states or modes of operation, as described above for the integrated circuit 100. The above mode of operation includes one or more low power modes or low power states, and the low power mode refers to selectively causing at least a portion of the microprocessor 200 to be in a low power state or not operating, the mechanism described above being similar to the previous integrated body. The manner in which circuit 100 is shown. As shown in the embodiment, the functional block 208 will utilize the control device 214 or other circuitry (not shown), either in a fully conductive state (full power state or full power mode) and selectively in one of the low power modes. When the functional block 208 is in the full power mode, the control device 214 will disable the bias generator 212 or be in a low power state, or control the bias generator 212 to drive the charging voltage level NCHG and the charging voltage level PCHG. The voltage is respectively applied to the voltage level of the core voltage VDD and the reference voltage VSS. During the full power mode of the function block 208, the control device 214 sets the clamp enable signal ENP to a low level, and turns on the P-channel clamp device of the function block 208 to clamp the base bias wire 204 as a core voltage. VDD. Similarly, the control device 214 in the full power mode sets the clamp enable signal ENN to a high level and turns on the N-channel clamp of the functional block 208 to clamp the base bias wire 206. It is the reference voltage VSS. When the function block 208 is in the low power mode, the control device 214 will control the bias circuit generator or turn it on to drive the charging voltage level NCHG higher than the core voltage VDD and the driving charging voltage level PCHG lower than the reference. Voltage VSS. The control device 214 sets the clamp enable signal ENP to a high level and disables the P-channel clamp device and drives the substrate bias voltage VBNA of the substrate bias conductor 204 to the voltage level of the charge voltage level NCHG. Similarly, the control device 214 in the low power mode sets the clamp enable signal ENN to a low level to disable the N-channel clamp device and drive the substrate bias voltage VBPA to the base bias conductor 206 to a charge voltage level. The voltage level of PCHG.

The functional block 208 includes a P-type channel selection circuit 216 and an N-type channel selection circuit 218. The P-type channel selection circuit 216 and the N-type channel selection circuit 218 are controlled by the clamp enable signals ENP and ENN, respectively, for selectively driving the substrate bias wires 204 and 206 to be the charging voltage level NCHG and the charging voltage level PCHG. Voltage level. The P-type channel selection circuit 216 includes a P-type level shifting circuit 221 having an input terminal for receiving the clamp enable signal ENP and an output terminal for providing an enable signal PENCH to P-type. The gate of the channel clamp device PA and the input of the inverter 217. The P-channel clamp device PA has a source coupled to the core voltage VDD and a drain coupled to the substrate biasing conductor 204. The output of the inverter 217 is coupled to the gate of another P-channel clamp device PB. The P-channel clamp device PB has a source that receives the voltage of the charging voltage level NCHG and a drain-base coupled to the substrate biasing conductor 204. As shown, the inverter 217 has a power line coupled between the reference voltage VSS and the charging voltage level NCHG. Therefore, its output can be switched between the core voltage VSS and the voltage level of the charging voltage level NCHG. N-type channel selection circuit 218 includes an N-type level shift circuit 233. The N-type level shifting circuit 233 has an input terminal for receiving the clamp enable signal ENN and an output terminal for providing an output of the enable signal NENCH to the gate of the N-channel clamp device NB and the output of the inverter 219. end. The N-channel clamp device NB has a source coupled with a reference voltage VSS and its drain and substrate coupled to the substrate biasing conductor 206. The output of the inverter 219 is coupled to the gate of another N-channel clamp device NA. The N-channel clamp device NA has a voltage at which the source receives the charging voltage level PCHG and its drain is coupled to the substrate biasing conductor 206. As shown, the inverter 219 has a power line coupled to the voltage of the core voltage VDD and the charging voltage level PCHG. Therefore, its output can be switched between the core voltage VDD and the voltage level of the charging voltage level PCHG.

The P-type channel selection circuit 216 can pass through the P-channel clamp device PA to clamp the substrate bias voltage VBNA to the core voltage VDD according to the clamp enable signal ENP, or to drive the substrate bias through the P-channel clamp device PB. The voltage of the VBNA to the voltage of the charging voltage level NCHG. The operation method of the P-type level shift circuit 221 approximates the P-type level shift circuit 116. During the full power mode of the functional block 208, when the clamp enable signal ENP is set to the reference voltage VSS, the P-channel clamp device PA will be turned on to clamp the potential of the substrate bias voltage VBNA to the core voltage VDD. The inverter 217 sets its output to the charging voltage level NCHG, which will drive the gate of the P-channel clamp device PB to a very high level so that the P-channel clamp device PB is not turned on. When the clamp enable signal ENP is set to the core voltage VDD in the low power mode, the P-type level shift circuit 221 sets the enable signal PENCH to the charging voltage level NCHG, so that P The type channel clamp device PA is not turned on and the inverter 217 sets its output terminal to the reference voltage VSS to turn on the P-type channel clamp device PB. When the P-channel clamp device PB is turned on, the substrate bias voltage VBNA disposed on the substrate bias wire 204 is the charge voltage level NCHG of the bias generator 212. In an approximate manner, the N-type channel selection circuit 218 can be converted to the clamp base bias voltage VBPA to the reference voltage VSS through the N-channel clamp device NB according to the clamp enable signal ENN, or through the N-channel device NA. The voltage of the substrate bias voltage VBPA is pushed to the voltage of the charging voltage level PCHG. The mode of operation of the N-type level shifting circuit 223 approximates the N-type level shifting circuit 118. During the full power mode of the function block 208, the level of the clamp enable signal ENN is set to the core voltage VDD, and the N-type level shift circuit 223 sets the enable signal NENCH to the core voltage VDD to make the N-type channel. The clamping device NB is turned on to clamp the substrate bias voltage VBPA to the reference voltage VSS. The inverter 219 sets its output to the charging voltage level PCHG to push the gate of the N-channel device NA to a very low level and make it non-conductive. When in the low power mode, the clamp enable signal ENN is set to the reference voltage VSS, and the N type level shift circuit 223 sets the enable signal NENCH to the charging voltage level PCHG, and causes the N-channel clamp device NB not to Turning on and the inverter 219 sets its output to the core voltage VDD, which will turn on the N-channel clamp NA. When the N-channel clamp device NA is turned on, the substrate bias voltage VBPA disposed on the substrate bias wire 206 is the voltage of the charge voltage level PCHG of the bias generator 212.

During the full power mode of the functional block 208, the P-channel clamp device PA and the N-channel clamp device NB clamp the base bias wires respectively. The substrate bias voltage VBNA of 204 is at the voltage level of the substrate bias voltage VBPA of the substrate bias wire 206, and the voltages of the substrate bias voltage VBNA and the substrate bias voltage VBNA are respectively clamped to the core voltage VDD and the reference voltage VSS. Functional block 208 can include additional P-channel clamps and N-channel clamps. As shown, the functional block 208 includes a P-channel clamp device PC1 coupled to the substrate biasing conductor 204 and an N-channel clamp device NC1 coupled to the substrate biasing conductor 206. The source of the P-channel clamp device PC1 is coupled to the core voltage VDD, and the drain of the P-channel clamp device PC1 is coupled to the substrate biasing conductor 204. The source-coupled core voltage VSS of the N-channel clamp device NC1 is coupled to the substrate biasing conductor 206 by its source and substrate. The clamp enable signal ENP is provided to the P-type level shift circuit 220. The P-type level shifting circuit 220 provides a corresponding clamped shift enable signal PEN and pushes the clamped shift enable signal PEN to the gate of the P-channel clamp device PC1. The P-type level shift circuit 220 operates in the same manner as the P-type level shift circuit 116, so when the clamp enable signal ENP is switched between the reference voltage VSS and the core voltage VDD, the clamp shift enable signal PEN is switched. Between the reference voltage VSS and the substrate bias voltage VBNA. The clamp enable signal ENN is provided at an input end of the N-type level shift circuit 222, the N-type level shift circuit 222 provides a corresponding clamp shift enable signal NEN, and drives the clamp shift enable signal NEN To the gate of the N-channel clamp IC1. The N-type channel level shifting circuit 222 operates in the same manner as the N-channel level shifting circuit 118, so when the clamp enable signal ENN is switched between the reference voltage VSS and the core voltage VDD, the shift enable signal is clamped. NEN is switched between the substrate bias voltage VBPA and the core voltage VDD. to In the full power mode of the function block 208, the control device 214 sets the clamp enable signal ENP to the reference voltage VSS, so the clamp shift enable signal PEN is also set to the reference voltage VSS, so that the P-channel clamp device PC1 is turned on. The wire 204 is biased to the core voltage VDD by clamping the substrate. Similarly, in the full power mode, the control device 214 sets the clamp enable signal ENN to the core voltage VDD, so the clamp shift enable signal NEN is also set to the core voltage VDD, and the N-channel clamp device NC1 is turned on to clamp The substrate bias wire 206 is a reference voltage VSS. In the low power mode of the function block 208, when the substrate bias voltage VBNA is set to be higher than the voltage of the charging voltage level NCHG of the core voltage VDD, the clamp enable signal ENP is set to the core voltage VDD, so the shift enable signal is clamped. PEN is set to the voltage level of the substrate bias voltage VBNA to keep the P-channel clamp device PC1 completely non-conductive. Similarly, in the low power mode, when the substrate bias voltage VBPA is set to be lower than the voltage of the charging voltage level PCHG of the reference voltage VSS, the clamp enable signal ENN will be set to the reference voltage VSS, so the shift enable signal is clamped. NEN is set to the voltage level of the substrate bias voltage VBPA to keep the N-channel clamp device NC1 completely non-conductive.

In one embodiment, during the full power mode of functional block 208, the potential of functional block 208 is relatively small and the potentials of clamps PC1 and NC1 are sufficiently large that base bias wires 204 and 206 are clamped to core voltage, respectively. VDD and reference voltage VSS. For example, with a given bias level, the clamping devices PC1 and NC1 are themselves sufficient to ensure that the voltage across the substrate biasing conductors 204 and 206 varies from the core voltage and the reference voltage by a predetermined minimum voltage level. In another embodiment, such as a larger work The energy block 208 or when a large number of P-type and N-channel devices are coupled to the substrate bias wires, at least one additional device is coupled to each of the substrate bias wires 204 and 206 in the functional block 208 (as shown in the figure). Additional clamping devices PC1 and NC1) are shown. In various embodiments, any additional number of devices may be provided in functional block 208 to clamp substrate biasing conductor 204 to core voltage VDD and to clamp substrate biasing conductor 206 to reference voltage VSS for minimizing voltage variations. . As shown, another P-type channel clamp device PCN at function block 208 is coupled to the substrate biasing conductor 204. In the method of the foregoing approximation, the drain of the P-channel clamp device PCN and the substrate are coupled to the substrate biasing conductor 204 and its source is coupled to the core voltage VDD. The P-channel clamp PCN can be any additional number of P-channel clamps used to clamp the substrate bias 204 to the core voltage VDD. Similarly, another N-type channel clamping device NCN at function block 208 is coupled to the substrate biasing conductor 206. In the foregoing approximation, the source and the substrate of the N-channel clamp device NCN are coupled to the substrate bias wire 206 and the source is coupled to the reference voltage VSS. The N-channel clamp NCN can be any number of additional N-channel clamps used to clamp the substrate bias wire 206 to the reference voltage VSS.

The P-channel clamp device PCN and the N-channel clamp device NCN are coupled to the substrate bias wires 204 and 206, respectively, and require a level-shifed signal PEN and NEN to drive the P-channel, respectively. The clamping device PCN and the N-channel clamping device NCN ensure that the clamping device is completely non-conducting in the low power mode. If the clamp shift enable signals PEN and NEN fail to provide sufficient power to drive an additional clamp, the voltage shift buffer circuit will be enabled. In an embodiment The clamp shift enable signal PEN is provided to the input of a p-type buffer (PBUF) 224 such that the output of the P-type buffer 224 pushes the gate of the clamp device PCN, and the clamp shift enables Signal NEN provides an input to an n-type buffer (NBUF) 226 such that the output of N-type buffer 226 pushes the gate of clamp device NCN. In any type of embodiment, voltage variations along the substrate biasing wires 204 and 206 are required to be minimized and any number of buffers and clamping devices included will be considered.

When the functional block 208 is in the low power mode, the control device 214 or the control bias generator 212 is used to drive the charging voltage level NCHG with the first substrate offset voltage higher than the core voltage VDD and utilize the first The voltage of the two substrate offset voltage driving charging voltage level PCHG is lower than the reference voltage VSS. The first substrate offset voltage and the second substrate offset voltage may be the same or different voltage levels. The control device 214 sets the clamp enable signal ENP to the high level and the clamp enable signal ENN signal to the low level, so the voltage of the charging voltage level NCHG is set to the voltage of the substrate bias voltage VBNA on the substrate biasing conductor 204. And the voltage of the charging voltage level PCHG is set to be the voltage of the substrate bias voltage VBPA on the substrate biasing wire 206. In this manner, during the low power mode, the P-type channel device P1 biased to the functional block 208 and the base of the other P-type channel device and the base of the N-channel device and the other N-channel device are reduced or minimized. The sub-critical leakage current in the functional block 208 of the low power mode. The clamping devices PA and NB in function block 208 and any additional clamping devices (e.g., PC1, PCN, NC1, NCN) will not conduct.

The functional block 208 is brought back to the normal operating mode by the low power mode, and the control device 214 will first control the bias generator 212 to drive the charging voltage level NCHG and the substrate bias voltage VBNA and the charging voltage of the substrate bias wires 204 and 206. The level PCHG and the substrate bias VBPA voltage are returned to the voltage levels of the core voltage VDD and the reference voltage VSS, respectively. Next, the control device 214 sets the clamp enable signal ENP to a low level and the clamp enable signal ENN to a high level, so that the clamp device is turned on and the base bias wires 204 and 206 are not coupled to the charging voltage level NCHG. With the charging voltage level PCHG. In various types of embodiments, during operation of the functional block 208 in the normal mode, the control device 214 may further disable the bias generator 212 or cause it to be in a low power mode, or a standby mode to retain electric power.

During the normal mode of operation of an embodiment, the clamping device is placed along the substrate biasing conductor to ensure that when the clamping device is enabled, the voltage of each of the substrate biasing conductors does not vary from the core voltage to the reference voltage. An established minimum voltage level. In one embodiment, the predetermined minimum voltage level is approximately 10 millivolts (mV). If the P-channel clamps PA and NB are unable to meet the voltage variation maintained at a given minimum voltage level, additional clamping devices (such as PC1, PCN, NC1, NCN, etc.) will be distributed along the substrate bias wires. In one embodiment, the actual position of the clamping device on the substrate biasing conductors 204 and 206 will depend on mathematical model analysis or dynamic simulation to maintain voltage and noise minimization to achieve optimal microprocessor 200. Performance performance.

Functional block 208 can be any size or type of work in the microprocessor The power unit, the microprocessor can selectively require power down of the functional unit or the functional block in any case (such as conserve power or heat reduction). For example, the function block 208 can be one of a data unit, a data catch unit, an integer unit, and a floating point unit (FPU). When the power of the functional block 208 is turned off, the substrate bias wires 204 and 206 will be respectively charged to offset bias with respect to one of the core voltage level VDD and the reference voltage level VSS to bias the functional block 208. The base of the P-type or N-type device is used to reduce the sub-critical leakage current. When the functional block 208 is operating normally, the clamping device clamps the base bias wires 204 and 206 to the core voltage level and the reference voltage level, minimizes voltage variation and noise, and improves circuit execution and operation. .

3 shows a P-type level shifting circuit 300 according to an embodiment of the invention. The above embodiment can also be applied to P-type level shifting circuits 116 and 220. The P-type level shifting circuit 300 includes an inverter 302, four P-type channel devices P1, P2, P3, and P4, and N-type channel devices N1, N2, N3, and N4. P-channel devices P1, P2, P3, and P4, respectively, have a source and an internal substrate coupled to a substrate biasing conductor 304 for providing a substrate bias voltage VBNA, said substrate biasing conductor 304 representing a substrate bias One of the voltages of the VBNA is a substrate biased conductor (such as 104 or 204). The N-type channel devices N1, N2, N3, and N4 have a source and an internal substrate coupled to the reference voltage VSS, respectively. The clamp enable signal ENP can be provided to the gate of the P-type channel device P1 and the input of the inverter 302. The drain of the P-type channel device P1 is coupled to the drain and gate of the N-channel device N1 The pole, and the gate of the N-channel device N2. The output end of the inverter 302 is coupled to the gate of the P-type channel device P2, and the drain of the P-type channel device P2 is coupled to the drain of the N-type channel device N2 and the P-channel device P3 and the N-channel device N3. Gate. The drain of the P-type channel device P3 is coupled to the drain of the N-channel device N3 and the gates of the P-channel device P4 and the N-channel device N4. The drain of the P-type channel device P4 is coupled to the drain of the N-channel device N4 to output a clamped shift enable signal PEN. In the operating mechanism, the input clamp enable signal ENP will be set between the reference voltage VSS and the core voltage VDD. The output clamp shift enable signal PEN will be set between the reference voltage VSS and the substrate bias voltage VBNA. When the clamp enable signal ENP is set to the reference voltage VSS, the P-type channel device P1 is turned on and the P-type channel device P2 is turned off (the output of the inverter 302 is the core voltage VDD). The P-type channel device P1 pushes the level of the gate of the N-type channel device N2 to rise to the substrate bias voltage VBNA, so the N-type channel device N2 will be turned on. The N-type channel device N2 pushes the gates of the P-type channel device P3 and the N-type channel device N3 to the reference voltage VSS, so that the P-type channel device P3 will be turned on without turning on the N-type channel device N3. The P-type channel device P3 pushes the gate-to-substrate bias VBNA of the P-channel device P4 and the N-channel device N4, and turns on the N-channel device N4 and the non-conducting P-channel device P4. Therefore, when the clamp enable signal ENP is set to the reference voltage VSS, the clamp shift enable signal PEN is made to be the reference voltage VSS through the N-channel device N4. When the clamp enable signal ENP is set to the core voltage VDD, the P-type channel device P1 is not turned on and the P-type channel device P2 is turned on. Since the P-channel device P1 is non-conducting, the N-channel device N1 will push The gate of the N-channel device N2 is extremely low, so the N-channel device N2 will not conduct. The P-type channel device P2 pushes the gate of the P-channel device P3 and the N-channel device N3 to the substrate bias voltage VBNA, and the P-channel device P3 is not turned on and the N-channel device N3 is turned on. The N-type channel device N3 pushes the gates of the P-type channel device P4 and the N-type channel device N4 to the reference voltage VSS, and turns on the P-type channel device P4 without conducting the N-type channel device N4. Therefore, when the clamp enable signal ENP is set to the core voltage VDD, the P-type channel device P4 pushes the clamp shift enable signal PEN to the substrate bias voltage VBNA. In this manner, the clamp enable signal ENP is switched between the reference voltage VSS and the core voltage VDD, and the output clamp shift enable signal PEN is switched between the reference voltage VSS and the substrate bias voltage VBNA.

Figure 4 is a diagram showing an N-type level shifting circuit 400 in accordance with an embodiment of the present invention, wherein the above-described embodiments are also applicable to N-type level shifting circuits 118 and 222. The LSN circuit 400 includes an inverter 402, four P-channel devices P1, P2, P3 and P4 and four N-channel devices N1, N2, N3 and N4. The P-type channel devices P1, P2, P3, and P4 have a source and an internal substrate coupled to the core voltage VDD, respectively. The N-type channel devices N1, N2, N3, and N4 respectively have a source and an internal substrate coupled to a substrate biasing wire 404 that provides a substrate bias voltage VBPA, and the substrate biasing wire 404 can be a voltage that provides a substrate bias voltage VBPA. A substrate biased wire (such as 106 or 206). The clamp enable signal ENN is provided to the gate of the N-type channel device N1 and the input of the inverter 402. The drain and the gate of the P-type channel device P1 are coupled to the drain of the N-channel device N1 and the gate of the P-channel device P2. The output of the inverter 402 is coupled to the N-type The gate of the N-channel device N2 is coupled to the drain of the P-channel device P2 and the gate of the P-channel device P3 and the N-channel device N3. The drain of the P-type channel device P3 is coupled to the drain of the N-channel device N3 and the gates of the P-channel device P4 and the N-channel device N4. The P-type channel device P4 is coupled to the drain of the N-type channel device N4 and outputs a clamped shift enable signal NEN signal. In the operating mechanism, the input clamp enable signal ENN is set between the reference voltage VSS and the core voltage VDD. The output clamp shift enable signal NEN is set between the core voltage VDD and the substrate bias voltage VBPA. When the clamp enable signal ENN is set to the core voltage VDD, the N-channel device N1 and the non-conducting N-channel device N2 are turned on (the output of the inverter 402 is the reference voltage VSS). The N-type channel device N1 pushes the gate of the P-type channel device P2 to the substrate bias voltage VBPA, so that the P-type channel device P2 is turned on. The P-type channel device P2 pushes the gates of the P-channel device P3 and the N-channel device N3 to the core voltage VDD, so the P-channel device P3 is not turned on and the N-channel device N3 is turned on. The N-type channel device N3 pushes the gate of the P-channel device P4 and the N-channel device N4 to the substrate bias voltage VBPA, so that the N-channel device N4 is not turned on and the P-channel device P4 is turned on. Therefore, when the clamp enable signal ENN is set to the core voltage VDD, the clamp shift enable signal NEN pushed through the P-type channel device P4 is the core voltage VDD. When the clamp enable signal ENN is set to the reference voltage VSS, the N-channel device N1 will not be turned on and the N-channel device N2 will be turned on. Since the N-type channel device N1 is non-conducting, the P-type channel device P1 pushes the gate of the P-type channel device P2 to a very high level, so the P-type channel device P2 is not turned on. N-channel device N2 pushes the gate-to-substrate bias voltage VBPA of the P-type channel device P3 and the N-type channel device N3, and turns on the P-type channel device P3 without conducting the N-type channel device N3. The P-type channel device P3 pushes the gates of the P-channel device P4 and the N-channel device N4 to the core voltage VDD, and will not turn on the P-channel device P4 to turn on the N-channel device N4. Therefore, when the clamp enable signal ENN is set to the reference voltage VSS, the N-type channel device N4 pushes the clamp shift enable signal NEN to the substrate bias voltage VBPA. In this manner, the clamp enable signal ENN is switched between the reference voltage VSS and the core voltage VDD, and the clamp shift enable signal NEN is switched between the substrate bias voltage VBPA and the core voltage VDD.

Figure 5 is a diagram showing a P-type buffer 224 in accordance with an embodiment of the present invention. The clamp shift enable signal PEN is supplied to the gates of the P-channel device P1 and the N-channel device N1. The source of the P-channel device P1 is coupled to the substrate biasing conductor 204 (providing the substrate bias voltage VBNA) and the drain of the P-channel device P1 is coupled to the drain of the N-channel device N1. The P-channel device P1 and the N-channel device N1 are coupled to the gates of the P-channel device P2 and the N-channel device N2. The P-type channel device P2 is coupled to the substrate biasing conductor 204 at the source and the substrate. The drain of the P-type channel device P2 is coupled to the drain of the N-channel device N2. The source of the N-type channel devices N1 and N2 is coupled to the core voltage VSS and the drain output buffer clamp enable signal BPEN of the P-channel device P2 and the N-channel device N2. The N-type channel devices N1 and N2 have a substrate (internal) coupled to the reference voltage VSS. Under the operating mechanism, when the driving clamp shift enable signal PEN is the reference voltage VSS, both the P-channel device P1 and the N-channel device N2 It will be turned on; when the P-type channel device P2 and the N-type channel device N1 are not turned on, the buffer clamp shift enable signal BPEN will be driven to the reference voltage VSS. When the clamp displacement enable signal PEN is the substrate bias voltage VBNA, neither the P-channel device P1 nor the N-channel device N2 is turned on; when the P-channel device P2 and the N-channel device N1 are both turned on, the buffer clamp is pushed. The shift enable signal BPEN is applied to the substrate bias voltage VBNA. In this manner, the buffer clamp shift enable signal BPEN and the clamp shift enable signal PEN are set to the same logic state and the buffer clamp shift enable signal BPEN is switched to the level of the reference voltage VSS and the substrate bias VBNA. Between voltage zones.

Figure 6 shows an N-type buffer 226 in accordance with an embodiment of the present invention. The clamp shift enable signal NEN is supplied to the gates of the P-channel device P1 and the N-channel device N1. The source of the P-type channel device P1 is coupled to the core voltage VDD and the drain of the P-type channel device P1 is coupled to the drain of the N-channel device N1. The source of the N-type channel device N1 is coupled to the substrate with a substrate biasing conductor 206 (provided to the substrate bias voltage VBPA). The P-channel device P1 and the N-channel device N1 are coupled to the gates of the P-channel device P2 and the N-channel device N2. The source of the P-type channel device P2 is coupled to the core voltage VDD and the drain of the P-type channel device P2 is coupled to the drain of the N-channel device N2. The source and base of the N-type channel device N2 are coupled to the base biasing conductor 206 and the drain of the P-channel device P2 and the drain output buffering displacement enable signal BNEN of the N-channel device N2. Both P-channel devices P1 and P2 have a substrate (internal) coupled to the core voltage VDD. Under the operating mechanism, when the clamp shift enable signal NEN is pushed to the substrate bias voltage VBPA, both the P-channel device P1 and the N-channel device N2 will be turned on, and at the same time The P-type channel device P2 and the N-type channel device N1 are not turned on, so the buffer clamps the shift enable signal BNEN to the substrate bias voltage VBPA. When the clamp shift enable signal NEN is the core voltage VDD, the P-channel device P1 and the N-channel device N2 are not turned on; at the same time, the P-channel device P2 and the N-channel device N1 are both turned on to push the buffer clamp The bit enables the signal BNEN to the core voltage VDD. In this manner, the buffer clamp shift enable signal BNEN and the clamp shift enable signal NEN are set to the same logic state and the buffer clamp shift enable signal BNEN is switched to the level shift of the core voltage VDD and the substrate bias voltage VBPA. Between voltage zones.

Figure 7 is a diagram showing a P-type level shift circuit 221 according to an embodiment of the present invention. The P-type level shift circuit 221 is similar to the P-type level shift circuit 300. The P-type level shifting circuit 221 is used to provide a conductive signal line 203 for the voltage of the charging voltage level NCHG instead of the substrate biasing line 304 for providing the substrate bias voltage VBNA. In this manner, the clamp enable signal ENP is set between the reference voltage VSS and the core voltage VDD, wherein the enable signal PENCH is set between the reference voltage VSS and the charge voltage level NCHG. However, the P-type level shift circuit 221 operates in exactly the same manner as the P-type level shift circuit 300.

Figure 8 shows an N-type level shifting circuit 223 in accordance with an embodiment of the present invention. The N-type level shift circuit 223 is similar to the N-type level shift circuit 400. The N-type level shifting circuit 223 is used to provide a conductive signal line 205 for the voltage of the charging voltage level PCHG instead of the substrate biasing line 404 for providing the substrate bias voltage VBPA. In this manner, the clamp enable signal ENN is set between the reference voltage VSS and the core voltage VDD, wherein The energy signal NENCH is set between the core voltage VDD and the charging voltage level PCHG. However, the N-type level shifting circuit 223 operates in exactly the same manner as the N-type level shifting circuit 400.

Many of the possible variables are still to be considered. For example, Fig. 9 shows a microprocessor 200 as shown in Fig. 2 of an embodiment. The substrate biasing circuit 202 and the functional block 208 are provided on the wafer of the microprocessor 200 by the aforementioned approximation, and the P-channel selection circuit 216 and the N-channel selection circuit 218 are located outside the functional block 208. In this scheme, the charging voltage level NCHG and the charging voltage level PCHG will be transmitted from the corresponding conductive signal lines 203 and 205 to the P-type channel selection circuit 216 and the N-type channel selection circuit 218, respectively. The P-type channel selection circuit 216 and the N-type channel selection circuit 218 respectively provide the substrate bias wires 204 and 206 corresponding to the substrate bias voltage VBNA and the substrate bias voltage VBPA. The base biasing wires 204 and 206 of the P-type channel selecting circuit 216 and the N-type channel selecting circuit 218 respectively send the substrate bias voltage VBNA and the substrate bias voltage VBPA to the functional block 208. The method of operation of this scheme is the same as that of the microprocessor 200 of FIG. FIG. 10 is a schematic diagram showing another embodiment of a microprocessor 200 in which a P-type channel selection circuit 216 and an N-type channel selection circuit 218 are located. The substrate bias voltage VBNA and the substrate bias voltage VBPA are directly provided on the substrate bias wires 204 and 206 to the functional block 208. Moreover, the method of operation is the same as that of the microprocessor 200.

Any of the foregoing embodiments can be applied to more types of architectures, and the reference voltage (such as VSS) can be approximated to 0 volts (Volts, V) and the core voltage (eg, VDD) can be approximated to 1V. In one embodiment, the bias generator drives an offset voltage of 800 millivolts (mV) to a corresponding core voltage level and a reference voltage level, respectively. In one embodiment, during the low power mode, when the core voltage VDD is 1V, the charge substrate bias voltage VBNA is approximately 1.8V, and when the reference voltage VSS is 0V, the push-down substrate bias voltage VBPA is approximately -800 millivolts. . The actual core voltage can be varied depending on the mode of operation of the device. For example, under actual architectural mode or actual state, the core voltage VDD can vary between approximately 500 mV and 1.4 V. In an embodiment, the offset voltage of the substrate bias voltage VBNA may be different from the offset voltage of the substrate bias voltage VBNA. For example, the offset voltages are 300 mV and 500 mV, respectively. However, although a bias generator (such as 112 or 212, etc.) is shown on the wafer, a bias generator or charge pump can be provided outside the wafer to charge the substrate bias wires. If it is provided outside the wafer, the operation method of the external control is the same as the foregoing method, but the control device (such as 114 or 214) cannot provide the control signal BCTL outside the wafer or provide other control signals BCTL outside the wafer. In any event, the bias voltage generator or charge pump is used to drive the substrate bias voltages VBNA and VBPA substrate bias wires 104/204 and 106/206, respectively, with an offset voltage relative to the corresponding core voltage and reference voltage.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention, and those skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The protected area of the present invention is subject to the definition of the scope of the patent application.

100‧‧‧ integrated circuit

101‧‧‧P type substrate

102, 202‧‧‧Base bias circuit

109‧‧‧P type well

103, 105, 107‧‧‧N well

111‧‧‧P type channel device

113‧‧‧N type channel device

104, 106, 204, 206, 304, 404‧‧‧ base bias wire

112, 212‧‧‧ bias generator

114, 214‧‧‧ control device

118, 222, 223‧‧‧N type level shift circuit

116, 220, 221‧‧‧P type level shift circuit

115, 117, 127‧‧‧P type diffusion zone

119, 123, 125‧‧‧N type diffusion zone

121, 129‧‧ ‧ gate insulation

203, 205‧‧‧ conductive signal lines

200‧‧‧Microprocessor

208‧‧‧ functional block

217, 219, 302, 402‧‧‧ Inverters

224‧‧‧P type buffer

226‧‧‧N type buffer

ENP, ENN‧‧‧ clamp enable signal

PEN, NEN‧‧ ‧ clamp displacement enable signal

BPEN, BNEN‧‧‧ buffer clamp displacement enable signal

VBNA, VBPA‧‧‧ substrate bias

BCTL‧‧‧ control signal

PC1, PA, PB, PCN‧‧‧P type channel clamp

NC1, NA, NB, NCN‧‧‧N type channel clamp

NCHG, PCHG‧‧‧ charging voltage level

P1, P2, P3, P4‧‧‧P type channel device

N1, N2, N3, N4‧‧‧N type channel devices

1 is a diagram showing a substrate biasing circuit including a conventional CMOS device integrated on a P-type substrate and more integrated in an integrated circuit according to an embodiment of the present invention. A schematic diagram of a substrate bias circuit.

2 is a block diagram of a substrate biasing circuit and an integrated wafer of microprocessors for minimizing subcritical leakage currents of functional blocks of a microprocessor, in accordance with an embodiment of the present invention.

3 is a schematic diagram showing a P-type level shifting circuit according to an embodiment of the present invention. The P-type level shifting circuit can be used as a P-type level shifting circuit of FIGS. 1 and 2.

4 is a schematic diagram showing an N-type level shifting circuit according to an embodiment of the present invention. The N-type level shifting circuit can be used as an N-type level shifting circuit of FIGS. 1 and 2.

5 and 6 are schematic views showing a P-type buffer and an N-type buffer according to an embodiment of the present invention.

Fig. 7 is a view showing a P-type level shift circuit of Fig. 2 according to an embodiment of the present invention.

Fig. 8 is a view showing an N-type level shift circuit of Fig. 2 according to an embodiment of the present invention.

Figures 9 and 10 show corresponding embodiments of the microprocessor of Figure 2.

200‧‧‧Microprocessor

202‧‧‧Base bias circuit

208‧‧‧ functional block

212‧‧‧ bias generator

214‧‧‧Control device

BCTL‧‧‧ control signal

220, 221‧‧‧P type level shift circuit

222, 223‧‧‧N type level shift circuit

224‧‧‧P type buffer

226‧‧‧N type buffer

ENP, ENN‧‧‧ clamp enable signal

PEN, NEN‧‧ ‧ clamp displacement enable signal

VBNA, VBPA‧‧‧ substrate bias

PC1, PA, PB, PCN‧‧‧P type channel clamp

NC1, NA, NB, NCN‧‧‧N type channel clamp

NCHG, PCHG‧‧‧ charging voltage level

Claims (18)

A microprocessor device comprising: a first power supply node providing a first core voltage; a functional block having a plurality of power modes, comprising: a plurality of semiconductor devices each having a base contact; and a first substrate a biasing wire disposed on the functional block and the base contact coupled to the at least one of the semiconductor devices; a first charging node; a first selection circuit coupled to the functional block when the functional block is in a low power mode a substrate biasing wire to the first charging node, and clamping the first substrate bias wire to the first power supply node when the functional block is in a full power mode; and a substrate bias circuit when the function When the block is in the low power mode, charging the first charging node to a first substrate bias relative to one of the first offset voltages of the first core voltage, wherein the substrate bias circuit comprises a bias a generator, when the functional block is in the low power mode, charging the first charging node and converting the functional block into the full power mode Driving the first node to the charging voltage of the first core. The microprocessor of claim 1, wherein the first selection circuit comprises: a first semiconductor device coupled between the first power supply node and the first substrate bias wire; a second The semiconductor device is coupled to the first substrate bias wire and Between the first charging nodes; and wherein the first selection circuit enables the first semiconductor device in the full power mode and the second semiconductor device in the low power mode. The microprocessor of claim 2, wherein: the substrate biasing circuit further comprises a control device for providing a control signal, wherein the control signal has a function when the functional block operates in the full power mode a first state, and having a second state when the functional block operates in the low power mode; and wherein the first selection circuit further includes a control input for receiving the control signal and the first selection circuit The first semiconductor device is enabled when the control signal is in the first state, and the second semiconductor device is enabled when the control signal is in the second state. The microprocessor of claim 1, further comprising: a second power supply node providing a second core voltage; and wherein the first selection circuit comprises: a control input receiving a control signal And the control signal is switched between the first core voltage and the second core voltage to indicate a power mode of the functional block; and the one-bit shift circuit has an input end for receiving the control signal and providing a bit An output terminal of the quasi-shift control signal, wherein the level shift control signal is switched between the first substrate bias voltage and the second core voltage; An inverter having an input end for receiving the level shift control signal and an output end, wherein an output end of the inverter is switched between the first substrate bias and the second core voltage; a semiconductor device comprising: receiving a gate of the level shift control signal, coupling a source of the first power supply node, and coupling one of the first substrate bias wires to a substrate; and a substrate; The second semiconductor device includes a gate coupled to the output of the inverter, a source coupled to one of the first charging nodes, and a drain coupled to one of the first substrate bias wires and a substrate. The microprocessor of claim 1, further comprising: a first clamping device coupled between the first power supply node and the first substrate biasing wire, the first clamping device Having a control input, wherein when the control input is enabled, the first clamping device clamps the first substrate biasing wire to the first power supply node; and a quasi-shift circuit has a receiving control An input end of the signal and an output end of the control input end coupled to the first clamping device, wherein when the functional block is in the low power mode, the level shifting circuit drives the output end to the first The substrate is biased such that the first clamping device is non-conducting. The microprocessor of claim 5, further comprising: a second clamping device coupled between the first power supply node and the first substrate biasing wire and having a control input Where The control input terminal is enabled, the second clamping device clamps the first substrate bias wire to the first power supply node; and a buffer has an input coupled to the output of the level shift circuit and an output The terminal is coupled to the gate of the second clamping device; wherein when the functional block is in the low power mode, the buffer driving its output end follows the output end of the level shifting circuit to The clamp device does not conduct. The microprocessor of claim 1, further comprising: a second power supply node, providing a second core voltage; wherein the functional block further comprises winding one of the functional blocks. a substrate biasing wire and the base contact of the at least one of the semiconductor devices different from the at least one semiconductor device coupled to the first substrate bias wire; a second charging node; a second selection circuit The function block is coupled to the second base bias wire to the second charging node and when the functional block is in the full power mode, and the second selection circuit clamps the second base bias wire And the second power supply node; and wherein the base bias circuit charges the second charging node to a second offset voltage corresponding to one of the second core voltages when the functional block is in the low power mode One of the second substrate biases. The microprocessor of claim 7, wherein the substrate bias circuit comprises a bias generator, wherein the bias generator generates the first charging node when the functional block is in the low power mode Charging, The first charging node has a positive voltage offset with respect to the first core voltage, and when the functional block is in the low power mode, the bias generator charges the second charging node to cause the foregoing The two charging nodes have a negative voltage offset with respect to the second core voltage. The microprocessor of claim 8, wherein: the first selection circuit comprises: a first P-type channel device having a source and a drain coupled to the first power supply node and Between the first substrate biasing wires; and a second P-channel device having a source and a drain coupled between the first charging node and the first substrate biasing wire; and the second The selection circuit includes: a first N-type channel device having a source and a drain coupled between the second power supply node and the second substrate bias wire; and a second N-channel device, A source and a drain are coupled between the second charging node and the second substrate bias. The microprocessor of claim 9, wherein: the substrate biasing circuit further comprises a control device, wherein the control device is provided with a P-type control signal and an N-type control signal, wherein the P-type control signal is The N-type control signals are respectively switched between the first core voltage and the second core voltage to indicate a power mode of the functional block; The first selection circuit further includes: a P-type level shift circuit having an input end for receiving one of the P-type control signals and an output terminal for providing a first level shift control signal, wherein the control signal is switched Between the second core voltage and the first substrate bias; a first inverter having an input terminal for receiving the first level shift control signal and having a switching to the second core voltage and the An output terminal between the substrate biases; wherein the first P-type channel device has a base coupled to one of the first substrate bias wires and a gate receiving the first level shift control signal; The second P-channel device has a base coupled to one of the first substrate bias wires and a gate coupled to the output of the first inverter; and wherein the second selection circuit further includes An N-type level shifting circuit having an input end for receiving one of the N-type control signals and an output terminal for providing a second level shift control signal, wherein the control signal is switched to the first core voltage and Between the second substrate biases; a second inverter having one of receiving the input of the second level shift control signal and switching between the first core voltage and the second substrate bias An output end; wherein the first N-type channel device has a base coupled to the second substrate biasing wire and receives the second level shift control a gate of the signal; and wherein the second N-channel device has a base coupled to one of the second substrate bias wires and one of the outputs coupled to the second inverter. The microprocessor of claim 1, wherein the first charging node and the first selection circuit are provided in the functional block. An integrated circuit comprising: a substrate; a functional block comprising a plurality of P-channel devices integrated into the substrate and a plurality of N-channel devices, wherein the P-channel device and the N-channel device individually comprise a base contact The functional block has a full power state and a low power state; a first substrate biasing wire is provided on the substrate of the functional block and coupled to at least one of the base contacts of the P-channel device a second substrate biasing wire provided on the substrate of the functional block and at least one of the substrate contacts coupled to the N-channel device; a first supply conductor provided on the substrate and providing a core voltage corresponding to a second supply conductor is provided at a reference voltage of the substrate; a substrate biasing circuit is provided on the substrate of the functional block, the substrate biasing circuit has a first output end and a second output end, The first output end is configured to charge the first substrate bias wire and the second output end for charging the second substrate bias wire, wherein the function is Block is converted by the low-power state to the full power state, the group a bottom bias circuit charging the first substrate bias wire to the core voltage and charging the second substrate bias wire to the reference voltage, and wherein the substrate bias circuit is charged when the functional block is in a low power state The first substrate biasing wire is biased to a first substrate higher than the core voltage and the second substrate biasing wire is charged to a second substrate biased lower than the reference voltage, wherein the substrate biasing circuit Included in the control device, the control device has a first output and a second output, the first output and the second output represent the full power state and the low power state; and a clamp circuit is used for the full power In the state, the clamping of the first substrate biasing wire to the first supply conductor and the clamping of the second substrate biasing wire to the second supply conductor include: a first clamping device coupled to the first supply Between the conductor and the first substrate biasing wire and having a control input; a second clamping device coupled to the second supply conductor Between the two substrate biasing wires and having a control input terminal; a first level shifting circuit having an input end coupled to the first output end of the control device and an output end coupled to the first clamping block The control input of the device, wherein the first level shifting circuit switches the output end between the reference voltage and the first substrate bias; and a second level shifting circuit has an input coupled to the The second output end of the control device and an output end are coupled to the control input end of the second clamping device, wherein the second level shifting power The circuit is switched between the core voltage and the second substrate bias; a third clamping device is coupled between the first supply conductor and the first substrate bias wire and has a control input a fourth clamping device is coupled between the second supply conductor and the second substrate biasing wire and has a control input; a first buffer having an input coupled to the first The output end of the level shifting circuit is coupled to an output end of the control input end of the third clamping device, wherein the first buffer drives the output end to follow the output end of the first level shifting circuit And a second buffer having an input coupled to the output end of the second level shifting circuit and an output coupled to the control input of the fourth clamping device, wherein the second buffer The output terminal is driven by the output terminal of the second level shifting circuit. The integrated circuit of claim 12, wherein the substrate biasing circuit further comprises: a first selection circuit having a control input, the first selection circuit comprising: a fifth clamping device, coupled Connected between the first supply conductor and the first substrate biasing wire; a first switching device coupled between the first substrate biasing wire and the first output end of the substrate biasing circuit; The first selection circuit is configured according to the first selection circuit The control input terminal selectively enables one of the first clamping device and the first switching device; a second selection circuit has a control input, and the second selection circuit includes: a sixth clamping device The second switching device is coupled between the second substrate biasing wire and the second output end of the substrate biasing circuit; And the one of the sixth clamping device and the second switching device is selectively enabled according to the control output end of the second selection circuit; and wherein the first output end of the control device is coupled to the first The control input end of a selection circuit and the second output end of the control device are coupled to the control input end of the second selection circuit, wherein the control device controls the above when the functional block is in the full power state a first selection circuit and the second selection circuit to clamp the first substrate bias wire to the core voltage and clamp the second substrate bias To said reference voltage, and when said functional block in the low-power mode, driving the first substrate bias voltage to the first conductor and the second substrate bias voltage to a substrate bias voltage to the second conductor substrate bias. The integrated circuit of claim 13, wherein the first selection circuit further comprises: a P-type level shift circuit having an input coupled to the control The first output end of the device and an output terminal for providing a first level shift voltage between the reference voltage and the first substrate bias; a first inverter having the first level received One of the input terminals of the shift voltage is coupled to one of the output terminals between the reference voltage and the first substrate bias; the fifth clamping device includes a first P-channel device, and the P-channel device has a coupling One of the first supply conductors is coupled to one of the first base biasing wires and one of the first base biasing wires and the first receiving substrate, and the first switching device includes a first switching device a P-channel device having a source coupled to the first output end of the substrate bias circuit, a drain coupled to the first substrate biasing lead and a substrate, and a gate The second output terminal is coupled to the output terminal of the first inverter; and the second selection circuit further includes: an N-type level shifting circuit having an input end coupled to the second output end of the control device a second level a bit voltage between the core voltage and the second substrate bias; the second inverter has an input terminal for receiving the second level shift voltage and switching to the core voltage and the An output terminal between the two substrate biases; the sixth clamping device includes a first N-channel device, the N-channel device having a source coupled to the second supply conductor, coupled to One of the second substrate biasing wires and one of the base and the gate receiving the second level shifting voltage; and the second switching device comprises a second N-channel device, the N-channel device having a source is coupled to the second output end of the substrate biasing circuit, and one of the second base biasing wires is coupled to a base and a gate is coupled to the output end of the second inverter . A method of selecting a substrate bias voltage for a plurality of semiconductor devices of a functional block of a microprocessor chip, the microprocessor die including a substrate biasing wire wound in a functional block for reducing at least the semiconductor device a critical leakage current, the method comprising: when the functional block is in a first power state, clamping the substrate bias wire to a first core voltage; when the functional block is in a second power state, the substrate is not clamped a biasing wire and driving the substrate biasing wire to a substrate bias, wherein the clamping step includes a clamping device capable of coupling between the substrate biasing wire and the first core voltage, wherein the clamping device The device includes a gate, a gate coupled to one of the first substrate bias wires and a substrate, and a source coupled to one of the first core voltages, wherein the clamping step includes driving the semiconductor device The gate to a second core voltage, and wherein the step of not clamping comprises driving the gate to the semiconductor device Substrate bias. The method of claim 15, further comprising: shifting the level of the consistent energy signal to a quasi-shift enable signal, The enable signal is switched between the first core voltage and the second core voltage, and the level shift enable signal is switched between the base bias voltage and the second core voltage; and the level shift is caused The signal can be applied to the gate of the semiconductor device. The method of claim 15, wherein the step of driving the substrate bias wire comprises: charging a charging node to an offset voltage corresponding to one of the first core voltages; and coupling the substrate bias wire To the above charging node. The method of claim 17, wherein the step of coupling the substrate bias wire to the charging node comprises enabling a semiconductor device coupled between the substrate bias wire and the charging node.