TW201013836A - Microprocessors, intergarated circuits and methods for reducing noises thereof - Google Patents

Abstract

A microprocessor including a substrate bias rail providing a bias voltage during a first operation mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes.

Description

201013836 VI. Description of the Invention: [Technical Field] The present invention is mainly concerned with providing a substrate biasing on a microprocessor die to reduce sub-threshold leakage, in particular It relates to an apparatus and method for separately clamping a substrate biasing wire to a core voltage and a reference voltage to minimize noise of the device substrate, thereby improving device performance. [Prior Art] Complementary Metal-Oxide Semiconductor (CMOS) circuits are denser than other types of integrated circuits (hereinafter referred to as 1C) and consume less power. Therefore, CMOS technology has become the dominant style of digital circuit design in integrated circuits. The CMOS circuit is composed of an N-channel metal-oxide-semiconductor (hereinafter referred to as NMOS) and a P-channel metal-oxide-semiconductor (hereinafter referred to as PMOS), depending on the design, scale, and material. Between material and process, NMOS and PMOS have a threshold voltage (this refers to the voltage of the gate to the source). As integrated circuit design and manufacturing technology continues to evolve, operating voltages and device sizes are also reduced. The 65 micrometer (nm) process is an advanced lithographic process for a large number of CMOS semiconductor processes and is more beneficial for the manufacture of very large scale integrated circuits (VLSI), such as

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Microprocessor, etc. As device size and voltage levels decrease, the channel length and oxide thickness of each device also decreases. Manufacturers have switched to gate materials with lower threshold voltages to increase sub-threshold leakage current. When the gate-to-source voltage is lower than the threshold voltage of the CMOS device, the sub-critical leakage current flows between the drain and the source. The base interface of each CMOS of the plurality of conventional circuits (or a well region or a bulk tie/connection) is coupled to a corresponding one of the power lines (eg, the PMOS substrate contacts are coupled to the core voltage VDD, the NMOS substrate The contact is coupled to the reference voltage VSS). In such conventional structures, the subcritical leakage current can account for about 30% or more of the total power consumption in a dynamic environment (e.g., during normal operation). Integral circuits are typically required to operate in a low power mode (such as sleep mode or hibernation mode) with as little power consumption as possible. During a low power mode, a bias generator or charge pump biases the substrate of the device at a different voltage level than the supplied power. The bias generator can be provided on-wafer or off-chip. Alternatively, the bias generator boosts the voltage of the base contact of pM〇s to a voltage higher than the core voltage VDD and lowers the voltage of the NMOS base contact to a voltage lower than the reference voltage να. Such a substrate bias is significantly reduced by the sub-critical voltage leakage current in the low power mode, thereby preserving the total amount of power. However, in large integrated devices, such as microprocessors, it is desirable to transfer the substrate bias to a plurality of devices distributed over the die. Although it is possible to provide a plurality of bias generators on the die, the above plurality of bias generators consume a valuable range of crystal grains, so

CNTR2419IOO-TW/06O8-A41899-TWF 5 201013836 It is required to minimize the number of bias generators. The substrate biasing wire is wound as far as possible from the grain to transfer the substrate bias. In low power mode, the bias generator drives the substrate bias to minimize sub-critical leakage current and reduce power. In the normal mode of operation, the bias generator drives the voltage of the biasing conductor to the corresponding supply voltage in an attempt to improve the performance of the device. The level of impedance associated with the biasing conductor distribution will result in voltage variations across the base of the integrated circuit. The substrate biased conductor also introduces noise due to capacitive coupling, affecting the performance of the device. In order to minimize voltage variations and noise and to maintain device performance, it is required to spread the substrate bias wires over the crystal grains of a large integrated device (e.g., a microprocessor), which is a problem that the prior art has to solve. SUMMARY OF THE INVENTION In view of the above, a microprocessor according to the embodiment includes a first-substrate biasing conductor that provides a bias voltage in a first mode of operation. The first power supply point provides a core H at least = connected to the first substrate bias wire and the first supply point. During the second mode of operation, the control respect-controls the clamping of the first-substrate biasing conductor to the "bit device conducting" mode, the non-conducting clamping device source supply node' and the first operation may be a semiconductor device For example, the first-substrate bias of the offset voltage. The microprocessor core is used to bias the clamp device to ensure the first operation; the quasi-shift:: one -9· during the lower mode is not suitable for 201013836 The Γ device 1 processor may include a buffer for controlling a plurality of home-mounted wire detachers: a base package bottom 底 bottom feed line 舆 a second base bias*

The second substrate is biased by μ. During the embodiment mode, during which the first substrate bias is provided with respect to the core voltage, the first bias voltage has a negative voltage offset offset with respect to the reference voltage | and the second substrate microprocessor may include a substrate In the embodiment, in the first mode of operation, the first base ==:r is located in the semi-conductance of the first region == the first £ domain + the conductor device remains powered on. Two base bias line _ bit device. The control device can == connect to the f-substrate biased wire and the second base (four) wire box = the embodiment according to the embodiment - the integrated circuit includes a substrate, a base-substrate (four) line and a second at the base The base biasing conductor, the first power supply conductor on the substrate provides a core voltage relative to a reference voltage, the reference voltage is provided by the second power supply conductor located on the substrate, located on the substrate and coupled to the first power supply conductor and the first At least one first clamping device between the substrate biasing wires, at least one second location on the substrate coupled between the second power supply conductor and the second substrate biasing wire, and a control device. Providing a first substrate biased to the first substrate biasing conductor during the first mode of operation of the integrated circuit, providing a second aesthetic bias to the second substrate biasing conductor, wherein the first substrate bias is higher than = Electricity

CNTR2419I00-TW/Q608-A41899-TWF 201013836 is pressed while the second substrate bias is lower than the reference voltage. The control device has a first output for controlling the first clamping device and a second output for controlling the second clamping device. In the first mode of operation, the control device disables the first and second clamping devices, and turns on the first and second clamping devices to clamp the first substrate biasing wire to the first power source in the second operating mode. The conductor is supplied and the second substrate biasing wire is clamped to the second power supply conductor. The integrated circuit can include a level shifting circuit to turn the clamping device on and off depending on the substrate bias level. The integrated circuit can include a buffer coupled to the clamping device. The substrate can be divided into first and second regions, each of the regions having a plurality of semiconductor devices, wherein the first substrate biasing wires and the second substrate biasing wires and the at least one first clamping device are located in a first region of the substrate. In accordance with an embodiment of the method of reducing micro-processed wafer noise, the micro-processed wafer includes a first substrate biasing conductor for reducing sub-critical leakage current. According to an embodiment, when the microprocessor chip is in the first power state, the first substrate bias wire clamps the first substrate bias wire to the core voltage, and the microprocessor chip does not clamp the first substrate when in the second power state The wire is biased and a first substrate biased to the first substrate biased wire is provided. The method includes conducting a plurality of selected first clamping devices, wherein the plurality of first clamping devices are configured to maintain a voltage of the first substrate biasing conductor at a first predetermined minimum voltage level with respect to the variation of the core voltage and A plurality of first clamping devices are distributed along the first substrate biasing wires. The method may include the step of coupling the drain and the source of the first semiconductor device between the first substrate bias wire and the core voltage, and when the microprocessor is in the CNTR2419IO0-TW/06O8-A41899-TWF 8 201013836 The power state, conducting the first semi-conductive state, not conducting the first semi-conducting: when the microprocessor is at the second electrical offset voltage (four), the first-substrate biasing method may include providing one or lower than the core voltage, And to mention that the voltage is higher than the core voltage - the gate of the semiconductor device is high: or the first; low above: the method may include the first: conductor

The micro-processing L: chip line and core voltage ' and α 杈 supply stage buffers are used to buffer the first clamp enable signal k for buffering the clamp enable signal to the gate of the second semiconductor device. The voltage level of the clamp-enhanced first-clamp enable signal is the same. The microprocessor die can be divided into first and second regions and can include a first substrate biasing wire. In one embodiment, the first substrate biasing wire is in the first region and the second substrate biasing wire is in the second region. In the present case, the above method further includes selecting to clamp the first and second substrate bias wires to the core voltage or selecting not to clamp the substrate bias wires and receiving corresponding offsets on the substrate bias wires in various power states of the microprocessor. Pressure. The above described objects, features and advantages of the present invention will become more apparent from the following description of the preferred embodiments. The present invention can be created and used by the following description 'depending on its actual application and needs'. However, anyone familiar with this skill can do 9

CNTR2419I00.TW/0608-A41899-TWF 201013836 Variations are preferred embodiments for use in other embodiments. Therefore, the object of the present invention is not limited to the embodiments shown, but should be disclosed to include a wide range and novel features in accordance with the principles. The inventors consider that the biasing of the substrate base to a voltage level different from the supply voltage when the conventional substrate bias is applied to the low power mode will have significant impedance and capacitive noise coupling. For example, its disadvantages include an increased voltage drop due to biasing the length of the wire along the substrate, which will cause significant variations in substrate bias, while in normal operating mode, noise coupled to the device causes performance to be performed. decline. Accordingly, the inventors have provided a microprocessor with a substrate bias clamp to reduce voltage variations and noise coupling' and are described below and in conjunction with Figures 1-8. 1 shows an embodiment of an integrated circuit 100 including a CMOS device integrated on a p-type substrate 110, and a substrate bias circuit 1 integrated in the integrated circuit 100 according to an embodiment. Block diagram of 〇2. Although the specific structure shown is a twin well process, other types of processes (such as N-well, P-well, and III) can still be considered. A well, etc.) N-type well regions 1〇3, 105, and 107 are formed in the P-type substrate 101, and the second: N-type well region 105 is a deep N-well region (deep N-well region) An isolated p-well zone 109 is formed in the deep N-well zone 105. The first n-well zone 103 is used to fabricate a P-channel device Π1, while the isolated P-well zone 109 Used to fabricate the N-channel device 113. It is understood by those skilled in the art that the third n-well region 107 can be applied to other devices. Although Figure 1 shows only two channel devices 111 and 113, those skilled in the art will be aware of any number. Extra 10

CNTR2419IO0-TW/O6O8-A41899-TWF 201013836 'The device can be applied to the P-type substrate 101. - A pair of P-type diffusion regions (P+)l 15 and 117 and an N-type diffusion region (N+) 119 form a P-type channel device in the n-type well region 103. The P-type channel device U1 further includes a gate insulating layer 121 covering the N-type wells of the P-type diffusion regions 115 and 117. The p-type diffusion region (ρ+) ιΐ5 is formed as a 汲 extreme, denoted as “D”; the P-type diffusion region (Ρ+)1 Π is formed as a source terminal, labeled “s,'; and the gate insulating layer 121 is formed as The gate terminal is marked as “G.” According to the special function of the device, the gate terminal G of the P-channel device 1U and the 汲 terminal D are coupled to corresponding signals (not shown) of the integrated circuit 1〇〇. The p-channel device The source terminal 3 of U1 is coupled to a core voltage ((), 1), 1). In an embodiment, the core voltage yDD is provided by a first power supply node. The region 119 is formed as a well region or substrate contact, and is labeled b" 'substrate bias φ rail 104 that is supplied to the substrate bias VBNA that provides the p-channel device η!. For the Ν-type channel arrangement (1), the pair-shaped ν-type diffusion regions (Ν+) 123 and 125 and the p-type diffusion region (ρ+) 127 are formed in the isolated ρ ^well region 109 and the gate insulating layer 129 It is formed on the p-type well region 1〇9 covering the v-type diffusion regions 123 and 125. The 扩散-type diffusion region 125 is formed as a 〆 and an extreme D ′ Ν type diffusion region 123 is formed as a source terminal S; and a gate insulating layer 129 is formed as a gate terminal G. The 通道-type channel device 113 is connected to the corresponding signal on the integrated circuit 10A according to the special function of the device (not shown), and the source terminal 3 of the channel device 113 is connected to the voltage VSS. In order to distinguish from the above-mentioned core voltage VDD, CNTR2419I〇0-TW/__A41899twf 201013836 is therefore referred to as a reference voltage VSS. The above-mentioned reference-voltage VSS is a ground signal in the embodiment. In an embodiment, the above reference voltage VSS is provided by a second power supply node. The P-type diffusion region 127 is formed as a well region or substrate contact B coupled to a substrate biasing conductor 106 for providing a substrate bias voltage VBPA to the N-channel device 113. The core voltage VDD and the reference voltage VSS can be transmitted through the conductor or conductive: a line or the like (for example, a conductive via, a conductive node, a conductive wire, a conductive bus bar and a bus bar signal, which are known to those skilled in the art) are provided in the entire integrated circuit or Wafer. The substrate bias wires 1〇4 and 1〇6 can also be implemented through conductors® or conductive lines. The substrate biasing circuit 102 includes a bias generator 112 having an output to provide substrate bias voltages VBNA and VBPA on the substrate biasing conductors 1〇4 and 1〇6, respectively. Although the bias generator II2 is implemented with a charge pump located in the integrated circuit 100 in the embodiment, it can be considered to be implemented with other types of voltage generators. The bias generator 112 is controlled by a bias control signal bctl provided by the control device 114. The control device 114 has an output terminal for providing a clamp enable signal ΕΝρ to a wheel-in terminal of a ρ-type level shift ❹ circuit (LSP) 116, and the ρ-type level shift circuit 116 has a round-out The terminal 'provides a corresponding clamped shift enable signal PEN to the _ type channel clamp device pci. The p-channel home device pc! has a core, a voltage VDD, and a pole is coupled to the substrate biasing wire 丨〇4. The control device 114 has another output terminal 'providing an additional -n bit enable signal to the input of the N_type level shifter (LSN) circuit 118, the N-type level shift

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- Circuit U8 has an output providing a corresponding clamped shift enable signal NEN - to the gate of N-channel clamp IC1. The source of the N-channel clamp device Να is lightly connected to the reference voltage VSS', and its pole is lightly connected to the substrate biasing wire 106. The control device Π4 switches the clamp enable signals ENp and ENN between the reference voltage vss of the integrated circuit 100 and the core voltage VDD. The P-type level shifting circuit 116 shifts the voltage range of the clamped shift enable signal pEN between the reference voltage vss and the substrate bias voltage VBNA, and the n-type level shifting circuit 118 shifts the voltage range of the clamped shift enable signal NEN. Between the substrate bias voltage VBPA and the core voltage VDD. Generally, when the control device 114 asserts the clamp enable signal ENp to a low level, the clamp shift enable signal PEN is set to a low level to turn on the p-channel clamp device PC1 to clamp the base bias wire 1〇4 to the core voltage. VDD. When the control device 114 sets the clamp enable signal ENP to a high level, the two-channel clamp device pci will not be turned on. When the control device 114 sets the clamp enable signal ENN to a high level, the clamp shift enable signal nen is set to the ^φ level to turn on the N-channel clamp device NC1 to manufacture the base bias wire 106 to the reference voltage VSS. . When the control device 114 sets the trigger enable signal ENN to a low level, the N-channel clamp device NC1 will not conduct. When the integrated circuit 100 is required to operate in the low power mode, the control device 114 sets the clamp enable signal enp to a high level, and sets the clamp enable i number ENN to a low level to disable the clamp. Pci and non-conductivity. It is noted that the integrated circuit 1 may have multiple operational states or modes of operation including one or more low power modes or low power states. The above low power mode is the integrated circuit 1

CNTR2419I00-TW/0608-A41899-TWF 13 201013836 A small portion of the area operates in a low power state (conditi〇n) or is off. In the low power mode, the control device 114 also controls the bias generator 丨12 and drives the substrate bias voltage VBNA to a voltage higher than the core voltage VDD with a first substrate bias offset voltage. The two substrate offset voltage drives the substrate bias voltage VBPA to be lower than the reference voltage VSS. Depending on the actual configuration, the first substrate offset voltage and the second substrate offset voltage may be equivalent or different voltages. That is, in the low power mode, the substrate bias voltage VBNA has a positive voltage offset with respect to the core voltage VDD, and the substrate bias voltage VBPA has a negative voltage 10 offset with respect to the reference voltage vss. Therefore, in the low power mode, the base voltage of the P-type channel device ln is driven to a voltage south of the core voltage VDD, and the base voltage of the N-channel device 113 is driven to a voltage lower than the reference voltage, so that the above two The subcritical leakage current of the device is minimized. When it is required to switch the integrated circuit 100 to the normal operation mode for normal operation, the control device 114 controls the bias generator 112 to drive the substrate bias voltage VBNA to the voltage level of the core voltage VDD, and drives the substrate bias voltage VBpA to Check the voltage level of the voltage VSS. Therefore, during the normal operation mode, the substrate B of the type channel device 111 is driven to the core voltage VDD, and the substrate B of the N-type channel device 113 is driven to the reference voltage vs. The substrate biasing wires 104 and 106 are ruffled to each device integrated into the p-type substrate ιοί (including the N-channel device 113 and the p-channel device m). The substrate bias voltages VBNA and A need to be consistent with the substrate bias wires 104 and the substrate bias wires 106, respectively. Typically a larger size P-type substrate 101 and/or larger integrated devices have

CNTR2419I00-TW/0608-A41899-TWF 14 201013836 Longer substrate bias wires 104 and 106. The substrate biasing wires 104 and 106 can be physical conductors whose impedance results in an increasing voltage drop along the length of the wire away from the bias generator 12. If one of the N-channel device Π3 and the p-channel device in is located far away from the bias generator 112, the base repeat vbna and the VBPA electrical level will be respectively related to the core voltage VDD and the reference voltage VSS. The difference between the two has led to a negative impact on the implementation of the operational mechanism. Furthermore, the substrate biasing wires 104 and 106 easily transmit noise generated by capacitive coupling or the like, which affects operation and reduces efficiency. The control bias generator 112 drives the voltage levels of the substrate bias voltages VBNA and VBPA to the core voltage VDD and the reference voltage vss, respectively, and the clamp enable signal ENP is low (so the clamp enable signal PEN is clamped) The low level) and the clamp enable signal ENN are at a high level (so the clamp shift enable signal NEN is at a low level) to switch the integrated circuit 1 回 back to the normal operation mode S. In this manner, the clamp devices PC1 and (10) respectively produce the substrate bias wires 104 and 106 to the core voltage VDD and the reference voltage vss. Although only one p-channel clamp device pci for the substrate biasing wire 1〇4 and one of the base biasing wires 1〇6 for the N-type pass=clamping device NC1' are shown, any number of clamps can be used. The devices are distributed along the length of the = wires 104 and 106, respectively. In an embodiment +, the number and position of the clamping devices are based on the minimum voltage level of the predetermined ', ♦, v center of the respective base bias voltages relative to the core voltage VDD and the reference voltage vss. In this mode, when the H-bit device is enabled, the substrate biasing wire (10)

The voltage of CNTR2419I00-TW/O6O8-A41899-TWF 15 201013836 is clamped to a core power having a predetermined minimum level, and the voltage of the substrate biasing conductor 106 is clamped to a reference voltage VSS having a predetermined minimum voltage level. The above-described clamping mechanism can reduce the noise generated by the capacitive coupling effect and minimize the voltage variation of the biased wires 1〇4 and 1〇6 along the substrate. In one embodiment, after the substrate bias wires 104 and 1〇6 are clamped to the core voltage VDD and the reference voltage VSS, if less noise is required and power is maintained, the bias generator 112 may be shut down or It is switched to low power mode. 2 is a block diagram showing the substrate bias circuit 202 integrated into a die of a microprocessor 200 having a distributed clamping device, in accordance with an embodiment. The substrate biasing circuit 202 is generally identical to the substrate biasing circuit 1〇2 of FIG. 1, and like devices and elements are designated by the same reference numerals. As shown, the bias generator 112 has an output terminal' that provides substrate bias voltages VBNA and VBPA at substrate biasing conductors 1 and 4, respectively. The substrate biasing leads 1 and 4 are wound around the die of the microprocessor to transfer the substrate bias voltages VBNA and VBPA to selected P-type and N-type channel devices integrated into the microprocessor 200. The P-channel device P1 shown in one embodiment has a base contact to substrate biasing wire 104, which is similar to the P-channel device 111 of FIG. 1, and the N-channel device N1 has a base contact to the substrate bias The crimping wire 106 is similar in operation to the N-channel device 113 of Fig. 1. Although only one P-channel device and one N-channel device are shown, those skilled in the art will appreciate that a plurality of devices can be provided to the microprocessor 200 and coupled to each other by a substrate contact in the foregoing approximation. One of the suitable substrate biasing wires 104 and 106 (indicated by dots). Coupling to the base biasing conductor CNTR2419I00-TW/0608-A41899-TWF 16 201013836 The P-channel clamping device PC1, PC2 pC8 of the line 104 is distributed along the substrate biasing wire 104' coupled to the substrate biasing wire ι6 The n-channel clamps NCI, NC2...NC8 are distributed along the substrate biasing wires 1〇6. The drain and the substrate of each of the P-type channel devices PC1-PC8 are coupled to the substrate biasing conductor 104, and the source thereof is coupled to the voltage VDD. Each of the N-channel clamp devices NC1-NC8 is coupled to the substrate biasing conductor 1〇6 and the source thereof to the reference voltage VSS. The control device 114 provides a control signal BCTL to control the bias generator 112, the operation method of which is similar to the operation method β applied to the integrated circuit 100 in Fig. j. As shown in Fig. 2, the control device 114 provides four pliers respectively. The bit enable signal £&gt; scares &lt;3:〇&gt; to the input terminals of the four p-type level shift circuits LSP 116, and the p-type level shift circuit 116 outputs the corresponding four clamp shift enablers Level_shifted clamp enable signal PEN&lt;3:0&gt;. Similarly, the control device ι14 provides four N-type clamp enable signals ΕΝΝ<3·〇> to the input terminals of the four N-type level shift circuits LSN 118. The N-type level shift circuit output corresponds to the output. The four clamp shift enable signals NEN &lt; 3: 〇 &gt;. The clamp shift enable signal PEN&lt;3:0&gt; is supplied to the corresponding p-type channel clamps PC1-PC4, respectively. Specifically, the clamp shift enable signal PEN&lt;3&gt; is supplied to the gate of the P-channel clamp device pci; the clamp shift enable signal PEN&lt;2&gt; is supplied to the gate of the p-channel clamp device pC2; The clamp shift enable signal PEN&lt;1&gt; is supplied to the gate of the p-channel clamp device PC3 and the clamp shift enable signal pEN&lt;〇&gt; is supplied to the gate of the p-channel clamp device PC4. Each of the clamp shift enable signals pEN&lt;3:〇&gt; is provided in one of the corresponding four P-type buffers 2〇1, respectively.

CNTR2419I00-TW/0608-A41899-TWF 17 201013836 end, P-type buffer 201 and provide corresponding four buffer clamp shift enable * signal BPEN &lt; 3: 〇 > 〇 specifically, buffer clamp shift The energy signal BPEN&lt;3&gt; is a buffer version of the clamp shift enable signal pEN&lt;3&gt;; the buffer clamp shift enable signal BpEN&lt;2&gt; is a buffered form of the clamp shift enable signal PEN&lt;2&gt;; The buffer clamp shift enable signal BPEN&lt;1&gt; is a buffered form of the clamp shift enable signal PEN&lt;1&gt; and the buffer clamp shift enable signal BPEN&lt;0&gt; is a clamp shift enable signal ΡΕΝ&lt;0&gt; Buffer form. The buffer clamp shift enable signal bPEN &lt;3&gt; is supplied to the gate of the P-type channel clamp device PC5; the buffer clamp shift enable signal Xinxin BPEN&lt;2&gt; is supplied to the gate of the P-type channel clamp device PC6; The buffered shift enable signal BPEN&lt;1&gt; is supplied to the gate of the p-channel clamp device pc7 and the buffer clamp shift enable signal BPEN&lt;〇&gt; is supplied to the gate of the p-channel clamp device PC8 . In this way, whenever the clamp enable signal ENP&lt;3:0&gt;2 is set to a low level, the corresponding clamped shift enable signal PEN&lt;3:0&gt;2- will be set to a low level. And the corresponding P-channel clamp device PC1-PC4 is turned on, and the corresponding buffer clamp displacement enable signal BPEN&lt;3:0&gt; is also set to a low level to correspond to the p-type channel clamp device PC5- PC8 is turned on. For example, when the clamp enable signal ENp&lt;1&gt; is set to a low level, the clamp shift enable signal pEN&lt;1&gt; and the buffer-made shift enable signal BPEN&lt;l>t are set to a low level, and thus the p-type The channel clamp device PC3 is electrically connected to the PC 7. In this manner, control device 114 can selectively enable any pair of P-channel clamps PC1-PC8. The method of approximating the above-mentioned approximation 'the shift enable signal NEN&lt;:3:0&gt; is supplied to the gates of the corresponding N-channel clamps NC1-NC4, respectively. With

CNTR2419I00-TW/0608-A41899-TWF 18 201013836 - In other words, the clamp shift enable signal NEN&lt;3&gt; is provided to the N-channel clamp-device NC1 gate; the clamp shift enable signal NEN&lt;2&gt; Provided to the gate of the N-channel clamp device NC2; the clamp shift enable signal Nen&lt;1&gt; is provided to the gate of the NP-type channel clamp device NC3 and the clamp shift enable signal NEN&lt;〇&gt; is provided to N The gate of the type channel clamp NC4. The system shift enable signal NE N &lt; 3 ·· 0 &gt; is respectively provided at one of the input terminals of one of the four n-type buffers 203, and the N-type buffer 203 provides four buffer clamp shifts corresponding thereto. The bit enable signal BNEN &lt; 3: 〇 &gt;. Specifically, the buffering/displacement shift enable signal BNEN&lt;3&gt; is a buffering form of the clamp shift enable signal NEN&lt;3&gt;; the buffer shift enable signal bnen&lt;2&gt; is a clamp shift enable signal The buffering form of NEN&lt;2&gt;; the buffer clamp shift enable signal BNEN&lt;1&gt; is a buffering form of the clamp shift enable signal NEN&lt;1&gt; and the buffer clamp shift enable signal ΒΝΕΝ&lt;0&gt; is a clamp shift Can signal ΝΕΝ &lt;0&gt; buffer form. The buffer clamp shift enable signal BNEN &lt;3&gt; is provided to the gate of the N-channel clamp device NC5; the buffer clamp is braked to cause the 彳§ BNEN&lt;2&gt; to provide the gate to the N-type channel tank device NC6 The buffer clamp shift enable signal BNEN &lt;1&gt; is provided to the gate of the N-channel clamp device NC7 and the buffer clamp shift enable signal ΒΝΕΝ&lt;0&gt; is supplied to the gate of the N-channel clamp device NC8. In this way, whenever one of the clamp enable signals ENN&lt;3:〇&gt;2 is set to the 咼 level, one of the corresponding clamped shift enable signals will be set to the same level. The corresponding N-channel clamp device NC1-NC4 $ is connected, and the corresponding buffer clamp shift enable signal BNEN &lt;3.0&gt; is also set to a high level to correspond to the n-type channel.

CNTR2419I0Q-TW/0608-A41899-TWF 19 201013836 One of the placement devices NC5-NC8 is turned on. For example, when the control device sets the clamp enable signal ENN &lt; 24 high level, the clamp shift enable signal 'NEN&lt;2&gt; and the buffer clamp enable signal bnEN&lt;2&gt; are also set to 'high level' The N-channel clamps NC2 and NC6 are turned on. In this manner, control device 114 can selectively enable any pair of N-channel clamp devices NC1-NC8. Although Figure 2 shows only eight P-channel clamps pci_pc8舆 eight N-channel clamps NC1_NC8. However, those skilled in the art can use any number of channel clamps and corresponding clamp enable signals depending on the size and architecture of the actual integrated circuit 100. Meanwhile, the grouping of the signal indicating the P-type channel device P1 and the p-channel clamping device and the signal about the grave-channel device N1 and the N-channel clamping device can be arbitrary, although only the above is displayed. Devices, those skilled in the art, may also consider a number of possible variations. For example, a single clamp control signal is provided by control device 114, which may be based on the number of clamps required to provide the desired number of buffers after moving the level. Meanwhile, although FIG. 2 shows that the clamp devices PC1_PC4 are a common group, the above devices may be respectively located at actual requirements (eg, similar to the corresponding devices). For example, the vertical devices PCi and PC2 are similar to each other. However, in reality, it is separated, and on the die of the microprocessor 2, the clamping devices PC1 and PC5 can be physically adjacent (cl〇sed). The clamping operation can be selectively enabled using a plurality of clamp control signals in selected portions of the microprocessor 200. In one embodiment, the number and actual position of the clamping devices that bias the wires 1〇4 and 1〇6 along the substrate are dynamically simulated or similar.

^NTR2419I00-TW/0608-A41899-TWF 20 201013836 - Decided to maintain the noise level at a minimum level to achieve optimal performance of the microprocessor. The microprocessor 2 has a plurality of operational states or operational modes as described above for the approximate method of the integrated circuit. The plurality of operational states or modes include one or more low power modes or low power states, and the low power mode refers to selectively causing at least a portion of the microprocessor 2 to be in a low power state or not to operate. Clamping devices, including clamping devices PC1-PC8 and NC1_NC8', are distributed along the substrate biasing wires 104 and 106 and across the substrate of the microprocessor 200. During the normal mode of operation of the microprocessor 2, the control device 114 will turn on or enable all of the clamping devices, or the selected clamping device, to clamp the substrate bias wires 104 and 106 to the core voltage VDD, respectively. With reference voltage vss. In the normal mode of operation, the control device U4 turns off the bias generator 112 or sets the bias generator 112 to a low power state, or controls the bias generator 112 to drive the substrate bias voltages VBNA and VBpA to the core voltage, respectively. The voltage level of φ VDD and the reference voltage VSS. The control device 114 may set the microprocessor to a low power mode or a low power state by first turning off all of the clamp devices or selecting at least one of them to be non-conductive. Next, the control device 114 enables or controls the bias generator U2 to drive the substrate bias voltage VBNA to a voltage higher than the core voltage VDD with a first substrate offset voltage, and to drive the substrate bias voltage with a second substrate offset voltage. VBPA to a voltage lower than the reference voltage vss. The first and second substrate offset voltages can be the same or different voltage levels. In order to pull the microprocessor back from the low power mode to the normal operating mode, the control device 114 first needs to control the bias generation.

CNTR2419I00-TW/0608-A41899-TWF 21 201013836 112' to bias the substrate biasing wires 1〇4 and i〇6, respectively, VBNA and VBPA back to core voltage vdd and reference voltage VSS. Next, the control device 114 turns on all of the clamping devices to conduct or at least one of the clamping devices. As previously described, 'control device n4 sets all clamp enable signals £3 &gt;3:0&gt; and ENN&lt;3:〇&gt;, or selects the clamp enable signal for the order &lt;3:0&gt; and ENN&lt;; 3: 0&gt; at least one of the settings to turn on or not turn on at least one of the clamp devices PC1-PC8 and NC1_NC8. Figure 3 is a diagram showing a p-type level shifting circuit LSP 116 according to an embodiment of the invention. The P-type level shifting circuit LSP 116 includes an inverted 301, four p-channel devices, p2, p3 and p4, and N-channel devices N1, N2, N3 and N4°P-type channel devices PI, P2. P3 and P4 respectively have a source and an internal substrate coupled to a substrate biasing conductor 104 for providing a substrate bias voltage VBNA, and the n-channel devices N1, N2, N3 and N4 are respectively coupled to a reference voltage VSS. The source and internal substrate. The clamp enable signal ENP is supplied to the gate of the P-channel device P1 and the input of the inverter 301. The drain of the p-channel device pi is coupled to the drain and gate of the N-channel device N1 and the gate of the N-channel device ® N2. The output end of the inverter 301 is coupled to the gate of the p-type channel device p2, and the drain of the P-type channel device P2 is coupled to the pole of the N-channel device N2 and the P-channel device P3 and the N-channel device N3. Gate. The drain of the P-type channel device P3 is lightly connected to the N-type channel and the gate of the N3 and the gate of the P-channel device P4 and the N-channel device N4. The p-type channel device P4 is coupled to the drain of the N-type channel device N4 and outputs a clamp shift enable signal PEN. Input clamp enable signal during operation

CNTR2419I00-TW/0608-A41899-TWF 22 201013836 ' ENP will be set between reference voltage VSS and core voltage vdd. The signal of the clamped shift enable signal PEN outputted between the reference voltage VSS and the substrate bias voltage VBNA. When the clamp enable signal ENP signal is set to the reference voltage VSS, the P-channel device is turned on and the p-channel device P2 is turned off (the output of the inverter 3〇1 is the core voltage VDD). The P-type channel device P1 pushes the level of the gate of the N-type channel device N2 up to the substrate bias voltage VBNA' so the N-channel is mounted! N2 will be turned on. The N-type channel device N2 pushes the gate of the P-type channel device P3&amp;N-type channel device N3 to the reference voltage VSS, so that the P-type channel device P3 will be turned on without turning on the N-channel device N3°P-type channel device P3 to push p The gate-to-substrate bias voltage VBNA of the type channel device P4 and the N-type channel device N4 will turn on the N-channel device N4 and the non-conducting P-channel device p4. Therefore, when the clamp enable signal ENP is set to the reference voltage vsS', the signal of the clamp shift enable signal pen is made to pass through the N-type channel device N4 as the reference voltage VSS. When the tank enable signal ENP is set to the core voltage vdD, the P-type pass device P1 is not turned on and the P-type channel device P2 is turned on. Since the p-type channel device P1 is non-conducting, the N-type channel device N1 will push the gate of the N-type channel device N2 to a very low level so that the N-channel device N2 will not conduct. The P-type channel device P2 pushes the gate of the P-channel device P3 and the n-channel device N3 to the substrate VBNA', then the P-channel device P3 is non-conducting and the N-channel device N3 is turned on. The N-type channel device N3 pushes the gates of the P-type channel device P4 and the N-type channel device N4 to the reference voltage VSS, and turns on the P-type channel device P4 without conducting the N-type channel device N4. Therefore, when the clamp enable signal ENP signal is set to the core voltage VDD, p

CNTR2419I00-TW/0608-A41899-TWF 23 The 201013836 type channel device P4 pushes the signal of the clamped enable signal pen to the substrate bias voltage VBNA. In this manner, the clamp enable signal ENP is switched between the reference voltage VSS and the core voltage VDD, and the output clamp shift enable signal PEN is switched between the reference voltage VSS and the substrate bias voltage VBNA.

Figure 4 is a diagram showing an N-type alignment shift circuit LSN 118 according to an embodiment of the present invention. The N-type level shifting circuit LSN Π8 includes an inverter 401, four p-type channel devices P1, p2, p3 and P4, and four N-type channel devices N1, N2, N3 and N4. P-channel devices P1, P2, P3, and P4 have a source and an inner substrate coupled to a core voltage VDD, respectively. The N-type channel devices N1, N2, N3, and N4 respectively have a source and an internal substrate coupled to a substrate biasing conductor 1〇6 that provides a substrate bias voltage VBPA. The clamp enable signal ENN can be supplied to the gate of the N-type channel device N1 and the input terminal of the inverter 401. The drain and gate of the β-channel device pi are coupled to the drain and p-channel of the N-channel device N1. The gate of device P2. The output end of the inverter 401 is coupled to the gate of the n-type channel device N2, and the drain of the N-type channel device N2 is coupled to the drain of the P-channel device P2 and the P-channel device P3 and the N-channel device. The gate of N3. The drain of the P-type channel device P3 is coupled to the drain of the N-channel device]Sf3 and the idler of the P-channel device P4 and the N-channel device N4. The p-type channel device P4 is coupled to the drain of the N-type channel device N4, and the output clamps the shift enable signal NEN signal. In operation, the input clamp enable signal ENN signal is set between the reference voltage vss and the core voltage VDD. The signal of the output clamp shift enable signal NEN is set between the base bias voltage VBPA and the core voltage VDD. When the clamp enable signal ENN CNTR2419I00-TW/0608-A41899-TWF 24 201013836

- Set to core voltage VDD, N-type channel device N1 is turned on and N-type channel. Device N2 is not turned on (the output of inverter 401 is reference voltage VSS). The N-type channel device N1 pushes the gate of the P-type channel device P2 to the substrate bias voltage VBPA, so that the P-type channel device P2 is turned on. The P-type channel device P2 pushes the gate of the P-channel device P3 and the N-channel device N3 to the core voltage VDD, so that the P-channel device P3 is not turned on and the N-channel device N3 is turned on. The N-channel device N3 pushes the gate of the P-channel device P4 and the N-channel device N4 to the substrate bias voltage VBPA, so that the N-channel device N4 is non-conducting and the P-channel device P4 is turned on. Therefore, when the clamp enable signal ENP signal is set to the core voltage VDD, the signal of the clamp shift enable signal NEN pushed through the P-channel device P4 is the core voltage VDD. When the clamp enable signal ENN is set to the reference voltage VSS, the N-channel device N1 will not be turned on and the N-channel device N2 will be turned on. Since the N-type channel device N1 is non-conducting, the P-type channel device P1 pushes the gate of the P-type channel device P2 to a very high level, so the P-type channel device P2 is not turned on. The N-type channel device N2 pushes the gate of the P-channel device P3 and the N-channel device ® N3 to the substrate bias voltage VBPA, which turns on the P-channel device P3 and does not conduct the N-channel device N3. The P-type channel device P3 pushes the gate of the P-channel device P4 and the N-channel device N4 to the core voltage VDD, and will not turn on the P-channel device P4 to turn on the N-channel device N4. Therefore, when the clamp enable signal ENN is set to the reference voltage VSS, the N-type channel device N4 pushes the clamp shift enable signal NEN signal to the substrate bias voltage VBPA. In this manner, the clamp enable signal ENN is switched between the reference voltage VSS and the core voltage VDD, and the clamp shift enable signal NEN CNTR2419I00-TW/0608-A41899-TWF 25 201013836 is switched to the substrate bias voltage VBPA and Between the core voltage VDD. Referring back to FIG. 1 'When the bias generator 112 drives the substrate bias voltage VBNA to be higher than the core voltage vdD, the P-type level shifting circuit 116 will ensure that the P-channel clamp device PC1 is completely in the low power mode. Not conductive. More specifically, when the bias generator 1!2 drives the substrate bias voltage VBNA higher than the core voltage VDD, the control device 114 sets the level of the clamp enable signal ENP to the core voltage VDD, and clamps the P-channel. The bit device PC1 is not turned on. If the clamp enable signal ENP is directly supplied to the gate of the P-channel clamp device PC1, the gate potential of the above-mentioned p-channel clamp device PC1 will be only at the core voltage VDD and the potential of the drain will be higher than the core. The voltage VDD may cause the p-channel clamp device to be partially turned on. However, 'the P-type level shifting circuit 116 drives the voltage level of the clamp shift enable signal PEN to the substrate bias voltage VBNA, so the gate and the drain of the P-channel clamp device PC1 are both higher than the core voltage VDD. The voltage level of the substrate bias voltage VBNA ensures that the p-channel clamp device pci is completely non-conductive. When the bias generator 112 drives the substrate bias voltage VBPA to a voltage lower than the reference voltage VSS, the N-type level shifting circuit 118 will ensure that the N-channel clamp unit NC1 is not conducting at all in the low power mode. More specifically, when the bias generator 112 drives the substrate bias voltage VBNA lower than the reference voltage VSS, the control device 114 sets the level of the clamp enable signal ENN to the reference voltage VSS to turn off the N-channel clamp device. NC1. If the clamp enable signal ENN is directly supplied to the gate of the N-channel clamp device NC1, the potential of the gate of the N-channel clamp device NC1 will be only at the reference voltage VSS and the potential of the drain will be lower than the reference. Voltage

CNTR2419IOO-TW/0608-A41899-TWF 26 201013836 ~ VSS, may cause the NCI channel clamp NCI part to be turned on. However, the N-type level shifting circuit Π8 drives the clamped shift enable signal NEN to the voltage level of the substrate bias voltage VBPA, so the potentials of the gate and the drain of the N-type level shifting circuit Π8 are lower than The voltage level of the substrate bias voltage VBPA of the reference voltage VSS ensures that the N-channel clamp device NC1 is not conducting. Next, referring to FIG. 2, when the substrate bias voltage VBNA of the substrate bias wire 104 is driven to a voltage level higher than the core voltage VDD, the corresponding at least one clamp enable signal ENP&lt;3:0&gt; is set to a high level. The P-type register shift circuit 116 respectively moves the corresponding clamp shift enable signal PEN&lt;3:0&gt; to ensure that one or more of the P-channel clamps PC1_PC4 are completely non-conducting. The P-type buffer circuit 201 drives the buffer clamp shift enable signal BPEN&lt;3:0&gt; to a level shift voltage region between the reference voltage VSS and the substrate bias voltage VBNA to ensure that the buffer clamp shift enable signal BPEN&lt;; 3: 0&gt; set to high-level on-time 'clamping device; PC5-PC8 is also completely non-conducting. Similarly, when the substrate bias voltage VBPA of the substrate bias wire 106 is driven to a voltage level lower than the reference voltage VSS, the corresponding at least one clamp enable signal ENN&lt;3: 〇&gt;s is set to a low level. The N-type level shifting circuit us respectively moves the corresponding clamped shift enable signal NEN&lt;3:0&gt; to ensure that one or more of the N-channel clamps NC1-NC4 are completely non-conducting. The Si-type buffer 203 drives the buffer clamp shift enable signal 3&gt;^&gt;^&lt;3:0&gt; to a level shift voltage region between the core voltage VDD and the substrate bias voltage VBPA to ensure buffer clamping When the shift enable signal BNEN &lt;3:0&gt; is set to the low level, the clamp devices NC5-NC8 are also completely non-conductive. Figure 5 is a diagram showing a p-type retardation according to an embodiment of the present invention.

CNTR2419I00-TW/0608-A41899-TWF 27 201013836 Punch 2:1. Clamping Shift Enable (4) pEN signal is supplied to the channel device Ρ1" Ν-type channel cleave N1. The source device 2α Ϊ of the channel device Ϊ is coupled to the substrate biasing wire 1〇4 (providing the substrate bias) The drain of the channel device Ρ1 is coupled to the gate Ν of the 通道-type channel device N1, the (four) channel device P1 and the N-type money-passing device N1 are coupled to the gate of the P-channel device ΡβΝ-type channel device N2. The source and the substrate of the channel device Ρ2 are connected to the base biasing wire I. The channel device Ρ2 and the pole is connected to the 汲-type channel device Ν2. The 通道-channel device Ν1 ^Ν2 secret to the reference voltage VSS'P type channel device P2 and N Landau device Μ 秘 秘 秘 移位 移位 移位 移位 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Both the device ρι and the N-type channel device N2 will be turned on, while the p-type channel device p2 and the N-type channel device N1 are not turned on, so the buffer clamp shift enable signal BPEN will be driven to the reference voltage VSS. When the shift enable signal is clamped When the PEN signal is the substrate bias voltage VBNA, neither the p-channel device pi nor the n-channel device N2 At the same time, both the P-channel device P2 and the N-channel device N1 are turned on to push the buffer clamp shift enable signal BPEN to the substrate bias voltage VBNA. In this manner, the buffer clamp shift enable signal βρεν and the clamp shift The bit enable signal PEN has the same logic state and is switched between the reference voltage VSS and the level shift voltage region of the substrate bias voltage VBNA. Fig. 6 shows an N-type buffer according to an embodiment of the present invention. The signal of the clamp shift enable signal NEN is supplied to the gates of the P-channel device P1 and the N-channel device N1. The CNTR2419IO0-TW/0608-A41899-TWF 28 of the P-channel device P1 28138138 The core voltage VDD is coupled to the p-type channel device P1

The material of the type channel device N1. The source and base of the N-channel device m are connected to the substrate biasing wire (10) (provided to the substrate bias vbpa). The p-type channel device P1 and the N-type channel device m are shredded to the gate of the p-type channel device P2 and the N-channel |N2. The source of the p-type channel device is connected to the source biasing of the core voltage VDD and the P-type channel device P2 to the source and the substrate of the P-type channel device n2 of the N-channel device N2 to the substrate biasing wire 1G6 And the drain of the p-type channel device p2 and the drain of the N-channel device N2 form a buffer clamp shift enable signal BNEN signal. In the operation of the machine, when the (four) township enable signal NEN signal to the base bias (4) ^ channel device ^ ❹ type channel device N2 will be turned on 'the p-channel device p2 and N-channel device N1 non-conducting (4) The dynamic buffer clamps the shift enable signal BNEN to the substrate bias voltage VBPA. When the clamp shift enable signal NEN is pushed to the core voltage VDD, the 'P-channel device ρ and the N-channel device N2 are not turned on'. The _p-channel device p2胄N-channel device is turned on to push the buffer. The shift enable signal BNEN is clamped to the core voltage VDD. In this manner, the 'buffer clamp shift enable signal bNEN has the same logic state as the tank shift enable signal NEN and the buffer clamp shift enable signal BNEN is switched to the level shift of the core voltage VDD and the substrate bias VBPA. Between voltage zones. Figure 7 is a diagram showing a substrate biasing circuit 706 integrated into a selected region of a die of a microprocessor 700, including a plurality of distributed clamping devices, in accordance with an embodiment. In an embodiment, the microprocessor

CNTR2419IO0^TW/0608-A41899-TWF 29 201013836 700 is in four regions or quadrants 7〇i, 702, 703 and - 704. In this embodiment, the biasing means in the quadrant 7〇4 of the microprocessor 7 is the substrate biasing circuit 706. As shown in the embodiment, in the low power mode, the substrate bias circuit 706 is used to bias the device located in the quadrant 7〇4 of the microprocessor 7. The substrate biasing circuit 706 is similar to the substrate biasing circuit 202' of Figure 2 and is located entirely or substantially in the quadrant 7〇4 of the microprocessor 7. The substrate biasing circuit 706 includes a first substrate biasing conductor 7〇8 for biasing a plurality of P-type channeling devices 726 in quadrants 7〇4 and a plurality of N-type channeling devices 728 for biasing the quadrants 704. The second substrate biases the φ line 710. The architecture of the above-described channel devices 726 and 728 is similar to the P-channel device 111 type channel arrangement 113 of Figure i. The plurality of 卩-type channel devices 726 and N-type channel devices 728 respectively have a plurality of substrate contacts coupled to the substrate bias wires 708 and 710. In a simple form (e.g., a square), display devices 726 and 728 are bonded to their substrate to substrate biasing conductors 7A and 71A. Although it is known to those skilled in the art that the plurality of p-type channel mounts/sets 726 and N-channel means 728 are distributed throughout the region of quadrants 7〇4, they are still shown at one edge of quadrant 704. _ In the embodiment shown herein, other devices 705 (e.g., a plurality of p-channel devices and N-channel devices) are distributed in quadrants 701-703 of microprocessor 7. In a low power mode, when the quadrants 726 and 728 of the quadrant 7 〇 4 cease to operate, the other devices 705 are still powered on and enabled. Any one or more other devices 7〇5 of the outside of the quadrant 7〇4 may have a separate substrate bias circuit or a separate substrate bias circuit depending on the actual architecture of the microprocessor 700. . In an embodiment

CNTR2419I00-TW/0608-A41899-TWF 30 201013836 When the operation mode is set to τ, the base bias voltage for the separation is divided. = 4 He quadrant, to bias the base of the above quadrant. In another embodiment, any of the other devices 7〇5 of the microprocessor 700 can be formed as part of the necessary circuit (ie), and there is no need to provide a base/house circuit for the (four) or biasing the substrate. Disconnecting a P-channel clamp device 712 coupled between the substrate bias wires 708 • / f core voltage VDD, the plurality of channel clamp devices 714 are consuming the substrate bias wires 710 and the reference Between voltage vss. The architecture and operation method of the channel clamp device 712 in an embodiment are respectively equivalent to the P-channel clamp device pci_pc8 of the microprocessor 200 in FIG. 2, and the structure and operation method of the n-channel clamp device 714 are respectively equivalent to N-channel clamps (10)-(10) of microprocessor 200, wherein clamps 712 and 714 are shown in a simple form, such as a circle symbol. The microprocessor 7 includes a central control unit 7G7 which controls the quadrant control (QC) unit 716 via a corresponding control nickname CCTL. Although the central control unit 707 is shown in quadrant 702, central control unit 7〇7 can be placed at any location in microprocessor 7. The quadrant control device jaws provide a control signal QCTL to control the bias detector _718, which operates in a manner similar to the aforementioned bias generator 112 and has an output terminal 'biasing the conductors 7〇8 and 71 respectively on the substrate 〇 Forms the substrate bias voltages VBpA and VBNA. Quadrant control device 716 provides clamp enable signals ENN and ENP to level shift circuit 72A. The level shifting circuit 72A includes a p-type level shifting circuit (not shown) and an N-type level shifting circuit (not shown), and the above-mentioned p CNTR2419I00-TW/0608-A41899-1 31 201013836 type and N The type level shifting circuits are respectively approximated by the aforementioned level shifting circuits 116^118' for respectively converting the clamps outputted by the quadrant control means 716 to cause the signals ENN and ENP to be the clamped shift enable signals NEN and PEN. In the illustrated embodiment, the clamp shift enable signal NEN is finally controlled by all P-channel home devices 712, while the clamp enable signal PEN is clamped to control all n-channel clamps m14t) P-type buffer h ( Pb) 722 / port clamps the signal line distribution of the shift enable signal PEN to meet the buffered shift enable signal PEN required for a plurality of locations. Similarly, the N-type buffer (NB) 724 is distributed along the signal line of the clamp shift enable signal nen to satisfy the buffer clamp shift enable signal NEN required by the plurality of positions. The method approximates the aforementioned substrate bias circuit 202. In normal mode of operation, devices 726 and 728 in quadrant 704 power up 'quadrant control device f 716 to indicate that bias generator 718 drives substrate bias wires 7 〇 8 and to core voltage vDd and reference voltage, respectively. The voltage level of vss. The quadrant control device 716 sets the home enable signals ENN and ENP to conduct the (four) bit devices 712 and 714, and clamps the substrate bias wires 7〇8 and 71〇 to the core voltages VDD and 10, respectively, to the reference voltage VSS. The voltage level at which the shift enable NEN and PEN are shifted to the level shift is set in accordance with the above-described level shift circuit 72. The substrate bias generator 718 can be non-conducting or in a low power mode if desired. In the low power mode, when the devices 726 and 728 in quadrant 7 电力 power down the 'quadrant control device 7 丨 6 sets the clamp 'enable signals ENN and ENP ' to disable the clamping devices 712 and 714 And the level shift circuit 720 sets the clamp shift enable signal NEN and the pEN letter

CNTR2419I00-TW/0608-A41899-TWF 32 201013836 The voltage level of the ‘number to the level shift. In the foregoing approximate manner, quadrant control. Device 716 instructs bias generator 718 to drive substrate biasing conductor 7〇8 to a substrate bias higher than core voltage VDD and drive substrate biasing conductor 710 to below reference voltage VSS. A substrate bias. Therefore, in the low power mode, the subcritical leakage current can be reduced and the bit devices 722 and 724 are fully turned off. In this manner, when quadrant 704 of microprocessor 700 effectively ceases to function, some or all of the devices in quadrants 701-703 remain powered on or enabled. _ People familiar with this art know that there may be multiple changes. The central control unit 707 can be located anywhere in the microprocessor 700 and can control other substrate bias circuits (not shown) that are similar to the substrate bias circuit 706 and located at the microprocessor 700. on. For example, the other quadrants 701-703 can each include an approximate substrate biasing circuit and control the substrate biasing circuit with a central control device 707 for biasing one or more other devices 705. Although the substrate bias circuit 706 is shown to bias φ the device located in the actual quadrant region 704 of the microprocessor 700, the substrate bias circuit 706 can adjust one of the corresponding ranges and positions of the bias voltage to bias Any selected range of microprocessors 700 is either a device of an area (e.g., 1/8, 1/4, 1/2, and 3/4, etc.). At the same time, any number of substrate biasing circuits can be used to bias the devices located in selected regions of the microprocessor 7A. In one embodiment, a plurality of substrate biasing circuits may share a bias generator. Figure 8 is a block diagram showing a microprocessor divided into regions according to an embodiment. The above regions respectively include distributed clamp means and a base bias circuit. Central control unit 802 provides control signals CTL1, CTL2 33

CNTR2419IOO-TW/O608-A41899-TWF 201013836 and CTL3 to control substrate bias, respectively for devices 804, 806 and 808. The base bias circuit 810 of the control signal CTL1 control region 804; the base bias circuit 816 of the control signal CTL2 control region 806 and the base bias circuit 822 of the control signal CTL3 control region 808. Substrate biasing circuits 810, 816 and 822, respectively, approximate substrate biasing circuit 706 of Figure 7 for providing a substrate biased to a corresponding pair of substrate biasing conductors for each of the regions. In this manner, the substrate bias circuit 810 provides a base.

Bottom bias, P-channel device 812 and N-channel device 814 for region 804; substrate bias circuit 816 provides substrate bias for P-channel device 818 and N-channel device 820 and substrate for region 806 Bias circuit 822 provides a substrate bias for P-channel device 824 and N-channel device 826 for region 808. The P-channel clamp device and the N-channel clamp device are respectively used to face the base bias wires of each of the regions 804, 806 and 808, and the clamps are controlled by the base bias circuits 81, gw and 822, respectively. The method of operation of the bit device (not shown in Figure 8) approximates the method of operation of the bias circuit 706 described above. In this manner, the central control unit 802 忐 selectively stops the operation of the device in any one or more of the regions 808 'where it is in the region where the operation is stopped, and the corresponding base bias circuit provides the base voltage to the pair (four), The above areas are operated and the sub-critical leakage current is minimized. At the same time, when the region m, 8 () 6 and the speaker 彳 τ are stopped, the substrate bias circuit having the level shift circuit will make the tank device completely non-conductive. However, when the region 8〇4, the intestine and the should be enabled, the corresponding clamping device will be turned on to clamp the substrate biasing wire to the core 4 to VDD and the reference voltage, respectively, to minimize the noise.

CNTR2419I00-TW/0608-A41899-TWF 34 201013836 - Any of the foregoing embodiments can be applied to more types of architectures, reference • Voltage (such as VSS) can be approximated to Volts (V) and core voltage (eg VDD) can be approximated to 1V. In one embodiment, the bias generator drives an offset voltage of 8 volts volts (mV) to a corresponding core voltage level and a reference voltage level, respectively. In one embodiment, during the low power mode, when the core voltage VDD is lv, the substrate bias voltage VBNA is approximately 1.8V, and when the reference voltage VSS is 0V, the substrate bias voltage VBPA is approximately _800 millivolts. The actual core voltage can be varied depending on the mode of operation of the device. For example, the core voltage VDD can vary between approximately 5 〇〇 mV and 14 V under actual architectural mode or actual state. In one embodiment, the offset voltage of the substrate bias VBNA may be different from the offset voltage of the substrate bias voltage VBPA, e.g., the offset voltage is 3 〇〇 mV and 5 〇〇 mV, respectively. In any event, bias generator 112 drives substrate bias voltage VBNA and VBPA substrate bias conductors 1〇4 and 1〇6, respectively, with an offset voltage relative to the corresponding core voltage and reference voltage. During the normal mode of operation of an embodiment, the clamping device is placed along the substrate bias wire to ensure that the voltage of each substrate biasing wire varies from core voltage to reference voltage when the clamping device is enabled. More than a predetermined minimum voltage level. In one embodiment, the predetermined minimum voltage level is approximately 10 mV. In one embodiment, the predetermined minimum voltage levels that are varied by the core voltage and the reference voltage are not the same. The predetermined minimum voltage level is determined according to the architecture and number of actual application devices (e.g., integrated circuit 100 or microprocessors 2, 7 and 8). The position of the clamp can be determined by any method (such as mathematical analysis or dynamic simulation) to ensure the base

CNTR2419I00-TW/O608-A41899-TWF 35 201013836 The bias voltage of the biasing conductor is maintained within the range of the predetermined minimum voltage level with respect to the fluctuation of the core voltage vdd盥 reference voltage VSS, respectively. In other embodiments, the substrate bias may be provided off-wafer, so the integrated circuit or wafer substrate may include a bias generator or may not include a bias generator. For example, the integrated circuit 1 or the microprocessor 2 may not include the bias generator 112' so that the substrate biases VBNA and VBPA are externally supplied. Similarly, microprocessor 700 does not include bias generator 718, and any of substrate bias circuits 810, 816, and 822 of microprocessor 800 bite multiple circuits. When the microprocessor 700 does not include a bias generator, there is substantially the same behavior since the suppressor still controls the clamp and the corresponding circuitry. The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention, and those skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The protected area of the present invention is subject to the definition of the scope of the patent application.

CNTR2419I00-TW/0608-A41899-TWF 201013836 [Simplified Schematic] FIG. 1 is a diagram showing a conventional substrate bias circuit including a conventional integrated circuit on a P-type substrate according to an embodiment of the present invention. A CMOS device and a schematic diagram showing a substrate bias circuit integrated in an integrated circuit in accordance with an embodiment. Figure 2 is a block diagram showing a substrate biasing circuit integrated into a microprocessor die, including a distributed φ clamping device, in accordance with an embodiment of the present invention. 3 is a schematic diagram showing a p-type level shifting circuit according to an embodiment of the present invention, and the P-type level shifting circuit can be used as a P-type level shifting circuit of FIGS. 1 and 2. Fig. 4 is a view showing an n-type level shifting circuit according to an embodiment of the present invention, wherein the N-type level shifting circuit can be used as the 1ST type level shifting circuit of Figs. 1 and 2; 5 and 6 are schematic views showing p-type and N-type buffers according to an embodiment of the present invention. Figure 7 is a schematic illustration of a substrate biasing circuit integrated into a selected region of a microprocessor wafer, including a distributed clamping device, in accordance with an embodiment of the present invention. Figure 8 is a block diagram showing a microprocessor divided into a plurality of regions, each of which includes a substrate biasing circuit and a distributed clamping device, respectively, in accordance with an embodiment of the present invention. [Description of main component symbols] CNTR2419I00-TW/0608-A41899-TWF 37 201013836 100 to integrated circuit 101 to P type substrate 102, 202, 706, 810, 816, 822 to base bias circuit 103, 105, 107~ N-type well regions 104, 106, 708, 710 to base biasing conductors 109 to P-type well regions 111, 726, 824, PI, P2, P3, P4 to P-type channel devices 112, 718 to bias generator 113, 728, 826, N1, N2, N3, N4~N type channel device 114~ control device 115, 117, 127~P type diffusion region 116~P type level shift circuit, LSP 118~N type level shift circuit , LSN 119, 123, 125~N type diffusion region 12 129 ～ gate insulating layer 200, 700, 800~ microprocessor 201, 722~P type buffer; 203~N type buffer 301, 401~ reverse 701, 702, 703, 704 to quadrant 705 to other devices 712 to a plurality of P-channel clamp devices 714 to a plurality of N-channel clamp devices 707, 802 to central control devices

CNTR2419I00-TW/0608-A41899-TWF 201013836 716~quad control device 720~level shift circuit 804, 806, 808~ area BCTL~bias control signal CCTL, QCTL, CTL1, CTL2, CTL3~ control signal ENP, ENN ~ Clamp enable signal NC1 ~ NC8 ~ N type channel clamp device PEN, NEN ~ clamp shift enable signal PC1 ~ PC8 ~ P type channel clamp device VBPA, VBNA ~ base bias VDD ~ core voltage VSS ~ reference Voltage

CNTR2419I00-TW/0608-A41899-TWF 39

Claims (1)

201013836 VII. Application for Patent Park··, including '· Provided during a first mode of operation. A microprocessor device-first substrate biasing wire, a first substrate bias; to the small original supply node' provides a core a voltage; ^ ^ ^, disposed between the first substrate biasing and guiding the rear disk t to the second power supply node; and the material line and the upper device coupled to the at least one of the clamping devices, During the first mode of operation, the first substrate biasing device is turned off to turn off the first operating mode 34 first power supply node and during the first mode of operation 'not conducting at least the above-described home device. 2. The microprocessor of claim 1, wherein: at least one of the clamp devices comprises a semiconductor device having a gate connected to the first power supply node - a source Depressing one of the first substrate biases; and wherein the control device provides a first clamp enable signal to control the gate of the semiconductor device. 3. The microprocessor of claim 2, further comprising: a quasi-shift circuit having an input for receiving the first clamp enable signal and providing a clamp shift enable signal And an output terminal of the semiconductor device; and during the first operation mode, the control device sets the first clamp enable signal to the core voltage, and causes the level shift circuit to set the clamp shift The enable signal is applied to the first substrate bias 40 CNTR2419I00-TW/0608-A41899-TWF 201013836 to disable the semiconductor device. 4. The microprocessor of claim 2, wherein the semiconductor device comprises one selected from the group consisting of a -P type channel device and an -N type channel device. 5. The microprocessor of claim 1, further comprising: a second substrate biasing wire, providing a second substrate bias during the first mode of operation; and an eighth power supply node, Providing a 〆 reference voltage; wherein, in the first mode of operation, the first substrate bias has a positive-element bias with respect to the core voltage, and the second substrate bias has a negative voltage offset with respect to the reference voltage At least one of the above-mentioned clamping devices includes a plurality of p-type channel devices coupled between the first substrate biasing wires and the first power supply node, and coupled to the second substrate biasing wires and the first a plurality of N-channel devices between the power supply points; and ', wherein the control device includes a first output terminal and a second output terminal, the first output terminal is configured to provide a --clamp enable signal The P-channel device is configured to provide a second bit enable signal to control the N-channel device. 6. The microprocessor of claim 5, further comprising: a P-type level shifting circuit 'having an input-portion coupled to the first output terminal of the control device And at least one output terminal of the gate of the device; and, an N-type level shifting circuit, having a button on the CNTR2419I00-TW/0608-A41899-TWF 201013836 end of the control device, and Translating at least one of the gates of the gate of the N-channel device; wherein the control device switches the previous signal between the reference power and the above ==, which causes the upper level shift circuit And the output terminal of the shift circuit according to the upper touch: between the == voltage and the first base-stitch, and (4) above: switching the N-type shift according to the second clamp enable signal The above 7 is between the above core voltage and the second substrate bias. The micro-processing H described in item 6 of the β patent range further includes: the above-mentioned p-type level shifting circuit having one input end of the output end and one of the at least one of the above devices An output terminal having an input terminal coupled to the output terminal of the Ν-type level shifting circuit and coupled to an output of at least one of the ν-type channel devices; The Ρ type buffer switches the output end of the p-type buffer between the reference voltage and the first substrate bias, and the 缓冲器 type buffer switches the output end of the 缓冲器 type buffer to the core voltage and Between the above second substrate biases. 8. The microprocessor of claim 1, further comprising a substrate having a first region and a second region; a plurality of first semiconductor devices located in the first region; and a plurality of second semiconductor devices, Located in the second region; and CNTR2419IO0-TW/0608-A41899-TWF 42 201013836, wherein the first substrate bias wire is wound around the first semiconductor device located in the first region of the substrate to be the first The operating mode biases the first semiconductor device while the second semiconductor device remains powered on. The microprocessor of claim 8, wherein the civic device is distributed along the first substrate biasing wire located in the first region of the substrate. The microprocessor of claim 1, further comprising: a substrate having a first region and a second region; wherein the first substrate biasing wire is located in the first region; The substrate biasing wire is located in the second region, and provides a second substrate bias in a three-operation mode; and includes the remaining first region and is face-to-face. -^^ ^: the first region is coupled to the upper portion The control device is configured to connect the upper clamp biasing lead and the second base cilia to the first base (four) point in the first clamp device and the second clamp, and the power supply is not provided and turned on in the ith mode In the second clamping device, the first clamping device does not conduct the second clamping device. The microprocessor described in the third mode of operation lh, as described in the scope of the patent application, includes: CNTR2419I00-TW/0608-A41899-TWF 43 201013836 A substrate 'having a - region-and a second region The above-mentioned first-substrate bias line is located in the above-mentioned first region; the first wire is located in the second region, and a second substrate is provided in the first operation mode; and the clamping device comprises the above-mentioned clamping device a first region and a light connection = - a base bias and the first power supply node = a reference: a first = bottom line and the first power supply node two first clamp devices; and wherein the control device is in the above During the second mode of operation, turning on the upper = the third bit device and not conducting the second clamping device to clamp the first base bias wire to the first power supply node, during the first mode, the first mode is not turned on And clamping the second clamping device to clamp the second substrate biasing wire to the first supply node. An integrated circuit comprising: a substrate; a first substrate biasing wire and a second substrate biasing wire on the substrate; a first power supply conductor located on the substrate to provide a a core voltage, wherein the core voltage is relative to a reference voltage provided by a second source supply conductor of the substrate; wherein during the first mode of operation of the integrated circuit, a first substrate bias is provided The first substrate biases the wire and provides - the first US CNTR2419IO0-TW/0608-A41899-TWF 44 201013836 bottom biased to the second substrate bias wire, wherein the first substrate bias is higher than the core voltage The second substrate bias is lower than the reference voltage; at least one first clamping device is provided on the substrate, and at least one of the first clamping devices is respectively coupled between the first power supply conductor and the first substrate bias wire At least one first clamping device is provided on the substrate, at least one of the above The second clamping device is respectively coupled between the second power supply conductor and the second substrate biasing wire; and a control device has a first output for controlling at least one of the first clamping devices, and Controlling at least one of the second clamping devices of the second clamping device; wherein the control device does not conduct at least the first clamping device and the at least the second clamping device in the first operating mode, The second operation mode turns on at least one of the first clamping device and the at least one second clamping device to: the first substrate biasing wire to the first power supply conductor and (4) the second substrate bias wire to The second power supply conductor described above. 13. The integrated circuit of claim 12, wherein at least the first clamping device comprises a -" channel device having a source connected to the first power supply conductor, (d) a second-type power supply guide for the bottom-biased conductor-drain and the gate-controlled by the upper end of the control device and at least one of the second and first first-type N-channel devices CNTE12419I00-TW/Q608-A41899-TWF 45 201013836 The source-source, which is controlled by the above-mentioned second round of the above-mentioned control device of the second base dust guide, is controlled by the patent application scope The integrated body according to Item 13 includes: the above-mentioned first-base=upper-substrate contact and t-the above-mentioned N-th-pass, one of the second base biasing wires of the wire In addition, the integrated circuit described in claim 13 of the patent application, the package-first level shifting circuit 'has the input-output terminal of the above-mentioned control-output terminal and Said to be connected to the above-mentioned upper device The control/the above-mentioned first output terminal of the channel control device to the reference voltage to the first-P-type channel device' and the end of the control device to the core voltage to not conduct the first-type output The first-level shifting circuit switches the first p-type pass and the gate to the reference voltage to turn on the first two and switch the gate of the first-P-type channel device to the d' bias The first P-channel device is not turned on; and the substrate-second level shift circuit has (4) an input terminal of the second output end of the control device, and the gate coupled to the first N device One of the output terminals, wherein the control device, the second output end of the track control device to the core voltage is returned to the first N-type channel device, and the fan terminal of the control device is switched to the reference voltage to not conduct the above The first N-channel output is CNTR2419I00-TW/0608-A41899-TWF 201013836. The second level shift circuit is switched over the first N-channel device. Passing the gate to the core voltage to turn on the first N-type channel device, and switching the gate of the first N-type channel device to the second substrate to not turn on the first N-type channel device. The integrated circuit of claim 15 further comprising: at least one of the first clamping devices comprising a second P-channel device having a source coupled to the first power supply conductor and coupled The first buffer has a drain and a gate; and the first buffer has an input coupled to the output of the first level shifting circuit, and coupled to the first An output terminal of the gate of the second P-type channel device, wherein the first buffer switches the output end of the first buffer with the output terminal of the first level shifting circuit at the reference voltage Between the first substrate biases; at least one of the second clamping devices includes a second N-channel device coupled to one of the second power supply conductors and coupled to the second base One of the biasing wires and one of the gates; and a second buffer having an input coupled to the output of the second level shifting circuit and coupled to the second N-channel device One of the output terminals of the gate, wherein the second buffer switches the output end of the second buffer, and the output terminal of the second level shifting circuit is biased to the core substrate and the second substrate between. 17. The integrated circuit of claim 12, wherein at least one of the first clamping devices comprises a plurality of first base biasing wires CNTR2419I00-TW/0608-A41899-TWF 47 201013836. a clamping device for conducting the first clamping device in the second state to maintain the voltage of the first substrate biasing wire within a first predetermined minimum voltage level with respect to the variation of the core voltage, wherein At least one of the second clamping devices includes a plurality of second clamping devices distributed along the second substrate biasing conductor for conducting the second clamping device in the second operating mode to maintain the second substrate bias The voltage of the wire is within a second predetermined minimum voltage level with respect to the change in the reference voltage. 18. The integrated circuit of claim 12, wherein the substrate is divided into a first region and a second region, each having a plurality of semiconductor devices, and wherein the first substrate bias wire and the second substrate are biased A wire and at least one of the first clamping devices are located in the first region of the substrate. 19. A method of reducing wafer noise for a microprocessor chip, the microprocessor chip comprising a first substrate biasing wire for reducing a sub-critical leakage current, the method comprising: when the microprocessor chip is a first power state, clamping the first substrate bias wire to a core voltage; and when the microprocessor chip is in a second power state, not clamping the first substrate bias wire and providing a first substrate bias Pressing to the first substrate biasing wire described above. 20. The wafer noise reduction method of claim 19, wherein the step of clamping the first substrate bias wire to the core voltage comprises turning on the selected plurality of first clamping devices, the plurality of first clamps CNTR2419I00-TW/0608-A41899-TWF 48 201013836 - The bit device is used to maintain the voltage of the substrate biasing conductor above the core voltage variation relative to the above, at a first predetermined minimum voltage level and along the plurality of first clamping devices The first substrate biased conductor is distributed as described above. 21. The wafer noise reduction method of claim 19, further comprising: coupling a drain of a first semiconductor device and a source between the first substrate bias wire and the core voltage When the microprocessor chip is in the first power state, turning on the first semiconductor device; when the microprocessor microprocessor is in the second power state, the first semiconductor device is not turned on. 22. The wafer noise reduction method of claim 21, wherein: the step of providing a first substrate bias further comprises providing an offset voltage to drive the voltage of the first substrate biasing conductor to be higher than the core And the step of not conducting the first semiconductor device includes: providing a first clamp enable signal, wherein the first clamp enable signal sets a gate of the first semiconductor device to be higher than the offset voltage of the core voltage Voltage level. 23. The wafer noise reduction method of claim 21, wherein: the step of providing a first substrate bias further comprises providing an offset voltage to drive the voltage of the first substrate bias wire to be lower than the above Core voltage; CNTR2419I00-TW/0608-A41899-TWF 49 201013836 and the step of not conducting the first semiconductor device therein includes providing a first clamp enable signal, and the first clamp enable signal is disposed on the first semiconductor device A gate to a voltage level lower than the above-mentioned offset voltage of the core voltage. 24. The wafer noise reduction method of claim 22, further comprising: coupling a drain of a second semiconductor device and a source between the first substrate bias conductor and the core voltage And providing a buffer to the microprocessor chip, wherein the buffer is configured to buffer the first clamp enable signal to provide a buffer clamp enable signal to one of the gates of the second semiconductor device, wherein the buffer clamp The bit enable signal is the same as the voltage level of the first clamp enable signal. 25. The wafer noise reduction method of claim 23, further comprising: coupling a drain of a second semiconductor device and a source between the first substrate bias wire and the core voltage And providing a buffer to the microprocessor chip, wherein the buffer is configured to buffer the first clamp enable signal to provide a buffer clamp enable signal to one of the gates of the second semiconductor device, wherein The buffer clamp enable signal is the same as the voltage level of the first clamp enable signal. 26. The wafer noise reduction method of claim 19, wherein the microprocessor chip is divided into a first region and a second region, and includes a second substrate bias wire, wherein the first The substrate is biased CNTR2419IO0-TW/06O8-A41899-TWF 50 201013836. The pressure wire is located in the first region, and the second substrate bias wire is located in the second region, and the chip noise reduction method further comprises: when the microprocessor chip And clamping the second base bias wire to the core voltage during the first power state and the second power state; and clamping the second base bias wire when the microprocessor chip is in a third power state And providing a second substrate bias to the second substrate biasing wire. The wafer noise reduction method of claim 19, wherein the microprocessor chip is divided into a first region and a second region, and includes a second substrate bias wire, wherein the a substrate biasing wire is located in the first region, and the second substrate biasing wire is located in the second region, and the chip noise reduction method further comprises: clamping the first chip when the microprocessor chip is in the second power state a second substrate biasing wire to the core voltage; and when the microprocessor chip is in the first power state, not clamping - the second substrate biasing wire and providing a second substrate bias to the second substrate bias wire. CNTR2419IO0-TW/O608-A41899-TWF 51