TWI387087B - Three-dimensional conducting structure and method of fabricating the same - Google Patents

Three-dimensional conducting structure and method of fabricating the same Download PDF

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TWI387087B
TWI387087B TW097129949A TW97129949A TWI387087B TW I387087 B TWI387087 B TW I387087B TW 097129949 A TW097129949 A TW 097129949A TW 97129949 A TW97129949 A TW 97129949A TW I387087 B TWI387087 B TW I387087B
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substrate
pad
hole
active surface
conductor
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TW097129949A
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Chinese (zh)
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TW201007914A (en
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Hsiang Hung Chang
Shu Ming Chang
Tzu Ying Kuo
Yuan Chang Lee
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Ind Tech Res Inst
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

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Description

立體導通結構及其製造方法Three-dimensional conduction structure and manufacturing method thereof

本發明是有關於一種導通結構及其製造方法,且特別是有關於一種立體導通結構及其製造方法。The present invention relates to a conductive structure and a method of fabricating the same, and more particularly to a three-dimensional conductive structure and a method of fabricating the same.

廣泛來說,系統構裝(System in Package,SiP)涵括了早期的多晶片模組(Multi-chip Module,MCM)技術、多晶片封裝(Multi-chip Package,MCP)技術、晶片堆疊(Stack die)、PoP(Package on Package)、PiP(Package in Package)以及將主/被動元件內埋於基板(Embedded Substrate)等技術。以結構外觀來說,MCM屬於二維的2D構裝,而MCP、晶片堆疊、PoP、PiP等則屬於立體的3D構裝;由於3D構裝更能符合小型化、高效能等需求,因而近年來備受業界青睞。Broadly speaking, System in Package (SiP) covers the early Multi-chip Module (MCM) technology, Multi-chip Package (MCP) technology, and wafer stacking (Stack). Die), PoP (Package on Package), PiP (Package in Package), and techniques for embedding the active/passive component in a substrate (Embedded Substrate). In terms of structural appearance, MCM belongs to the two-dimensional 2D structure, while MCP, wafer stacking, PoP, PiP, etc. belong to the three-dimensional 3D structure; since the 3D structure can meet the requirements of miniaturization and high efficiency, it has been in recent years. Come to be favored by the industry.

若進一步就互連技術(Interconnection)來看,傳統的2D或3D構裝多以打線接合(Wire bonding)為主,少部分採用覆晶技術(Flip Chip),或是結合兩者。以晶片堆疊(Stack die)為例,上層晶片仍須藉由打線接合技術與其他晶片互連,當堆疊的晶片數目增加時,越上層的晶片所需的銲線長度則越長,也因此影響了整個封裝系統的效能;再者,為了保留打線空間,晶片與晶片之間需適度的插入隔板,也會造成封 裝體積增加。Further, in terms of interconnect technology, the conventional 2D or 3D structure is mostly based on wire bonding, a small part is Flip Chip, or a combination of both. Taking a stack die as an example, the upper wafer must still be interconnected with other wafers by wire bonding technology. When the number of stacked wafers is increased, the longer the bonding wire length of the upper wafer is, and thus the effect is affected. The performance of the entire package system; in addition, in order to preserve the wire space, a proper insertion of the spacer between the wafer and the wafer will also result in a seal. The volume of the package is increased.

近年來,業界所研發的新互連技術-矽通道技術(Through Silicon Via,TSV)誕生。請參照第1A~1F圖,其繪示矽通道導體結構之製造方法的示意流程圖。首先,如第1A圖所示,提供晶片10,晶片的正面10a具有增厚的銲接墊12。接著,如第1B圖所示,施行第一次雷射鑽孔,從晶片背面10b以雷射鑽孔,並停止在焊接墊12表面,形成開孔14。由於必須從晶片背面10b鑽孔,也容易產生對位不準確的問題。另一方面,由於雷射功率不穩定,加上對於矽(晶片的材料)與金屬(焊接墊的材料)選擇比不高,導致在此步驟中雷射很容易打穿焊接墊。雖然這個問題可以藉由將焊接墊12增厚的方式解決,但是增厚焊接墊12無疑地會增加製造過程中金錢與時間的成本。In recent years, the new interconnect technology developed by the industry, the Through Silicon Via (TSV), was born. Please refer to FIGS. 1A-1F for a schematic flow chart of a method for manufacturing a channel conductor structure. First, as shown in FIG. 1A, a wafer 10 is provided, and the front surface 10a of the wafer has a thickened solder pad 12. Next, as shown in FIG. 1B, the first laser drilling is performed, and the hole is drilled from the wafer back surface 10b by laser, and the surface of the solder pad 12 is stopped to form the opening 14. Since it is necessary to drill holes from the back surface 10b of the wafer, it is easy to cause a problem of inaccurate alignment. On the other hand, since the laser power is unstable, and the selection ratio for the germanium (the material of the wafer) and the metal (the material of the solder pad) is not high, it is easy for the laser to penetrate the solder pad in this step. While this problem can be solved by thickening the solder pads 12, thickening the solder pads 12 undoubtedly increases the cost of money and time in the manufacturing process.

請參照第1C圖,將絕緣材料16填入開孔14。接著,施行第二次雷射鑽孔,如第1D圖所示,在絕緣材料16內鑽孔並同樣停止在焊接墊12表面,形成通道17。之後,如第1E圖所示,將導電材料18填入通道17內。最後,如第1F圖所示,將晶片10與另一晶片20黏合在一起,晶片10之焊接墊12係透過導電材料18與另一晶片20之焊接墊22電性連接。Referring to FIG. 1C, the insulating material 16 is filled into the opening 14. Next, a second laser drilling is performed, as shown in Fig. 1D, drilling holes in the insulating material 16 and also stopping on the surface of the solder pad 12 to form the channel 17. Thereafter, as shown in FIG. 1E, the conductive material 18 is filled into the channel 17. Finally, as shown in FIG. 1F, the wafer 10 is bonded to another wafer 20, and the solder pads 12 of the wafer 10 are electrically connected to the solder pads 22 of the other wafer 20 through the conductive material 18.

然而,在第二次雷射鑽孔以形成通道17時,非常容易擴孔而導致漏電流問題。當以雷射鑽孔至焊接墊12時,金屬材質(i.e.焊接墊12)會反射或折射雷 射光,鄰近焊接墊12的絕緣材料16也同時會被雷射燒掉,導致通道17末端孔徑較大甚至暴露出晶片10。當通道17內重新填入導電材料18,將使得導電材料18接觸到晶片10,造成原本必須絕緣的導電材料18與晶片10產生電性連接,也就是所謂的漏電流問題。However, when the second laser is drilled to form the channel 17, it is very easy to ream the hole and cause a leakage current problem. When drilling with a laser to the solder pad 12, the metal material (i.e. solder pad 12) will reflect or refract the thunder The light-emitting, insulating material 16 adjacent to the solder pad 12 is also simultaneously burned by the laser, resulting in a larger aperture at the end of the channel 17 or even exposing the wafer 10. Refilling the conductive material 18 in the channel 17 will cause the conductive material 18 to contact the wafer 10, causing the conductive material 18, which would otherwise have to be insulated, to make an electrical connection with the wafer 10, a so-called leakage current problem.

本發明係有關於一種立體導通結構及其製造方法。The present invention relates to a three-dimensional conductive structure and a method of fabricating the same.

本發明提出一種立體導通結構,係應用於封裝件。立體導通結構包括基板、第一重佈導體、第二重佈導體以及絕緣材料。基板具有主動表面及與其相對之被動表面,基板具有焊接墊以及貫孔,焊接墊位於主動表面上。第一重佈導體包括隆起部與承接部,隆起部由基板之主動表面向外隆起,並電性連接於焊接墊;承接部位於主動表面之外側,並連接於隆起部,其中隆起部與承接部係構成容置空間,容置空間係與貫孔連通。第二重佈導體位於貫孔內以及容置空間內,且第二重佈導體係接觸承接部,並沿著貫孔由承接部朝向被動表面方向延伸出去。絕緣材料填充於第二重佈導體與基板以及第二重佈導體與隆起部之間。The invention proposes a three-dimensional conduction structure applied to a package. The three-dimensional conduction structure includes a substrate, a first redistribution conductor, a second redistribution conductor, and an insulating material. The substrate has an active surface and a passive surface opposite thereto, the substrate has a solder pad and a through hole, and the solder pad is located on the active surface. The first redistribution conductor includes a ridge portion and a receiving portion, the ridge portion is bulged outward from the active surface of the substrate, and is electrically connected to the solder pad; the receiving portion is located on the outer side of the active surface, and is connected to the ridge portion, wherein the ridge portion and the ridge portion are received The department system constitutes a accommodating space, and the accommodating space is connected to the through hole. The second redistribution conductor is located in the through hole and in the accommodating space, and the second redistribution system contacts the receiving portion and extends along the through hole from the receiving portion toward the passive surface. The insulating material is filled between the second redistribution conductor and the substrate and the second redistribution conductor and the ridge.

本發明提出一種立體導通結構的製造方法,係應用於封裝件,方法包括:(a)提供基板,基板具有主動 表面及與其相對之被動表面,基板具有焊接墊位於主動表面;(b)從基板之主動表面鑽孔至被動表面,據此形成貫孔;(c)在主動表面形成第一重佈導體,第一重佈導體係連接焊接墊並由主動表面向外隆起,據以構成與貫孔連通之容置空間;(d)填入絕緣材料於貫孔以及容置空間內;(e)施行雷射鑽孔,沿著貫孔與容置空間在絕緣材料內形成通孔,通孔末端係暴露出第一重佈導體;以及(f)填入導電材料於通孔內,據以形成接觸第一重佈導體之第二重佈導體。The invention provides a method for manufacturing a three-dimensional conduction structure, which is applied to a package, and the method comprises: (a) providing a substrate, the substrate having an active a surface and a passive surface opposite thereto, the substrate having a solder pad on the active surface; (b) drilling from the active surface of the substrate to the passive surface, thereby forming a through hole; (c) forming a first repeating conductor on the active surface, A heavy-distribution system is connected to the soldering pad and is bulged outward from the active surface to form an accommodating space communicating with the through-hole; (d) filling the insulating material in the through-hole and the accommodating space; (e) performing laser Drilling, forming a through hole in the insulating material along the through hole and the accommodating space, the end of the through hole exposing the first redistributed conductor; and (f) filling the conductive material in the through hole, thereby forming a contact first Re-strip the second repeat conductor of the conductor.

為讓本發明之上述內容能更明顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳細說明如下:In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below, and in conjunction with the drawings, a detailed description is as follows:

本發明主要提供一種立體導通結構及其製造方法,立體導通結構包括基板、第一重佈導體、第二重佈導體以及絕緣材料。基板具有主動表面及與其相對之被動表面,基板具有焊接墊以及貫孔,焊接墊位於主動表面上。第一重佈導體包括隆起部與承接部,隆起部由基板之主動表面向外隆起並電性連接於焊接墊,承接部位於主動表面之外側並連接於隆起部,其中隆起部與承接部係構成容置空間,容置空間係與貫孔連通。第二重佈導體位於貫孔內以及容置空間內,且第二重佈導體係接觸承接部,並沿著貫孔由承接部朝向被動表面方向延伸出去。絕緣材料填充於第二重 佈導體與基板以及第二重佈導體與隆起部之間。The present invention mainly provides a three-dimensional conduction structure including a substrate, a first redistribution conductor, a second redistribution conductor, and an insulating material. The substrate has an active surface and a passive surface opposite thereto, the substrate has a solder pad and a through hole, and the solder pad is located on the active surface. The first redistribution conductor includes a ridge portion and a receiving portion. The ridge portion is bulged outward from the active surface of the substrate and electrically connected to the solder pad. The receiving portion is located on the outer side of the active surface and is connected to the ridge portion, wherein the ridge portion and the receiving portion are The accommodating space is formed, and the accommodating space is connected to the through hole. The second redistribution conductor is located in the through hole and in the accommodating space, and the second redistribution system contacts the receiving portion and extends along the through hole from the receiving portion toward the passive surface. Insulation material is filled in the second weight Between the cloth conductor and the substrate and the second redistribution conductor and the ridge.

本發明之導通結構係可以垂直地穿過基板並水平地延伸,在多個元件需相互連通的封裝結構內實現三維空間佈線,不僅可以縮小封裝體積還可以縮短導線路徑,讓傳輸速度更快、雜訊更小、效能更佳。以下係舉出幾組實施例,配合圖示詳細說明立體導通結構的製造流程與結構特徵,並描繪出立體導通結構於封裝結構的配置方式,然熟悉此技藝者當可明瞭,這些圖示與文字僅為說明之用,並不會對本發明之欲保護範圍造成限縮。The conductive structure of the present invention can vertically pass through the substrate and extend horizontally, and realize three-dimensional space wiring in a package structure in which a plurality of components need to communicate with each other, which can not only reduce the package volume but also shorten the wire path, and make the transmission speed faster. The noise is smaller and the performance is better. In the following, several sets of embodiments are given, and the manufacturing process and structural features of the three-dimensional conductive structure are described in detail with reference to the drawings, and the arrangement of the three-dimensional conductive structure in the package structure is depicted. However, those skilled in the art can understand that these The text is for illustrative purposes only and does not limit the scope of the claimed invention.

第一實施例First embodiment

請參照第2A~2J圖,其繪示依照本發明之第一實施例的具有立體導通結構之封裝件之製造流程圖。本實施例之具有立體導通結構之封裝件的製造方法包括下列步驟。首先,請參照第2A圖,提供第一基板110,第一基板110具有主動表面112及與其相對之被動表面114,第一基板110具有焊接墊116位於主動表面112。第一基板110較佳的是影像感測晶片(CMOS Image Sensor,CIS),經由主動表面112接受影像或光線。Please refer to FIGS. 2A-2J for a manufacturing flow diagram of a package having a three-dimensional conduction structure according to a first embodiment of the present invention. The manufacturing method of the package having the three-dimensional conduction structure of this embodiment includes the following steps. First, referring to FIG. 2A, a first substrate 110 is provided. The first substrate 110 has an active surface 112 and a passive surface 114 opposite thereto. The first substrate 110 has a solder pad 116 on the active surface 112. The first substrate 110 is preferably a CMOS Image Sensor (CIS) that receives image or light through the active surface 112.

之後,從第一基板110之主動表面112鑽孔至被動表面114,據此形成貫孔118,貫孔118可以設置於第一基板110的任意位置,例如是可以是直接穿 過焊接墊116(如第2B圖所示)或是穿過線路較不密集的基板(如本發明第二實施例,如第4B圖所示)。從主動表面上可以清楚地觀察到焊接墊位置及金屬線路圖案,無論預計將貫孔穿過焊接墊116或者是基板上任意位置,由主動表面進行鑽孔的方式都可以精確地將貫孔118形成於預設位置,換句話說,本實施例經由第一基板110之主動表面112進行鑽孔,可以有效地解決傳統上對位不精準的問題。Then, the active surface 112 of the first substrate 110 is drilled to the passive surface 114, thereby forming a through hole 118. The through hole 118 can be disposed at any position of the first substrate 110, for example, it can be directly worn. Over solder pads 116 (as shown in FIG. 2B) or substrates that are less dense through the lines (as in the second embodiment of the invention, as shown in FIG. 4B). The position of the solder pad and the metal line pattern can be clearly observed from the active surface. Whether the through hole is expected to pass through the solder pad 116 or any position on the substrate, the hole can be accurately drilled by the active surface. Formed in the preset position, in other words, the present embodiment is bored through the active surface 112 of the first substrate 110, which can effectively solve the problem of conventional misalignment.

接著,在第一基板的主動表面112形成第一重佈導體(如第2G圖之130),由於第一重佈導體的製造方法可以有很多種,本實施例提出其中一種方法並配合第2C~2G圖詳細說明如下。首先,如第2C圖所示,提供第二基板120,並形成至少一個接墊122於第二基板120上。第二基板120較佳的是透明基板,例如是玻璃基板,使得光線可以穿透第二基板120進入其下方基板。通常是藉由形成金屬層於第二基板120上,並移除部分之金屬層以形成圖案化金屬層,例如是接墊122,於第二基板120上。之後,請參照第2D圖,覆蓋絕緣層124於接墊122以及第二基板120上,絕緣層124較佳的是ABF絕緣膜(Ajinomoto Build-up Film,ABF)或異方性導電膠膜(Anisotropic Conductive Film,ACF)。接著,請參照第2E圖,移除部份之絕緣層124,藉此形成絕緣層124之凹口126,且凹口126係暴露出接墊122。另一方面,絕 緣層124較佳地具有開口127,對應至第一基板110主動表面上112。至此,完成第二基板組件120a,其表面覆蓋絕緣層124,絕緣層124具有凹口126暴露出接墊122。然後,請參照第2F圖,形成導電層128於接墊122、凹口126內壁以及部分之絕緣層124上。導電層128可以透過濺鍍(sputter)、化學氣相沈積(Chemical Vapor Deposition,CVD)、印刷(printing)等方式形成。根據分佈位置,導電層128進一步地分為隆起部128a與承接部128b,隆起部128a包括位於絕緣層124上與凹口126內壁之導電層128,承接部128b包括位於接墊122上之導電層128,承接部128b連接於隆起部128a,其中隆起部128a與承接部128b係構成容置空間136。隆起部128a與承接部128b較佳的是一體成型。在本實施例中,導電層128以及接墊122較佳地構成第一重佈導體130。Next, a first redistribution conductor is formed on the active surface 112 of the first substrate (such as 130 in FIG. 2G). Since the manufacturing method of the first redistributed conductor can be various, the present embodiment proposes one of the methods and cooperates with the second C. The ~2G diagram is described in detail below. First, as shown in FIG. 2C, the second substrate 120 is provided, and at least one pad 122 is formed on the second substrate 120. The second substrate 120 is preferably a transparent substrate, such as a glass substrate, such that light can penetrate the second substrate 120 into the underlying substrate. Typically, a metal layer is formed on the second substrate 120, and a portion of the metal layer is removed to form a patterned metal layer, such as pad 122, on the second substrate 120. Then, referring to FIG. 2D, the insulating layer 124 is covered on the pad 122 and the second substrate 120. The insulating layer 124 is preferably an ABF insulating film (ABF) or an anisotropic conductive film (AJ). Anisotropic Conductive Film, ACF). Next, referring to FIG. 2E, a portion of the insulating layer 124 is removed, thereby forming a recess 126 of the insulating layer 124, and the recess 126 exposes the pad 122. On the other hand, absolutely The edge layer 124 preferably has an opening 127 corresponding to the active surface 112 of the first substrate 110. To this end, the second substrate assembly 120a is completed, the surface of which covers the insulating layer 124, and the insulating layer 124 has a recess 126 exposing the pad 122. Then, referring to FIG. 2F, a conductive layer 128 is formed on the pad 122, the inner wall of the recess 126, and a portion of the insulating layer 124. The conductive layer 128 can be formed by sputtering, chemical vapor deposition (CVD), printing, or the like. According to the distribution position, the conductive layer 128 is further divided into a ridge portion 128a and a receiving portion 128b. The ridge portion 128a includes a conductive layer 128 on the insulating layer 124 and the inner wall of the recess 126. The receiving portion 128b includes a conductive layer on the pad 122. The layer 128, the receiving portion 128b is connected to the ridge portion 128a, wherein the ridge portion 128a and the receiving portion 128b constitute the accommodating space 136. The raised portion 128a and the receiving portion 128b are preferably integrally formed. In the present embodiment, the conductive layer 128 and the pads 122 preferably constitute the first redistribution conductor 130.

需注意的是,第二基板120上之接墊122是可以省略的,第二基板組件120a內就算沒有接墊122,也可以沿著凹口126形成同樣形狀的導電層128,因此,在其他較佳實施例中,導電層128係單獨地構成第一重佈導體130。It should be noted that the pads 122 on the second substrate 120 can be omitted. Even if there is no pad 122 in the second substrate assembly 120a, the same shape of the conductive layer 128 can be formed along the recess 126. Therefore, in other In the preferred embodiment, the conductive layer 128 separately constitutes the first redistribution conductor 130.

值得一提的是,本實施例在形成第二基板組件120a的過程中係採用兩次黃光蝕刻步驟,分別用以蝕刻出接墊以及絕緣層開口,而黃光蝕刻並不會損傷玻璃表面,因此通過當光線通過第二基板120(e.g. 玻璃)與絕緣層開口進入第一基板110(e.g.影像感測晶片)時,影像感測晶片得以接收到清晰無誤的影像,避免影像出現由玻璃表面刮傷引起的雜訊或污點。It should be noted that in the process of forming the second substrate assembly 120a, the present embodiment uses two yellow etching steps to etch the pads and the opening of the insulating layer, respectively, and the yellow etching does not damage the glass surface. So by passing light through the second substrate 120 (eg When the glass substrate and the insulating layer are opened into the first substrate 110 (e.g. image sensing wafer), the image sensing wafer can receive a clear and unambiguous image to avoid noise or stain caused by scratching of the glass surface.

接著,請參照第2G圖,翻覆第二基板組件120a,對應地將其黏合於第一基板110之主動表面112側,其中將位於絕緣層124上之導電層128係連接於焊接墊116,並將位於接墊122上以及凹口內壁之導電層128面對貫孔118,據此於第一基板110之主動表面112形成第一重佈導體130。至此,在第一基板110的主動表面112已經形成第一重佈導體130,第一重佈導體130係連接焊接墊116並由主動表面112向外隆起,據以構成與貫孔118連通之容置空間136,如第2G圖所示。Next, referring to FIG. 2G, the second substrate assembly 120a is flipped over, correspondingly bonded to the active surface 112 side of the first substrate 110, wherein the conductive layer 128 on the insulating layer 124 is connected to the solder pad 116, and The conductive layer 128 on the pad 122 and the inner wall of the recess faces the through hole 118, whereby the first redistribution conductor 130 is formed on the active surface 112 of the first substrate 110. So far, the first redistribution conductor 130 has been formed on the active surface 112 of the first substrate 110, and the first redistribution conductor 130 is connected to the solder pad 116 and bulged outward by the active surface 112, thereby forming a connection with the through hole 118. Space 136 is placed as shown in Figure 2G.

接著,填入絕緣材料134於貫孔118以及容置空間136內,如第2H圖所示。在較佳的實施例中,將第三基板140設置於第一基板110的被動表面114,而絕緣材料134也覆蓋於第三基板140以及第一基板110的被動表面114上。第三基板140也具有主動表面及與其相對之被動表面,第三基板140之主動表面包括焊接墊142,焊接墊142較佳的是遠離第一基板110之被動表面114。Next, the insulating material 134 is filled in the through hole 118 and the accommodating space 136 as shown in FIG. 2H. In a preferred embodiment, the third substrate 140 is disposed on the passive surface 114 of the first substrate 110, and the insulating material 134 also covers the third substrate 140 and the passive surface 114 of the first substrate 110. The third substrate 140 also has an active surface and a passive surface opposite thereto. The active surface of the third substrate 140 includes a solder pad 142. The solder pad 142 is preferably away from the passive surface 114 of the first substrate 110.

之後,從被動表面114朝向主動表面112的方向沿著貫孔118與容置空間136在絕緣材料134內 鑽孔,形成通孔146,通孔146末端係暴露出第一重佈導體130之導電層128,如第2I圖所示。鑽孔方法較佳地是施行雷射鑽孔技術(laser drilling),由於雷射對於絕緣材料與金屬材料的選擇比很高,要控制雷射使其蝕刻完絕緣材料134後不會繼續蝕刻導電層128是比較容易達成的,因此可以避免傳統上打穿導電層的問題。在較佳的實施例中,可以透過相同或不同的方式移除絕緣材料134形成開孔147,以暴露出第三基板140之焊接墊142。Thereafter, the direction from the passive surface 114 toward the active surface 112 is along the through hole 118 and the accommodating space 136 in the insulating material 134. The hole is drilled to form a through hole 146, and the end of the through hole 146 exposes the conductive layer 128 of the first redistribution conductor 130, as shown in Fig. 2I. The drilling method is preferably laser drilling. Since the laser has a high selection ratio of the insulating material and the metal material, the laser is controlled so that the etching does not continue to etch after the insulating material 134 is etched. The layer 128 is relatively easy to achieve, so that the problem of conventionally penetrating the conductive layer can be avoided. In a preferred embodiment, the insulating material 134 may be removed in the same or different manner to form the opening 147 to expose the solder pad 142 of the third substrate 140.

接著,填入導電材料於通孔146內,據以形成接觸第一重佈導體130之第二重佈導體148,如第2J圖所示。Next, a conductive material is filled in the via 146 to form a second redistribution conductor 148 that contacts the first redistribution conductor 130, as shown in FIG. 2J.

根據上述製造方法製成之立體導通結構的結構特徵揭露如下。請參照第2G圖,本實施例之立體導通結構包括:第一基板110、第一重佈導體130、第二重佈導體148以及絕緣材料134。第一基板110具有焊接墊116以及貫孔118,焊接墊116位於主動表面112上。在本實施例中,貫孔118係較佳地是穿過焊接墊116。The structural features of the three-dimensional conduction structure fabricated according to the above manufacturing method are disclosed as follows. Referring to FIG. 2G , the stereo conduction structure of the embodiment includes a first substrate 110 , a first redistribution conductor 130 , a second redistribution conductor 148 , and an insulating material 134 . The first substrate 110 has a solder pad 116 and a through hole 118 on the active surface 112. In the present embodiment, the through holes 118 are preferably passed through the solder pads 116.

第一重佈導體130包括隆起部128a與承接部128b,隆起部128a與承接部128b較佳的是一體成型。隆起部128a(即位於凹口126內壁之導電層128)由第一基板110之主動表面112向外隆起,並電性連接於焊接墊116,本實施例之隆起部128a較佳的是 設置於焊接墊116上。承接部128b(即位於接墊122表面之導電層128)位於主動表面112之外側,並連接於隆起部128a,其中隆起部128a與承接部128b係構成容置空間136,容置空間136係與貫孔連通118。在本實施例中,第一重佈導體130較佳地更包括接墊122,係設置於第二基板120上,並與承接部128b相連。The first redistribution conductor 130 includes a ridge portion 128a and a receiving portion 128b, and the ridge portion 128a and the receiving portion 128b are preferably integrally formed. The raised portion 128a (i.e., the conductive layer 128 on the inner wall of the recess 126) is bulged outward from the active surface 112 of the first substrate 110 and electrically connected to the solder pad 116. The raised portion 128a of the present embodiment is preferably It is disposed on the solder pad 116. The receiving portion 128b (ie, the conductive layer 128 on the surface of the pad 122) is located on the outer side of the active surface 112 and is connected to the ridge portion 128a. The ridge portion 128a and the receiving portion 128b constitute an accommodating space 136. The through hole is connected to 118. In this embodiment, the first redistribution conductor 130 preferably further includes a pad 122 disposed on the second substrate 120 and connected to the receiving portion 128b.

第二重佈導體148位於貫孔118內以及容置空間136內,且第二重佈導體148係接觸承接部128b,並沿著貫孔118由承接部128b朝向被動表面114方向延伸出去。絕緣材料134填充於第二重佈導體148與第一基板110以及第二重佈導體148與隆起部128a之間。The second redistribution conductor 148 is located in the through hole 118 and in the accommodating space 136, and the second redistribution conductor 148 is in contact with the receiving portion 128b and extends along the through hole 118 from the receiving portion 128b toward the passive surface 114. The insulating material 134 is filled between the second redistribution conductor 148 and the first substrate 110 and the second redistribution conductor 148 and the ridge portion 128a.

請注意,第一基板110之焊接墊116連接第一重佈導體130(包括第二基板之接墊122與導電層128),第一重佈導體130連接第二重佈導體148,如此一來,第一基板110之電訊號得以經由第一重佈導體130與第二重佈導體148傳遞出去。值得一提的是,本實施例之立體導通結構可以避免漏電流的問題。詳細地說,傳統上以雷射鑽孔至導電層128時,導電層128會反射或折射雷射光,鄰近導電層128的絕緣材料134也同時會被雷射燒掉,導致通孔146末端孔徑較大甚至暴露出周圍材料(例如是基板),當通孔146內重新填入導電材料,將使得導電材料接觸 到周圍材料,造成原本必須絕緣的導電材料與基板產生電性連接,也就是所謂的漏電流問題。然而,本實施例之立體導通結構以導電層128環繞通孔146末端,就算以雷射鑽孔時發生擴孔現象,填入的導電材料(即第二重佈導體148)仍是與導電層128接觸,不會將電流傳遞至基板,因此本實施例之立體導通結構可以解決傳統上矽通道導通結構(Through Silicon Via,TSV)難以避免的漏電流問題。Please note that the solder pads 116 of the first substrate 110 are connected to the first redistribution conductors 130 (including the pads 122 of the second substrate and the conductive layer 128), and the first redistribution conductors 130 are connected to the second redistribution conductors 148. The electrical signal of the first substrate 110 is transmitted through the first redistribution conductor 130 and the second redistribution conductor 148. It is worth mentioning that the three-dimensional conduction structure of the embodiment can avoid the problem of leakage current. In detail, when the laser is conventionally drilled into the conductive layer 128, the conductive layer 128 reflects or refracts the laser light, and the insulating material 134 adjacent to the conductive layer 128 is also burned by the laser, resulting in the aperture at the end of the through hole 146. Larger or even exposed surrounding material (for example, a substrate), when the conductive material is refilled in the through hole 146, the conductive material will be contacted. To the surrounding materials, the conductive material that must be insulated is electrically connected to the substrate, which is a so-called leakage current problem. However, the three-dimensional conductive structure of the present embodiment surrounds the end of the through hole 146 with the conductive layer 128, and even if the hole expansion occurs during the laser drilling, the filled conductive material (ie, the second redistribution conductor 148) is still with the conductive layer. The contact of the 128 does not transfer current to the substrate. Therefore, the three-dimensional conduction structure of the embodiment can solve the leakage current problem that is difficult to avoid by the conventional over-silicon via (TSV).

最後,在較佳的實施例中,導電材料也填入開孔147,在絕緣材料134表面形成圖案化導電層152/154/156,覆蓋絕緣層150於第一基板110與第三基板140,蝕刻絕緣層150並填入導電材料形成焊接墊162/164/166,最後於焊接墊162/164/166植上銲球172/174/176,藉此完成封裝件100,如第2J圖所示。Finally, in a preferred embodiment, the conductive material is also filled into the opening 147, and a patterned conductive layer 152/154/156 is formed on the surface of the insulating material 134 to cover the insulating layer 150 on the first substrate 110 and the third substrate 140. The insulating layer 150 is etched and filled with a conductive material to form a solder pad 162/164/166, and finally solder balls 172/174/176 are implanted on the solder pads 162/164/166, thereby completing the package 100, as shown in FIG. 2J. .

本實施例之封裝件100利用立體導通結構可以在基板與基板之間或者是基板與外部元件之間傳遞電訊號。舉例來說,第一基板110可以透過焊接墊116、第一重佈導體130、第二重佈導體148、導電層152、焊接墊162以及銲球172構成的路徑與外部元件傳遞電訊號;第一基板110也可以透過焊接墊116、第一重佈導體130、第二重佈導體148、導電層156、焊接墊166以及銲球176構成的路徑傳送電訊號至第三基板140,例如是將接收到的影像傳送至 第三基板進行影像處理。The package 100 of the present embodiment can transmit electrical signals between the substrate and the substrate or between the substrate and the external components by using the three-dimensional conduction structure. For example, the first substrate 110 can transmit electrical signals through the path formed by the solder pad 116, the first redistribution conductor 130, the second redistribution conductor 148, the conductive layer 152, the solder pad 162, and the solder ball 172, and the external component; A substrate 110 can also transmit electrical signals to the third substrate 140 through a path formed by the solder pads 116, the first redistributing conductors 130, the second redistributable conductors 148, the conductive layer 156, the solder pads 166, and the solder balls 176, for example, The received image is transmitted to The third substrate performs image processing.

本實施例雖已揭露第二基板120較佳的是玻璃基板,第一基板110較佳的是影像感測晶片(CMOS Image Sensor,CIS)可以透過玻璃基板經由主動表面112接受影像或光線,第三基板140較佳的是數位訊號處理器(Digital Signal Processor,DSP),用以將由第一基板110(e.g.影像感測晶片)接收到的影像處理之後傳送出去。然而,此技術領域中具有通常知識者當可明瞭,本發明之立體導通結構及其製造方法之應用範圍並不限定於此,亦可以應用至微機電系統(Micro-Electro-Mechanical Systems,MEMS)或其他封裝結構或技術。In this embodiment, it is disclosed that the second substrate 120 is preferably a glass substrate. The first substrate 110 is preferably a CMOS image sensor (CIS) that can receive images or light through the active surface 112 through the glass substrate. The three substrate 140 is preferably a digital signal processor (DSP) for transmitting the image received by the first substrate 110 (eg image sensing wafer) and then transmitting it. However, it is obvious to those skilled in the art that the application range of the three-dimensional conductive structure and the manufacturing method thereof of the present invention is not limited thereto, and can also be applied to Micro-Electro-Mechanical Systems (MEMS). Or other packaging structure or technology.

再者,本實施例雖已揭露第二基板組件形成步驟於第2C~2E圖,然而形成步驟並不限定於此。舉例來說,請參照第3A~3E圖,其繪示依照本發明之第一較佳實施例之第二基板組件的另一形成方法的示意流程圖。首先,如第3A圖所示,提供第二基板120,並形成圖案化金屬層於第二基板120上,圖案化金屬層包括保護層222以及至少一個接墊122,圖案化金屬層厚度較佳的是大約1μm。之後,請參照第3B圖,覆蓋絕緣層124於保護層222、接墊122以及第二基板120上,絕緣層124的厚度較佳的是大約40μm。接著,請參照第3C圖,移除一部分之絕緣層124,據此暴露出保護層222。較佳的是以雷射移除絕緣 層,由於雷射也會蝕刻第二基板120,如果沒有保護層222,此一步驟之雷射非常容易在第二基板120表面形成傷痕,加上雷射對於絕緣材料與金屬材料(接墊122)的選擇比很高,因此保護層222可以有效地防止第二基板120被雷射破壞。然後,請參照第3D圖,以黃光製程蝕刻暴露出來的保護層222以形成絕緣層之開口127,對應至第一基板110主動表面上112之感光區,使得光線可以穿透第二基板120以及開口127進入其下方基板。最後,請參照第3E圖,移除另一部分之絕緣層124,藉此形成絕緣層124之凹口126,且凹口126係暴露出接墊122,此步驟較佳的是施行雷射鑽孔技術來移除絕緣材料。值得一提的是,本實施方法利用兩次雷射鑽孔以及一次黃光製程來完成第二基板組件,可以保持第二基板表面平整度,且製造成本較為低廉。此外,由於雷射對於絕緣材料與金屬材料的選擇比很高,要控制雷射使其蝕刻完絕緣材料後不會繼續蝕刻金屬材料是比較容易達成的,因此可以避免傳統上打穿金屬材料的問題。Furthermore, although the second substrate assembly forming step is disclosed in FIG. 2C to FIG. 2E, the forming step is not limited thereto. For example, please refer to FIGS. 3A-3E, which illustrate a schematic flow chart of another method of forming a second substrate assembly in accordance with a first preferred embodiment of the present invention. First, as shown in FIG. 3A, a second substrate 120 is provided, and a patterned metal layer is formed on the second substrate 120. The patterned metal layer includes a protective layer 222 and at least one pad 122, and the patterned metal layer has a better thickness. It is about 1 μm. Thereafter, referring to FIG. 3B, the insulating layer 124 is covered on the protective layer 222, the pad 122, and the second substrate 120. The thickness of the insulating layer 124 is preferably about 40 μm. Next, referring to FIG. 3C, a portion of the insulating layer 124 is removed, thereby exposing the protective layer 222. It is preferred to remove the insulation by laser The layer, since the laser also etches the second substrate 120, if there is no protective layer 222, the laser of this step is very easy to form a scratch on the surface of the second substrate 120, plus the laser for the insulating material and the metal material (the pad 122) The selection ratio is high, so the protective layer 222 can effectively prevent the second substrate 120 from being damaged by the laser. Then, referring to FIG. 3D, the exposed protective layer 222 is etched in a yellow light process to form an opening 127 of the insulating layer, corresponding to the photosensitive region 112 on the active surface of the first substrate 110, so that light can penetrate the second substrate 120. And the opening 127 enters the substrate below it. Finally, referring to FIG. 3E, another portion of the insulating layer 124 is removed, thereby forming the recess 126 of the insulating layer 124, and the recess 126 is exposed to the pad 122. This step preferably performs laser drilling. Technology to remove insulation. It is worth mentioning that the method of the present invention utilizes two laser drilling and one yellow light process to complete the second substrate assembly, which can maintain the flatness of the surface of the second substrate and is relatively inexpensive to manufacture. In addition, since the laser has a high selection ratio of the insulating material and the metal material, it is relatively easy to control the laser so that the etching of the insulating material does not continue to etch the metal material, thereby avoiding the traditional metal-punching material. problem.

第二實施例Second embodiment

本實施例與上述實施例不同之處在於貫孔位置、第一重佈導體的結構及其形成方法,其餘相同的元件與步驟係沿用相同標號,於此不再贅述。The difference between the embodiment and the above embodiment is the position of the through hole, the structure of the first redistributed conductor, and the method for forming the same. The same components and steps are denoted by the same reference numerals and will not be described again.

請參照第4A~4E圖,其繪示依照本發明之第二實施例之具有立體導通結構之封裝件的製造流程示 意圖。請參照第4A圖,第一基板110具有焊接墊116於其主動表面112上,且具有貫孔218。接著,在第一基板110的主動表面112形成第一重佈導體,其步驟揭露如下。Please refer to FIGS. 4A-4E, which illustrate a manufacturing process of a package having a three-dimensional conduction structure according to a second embodiment of the present invention. intention. Referring to FIG. 4A, the first substrate 110 has a solder pad 116 on its active surface 112 and has a through hole 218. Next, a first redistribution conductor is formed on the active surface 112 of the first substrate 110, the steps of which are disclosed below.

首先,如第4A圖所示,形成導電凸塊228於第一基板110之主動表面112上,例如是電鍍或印刷等方式。導電凸塊228係由第一基板110之主動表面112向外隆起,並電性連接於該焊接墊116,構成本實施例之第一重佈導體之隆起部。在本實施例中,導電凸塊228較佳的是設置於焊接墊116上,並延伸至貫孔218周圍之主動表面112上。相較於第一實施例,本實施例藉由導電凸塊228重新佈線的功能,將貫孔218遠離焊接墊116,例如是設置於第一基板110邊緣或是線路較不集中的地方,藉此提高第一基板線路佈局的自由度。First, as shown in FIG. 4A, conductive bumps 228 are formed on the active surface 112 of the first substrate 110, such as by electroplating or printing. The conductive bump 228 is bulged outward from the active surface 112 of the first substrate 110 and electrically connected to the solder pad 116 to form a ridge of the first redistribution conductor of the embodiment. In the present embodiment, the conductive bump 228 is preferably disposed on the solder pad 116 and extends onto the active surface 112 around the through hole 218. Compared with the first embodiment, in this embodiment, the through hole 218 is separated from the solder pad 116 by the function of rewiring the conductive bump 228, for example, at the edge of the first substrate 110 or where the line is less concentrated. This increases the degree of freedom in the layout of the first substrate line.

接著,如第4B圖所示,提供第二基板組件220a,包括第二基板120、接墊122以及絕緣層124,接墊122以及絕緣層124係相鄰地設置於第二基板120上。Next, as shown in FIG. 4B, a second substrate assembly 220a is provided, including a second substrate 120, pads 122, and an insulating layer 124. The pads 122 and the insulating layer 124 are adjacently disposed on the second substrate 120.

之後,如第4C圖所示,翻覆第二基板組件220a,將第二基板組件220a之接墊122焊接於第一基板110之導電凸塊228,並將第二基板組件220a黏合於第一基板110之主動表面112,據此於第一基板110之主動表面112形成第一重佈導體230。Then, as shown in FIG. 4C, the second substrate assembly 220a is flipped, the pads 122 of the second substrate assembly 220a are soldered to the conductive bumps 228 of the first substrate 110, and the second substrate assembly 220a is bonded to the first substrate. The active surface 112 of the 110, whereby the first redistribution conductor 230 is formed on the active surface 112 of the first substrate 110.

本實施例之第一重佈導體230係由第二基板120之接墊122以及第一基板110之導電凸塊228對組而成。從結構上來看,第一重佈導體230包括隆起部(i.e.導電凸塊228)與承接部(i.e.接墊122),隆起部(i.e.導電凸塊228)由第一基板110之主動表面112向外隆起,並電性連接於焊接墊116。承接部(i.e.接墊122)位於主動表面112之外側,並連接於隆起部(i.e.導電凸塊228),其中隆起部(i.e.導電凸塊228)與承接部(i.e.接墊122)係構成容置空間236,容置空間236係與貫孔連通218。The first redistribution conductor 230 of the present embodiment is formed by a pair of pads 122 of the second substrate 120 and conductive bumps 228 of the first substrate 110. Structurally, the first redistribution conductor 230 includes a raised portion (ie conductive bump 228) and a receiving portion (ie pad 122), and the raised portion (ie conductive bump 228) is directed by the active surface 112 of the first substrate 110 The outer ridge is raised and electrically connected to the solder pad 116. The receiving portion (ie pad 122) is located on the outer side of the active surface 112 and is connected to the ridge portion (ie conductive bump 228), wherein the ridge portion (ie conductive bump 228) and the receiving portion (ie pad 122) constitute a capacity The space 236 is disposed, and the accommodation space 236 is connected to the through hole 218.

最後,依序形成絕緣材料134、第二重佈導體148、第三基板140、銲球170等,完成封裝件200,如第4D圖所示。第二重佈導體148位於貫孔218內以及容置空間236內,且第二重佈導體148係接觸承接部(i.e.接墊122),並沿著貫孔218由承接部(i.e.接墊122)朝向被動表面114方向延伸出去。Finally, the insulating material 134, the second redistribution conductor 148, the third substrate 140, the solder balls 170, and the like are sequentially formed to complete the package member 200 as shown in FIG. 4D. The second redistribution conductor 148 is located in the through hole 218 and in the accommodating space 236, and the second redistribution conductor 148 is in contact with the receiving portion (ie pad 122), and is received by the receiving portion along the through hole 218 (ie pad 122 ) extends toward the passive surface 114.

雖然本實施例之第一重佈導體230與第一實施例之第一重佈導體130的形成方式不同,但本實施例之導電凸塊228與接墊122組成之第一重佈導體係230同樣具有容置空間,就算鑽孔時發生擴孔現象,填入的導電材料(即第二重佈導體148)仍是與第一重佈導體230接觸,不會將電流傳遞至基板,因此本實施例之立體導通結構仍然可以解決傳統上矽通道導通結構(Through Silicon Via,TSV)的漏電流問題。Although the first redistribution conductor 230 of the present embodiment is different from the first redistribution conductor 130 of the first embodiment, the first bumping system 230 of the conductive bump 228 and the pad 122 of the embodiment is formed. Similarly, there is a accommodating space, and even if a hole expansion phenomenon occurs during drilling, the filled conductive material (ie, the second redistribution conductor 148) is still in contact with the first redistribution conductor 230, and does not transmit current to the substrate, so The three-dimensional conduction structure of the embodiment can still solve the leakage current problem of the conventional upper silicon via (TSV).

值得一提的是,本實施例之第一重佈導體230的隆起部(i.e.導電凸塊228)較佳的是由電鍍法所形成,因此第一重佈導體230整體結構較為穩固紮實,不易損壞。It is worth mentioning that the raised portion (ie conductive bump 228) of the first redistribution conductor 230 of the present embodiment is preferably formed by electroplating, so that the overall structure of the first redistributed conductor 230 is relatively stable and solid, and is difficult to be damage.

另一方面,本實施例雖然藉由導電凸塊228重新佈線的功能,讓貫孔218遠離焊接墊116,然本發明並不限定於此。本實施例也可以讓貫孔穿過焊接墊,並直接將導電凸塊設置於焊接墊上也會位於貫孔周圍,之後與第二基板的接墊焊接在一起,同樣也可以構成上述結構但位置不同之第一重佈導體。On the other hand, in the present embodiment, the through hole 218 is separated from the solder pad 116 by the function of rewiring the conductive bump 228, but the present invention is not limited thereto. In this embodiment, the through hole can also pass through the soldering pad, and the conductive bump can be directly disposed on the soldering pad and also around the through hole, and then soldered together with the pad of the second substrate, and the above structure can also be constructed but the position can also be Different first repeat conductors.

本發明上述實施例所揭露之立體導通結構,可以垂直地穿過基板並水平地延伸,在多個元件需相互連通的封裝結構內實現三維空間佈線,不僅可以縮小封裝體積還可以縮短導線路徑。此外,第一重佈導體具有隆起部與承接部構成特殊的形狀,即使雷射鑽孔過程中發生擴孔,也不會產生漏電流問題。另一方面,本發明提出的立體導通結構的製造方法,可以由基板正面鑽孔避免對位不精準的問題。此外,形成金屬層保護基板使得雷射鑽孔過程中不會刮傷基板表面。The three-dimensional conduction structure disclosed in the above embodiments of the present invention can vertically pass through the substrate and extend horizontally, and realize three-dimensional space wiring in a package structure in which a plurality of components need to communicate with each other, which can not only reduce the package volume but also shorten the wire path. Further, the first redistribution conductor has a special shape formed by the ridge portion and the receiving portion, and even if a hole is reamed during the laser drilling, no leakage current problem occurs. On the other hand, the manufacturing method of the three-dimensional conduction structure proposed by the present invention can avoid the problem of inaccurate alignment due to the drilling of the front side of the substrate. In addition, the formation of the metal layer protection substrate does not scratch the substrate surface during the laser drilling process.

綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧晶片10‧‧‧ wafer

10a‧‧‧晶片正面10a‧‧‧ wafer front

10b‧‧‧晶片背面10b‧‧‧ wafer back

12‧‧‧焊接墊12‧‧‧ solder pad

14‧‧‧開孔14‧‧‧Opening

16‧‧‧絕緣材料16‧‧‧Insulation materials

17‧‧‧通道17‧‧‧ channel

18‧‧‧導電材料18‧‧‧Electrical materials

20‧‧‧晶片20‧‧‧ wafer

22‧‧‧焊接墊22‧‧‧ solder pad

100‧‧‧封裝件100‧‧‧Package

110‧‧‧第一基板110‧‧‧First substrate

112‧‧‧主動表面112‧‧‧Active surface

114‧‧‧被動表面114‧‧‧ Passive surface

116‧‧‧焊接墊116‧‧‧ solder pad

118‧‧‧貫孔118‧‧‧through holes

120‧‧‧第二基板120‧‧‧second substrate

120a‧‧‧第二基板組件120a‧‧‧Second substrate assembly

122‧‧‧接墊122‧‧‧ pads

124‧‧‧絕緣層124‧‧‧Insulation

126‧‧‧凹口126‧‧‧ notch

127‧‧‧開口127‧‧‧ openings

128‧‧‧導電層128‧‧‧ Conductive layer

128a‧‧‧隆起部128a‧‧‧Uplift

128b‧‧‧承接部128b‧‧‧Acceptance Department

130‧‧‧第一重佈導體130‧‧‧First heavy conductor

134‧‧‧絕緣材料134‧‧‧Insulation materials

136‧‧‧容置空間136‧‧‧ accommodating space

140‧‧‧第三基板140‧‧‧ third substrate

142‧‧‧焊接墊142‧‧‧ solder pad

146‧‧‧通孔146‧‧‧through hole

147‧‧‧開孔147‧‧‧ openings

148‧‧‧第二重佈導體148‧‧‧Second heavy conductor

150‧‧‧絕緣層150‧‧‧Insulation

152、154、156‧‧‧圖案化導電層152, 154, 156‧‧‧ patterned conductive layers

162、164、166‧‧‧焊接墊162, 164, 166‧‧‧ solder pads

170、172、174、176‧‧‧銲球170, 172, 174, 176‧‧‧ solder balls

200‧‧‧封裝件200‧‧‧Package

218‧‧‧貫孔218‧‧‧through holes

220a‧‧‧第二基板組件220a‧‧‧Second substrate assembly

222‧‧‧保護層222‧‧‧Protective layer

228‧‧‧導電凸塊228‧‧‧Electrical bumps

230‧‧‧第一重佈導體230‧‧‧First heavy conductor

236‧‧‧容置空間236‧‧‧ accommodating space

第1A~1F圖繪示矽通道導體結構之製造方法的示意流程圖。1A to 1F are schematic flow charts showing a method of manufacturing a germanium channel conductor structure.

第2A~2J圖繪示依照本發明之第一實施例的具有立體導通結構之封裝件之製造流程圖。2A to 2J are views showing a manufacturing flow chart of a package having a three-dimensional conduction structure according to a first embodiment of the present invention.

第3A~3E圖繪示依照本發明之第一較佳實施例之第二基板組件的另一形成方法的示意流程圖。3A-3E are schematic flow charts showing another method of forming the second substrate assembly in accordance with the first preferred embodiment of the present invention.

第4A~4D圖繪示依照本發明之第二實施例之具有立體導通結構之封裝件的製造流程示意圖。4A to 4D are views showing a manufacturing process of a package having a three-dimensional conduction structure according to a second embodiment of the present invention.

110‧‧‧第一基板110‧‧‧First substrate

120‧‧‧第二基板120‧‧‧second substrate

122‧‧‧接墊122‧‧‧ pads

148‧‧‧第二重佈導體148‧‧‧Second heavy conductor

170‧‧‧銲球170‧‧‧ solder balls

200‧‧‧封裝件200‧‧‧Package

228‧‧‧導電凸塊228‧‧‧Electrical bumps

230‧‧‧第一重佈導體230‧‧‧First heavy conductor

Claims (22)

一種立體導通結構,係應用於一封裝件,該立體導通結構包括:一基板,具有一主動表面及與其相對之一被動表面,該基板具有一焊接墊以及一貫孔,該焊接墊位於該主動表面上;一第一重佈導體,包括:一隆起部,由該基板之該主動表面向外隆起,並電性連接於該焊接墊;及一承接部,位於該主動表面之外側,並連接於該隆起部,其中該隆起部與該承接部係構成一容置空間,該容置空間係與該貫孔連通;一第二重佈導體,位於該貫孔內以及該容置空間內,且該第二重佈導體係接觸該承接部,並沿著該貫孔由該承接部朝向該被動表面方向延伸出去;以及一絕緣材料,填充於該第二重佈導體與該基板以及該第二重佈導體與該隆起部之間。A three-dimensional conductive structure is applied to a package, the three-dimensional conductive structure includes: a substrate having an active surface and a passive surface opposite thereto, the substrate having a solder pad and a consistent hole, the solder pad being located on the active surface a first redistribution conductor comprising: a ridge portion bulging outwardly from the active surface of the substrate and electrically connected to the solder pad; and a receiving portion located on an outer side of the active surface and connected to The ridge portion, wherein the ridge portion and the receiving portion form an accommodating space, the accommodating space is in communication with the through hole; a second redistribution conductor is located in the through hole and in the accommodating space, and The second re-distribution system contacts the receiving portion and extends away from the receiving portion toward the passive surface along the through hole; and an insulating material filling the second redistributing conductor and the substrate and the second Between the conductor and the ridge. 如申請專利範圍第1項所述之結構,其中該貫孔係穿過焊接墊。The structure of claim 1, wherein the through hole is passed through the solder pad. 如申請專利範圍第2項所述之結構,其中該隆起部係設置於該焊接墊上。The structure of claim 2, wherein the ridge portion is disposed on the solder pad. 如申請專利範圍第1項所述之結構,其中該貫孔係遠離該焊接墊。The structure of claim 1, wherein the through hole is away from the solder pad. 如申請專利範圍第4項所述之結構,其中該 隆起部係設置於該焊接墊上,並延伸至該貫孔周圍之該主動表面上。Such as the structure described in claim 4, wherein A raised portion is disposed on the solder pad and extends onto the active surface around the through hole. 如申請專利範圍第1項所述之結構,其中該隆起部係一導電凸塊。The structure of claim 1, wherein the ridge is a conductive bump. 如申請專利範圍第1項所述之結構,其中該隆起部與該承接部係一體成型。The structure of claim 1, wherein the ridge portion is integrally formed with the receiving portion. 如申請專利範圍第1項所述之結構,其中該基板係一第一基板,該封裝件更包括一第二基板,該第二基板係位於該第一基板之該主動表面側,並與該第一基板實質上平行設置。The structure of claim 1, wherein the substrate is a first substrate, the package further comprises a second substrate, the second substrate is located on the active surface side of the first substrate, and The first substrates are arranged substantially in parallel. 如申請專利範圍第8項所述之結構,其中該第一重佈導體更包括一接墊(pad),係設置於該第二基板上,並與該承接部相連。The structure of claim 8, wherein the first redistribution conductor further comprises a pad disposed on the second substrate and connected to the receiving portion. 如申請專利範圍第8項所述之結構,其中該承接部接觸該第二基板。The structure of claim 8, wherein the receiving portion contacts the second substrate. 如申請專利範圍第8項所述之結構,其中該第一基板係一影像感測晶片(CMOS Image Sensor,CIS),該第二基板係一透明基板。The structure of claim 8, wherein the first substrate is a CMOS Image Sensor (CIS), and the second substrate is a transparent substrate. 如申請專利範圍第8項所述之結構,其中該封裝件更包括一第三基板,係設置於該第一基板之該被動表面。The structure of claim 8, wherein the package further comprises a third substrate disposed on the passive surface of the first substrate. 如申請專利範圍第12項所述之結構,其中該第三基板包括一焊接墊,且該焊接墊係遠離該第一基板之該被動表面。The structure of claim 12, wherein the third substrate comprises a solder pad, and the solder pad is away from the passive surface of the first substrate. 如申請專利範圍第12項所述之結構,其中該第三基板之該焊接墊係係透過該第一重佈導體以及該第二重佈導體與該第二基板之該焊接墊電性連接。The structure of claim 12, wherein the solder pad of the third substrate is electrically connected to the solder pad of the second substrate through the first redistribution conductor and the second redistribution conductor. 如申請專利範圍第12項所述之結構,其中該第三基板係一數位訊號處理器(Digital Signal Processor,DSP)。The structure of claim 12, wherein the third substrate is a Digital Signal Processor (DSP). 如申請專利範圍第8項所述之結構,其中該封裝件更包括:一絕緣層,係覆蓋於該第一基板以及該第三基板;以及一銲球,係位於該絕緣層之下,並連接於該第二重佈導體。The structure of claim 8, wherein the package further comprises: an insulating layer covering the first substrate and the third substrate; and a solder ball under the insulating layer, and Connected to the second redistributor conductor. 一種立體導通結構的製造方法,係應用於一封裝件,該方法包括:提供一基板,該基板具有一主動表面及與其相對之一被動表面,該基板具有一焊接墊位於該主動表面;從該基板之該主動表面鑽孔至該被動表面,據此形成一貫孔;在該主動表面形成一第一重佈導體,該第一重佈導體係連接該焊接墊並由該主動表面向外隆起,據以構成與該貫孔連通之一容置空間;填入一絕緣材料於該貫孔以及該容置空間內; 沿著該貫孔與該容置空間在絕緣材料內形成一通孔,該通孔末端係暴露出該第一重佈導體;以及填入一導電材料於該通孔內,據以形成接觸該第一重佈導體之一第二重佈導體。A method for manufacturing a three-dimensional conductive structure is applied to a package, the method comprising: providing a substrate having an active surface and a passive surface opposite thereto, the substrate having a solder pad on the active surface; Drilling the active surface of the substrate to the passive surface, thereby forming a uniform aperture; forming a first redistribution conductor on the active surface, the first redistribution system connecting the soldering pad and bulging outward from the active surface, Forming a receiving space in communication with the through hole; filling an insulating material in the through hole and the receiving space; Forming a through hole in the insulating material along the through hole, the end of the through hole exposing the first redistributing conductor; and filling a conductive material in the through hole, thereby forming a contact with the first hole One of the second cloth conductors is a second cloth conductor. 如申請專利範圍第17項所述之方法,其中該基板係一第一基板,形成該第一重佈導體之步驟包括:提供一第二基板組件,其表面覆蓋一絕緣層,該絕緣層具有一凹口暴露出一接墊;形成一導電層於該接墊、該凹口內壁以及部分之該絕緣層上,其中該導電層以及該接墊係構成該第一重佈導體;以及翻覆該第二基板組件,對應地將其黏合於該第一基板之該主動表面,其中將位於該絕緣層上之該導電層係連接於該焊接墊,並將位於該接墊上以及該凹口內壁之該導電層面對該貫孔,據此於該第一基板之該主動表面形成該第一重佈導體。The method of claim 17, wherein the substrate is a first substrate, and the step of forming the first redistribution conductor comprises: providing a second substrate assembly having a surface covered with an insulating layer, the insulating layer having a recess exposes a pad; forming a conductive layer on the pad, the inner wall of the recess, and a portion of the insulating layer, wherein the conductive layer and the pad form the first redistribute conductor; and flipping The second substrate assembly is correspondingly bonded to the active surface of the first substrate, wherein the conductive layer on the insulating layer is connected to the solder pad, and is disposed on the pad and in the recess The conductive layer of the wall is opposite the via, whereby the first redistributor conductor is formed on the active surface of the first substrate. 如申請專利範圍第18項所述之方法,其中提供該第二基板組件之步驟包括:提供一第二基板;形成一圖案化金屬層於該第二基板上,該圖案化金屬層至少包括一保護層以及該接墊;覆蓋一絕緣層於該保護層、該接墊以及該第二基板上; 移除一部分之該絕緣層,據此暴露出該保護層;蝕刻該保護層;以及移除另一部分之該絕緣層,藉此形成該絕緣層之該凹口,且該凹口係暴露出該接墊。The method of claim 18, wherein the step of providing the second substrate assembly comprises: providing a second substrate; forming a patterned metal layer on the second substrate, the patterned metal layer comprising at least one a protective layer and the pad; covering an insulating layer on the protective layer, the pad and the second substrate; Removing a portion of the insulating layer, thereby exposing the protective layer; etching the protective layer; and removing another portion of the insulating layer, thereby forming the recess of the insulating layer, and the recess exposes the Pads. 如申請專利範圍第18項所述之方法,其中提供該第二基板組件之步驟包括:提供一第二基板,並形成一接墊於該第二基板上;覆蓋一絕緣層於該接墊以及該第二基板上;以及移除一部份之該絕緣層,藉此形成該絕緣層之該凹口,且該凹口係暴露出該接墊。The method of claim 18, wherein the step of providing the second substrate assembly comprises: providing a second substrate and forming a pad on the second substrate; covering an insulating layer on the pad and And removing a portion of the insulating layer, thereby forming the recess of the insulating layer, and the recess exposes the pad. 如申請專利範圍第17項所述之方法,其中該基板係為一第一基板,其中形成該第一重佈導體之步驟包括:形成一導電凸塊於該第一基板之該主動表面上;提供一第二基板組件,包括一第二基板、一接墊以及一絕緣層,該接墊以及該絕緣層係相鄰地設置於該第二基板上;翻覆該第二基板組件,將該第二基板組件之該接墊焊接於該第一基板之該導電凸塊,並將第二基板組件黏合於該第一基板之該主動表面,據此於該第一基板之該主動表面形成該第一重佈導體。The method of claim 17, wherein the substrate is a first substrate, and the step of forming the first redistribution conductor comprises: forming a conductive bump on the active surface of the first substrate; Providing a second substrate assembly, including a second substrate, a pad, and an insulating layer, the pad and the insulating layer are disposed adjacent to the second substrate; and flipping the second substrate assembly The pad of the second substrate assembly is soldered to the conductive bump of the first substrate, and the second substrate component is bonded to the active surface of the first substrate, thereby forming the first surface of the first substrate A heavy cloth conductor. 如申請專利範圍第21項所述之方法,其中該導電凸塊係形成於該焊接墊上,並延伸至該貫孔 周圍之該主動表面上。The method of claim 21, wherein the conductive bump is formed on the solder pad and extends to the through hole On the active surface around it.
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