TWI384401B - Rf and/or rf identification tag/device having an integrated interposer, and methods for making and using the same - Google Patents

Description

Radio frequency and/or radio frequency identification electronic tag/device with integrated substrate and manufacturing and using method thereof

The present invention relates to sensors, electronic article surveillance (EAS), radio frequency (RF) and/or radio frequency identification (RFID) electronic tags and devices. More particularly, embodiments of the present invention relate to the structure of electronic article surveillance systems, radio frequency and/or radio frequency identification devices, and methods of making and/or producing same. Accordingly, the present invention can provide a low cost process for manufacturing an electronic tag of a radio frequency identification device (or electronic article surveillance system). The electronic tag includes a substrate, a radio frequency front end or a subset of a radio frequency front end, a memory and a logic circuit.

Today, remotely powered electronic devices and related systems are known. For example, a remote drive device is disclosed in U.S. Patent No. 5,099,227, the entire disclosure of which is incorporated herein by reference. The remote drive utilizes electromagnetic coupling to take power from a remote source, and then utilizes electromagnetic and electrostatic coupling to transfer the stored data to a receiving end. The receiving end is typically placed with the remote source. This remotely driven communication device is known as an RFID tag electronic tag.

Radio frequency identification device electronic tags and related systems have a variety of uses. For example, radio frequency identification device electronic tags are often used to automate the identification and protection of protected buildings or areas of an automated gate sentry application system. These electronic tags are typically in the form of access control cards. The information stored in the RFID tag is used to identify the holder of the electronic tag that is attempting to enter the secured building or area.

Old-style automated portal guard applications typically require people with access to a secured building to insert or swipe their identification card or electronic tag through a reader for the system to be used by the identification card or electronic tag. Read the information. The new RFID device electronic tag system utilizes radio frequency data transmission technology to allow the electronic tag to be read at a short distance, thereby eliminating the need to insert or brush the identification tag through the reader.

Most notably, the user only needs to hold the electronic tag and approach a base station or place the electronic tag near the base station. The base station is coupled to a security system to protect the building or area. The base station transmits an excitation signal to the electronic tag to drive the circuit on the electronic tag. The circuit is responsive to the trigger signal and transmits the stored information from the electronic tag to the base station. The base station receives and decodes the information. This information is then processed by the security system to determine if the access is appropriate. Also, the identification electronic tag can be written (eg, programmed and/or deactivated) by a trigger signal. The trigger signal is suitably modulated by a predetermined method.

Some conventional RFID devices electronic tags and systems primarily use electromagnetic coupling to remotely drive the remote device. The remote unit is coupled to an exciter system and a receiving system. The excitation system generates an electromagnetic trigger signal to drive the device and cause the device to transmit a signal that may include the stored information. The receiving system receives the signal generated by the remote device.

At a more basic level, the RFID tag electronic tag circuit typically performs some or all of the functions listed below: (1) absorbing RF energy from the reader region; (2) converting a RF signal to drive the wafer a DC signal; (3) demodulation of the incoming clock, timing, and/or command signal in the RF signal transmitted by the reader; (4) generating a state machine (state machine) The decision and control logic is used to act on revenue or current instructions; (5) to read data in digital form from a memory array or other source (eg, the output of a sensor). The data is read in the same manner as a counter or a registrar; (6) has a storage element (such as a memory) for storing identity codes or other information that is read into the reader and/or used for secure authentication. For example, an EAS deactivation-type memory is used to calculate a predetermined number of uses for a transport ticket and/or to return information to the reader by a sensor; and (7) return the pair The encoded data, timing signals, or other commands of the electronic tag antenna are modulated for transmission to the electronic tag reader.

On the other hand, the EAS electronic tag circuit can exclude some of the above steps and/or functions. For example, the logic-divided EAS drives an internal logic divider with basic RF energy. The logic division circuit then modulates the antenna of the electronic tag such that a unique sub-harmonic signal is transmitted back to the reader (see, for example, British Patent No. GB 2,017,454 A). This subharmonic signal can be easily separated from other sources of noise, such as the harmonics of the carrier, and produces a valid EAS signal. In some instances, the non-linear effects resulting from the semiconductor device are even more simplistic, such as the example disclosed in U.S. Patent No. 4,670,740. Non-linear effects in semiconductor devices or varactors result in sub-harmonic signals, and sub-harmonic signals can be detected by the reader without the need for relayed RF-DC power conversion or logic processing.

Please refer to Figure 1A. Conventional RFID devices are formed by a process. The process includes cutting wafers 10 fabricated by conventional wafer processes into a plurality of wafers 20. The wafer 20 is then placed onto a carrier of an antenna or inductor (which may include an etched, cut or printed metal antenna, inductor coil or other conductive structure). Alternatively, as shown in FIG. 1B, the wafer 20 can be placed on an interposer strap 40 or an interposer carrier 40, and the carrier tape 40 can then be attached to an inductor on a support film 50. / antenna 52.

This process may involve a variety of physical bonding techniques such as adhesion or through wire bonding, anisotropic conductive epoxy bonding, ultrasonic, bump-bonding or flip-chip (flip- The chip) method establishes an electrical internal connection. The bonding process typically involves exposure using heat, time, and/or ultraviolet light. Because the wafers 20 are typically as small as possible (less than 1 mm) to reduce the cost per wafer 20, the pad elements on the wafer 20 for electrical connections may be relatively small. This means that the placement of the wafer 20 requires considerable accuracy for high speed mechanical operation (e.g., positioning at a predetermined location within 50 microns is typically necessary).

This process involves picking up a different wafer, placing the wafer in the correct position on the antenna, inductor, carrier or carrier plate in a bonded manner and forming a physical or electrical internal connection. Overall, the process can be a fairly slow and expensive process.

If the process uses a relay carrier board, it will have the advantage of cost and throughput. First, the wafer 20 is attached to a web roll of the carrier carrier 40. This action can be done easily and sometimes in parallel. Because the carrier carriers 40 are typically separated at close distances, other novel placement operations, such as fluidic self-assembly or pin bed attachment processes, can be easily accomplished. Carrier carrier 40 typically includes electrical channels 34,36. The distribution of the electrical channels 34, 36 begins at the wafer 20 and is distributed over a relatively large and/or wide area elsewhere on the carrier 40. Electrical channels 34, 36 may allow for high throughput and low resolution attach operations, such as crimping or conductive adhesive attachment. The conductive adhesive is functionally similar to a conventional metal strap in comparison to a pick-and-place and/or wire bonding process for integrating a wafer with an inductor substrate. .

In some instances, the low resolution attachment process for metal strips is based on commercially available equipment or materials (M The hlbauer TMA 600 or less) may cost $0.003 or less. The carrier 40 is then attached to an inductor (not shown) such that an electrical connection is formed at this location. This carrying process may also have advantages for flip chip or bump bonding methods. In contrast, it may be more expensive or less advantageous to form the required stubs, bumps or other internal connecting elements on a larger inductor/carrier substrate by conventional methods such as wire bonding.

In order to achieve the goal of costing approximately $0.01 for each RFID device electronic tag, and for single-item sales applications and other low-cost and high-volume applications, it is possible to combine (integrate optimally) a less expensive substrate, A stable and efficient antenna, RF front-end device and one of the high-resolution graphical logic circuits are required for the electronic tag structure and process.

Embodiments in accordance with the present invention are directed to a MOS radio frequency and/or radio frequency identification device, sensor or electronic tag having an integrated substrate, and methods of making and using same. The device generally comprises (a) a substrate; (b) an antenna and/or an inductor on the substrate; and (c) formed on the substrate in addition to the antenna and/or the inductor One of the integrated circuits in one position. The integrated circuit has one of the lowest layers in contact with one of the surfaces of the substrate.

The manufacturing method generally comprises the steps of: (1) forming a bottom layer of one of the integrated circuits on a surface of a substrate; and (2) forming a continuous layer of the integrated circuit on the integrated circuit. And on the bottom layer; and (3) attaching an electrically conductive functional layer to the substrate. Alternatively, the manufacturing method may include the steps of: (1) forming the bottom layer of the integrated circuit on the surface of the substrate; (2) forming the continuous layer of the integrated circuit at the most of the integrated circuit And (3) forming a conductive structure by an active layer attached to one of the substrates.

The method of use generally comprises the steps of: (i) causing or inducing a current in the identification device sufficient to cause the identification device to radiate, reflect or modulate a detectable electromagnetic a signal; (ii) detecting the detectable electromagnetic radiation; and selectively (iii) processing information transmitted by the electromagnetic radiation. Optionally, the method of use may further comprise (iv) transporting or transmitting the information by the identification device (or sensor) to a reading device.

Printing techniques using sheet-fed or web-fed are highly likely to manufacture RFID tags for electronic tags at very low cost. Printing technology has potential cost advantages because it can increase material utilization (eg, additive or semi-additive processing), combine deposition and forming steps, and reduce major expense and equipment operating costs . In addition, conventional high-volume printing processes can be used with soft substrates (eg, a plastic sheet or a metal foil sheet) to enhance the application of electronic labels. The utilization of the materials and the treatment of the additives result in a lower cost per unit area of the processed substrate (or wafer), resulting in a low cost of the adhesion process and/or integration process between the passive device and the active circuit. Moreover, it is easier to achieve a customized service of the RFID device without a mask-less process. For example, each radio frequency identification device provides a unique identification code and/or a unique response time delay based on an inquiry from a reader.

In addition, if the circuit can be printed directly onto the antenna or inductor, the steps of attachment and associated costs can be eliminated. This approach differs from traditional methods of cost savings for semiconductor wafers, which is to reduce the cost of the wafer by reducing the size of the wafer (but this approach may be self-limiting for directly attached 矽-based RFID devices). Because the smaller the wafer, the cost of the attachment process increases. However, all RFID-enabled electronic tags that are printed and without area restrictions may further benefit from the development of certain processes, tools, and/or materials. These processes, tools and/or materials may not be widely available or may not be commercially available for sale. The "integrated substrate" indicated in this specification allows printing technology to be integrated with a low cost imaging process per unit area. For example, the current processing cost of a 0.35 micron germanium wafer is US$25/in ² , and the processing cost of conventional polycrystalline germanium imaging is US$0.50-$0.90/in ² , and the processing cost of printing technology is expected to be much less than US$0.50/in ^{2 .} .

Some or all of the conventional processes of thin film development and optoelectronic materials are possible by using an interposer-based process. Processes for optoelectronic materials include a well developed roll-to-roll fabrication process for inorganic semiconductors, dielectrics, and other thin films on metal foil sheets, sheets, and/or other flexible substrates. For a single film, the cost of this process is around US$0.01/in ² or less. Therefore, for a relatively small substrate (about 25 mm ² ), the cost of this process is not high. However, if all of the inductors or wire substrates must be processed (ie, the area is much larger than 100 mm ² ), the cost is expected to be more expensive. This process provides greater cost savings than low-resolution substrate attachment (US$0.003), and this process provides an efficient way to combine RFID tags with imaging and optoelectronic materials (or, and print steps) The combination results in a complete manufacturing process that does not require the development of a complete instrument and material for the electronic tag of the printed RFID device.

In the end, however, such processes include spool-based and/or roll-to-roll printing processes. This process can result in lower manufacturing costs due to lower equipment costs, higher throughput (several hundred square meters per hour), increased material usage, and/or reduced process steps.

The present invention advantageously provides a low cost radio frequency and/or radio frequency identification device electronic tag. The radio frequency and/or radio frequency identification device electronic tag can have the standard application and operation of conventional radio frequency, radio frequency identification device electronic tags and/or electronic device anti-theft system devices and systems. By reducing the number of expensive and/or low throughput attachment steps and reducing the cost of manufacturing active electronic circuits, a low cost electronic tag can be formed by direct printing or otherwise forming the circuit on a substrate. The substrate is then attached to an inductor/carrier with relatively low accuracy and relatively inexpensive cost.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

Specific embodiments of the invention will be described in greater detail herein, examples of which are illustrated in conjunction with the drawings. The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. In addition, in the following detailed description of the invention, numerous specific details are set forth in order to provide a However, those skilled in the art will be able to devise the invention without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail.

For convenience and simplification, the words "coupled to", "connected to" and "communicated with" in the context of the text mean direct or indirect coupling, connection or communication, unless the context dictates otherwise. These terms are usually alternating and may be alternated, but generally given the meaning they are recognized in the field. Also, for convenience and simplification, the words "radio frequency", "radio frequency identification" and "identification" may be alternated depending on the purpose of use and/or a device and/or electronic tag. Also, the words "electronic tag" or "device" may be used herein to refer to any radio frequency and/or radio frequency identification sensor, electronic tag and/or device. Also, the word "integrated circuit" means a single structure that includes a plurality of electrically active devices. The active devices are formed from a plurality of conductor, semiconductor, and insulator films, but typically do not include discrete, mechanically attached components (such as wafers, wire bonds and leads, substrates or an antenna and/or inductor components) or Mainly has a sticky function of the material. In addition, the words "items", "objects" and "items" are used interchangeably and also include other words when one of them is used. In the present invention, a "major face" of a structure or object is defined to some extent by at least the largest axis of the structure or object. For example, if the structure is circular and has a radius greater than one of its thicknesses, the radius surface [s] (radial surface) is the major face of the structure.

The invention relates to a radio frequency sensor, a radio frequency anti-theft system and/or a radio frequency identification device, comprising: (a) a substrate; (b) an antenna and/or an inductor on the substrate; and (c) An integrated circuit formed at one of the positions on the substrate outside the antenna and/or the inductor. The integrated circuit has one of the lowest layers in contact with one of the surfaces of the substrate. In various embodiments, the integrated circuit includes a thin film transistor, a diode, an optional capacitor and/or resistor, and a metallization element for internally connecting the circuit elements. In other embodiments, at least one of the integrated circuits includes a printed or laser patterned layer.

Further, the present invention relates to a method of fabricating a radio frequency sensor, a radio frequency anti-theft system, and/or a radio frequency identification device. The manufacturing method generally comprises the steps of: (1) forming a bottom layer of one of the integrated circuits on a surface of a substrate; and (2) forming a continuous layer of the integrated circuit at the bottom of the integrated circuit; And (3) attaching a conductive layer to the substrate. Alternatively, the manufacturing method may include the steps of: (1) forming the bottom layer of the integrated circuit on the surface of the substrate; (2) forming a continuous layer of the integrated circuit at the bottom of the integrated circuit; And (3) forming a conductive structure by an active layer attached to one of the substrates.

In various embodiments, one or more layers of the integrated circuit are formed by printing or laser patterning the layer of material. In one embodiment, the step of forming the bottommost layer of the integrated circuit includes printing or laser patterning the bottom layer.

Still further, the present invention relates to a method of detecting a item or object. The method generally comprises the steps of: (A) causing or inducing a current in the anti-theft system and/or identification device associated with or associated with the item or object, the current being sufficient to cause the device to radiate, reflect or Modulating a detectable electromagnetic signal; (B) detecting the detectable electromagnetic radiation; and selectively (C) processing information transmitted by the electromagnetic radiation. Optionally, the method may further comprise transmitting or transmitting the information to the reading device by the identification device (or sensor).

Different aspects of the present invention can be further understood by the following exemplary embodiments.

Exemplary MOS RFID device electronic tag/device

One aspect of the present invention is directed to an RFID device comprising (a) a substrate; (b) an antenna and/or an inductor on the substrate; and (c) in addition to the antenna and/or the inductor, An integrated circuit formed at one of the locations on the substrate. The integrated circuit has one of the lowest layers in contact with one of the surfaces of the substrate.

Accordingly, the present invention provides a low cost radio frequency identification (or electronic article surveillance system) electronic tag (which may also include a sensor and an active RFID device, such as an electronic tag having a battery). The signal modulation behavior of the sensor generally varies due to some external changes in the environment (eg, temperature, conductivity of the structure, or surface to which the sensor is attached, etc.). The electronic tag includes a substrate, an antenna/inductor, and an RF front end (or a subset of the RF front end and logic). The electronic tag can operate in accordance with today's radio frequency identification standards.

It has been shown that printed electronic components based on inorganic materials (eg, laser printed nanocrystals) can be formed on certain flexible substrates, such as high temperature polyimide or metal foil, provided that A suitable thermal isolation/barrier layer is interposed between the substrate (eg, a metal foil panel) and the splicing layer to be treated by the laser. Accordingly, the present invention utilizes such materials as a soft (at least partially soft) printed article electronic security system, radio frequency, radio frequency identification device electronic tag or device.

The substrate typically has a size that can be processed and cost effectively processed by conventional thin film processes and/or novel or state of the art printing processes to produce low cost RF circuits. The integrated circuit can be formed on a flexible substrate such as polyamine, glass/polymer laminate, high temperature polymer or metal foil, and the substrate described above can further comprise one or more barrier layers. In general, such substrates are generally less expensive than conventional tantalum wafers having similar dimensions. However, the substrate of a conventional radio frequency identification device usually has an area of 1 cm ² . In contrast, a conventional silicon wafer substrate radio frequency identification device may have an area of 0.01 cm ² or less.

For example, it is advantageous to use the substrate in the following cases: (1) using the substrate as an electroplated aluminum, aluminum/copper, stainless steel or similar metal foil plate; (2) using the substrate as an internal connection, an electrode, and Dielectric for large storage or IC resonant capacitors and inductors; (3) for electrodes of diodes, MOS devices or FETs; and (4) for the substrate as WORM/OTP, deactivated components (deactivation) ) or other memory storage components. An example of such a substrate can be found in U.S. Patent No. 10/885,283 (Attorney Docket No. IDR0121) and U.S. Patent No. 11/104,375 (Attorney Docket IDR0312). Thus, in many embodiments, the antenna and/or inductor will be formed on a first surface of the substrate, and the integrated circuit will be formed on a second surface of the first surface relative to the substrate.

Accordingly, the present invention is directed to an identification device comprising (a) a substrate; (b) an antenna and/or an inductor formed on a first surface of the substrate; and (c) formed in relation to An integrated circuit on one of the second surfaces of the first surface of the substrate. The integrated circuit has a bottommost layer that is in physical contact with the second surface of the substrate.

In one embodiment, the integrated circuit includes at least one printed layer. The printed layer may comprise a semiconductor layer, an interlayer dielectric, an interconnect metal layer and/or a gate metal layer.

Generally, the integrated circuit may include a gate metal layer, one or more semiconductor layers (eg, a transistor channel layer, a source/germanium terminal layer, and/or one or more lightly doped or a heavily doped diode layer), a gate insulating layer between the gate metal layer and the semiconductor layer, and one or more capacitor electrodes (each capacitor electrode is typically coupled to another capacitor electrode). The capacitor electrode may also be part of an integrated circuit or the capacitor electrode may be integrated or part of the substrate or antenna/inductor layer), with the gate metal layer, the source terminal and the gate terminal and And a plurality of metal conductors electrically connected to the topmost diode layer and/or the capacitor electrode and/or an interlayer dielectric layer between the metal conductors and the semiconductor layer. The integrated circuit may further comprise one or more resistors comprising a metal and/or a lightly doped or heavily doped polysilicon.

In one embodiment, the integrated circuit includes a gate metal layer, a plurality of semiconductor layers (a transistor channel layer in contact with a source/germanium terminal layer), a gate metal layer, and the gate electrode layer a gate insulating layer between the transistor channel layers and a plurality of metal conductors electrically connected to the gate metal layer, the source terminal and the germanium terminal. According to the manufacture of a MOS RFID device electronic tag/device, the exemplary layer of the integrated circuit is detailed below.

The substrate may comprise a soft material and the soft material may be resistant to relatively high temperatures (eg, temperatures ranging from 300 ° C, 350 ° C, 400 ° C, 450 ° C or higher, to 500 ° C, 600 ° C or 1000 ° C.) At such temperatures, soft materials generally do not have significant degradation or degradation in their mechanical and/or electrical properties. For example, the substrate may comprise a thin piece of glass (50-200 microns) or a slip, a glass/polymer layer, a high temperature polymer (eg, polyimide, polyethersulfone, polyethylene naphthalate [PEN], polyether Ether ketone [PEEK], etc.) or a metal foil plate, such as aluminum or stainless steel. Representative thicknesses are based on the materials used, but are generally between 25 microns and about 200 microns (e.g., from about 50 microns to about 100 microns).

The antenna and/or inductor may comprise the antenna, the inductor, or both, and may further comprise a capacitor electrode coupled to or integrated into one of the above structures (see U.S. Patent Application Serial No. 10/885,283, filed on July 6, 2004) and US Patent Application No. 11/104,375 (application date is April 11, 2005)). Typically, the antenna and/or inductor comprise a metal.

In one embodiment, the metal is commercially available as a foil (eg, aluminum, stainless steel, copper, or an alloy of these metals). In these cases (the antenna and/or inductor are made of the metal foil sheet. On the other hand, the integrated circuit is located on the opposite side of the substrate) to produce a radio frequency identification and/or electronic anti-theft device (see The method of the following paragraphs may further comprise removing a portion or more of the metal from the metal foil sheet. The metal is located below (or vice versa) the active integrated circuit (eg, a transistor and a diode, but a portion of the metal foil is used as an electrode or a flat capacitor).

In one embodiment, if an inductor includes an antenna and an inductor, the inductor can be used as a variable inductor (see, for example, U.S. Patent Application Serial No. 11/104,375). Therefore, the metal forming the antenna and the inductor may be discontinuous, and an electronic electronic anti-theft system and/or identification device according to the present invention may include a first (eg, external) coupled to one of the first panel capacitors. An inductor, a second (eg, internal) inductor coupled to a second plate capacitor, and the first (external) inductor, the second (internal) inductor, and the first and second panel capacitors A dielectric film on top. The first dielectric film has holes to expose the ends of the first inductor and the second inductor (eg, external and internal).

In another embodiment, the panel capacitor can be linear or non-linear and/or the device can further include first and second non-linear plate capacitors formed on the dielectric film. The first and second nonlinear plate capacitors are respectively coupled to the first and second linear plate capacitors.

The apparatus of the present invention may further include a support and/or backing layer (not shown) formed on one surface of the inductor 110 and relative to the dielectric film 20. The support and/or support layer is common and well known in the art of electronic electronic security systems and radio frequency identification devices (see U.S. Patent Publication No. 2002/0163434 and U.S. Patent Nos. 5,841,350, 5,608,379, 4,063,229).

Typically, such a support and/or support layer provides the following functions: (1) as an adhesive surface for attachment or placement of the electronic tag/device to an item to be tracked or monitored; and/or (2) Some mechanical support for the electronic tag/device. For example, the device of the present invention may be attached to the back side of an identification mark or price tag, and an adhesive layer is applied or placed on the surface of the device and relative to the identification mark or price tag (optional cover) A conventional release sheet is used until the label is to be used to form a trademark or label for use in a conventional RFID system.

Exemplary method for manufacturing a MOS RFID device electronic tag/device

In one embodiment, the invention is directed to a method of making an identification device. The manufacturing method comprises the steps of: (1) forming a bottom layer of one of the integrated circuits on a surface of a substrate; (2) forming a continuous layer of the integrated circuit on the bottommost layer of the integrated circuit; (3) Attaching a conductive layer to the substrate, usually at a position other than the integrated circuit.

Alternatively, the manufacturing method may further comprise the steps of: (1) forming the bottom layer of the integrated circuit on the surface of the substrate; (2) forming the continuous layer of the integrated circuit in the integrated circuit And the substrate (for example, when the substrate comprises a conductive material, such as a metal foil plate) or an active layer attached to the substrate (for example, when the substrate comprises a conductive material) A laminate and a non-conductive material, such as a metal foil sheet, having an oxide film formed or grown on one of the layers to form a conductive structure. Accordingly, the present invention provides a cost effective method for fabricating a radio frequency identification device.

2A and 2B illustrate a first exemplary method for fabricating a radio frequency identification device in accordance with the present invention. As shown in FIG. 2A, an electronic tag precursor 100 includes a substrate 132 having contacts 134, 136 and integrated circuitry 110 thereon. Generally, the integrated circuit 110 is formed on one of the first major surfaces of the substrate 132. The integrated circuit 110 can be a printed inorganic circuit, mainly using US Patent Application No. 10/885,283 (filed on July 6, 2004) and US Patent Application No. 11/104,375 (filed on April 2005) 11th). Exemplary steps for using this method to form a "bottom gate" device are described in a partial cross-sectional view of Figures 3A through 3H.

Thereafter, the contacts 134, 136 and the integrated circuit 110 are formed on the same surface of the substrate 132, similar to the process of forming the contacts 34, 36 in FIG. However, as shown in the exemplary process of FIG. 2A, the uppermost dielectric layer in the integrated circuit 110 typically has vias or holes therein (sometimes a conventional passivation layer). ), to electrically connect circuit components here (usually, the uppermost layer is metallized or as an internal interconnect, see Figure 3G and Figure 3H and its discussion). Contacts 134, 136 essentially provide the same functionality as contacts 34, 36 in Figure A.

Then, via holes or holes may be formed on the main surface of the substrate 132, and the contacts 134, 136 and the integrated circuit 110 are formed on the surface opposite to the main surface. Generally, referring to FIG. 2A, a via or hole is passed through the substrate 132 and exposes one surface of the contacts 134, 136 to electrically connect one of the terminals of the antenna/inductor 152. Typically, each via/hole is located at a location and has its dimensions. By using a relatively high throughput, low resolution attachment operation (see Figure IB), one of the pick-and-place operations or wire routing processes for integrating a wafer 20 into an inductor substrate 40. Specifically, one of the antenna/inductor 152 terminals and the corresponding contact are easily in contact with each other.

See Figure 2B again. An antenna and/or inductor 152 (possibly attached or positioned to an applicator sheet 150) is then attached or attached to the substrate 132 such that electrical connections are made at the contacts 134, 136, antenna/inductor The position of the terminal of 152 corresponds to a via or hole in the substrate 132. A short-range annealing step (which may further include applying a slight pressure to the opposing major faces of the substrate 132 and the coated sheet 150) may ensure that the inductor and/or antenna 152 are formed on the substrate 132 without errors.

The process described herein can generally result in a lower cost electronic tag by reducing the number of expensive/low throughput attachment steps and reducing the cost of manufacturing the active electronic component. A low cost electronic tag can be formed on a substrate by direct printing or otherwise forming the circuit. The substrate is then attached to an inductor/carrier with relatively low accuracy and relatively inexpensive cost. The integrated circuit can be formed on a flexible substrate such as polyamine, glass/polymer laminate, high temperature polymer or metal foil, and the substrate described above can further comprise one or more barrier layers.

The substrate typically has a size that can be processed and cost effectively processed by conventional thin film processes and/or novel or state of the art printing processes to produce low cost RF circuits. These processes include sputtering, evaporation, LPCVD, PECVD, bath etching, dry etching, direct laser printing of device components, inkjet printing of any component or layer, spray coating, blade coating. (blade coating), extrusion coating, photolithography, lithographic lithography of any layer (such as laser or inkjet), offset printing, gravure printing Gravure printing, contact printing, screen printing, combinations of the above, and/or other techniques.

Any of the layers of the integrated circuit according to the present invention can be made substantially by any of the techniques described above. In particular, the invention can manufacture RFID devices and/or electronic anti-theft electronic tags at low cost by low-cost process technology, such as printing, or a combination of printing and conventional imaging processes (eg, flat panel displays). . In the latter example, the substrate used to fabricate the integrated circuit can reduce an effective area, and the effective area can be formed on a blanket-deposited (eg, by CVD) and/or by conventional The active material used in the equipment/process for manufacturing integrated circuits. Thus, for example, the method of the present invention may further comprise the step of forming one or more second layers in an integrated circuit by a conventional imaging process.

As will be understood from the following description, the antenna and/or inductor in the present invention may be formed on the same or different sides of the substrate. Also, a process for processing a continuous bobbin or roll substrate can be used to fabricate an integrated circuit formed on a substrate (in addition to attaching the antenna/inductor structure. In the above embodiments, the antenna and/or the inductor After the integrated circuit is fabricated, it is attached to the substrate).

Demonstration method for manufacturing integrated circuits

Generally, the integrated circuit is formed directly on one of the first major surfaces of the substrate 132. For a "top gate" type device having an integrated capacitor and a diode, the integrated circuit 110 can be used in US Patent Application No. 11/084,448 (filed on March 18, 2005), U.S. Patent Application Serial No. One (partial) printed and substantially formed by the technology disclosed in 11/203,563 (filed on August 11, 2005) and US Patent Application No. 11/452,108 (filed on January 12, 2006) It is an integrated circuit 110 of an inorganic circuit.

Exemplary steps for forming a "bottom gate" type device are described in a partial cross-sectional view of Figures 3A through 3H below. Many of the techniques that will be described below (although not necessary to make a bottom gate device) are also described in U.S. Patent Application Serial No. 11/084,448, filed on March 18, 2005, and U.S. Patent Application Serial No. 11/203,563. (Application date is August 11, 2005) and US Patent Application No. 11/452,108 (application date is January 12, 2006).

Preparation of substrate

Please refer to Figure 3A. Substrate 210 may comprise any substrate that is either soft or non-soft, conductive or insulating. The substrate has the following functions: (i) providing a physical support for the integrated circuit to be formed on the substrate when the integrated circuit is formed, and for attaching the RF transmitter/receiver element to the substrate; (ii) having thereon formed thereon The integrated circuit (better printed); and (iii) the electrical connection is formed through the substrate, that is, the signal can be formed on the main surface of one of the main surfaces of the substrate and the main surface opposite to the substrate Transfer between the RF transmitter/receiver elements on the top. Thus, substrate 210 may comprise a metal foil sheet (preferably having a dielectric film (possibly electroplated) thereon), a polyimide, a thin glass or an inorganic/organic laminate substrate.

Typically, the substrate 210 is conventionally cleaned and coated with a barrier material 220, such as ceria or alumina, prior to the one-step process. The step of coating may include oxidation and/or electroplating of a surface material of one of the substrates (eg, metal foil sheets), barrier film deposited by rotation or fluid coating (Honeywell AcuGlass series or others), sputtering, CVD, Spraying a barrier material onto the substrate or any combination of the above techniques. As shown in FIG. 3A, barrier materials 220a-b are coated on at least two major surfaces of substrate 210. Optionally, the surface of at least one barrier material layer (e.g., 220a) can be processed (e.g., roughened, activated, etc.) and/or cleaned prior to the next step. To a certain extent, the substrate comprises a sheet of metal or foil which can be etched and/or trimmed as described in U.S. Patent Application Serial No. 10/885,283, filed on Jul. 6, 2004. Patent Application No. 11/104,375 (filed on April 11, 2005) and U.S. Patent Application Serial No. 11/452,108 (filed on January 12, 2006).

Formation of internal connections of gate and gate layers

Please refer to Figure 3B. A gate metal layer 230 can be conventionally sputtered onto the barrier material layer 220a. The gate metal layer 230 may include metals commonly used in integrated circuits and/or printed circuits, such as Al, Ti, Ta, Cr, Mo, W, Fe, Co, Rh, Ir, Ni, Pa, Pt, Cu. , Ag, Au, Zn, etc. Alternatively, the gate metal layer 230 may comprise an alloy of the above metals, such as Al-Ti, Al-Cu, Al-Si, Mo-W, Ti-W, and the like. Alternatively, the gate metal layer 230 may comprise a conductive compound of the above metal, such as titanium nitride, titanium telluride, tantalum nitride, tantalum telluride, molybdenum nitride, molybdenum telluride, tungsten nitride, tungsten telluride, cobalt telluride, and the like. The gate metal layer 230 may have a conventional thickness, such as 50 nm to 5000 nm, preferably 80 nm to 3000 nm, more preferably 100 nm to 2500 nm, or any range within the conventional thickness range.

Thereafter, a resist can be deposited thereon. The resistive material may comprise a conventional photoresist or thermal resistance and may be formed in a gate metal layer 230, such as spin coating or ink jet, in a conventional manner. Conventional lithography processes or printing/forming lithography processes using laser illumination can be performed (eg, selectively illuminating a portion of the impedance material and then developing the impedance material [based on the impedance material being positive or negative, by conventional The developer (see, for example, U.S. Patent Application Serial No. 11/203,563, filed on Aug. 11, 2005) selectively removes the illuminating or non-irradiated portion of the resistive material) to leave a defined gate The patterned impedance material 235 (as shown in Figure 3B) and the internal connections of the gate level. The internal connections are not shown in the figures, but may be located outside of the device or in the active region of a transistor in the form of a conventional "landing pad" or in the formation of a gate metal layer 230. On other circuit components.

The exposed gate metal layer 230 is then etched and the patterned resistive material 235 is stripped to form gates (e.g., 232 and 234 in Figure 3C) and internal connections of the gate level. Alternatively, the gate metal layer 230 can be deposited and patterned by laser printing of a metal precursor ink (eg, ink jet) and subsequent curing and/or laser scanning of a metal precursor layer. The metal precursor layer may comprise direct conversion (eg, laser induced direct conversion to metal) and indirect conversion (eg, laser-induced cross-linking of metal-containing species followed by annealing to form a conductive metal film).

Gate dielectric

Please refer to Figure 3D. A gate dielectric layer 240 (including, for example, a nitride and/or germanium, aluminum oxide, etc.) is formed on the gate and gate level internal connections by sputtering, CVD, or other blanket deposition process. 234. The gate dielectric layer 240 may have a thickness of from 10 nm to 100 nm, preferably from 10 nm to 50 nm, more preferably from 10 nm to 40 nm, or any range within the conventional thickness range.

Alternatively, the gate dielectric layer 240 can be printed (e.g., by ink jet or other printing process, as described in U.S. Patent Application Serial No. 10/885,283, and/or U.S. Patent Application Serial No. 11/104,375). Formed on the internal connections 232, 234 of the gate and gate levels. Suitable film properties and/or properties (e.g., thickness, density, dielectric constant, etc.) can be provided by printing and subsequent processing of the plurality of layers. Such subsequent processing may include oxidizing a printed dielectric precursor material (such as nanoparticle of tantalum and/or aluminum), densifying the dielectric material, and doping the dielectric material (doping )Wait.

Alternatively, a gate dielectric layer can be formed by gate-grade metal structures 232 and/or 234 by direct, conventional thermal or electrochemical (e.g., electroplating) oxidation. One or more of the gate level metal structures can generally be masked (e.g., with a photoresist or laser patterned resistive material) if a dielectric film is not formed thereon.

Forming a semiconductor layer

Thereafter, as shown in FIG. 3D, a semiconductor layer 250 (which may include germanium or lightly doped germanium) may be sputtered, coated, or blanket deposited (eg, CVD) over the gate dielectric layer 240. . The semiconductor layer 250 may have a thickness ranging from 80 nm to 2000 nm, preferably 100 nm to 1500 nm, more preferably 150 nm to 1000 nm, or any range within the above thickness range. The semiconductor layer 250 formed by a conventional lithography process or a laser patterning process (see, for example, U.S. Patent Application Serial No. 11/203,563, filed on Aug. 11, 2005) is generally incorporated herein by reference.

Alternatively, a contact layer can be deposited by conventional masking and ion implantation or by sputtering, coating or other blanket deposition (eg, CVD) to deposit a heavily doped layer. The germanium (source/drain) contact layer is formed on the semiconductor (channel) layer 250. Then, if the source/drain contact layer is blanket deposited, the source and drain contact structures 252a and 252b can be planarized by conventional planarization processes (eg, grinding [chemical mechanical polishing], or deposition of a heated surface. (thermally planarizable) material, such as an impedance material and non-selective etch back.

Moreover, silicon islands can be lithography patterning by conventional lithography processes, laser irradiation of thermal impedance materials, or printed (eg, inkjet) impedance materials, followed by dry etching. Or formed by wet etching and stripping of the impedance material. Portion 255 of the heavily doped germanium layer over the gate may not be formed (eg, not printed) or removed prior to subsequent processing. The removal may be by lithography and etching, or by forming an amorphous layer 252, then irradiating (eg, crystallizing) the amorphous layer 252 without using lasers, and removing the non-etched by selective etching. The part that is illuminated.

Alternatively, as shown in FIG. 3E, the semiconductor layer 250 and the heavily doped germanium contact layers 252a-b may be printed by a semiconductor (eg, doped or undoped germane) ink to the location corresponding to the island. (See, for example, U.S. Patent Application Serial Nos. 10/789,317, 10/950,373, 10/949,013, 10/956,714, and 11/246,014, filed on February 27, 2004, September 24, 2004, and September 9, 2004, respectively. Month 24th, October 1st, 2004, October 8th, and October 6th, 2005). Typically, the semiconductor layer 250 is printed and then processed before the heavily doped germanium contact layers 252a-b (which does not include the portion 255 above the gate) are printed. After printing, the ink is dried, cured, and/or annealed to alter its surface morphology (eg, at least partially crystallized ink). Annealing or laser irradiation may also activate some or all of the dopants in the ink. The printing process not only increases throughput by avoiding deposition and removal steps of the resistive material, but also directly forms discrete source and drain contact layers 252a and 252b.

Forming interlayer dielectric and via

The interlayer dielectric and via holes formed by the semiconductor layer and the gate layer are mainly known processes. For example, as shown in FIG. 3F, a relatively thick dielectric layer 260 may be deposited on the semiconductor layer 250 (as viewed in FIG. 3F, the contact layer 252), and then the vias 262 may be used by Known lithography processes, laser illumination of thermal impedance materials, or lithography patterning of printed resistive materials are then formed via a conventional dielectric etch process. Alternatively, a patterned dielectric layer 260 (e.g., having vias 262 therein) can be printed over the semiconductor layer 250 (e.g., by ink jetting, with reference to the description of the previous gate dielectric layer 240). The interlayer dielectric layer 260 has a thickness. For example, the thickness is at least 0.5 μm, preferably 1 μm to 25 μm, 2 μm to 10 μm, or any range within the above thickness range.

Form source/drain (S/D) and interlayer interconnects

If the heavily doped semiconductor layers 252a-b are not yet formed (see, for example, FIG. 3E), the S/D layer 270 can be sputter coated, coated, or otherwise blanket deposited onto the interlayer dielectric layer 260 and vias. 262. In general, S/D layer 270 includes a semiconductor material that is heavily doped like one of heavily doped semiconductor layers 252a-b. The S/D layer 270 may have, for example, a thickness ranging from 20 nm to 1000 nm, preferably 40 nm to 500 nm, more preferably 50 nm to 100 nm, or any range within the above thickness range.

Please refer to Figure 3G. The interconnect metal layer 280 can be sputter coated, coated, or otherwise blanket deposited onto the S/D layer 270 (including vias 262). Interconnect metal layer 280 typically comprises a metal, alloy or conductive compound. Like the gate metal layer 230, the interconnect metal layer 280 may have, for example, a thickness ranging from 0.5 μm to 10 μm, preferably 0.75 μm to 8 μm, more preferably 1 μm to 5 μm, or any of the above thickness ranges. range. Because the interconnect metal layer 280 can contact a germanium containing layer, the interconnect metal layer 280 can further comprise a lower germanium barrier layer (eg, a metal nitride such as TiN).

The S/D layer and the internal interconnect layer of the blanket deposition formed by the conventional lithography process, the laser irradiation of the thermal impedance material or the lithography process of the inkjet impedance material define the S/D layer region and the internal mutual Layers, and conventional metal (and semiconductor) etching form the actual internal interconnect. A similar connection may be formed at a predetermined location along the gate metal, but a preferred location is one location other than the island 255 (see, for example, FIG. 3E) (eg, outside the island 255).

Alternatively, as shown in FIG. 3H, the S/D structures 272-278 may be printed by a semiconductor (eg, doped or undoped germane) ink to the corresponding via 262 (see, for example, US patent) Application Nos. 10/885, 283 and/or 11/104, 375). If an undoped ink is used, the process of forming S/D structures 272-278 may further include a doping step (e.g., including conventional ion implantation or ion shower doping). Thereafter, if desired, the interconnect metal structure 280 can be attached with a lower level of adhesive and/or barrier layer and formed as previously described.

After the integrated circuit is substantially formed, the method according to the present invention may further comprise the step of deactivating the integrated circuit and/or the device (eg, forming a passivation layer or a dielectric layer on the integrated circuit (to some extent) Upper exposed) and part of the substrate). The passivation layer generally inhibits or prevents the ingress of water, oxygen, and/or other species, resulting in degradation or failure of the performance of the integrated circuit or device, and may increase mechanical support to the device, particularly during further processing of the device. in.

Traditionally, the passivation layer can be applied to the upper surface of the integrated circuit and/or device by coating one or more inorganic barrier layers. The inorganic barrier layer may be a polysiloxane, a nitride of bismuth and/or aluminum, an oxide, and/or one or more inorganic barrier layers (such as parylene). ), a fluoroorganic polymer or other barrier material. Alternatively, the passivation layer may further comprise an underlying dielectric layer, and the dielectric layer comprises a material having a lower stress than the passivation layer. For example, the dielectric layer may comprise an oxide such as cerium oxide (eg, CVD TEOS), USG, FSG, and BPSG, and the passivation layer may comprise tantalum nitride or silicon oxynitride. . Also, the thickness of the passivation layer is slightly larger than the dielectric layer.

Under the characteristics of such a process (or a material further providing some physical or mechanical support to the integrated circuit), the physical or mechanical support function of the substrate is no longer necessary. Therefore, the substrate partially supporting the integrated circuit can be completely removed (for example, the substrate is usually used for insulation) or partially removed. In the partially removed example, the substrate is electrically conductive (e.g., a metal foil plate), and the remaining portion of the substrate can form an antenna, one or more inductors, and/or wires. Via the "remaining" substrate to the integrated circuit or to individual wires connected to one of the integrated circuits, the wires are used to electrically connect the antenna and/or inductor to a via or contact. In such an example, the substrate in the final device, electronic tag or sensor may be a dielectric film or other insulator formed on the same surface of the metal foil plate, and the integrated circuit is formed. On the metal foil board.

Hybrid integrated circuit

Alternatively, the electronic label precursor (e.g., substrate 132 in FIG. 2A having integrated circuitry 110 and contacts 132, 134 thereon) may take the form of a "hybrid". For example, a radio frequency "front end" incorporating a printed, inorganic semiconductor and/or conductor substrate and a relatively inexpensive, easy to manufacture and highly functional organic or conventional germanium wafer substrate (digital) logic And/or a memory circuit would be advantageous. "RF front-end" refers to inductors, capacitors, diodes, and field-effect transistors whose frequency operates at or near the carrier frequency and/or inductors, capacitors, and diodes used to modulate the carrier frequency. Body and field effect transistors. The RF front end is shown by the "IC" area 110 in Figures 2A and 2B. These components (and circuit blocks that primarily comprise or consist of these components) are typically analogous in nature (eg, operating and/or operating in analogy or continuity) and are compared to digital logic circuits that are relatively slow in speed. Next, a device with higher performance may be required.

In the case of organic circuits, this "hybrid" form has certain advantages in terms of material and/or manufacturing costs. The organic circuitry can be applied to the controller, logic, and/or memory regions of the circuit, which typically operate at frequencies well below the radio frequency (eg, below MHz or lower). However, an airport effect transistor circuit may not operate efficiently at the carrier frequency (eg, approximately 13.56 MHz or higher). For example, diodes based on organic materials with desirable rectification, leakage, and breakdown characteristics have conventional difficulties in design and fabrication. Moreover, it is difficult to operate an organically modulated field effect transistor or an organic clock-related field effect transistor at a carrier frequency. In this case, one of the disclosed hybrid circuits includes an RF front end and is fabricated directly from the high performance printed inorganic material and an organic logic and/or memory circuit at the RF front end (the substrate or carrier to be used underneath) Made up. Therefore, the hybrid circuit is feasible in manufacturing.

Accordingly, the present invention is directed to a method of making an identification device or electronic tag. The manufacturing method comprises the steps of: (1) forming a bottom layer of one of the integrated circuits on a first surface of a substrate; and (2) forming a continuous layer of the integrated circuit on the bottommost layer of the integrated circuit And (3) attaching a conductive layer to a second surface of the first surface relative to the substrate. Therefore, the present invention can provide a low-cost process for manufacturing an RFID tag (or electronic anti-theft system) electronic tag. The electronic tag includes a substrate, a radio frequency front end or a subset of a radio frequency front end and logic circuits.

Exemplary method for reading an electronic tag of a radio frequency identification device of the present invention

The invention further relates to detecting a item or object located in a detection block. The method comprises the steps of: (a) causing or inducing a current in the identification device, the current being sufficient to cause the identification device to radiate a detectable electromagnetic signal (preferably, the frequency of the signal is an applied electromagnetic field) An integer multiple of the frequency, or the frequency of the applied electromagnetic field is an integer multiple of the frequency of the signal); (b) detecting the detectable electromagnetic radiation; and selectively (c) processing the transmission by the electromagnetic radiation News. Typically, when the device is located in a detection block that includes an oscillating electromagnetic field, current and voltage are induced in the identification device and are sufficient to cause the identification device to radiate a detectable electromagnetic signal. The oscillating electromagnetic field is manufactured or produced by conventional commodity electronic theft prevention systems and/or radio frequency identification devices and/or systems.

Therefore, the method may further comprise the steps of: (d) transmitting or transmitting the information by the identification device (or sensor) to a reading device, or attaching or appending the identification device to the device prior to step (a) Detecting an object or item (for example, one of the packaged identification cards for the goods to be shipped). Alternatively, the identification device is included in or encapsulated in the object or item.

To some extent, the electronic tag of the present invention is designed to operate in conjunction with an electronic identification and/or security system. The electronic identification and/or security system is capable of sensing disturbances in radio frequency electromagnetic fields. Such electronic systems typically establish an electromagnetic field in a region controlled by one of the inlets (pOrta1s). Products must pass through the controlled area when leaving the controlled premises (eg, a retail store, library, etc.), or the item must be placed in a location to be read and identified. An electronic tag having a resonant circuit is attached to each such article, and when the electronic tag circuit is in the controlled area, the electronic tag is sensed by a receiving system. The receiving system is configured to detect the electronic tag and process information that is available from the electronic tag (eg, to decide to remove an unauthorized item, or to determine the identity of the item in the container in which the electronic tag is attached). Most electronic tags operating under this principle are single-use or disposable, so such electronic tags are manufactured with very high throughput and low cost.

Alternatively, the electronic tag of the present invention may be in the form of a sensor, and the characteristics and/or properties of the radio frequency signal of the electronic tag may change when the characteristics and/or properties of the object or product to which the electronic tag is attached are changed. . For example, the inductor of the present invention can be attached to a stainless steel (or other metal) object, structure or surface. The characteristics and/or properties of the radio frequency signal radiated, reflected or modulated by the inductor of the present invention also change in a detectable manner as the object, structure or surface changes. For example, when the steel is oxidized, or a metal having electromagnetic properties is magnetized or entrained with a minimum threshold value, or the object or surface is changed in temperature by a predetermined amount of change or a threshold (ignoring the material of the object or surface) composition).

The electronic tag of the present invention can be used (and/or applicable, reusable, if desired) for any commercial product electronic anti-theft system and/or radio frequency identification device, and primarily such applications Any frequency band. For example, the electronic tag of the present invention may use the frequencies and regions and/or ranges described in the tables below.

Accordingly, the present invention is also directed to a commodity monitoring technique in which an electromagnetic wave system is transmitted to an area of the site and the site is protected at a dominant frequency (e.g., 13.56 MHz). Unauthorized merchandise located in the area is sensed by the receipt and detection of electromagnetic radiation. Electromagnetic radiation is emitted by the apparatus 100 of the present invention. The emitted electromagnetic radiation may comprise electromagnetic waves of a second harmonic or a subsequent harmonic frequency, and the electromagnetic waves are radiated by a sensor-transmitter element, brand or film comprising the apparatus of the invention. The device of the present invention is attached to or embedded in the article, and in the above circumstances, the trademark or film is not deactivated or, in addition, the trademark or film leaves the device with authorization The location is adjusted.

Conclusion / Summary

Accordingly, the present invention provides a MOS identification device having an integrated substrate and a method of fabricating and using the same.

The device generally comprises (a) a substrate; (b) an antenna and/or an inductor formed on a first surface of the substrate; and (c) formed on the first surface relative to the substrate One of the integrated circuits on one of the second surfaces. The integrated circuit has one of the lowest layers of physical contact (in some embodiments, electrical contact) with the second surface of the substrate.

The manufacturing method generally comprises the steps of: (1) forming the bottom layer of the integrated circuit on a surface of a substrate; (2) forming a continuous layer of the integrated circuit at the bottom of the integrated circuit; And (3) attaching a conductive layer to the other opposing surface of the substrate.

The method of use generally comprises the steps of: (i) causing or inducing a current in the identification device of the present invention, the current being sufficient to cause the device to radiate a detectable electromagnetic signal; and (ii) detecting the detectable Electromagnetic radiation; and optionally (iii) processing information transmitted by the electromagnetic radiation and/or (iv) transmitting or transmitting the information by the identification device (or sensor) to a reading device.

The present invention advantageously provides a low cost radio frequency and/or radio frequency identification device electronic tag. The radio frequency and/or radio frequency identification device electronic tag can have the standard application and operation of conventional radio frequency, radio frequency identification device electronic tags and/or electronic device anti-theft system devices and systems. By reducing the number of expensive and/or low throughput attachment steps and reducing the cost of manufacturing active electronic circuits, a low cost electronic tag can be formed by direct printing or otherwise forming the circuit on a substrate. The substrate is then attached to an inductor/carrier with relatively low accuracy and relatively inexpensive cost.

The novelty of the present invention may comprise: (i) the fabrication/processing steps of the circuit are directly integrated onto a substrate and/or (ii) printed directly onto a substrate carrier, which substrate carrier is then attached to a substrate at a low cost An inductor on the substrate, or the inductor is derived from a low cost substrate material (such as a metal foil plate).

In one embodiment, the inductor has a larger area (and thus may have two larger dimensions) than the substrate. This direct manufacturing/processing step is compatible with web, continuous, roll and/or sheet processing, and is compatible with conventional soft, thin RF trademarks, and in electronic labels. The production process increases the production. Since the picking process for combining the substrate and the inductor/antenna has a resolution, the circuit component is directly fabricated on the substrate to enable low-cost manufacturing.

The method of the present invention enables the substrate material of the device to be used at low cost and cost. The substrate material is thermally and chemically compatible with the fabrication of the RFID tag and/or the electronic tagging system electronic tag and/or provides suitable barrier properties. But in addition, if the substrate material is used for a substrate of an entire electronic tag, the cost may be too expensive.

The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. Therefore, the scope of the patented scope of the invention should be construed as broadly construed in the

10. . . Wafer

20. . . Wafer

34, 36. . . Electrical channel

40. . . Bearer carrier

50. . . Support film

52. . . Inductor / antenna

100. . . Electronic label precursor

110. . . Integrated circuit

132. . . Substrate

134, 136. . . contact

150. . . Coated sheet

152. . . Inductor / antenna

210. . . Substrate

220a, 220b. . . Barrier material

230. . . Gate metal layer

232, 234. . . Internal connection

235. . . Impedance material

240. . . Gate dielectric layer

250. . . Semiconductor layer

252a, 252b. . . Contact layer

255. . . Yeouido

260. . . Dielectric layer

262. . . Via

270. . . Source/drain layer

272~278. . . S/D structure

280. . . Interconnect metal layer

1A to 1C show the steps of a conventional process for manufacturing an RFID tag electronic tag. The process includes attaching a conventional semiconductor wafer to a substrate.

2A and 2B illustrate the key steps in an exemplary process for fabricating an RFID tag/device for an RFID device having an integrated substrate in accordance with the present invention.

Figures 3A through IIIH illustrate the key steps in an exemplary process for fabricating an integrated circuit on a substrate for use in an electronic tag/device of a radio frequency identification device in accordance with the present invention.

110. . . Integrated circuit

132. . . Substrate

134, 136. . . contact

150. . . Coated sheet

152. . . Inductor / antenna

Claims (20)

An identification device comprising: a substrate; an antenna and/or an inductor on a coated sheet, the antenna and/or the inductor being attached to or attached to the substrate, the antenna and/or the inductor having a relative a first terminal and a second terminal; and an integrated circuit on the substrate, the integrated circuit is electrically connected to the antenna and/or the inductor via a first via hole and a second via hole respectively The first terminal and the second terminal, the integrated circuit having one of the lowest layers in contact with one of the surfaces of the substrate. The identification device of claim 1, wherein the integrated circuit comprises at least one printed layer. The identification device of claim 2, wherein the at least one printed layer comprises a semiconductor layer. The identification device of claim 3, wherein the integrated circuit further comprises a gate metal layer and a gate insulating layer interposed between the gate metal layer and the semiconductor layer. The identification device of claim 4, wherein the integrated circuit further comprises a source terminal and a terminal. The identification device of claim 5, wherein the integrated circuit further comprises a plurality of metal conductors electrically connected to the gate metal layer, the source terminal and the anode terminal. The identification device of claim 6, wherein the integrated circuit further comprises an interlayer dielectric layer between the metal conductors and the semiconductor layer. The identification device of claim 2, wherein the at least one printed layer comprises at least one of the group consisting of a gate metal layer, an interlayer dielectric layer, and an interconnect metal layer. The identification device of claim 1, wherein the substrate comprises a polymethyleneamine, a glass/polymer laminate, a high temperature polymer or a metal foil plate. A method of fabricating an identification device comprising the steps of: (a) forming a bottommost layer of an integrated circuit on a surface of a substrate and in physical contact therewith; (b) forming a continuous layer of the integrated circuit And (c) opposing an antenna, an inductor, and/or a conductive layer on a coated sheet via a first and second via holes or holes in the substrate, respectively; The first and second terminals are electrically connected to the integrated circuit. The method of claim 10, wherein the step of forming the bottommost layer of the integrated circuit comprises printing the bottom layer of the integrated circuit. The method of claim 10, wherein the step of forming the continuous layer of the integrated circuit comprises printing at least one of the continuous layers. The method of claim 12, wherein at least one of the continuous layers comprises a semiconductor layer. The method of claim 10, wherein the continuous layer of the integrated circuit comprises a source/drain layer, a gate dielectric layer, a gate metal layer, and an interconnect/metallization layer . The method of claim 10, wherein at least one of the bottommost layer and the continuous layer of the integrated circuit comprises a transistor channel layer. The method of claim 10, wherein the step of forming the bottommost layer of the integrated circuit comprises printing the bottom layer or forming the bottom layer by a conventional development process, and forming the integrated circuit The step of at least one of the continuous layers includes printing the at least one continuous layer or another manner of forming the at least one continuous layer by conventional development processing. The method of claim 10, wherein the substrate comprises a dielectric quality. The method of claim 10, wherein the electrically conductive layer comprises a metal foil sheet. The method of claim 18, further comprising the step of etching the metal foil sheet to form the antenna and/or the inductor. A method for reading an identification device, comprising the steps of: (a) causing or inducing a current in the identification device of claim 1 that is sufficient to cause the identification device to radiate, reflect or modulate a a detectable electromagnetic signal; and (b) detecting the detectable electromagnetic signal.