JP2009048371A - Rf tag/device having integrated interposer and/or rfid tag/device, production method thereof, and use method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively provide an inexpensive RFID (Radio Frequency IDentification) tag. <P>SOLUTION: This tag is equipped with; an interposer; an antenna and/or an inductor thereon, and an integrated circuit prepared on the interposer avoiding the antenna, etc., and having a bottom layer in contact with a surface of the interposer physically. This production method includes a step of forming a bottom layer of the integrated circuit on a surface of the interposer; a step of forming a following layer of the integrated circuit on the bottom layer of the integrated circuit; and a step of connecting a conductive layer to the interposer. A structure having conductivity may be formed from a functional layer attached to the interposer. This method includes; a step in which this device emits a detectable electromagnetic signal to generate sufficient current to reflect or modulate, or guides; a step of detecting the signal; and a step of processing information carried by the detectable electromagnetic signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

Field of Invention

  [0001] The present invention relates to the field of sensors, electronic article surveillance (EAS) tags or devices, radio frequency (RF) tags or devices, and / or RF recognition (RFID) tags or devices. is there. In particular, embodiments of the present invention relate to EAS, RF and / or RFID structures and to methods for their manufacture and / or production. As a result, the present invention can provide an inexpensive process for producing RFID (or EAS) tags comprising a substrate, RF front end or subset of RF front end, memory and logic circuitry.

Background explanation

  [0002] Electronic devices and related systems that are powered remotely are known. For example, Geiszler et al., US Pat. No. 5,099,227, entitled “Proximity Detecting Apparatus”, uses electromagnetic coupling to obtain power from a remote power source, followed by electromagnetic coupling and electrostatic coupling. A remote power supply device is disclosed that transmits stored data to a receiver that is typically located with a remote power source. In general, such remotely powered communication devices are known as RFID tags.

  [0003] RFID tags and related systems have many uses. For example, RFID tags are often used for identification purposes in automated gate surveillance applications that protect protected areas or buildings. These tags typically take the form of access restriction cards. The information stored in the RFID tag identifies the tag owner who intends to access the secure area or building. In previous automated gate monitoring applications, a person approaching a building typically inserts a recognition card or tag into the reader of the system so that the system can read information from the recognition card or tag, or It was necessary to pass. In the new RFID tag system, high frequency data transmission technology is utilized and the recognition tag is read at a short distance, so there is no need to insert or pass a certification tag through the reader. Most typically, a user simply has or places a tag near a base station that is coupled to a security system that protects the building or area. The base station sends an excitation signal to the tag and supplies power to the circuit contained in the tag. In response to the excitation signal, the circuit transmits stored information from the tag to the base station, which receives and decodes the information. The information is then processed by the security system to determine whether access is appropriate. Also, RFID tags can be written remotely (eg, programmed and / or deactivated) with excitation signals appropriately modulated in a predetermined manner.

  [0004] Some conventional RFID tags and systems primarily utilize electromagnetic coupling to remotely supply power to the remote device and connect the remote device to the excitation and reception systems. The excitation system generates an electromagnetic excitation signal that provides power to the remote device and causes the device to transfer a signal that may include stored information. The receiver receives a signal generated by the remote device.

[0005] More basically, RFID tag circuitry generally performs some or all of the following functions.
1. 1. Absorption of RF energy from the reader's electromagnetic field. 2. Conversion of RF signal to DC signal that supplies power to the chip 3. Demodulate input clock signal, input timing signal and / or input command signal obtained in RF signal from reader to RF signal 4. State machine decision making and control logic operates based on input commands or preset commands 5. Read based on a counter or register of data in digital form from a memory array or other source (eg, output from a sensor) A storage element (eg, memory) (also, eg, configured to count a predetermined number of uses (eg, in a traffic ticket) and / or to relay information from a sensor to a reader 6. EAS non-volatile memory) is read by a reader and / or stores an ID code or other information used for security authentication. Modulation of encoded data, timing signals, or other commands sent back to the tag antenna for transfer to the tag reader

  [0006] On the other hand, according to the EAS tag circuit, some of these steps and / or functions can be eliminated. For example, a logic-based frequency division EAS uses basic RF energy to power an internal logic divider that modulates the tag's antenna so that a unique subharmonic signal is sent back to the reader. (See, for example, GB-A-2017454). The subharmonic signal is easily distinguishable from other noise sources (such as carrier harmonics) and produces a valid EAS signal. As disclosed in US Pat. No. 4,670,740, in some cases, this can be simplified by using non-linear effects arising from the semiconductor device. Like the latter, non-linear effects in semiconductor diodes or varactors can be used to generate subharmonic signals that can be detected by the reader without intermediate RF to DC power conversion or logic processing.

  [0007] As shown in FIG. 1A, a process of cutting a wafer 10 manufactured by a conventional wafer-based process into a plurality of chips 20, and then chip 20 into an antenna or inductor / carrier sheet ( Placed on an etched, cut or printed metal antenna, inductor coil or other conductive mechanism) or on an interposer strap (or carrier) 40 as shown in FIG. A conventional RFID tag can be formed by a process that can include the steps of: interposer strap 40 can then be attached to inductor / antenna 52 on support film 50. This process includes not only wire bonding, anisotropic conductive epoxy bonding, ultrasonic bonding, bump bonding or flip-chip techniques for electrical interconnection, but also various physical processes such as adhesive bonding. Typical joining techniques can also be included. The bonding process typically includes heating, passage of time, and / or UV irradiation. In order to reduce the cost per chip, since the Si chip 20 is usually made as small as possible (<1 mm), the pad components for electrical contact on the chip 20 may be relatively small. This means that even high-speed mechanical work requires that the placement work be relatively accurate (eg, typically placed within 50 microns of the desired location). ).

  [0008] Overall, picking an isolated chip, moving the chip to the appropriate location on the interposer, antenna, inductor or carrier to which the chip is to be bonded, and accurately positioning it at the appropriate location; The process of forming physical and electrical interconnections can be a relatively time consuming and expensive process. In the case of a process using an intermediate interposer, when the chip 20 is first attached to the web roll of the interposer carrier 40, the interposer carrier is arranged at a narrow interval and a fluidic self-assembly process is performed. ) Or other novel joining operations, such as a pin bed attachment process, can be done quickly or simultaneously, which is advantageous in terms of cost and throughput. Crimping or mounting with conductive adhesive (when integrating the chip directly onto the inductor substrate, compared to pick-and-place and / or wire bonding based processes The carrier 40 is generally located at other locations on the carrier 40 from the chip 20 so that a high throughput and low resolution connection operation is possible (such as somewhat functionally similar to a conventional strap). Provide an electrical path (eg, 34 or 36) to a relatively large and / or large section area. Based on commercially available equipment and materials (Muhlbauer TMA6000 or similar), in some cases, a low resolution attachment process suitable for a strap can be performed at a cost of about $ 0.003 or less. The carrier 40 is then connected to an inductor (not shown) in which electrical connections are made elsewhere. Performing the necessary stubs, bumps and other interconnectors on a larger inductor / carrier substrate using conventional methods (eg, wire bonding) is expensive and disadvantageous, so the process using the interposer is flip-chip or It is also advantageous compared to the bup bonding method.

  [0009] In order to reduce the price of RFID tags to $ 0.01 for retailing at the item level, and to reduce costs and increase capacity, an inexpensive substrate, a stable and effective antenna, an RF front-end device, And a tag structure and process that incorporates (and properly integrates) logic circuitry patterned with high resolution.

Summary of the Invention

  [0010] Embodiments of the present invention relate to MOS RF devices and / or RFID devices, sensors, or tags having integrated interposers, and methods for making and using the same. MOSRF devices and / or RFID devices are generally provided on an interposer at (a) an interposer, (b) an antenna and / or inductor on the interposer, and (c) at a location other than the antenna and / or inductor. Integrated circuit having a bottom layer in physical contact with the surface of the interposer.

  [0011] The manufacturing method according to the present invention is generally described as follows: (1) forming a bottom layer of an integrated circuit on the surface of the interposer; and (2) continuation of the integrated circuit on the bottom layer of the integrated circuit. Forming a plurality of layers, and (3) connecting the conductive layer to the interposer. Alternatively, the manufacturing method according to the present invention includes the steps of (1) forming a lowermost layer of an integrated circuit on the interposer surface, and (2) forming a plurality of successive layers of the integrated circuit on the lowermost layer. And (3) forming a conductive structure from a functional layer connected to the interposer.

  [0012] The method of use according to the present invention is generally described as follows: (i) the device according to the present invention generates sufficient current to radiate, reflect or modulate a detectable electromagnetic signal. And (ii) detecting detectable electromagnetic radiation, and optionally (iii) processing information transferred by the detectable electromagnetic radiation. Includes steps. Optionally, the method of use may further comprise the step of transmitting or transferring information from the device (or sensor) back to the reader.

  [0013] As one feasible method for manufacturing very inexpensive RFID tags, it is possible to use printing techniques in web-fed or sheet-fed processes. Printing technology can increase material utilization (e.g., additional or quasi-additional processing), can combine deposition and patterning steps, and has low equipment and equipment management costs. Has potential advantages in terms of cost. Furthermore, conventional printing processes with high throughput can be applied to flexible substrates (eg, plastic sheets or metal films), thus increasing tag utilization in various fields (applications). The method of improving material efficiency and performing additional processing can reduce the cost per unit area of the processed interposer (or chip, if used), resulting in lower cost. It enables the attachment process and allows the integration of passive devices with active circuits. Further, for example, if each RF device is given a unique identification code and / or a unique reaction time delay for the search signal of the reader, the RF device can be activated by a maskless process such as printing. Can be easily customized.

[0014] Furthermore, if the circuit can be printed directly on the antenna or inductor structure itself, the connection step and associated costs can be eliminated. This method reduces chip cost by reducing the chip size (although this method may be self-limiting for directly connected silicon RFID tags because of the increased cost associated with mounting smaller chips) This is different from the semiconductor wafer cost reduction method. However, advances in processes, means and / or materials that are not widely available or not commercially available make RFID tags that are fully printed and free of area limitations even more advantageous. The “integrated interposer” method outlined here allows for a combination of display processing and printing with low cost per unit area (eg, 0.35 micron Si chip processing costs are currently around 25). is $ / in ^2, the processing cost of conventional polysilicon for displays of 0.50 dollars / in ² to 0.90 dollars / in ^2, processing cost based on the print is than 0.50 dollars / in ² Expected).

[0015] The use of an interposer-based process allows for some or all conventional film display processing and processing of photoelectric materials. For the processing of photovoltaic materials, the process of producing inorganic semiconductor layers, insulator layers or other layers in a highly developed roll-to-roll system on films, sheets and / or other flexible substrates Is included. For a single layer, the cost to the process can be kept below about $ 0.01 / in ² . Thus, the costs associated with such processing methods are applicable when the interposer is relatively small (on the order of 25 mm ² ), but the entire inductor or antenna substrate (ie, 100 mm ² or more) must be processed. In some cases, application is expected to be difficult. When this processing method is used, the cost can be further reduced from the cost ($ 0.003) required when using the method of attaching the interposer with low resolution, and the display and photovoltaic type processing apparatus itself is used. (And alternatively, in combination with printing steps that allow the entire manufacturing process without waiting for complete means and / or material advancements for printed RFID tags) and effectively producing RFID tags be able to. Ultimately, however, such processes include spool-based printing processes and / or roll-to-roll printing processes, which include low equipment costs, high throughput (several hundred m ² / hr), and material usage efficiency. Manufacturing costs should be further reduced by improvement and / or reduction of processing steps.

  [0016] The present invention provides a low-cost RF tag and / or RFID tag capable of standard applications and operations using conventional RF equipment or systems, RFID equipment or systems, and / or EAS equipment or systems. Provide effectively. Interposer connected to inductor / carrier with relatively low accuracy and relatively low cost by reducing the number of high-cost and / or low-throughput connection steps as well as reducing the production cost of active electrical components Inexpensive tags can be produced by forming the circuit directly or by printing the circuit on it. In the following, suitable embodiments will be described in detail to clarify these and other advantages of the present invention.

Detailed Description of the Preferred Embodiment

  [0020] Preferred embodiments according to the present invention, which are examples depicted in the accompanying drawings, will now be described in detail. While the invention will be described in conjunction with the preferred embodiments, these embodiments are not intended to limit the invention to those embodiments. Also, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, various specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

  [0021] For convenience and simplicity, "couple", "attach", and "connect" mean direct or indirect coupling, attachment, or connection, unless the context indicates otherwise. These terms here can be interchanged with each other, but represent a known meaning in the technical field. Also, for convenience and simplicity, “RF”, “RFID” and “recognition” may refer to each other depending on the intended use and / or function of the device or the intended use and / or function of the tag. The “tag” or “device” here can be replaced with an RF sensor or RFID sensor, an RF tag or RFID tag, or an RF device or RFID device (RF and / or RFID sensor, tag and / or device). Can be used to indicate any of Furthermore, the term “integrated circuit” refers to a unitary structure that includes a plurality of electrically active devices formed from a plurality of conductors, semiconductors, and insulator films, but separate elements that are mechanically connected ( Chips, wire bonds or conductors, interposers, or elements such as antennas or inductors) or materials that have inherently adhesive functions are generally not included. In addition, the terms “article”, “object” and “article” can be interchanged, and when any of the terms is used, other terms are also included. In this application, the “principal surface” of a structure or mechanism refers to the surface defined at least in part by the maximum axis of the structure or mechanism (eg, radial if the structure is circular and has a radius greater than thickness). Is the main surface of the structure).

  [0022] The present invention is (a) an interposer, (b) an antenna and / or inductor on the interposer, and (c) an integrated circuit provided on the interposer at a position other than the antenna and / or inductor, The present invention relates to an RF sensor, an RF monitoring device, and / or an RFID device having a lowermost layer in physical contact with the surface of an interposer. In various embodiments, the integrated circuit comprises membrane transistors, diodes, optional capacitors and / or resistors, and metallization layers that interconnect the circuit components. In other embodiments, one or more layers of the integrated circuit are composed of printed layers or laser patterned layers.

  [0023] In a further aspect, the present invention provides: (1) forming a bottom layer of an integrated circuit on the interposer surface; and (2) a plurality of successive integrated circuits on the bottom layer of the integrated circuit. The present invention relates to a method for manufacturing a sensor, a monitoring device, and / or a recognition device, including a step of forming a layer and (3) connecting a conductive layer to an interposer. Alternatively, the manufacturing method includes (1) forming a bottom layer of the integrated circuit on the interposer surface, (2) forming a plurality of layers following the integrated circuit on the bottom layer, and (3 ) Forming a conductive structure from a functional layer coupled to the interposer. In various embodiments, one or more layers of the integrated circuit are formed by printing or by laser patterning. In one embodiment, the bottom layer forming step of the integrated circuit includes a printing process or a laser patterning process.

  [0024] As a still further aspect, the present invention provides: (A) the monitoring device and / or the recognition device according to the present embodiment attached to or coupled to an article or article emits a detectable electromagnetic signal. Generating or inducing sufficient current in the device to reflect, or modulate or (B) detect detectable electromagnetic radiation (and optionally (C) detect And a method for detecting an article or article (reading method) comprising the step of processing information transferred by means of possible electromagnetic radiation. Optionally, the method of use according to this embodiment may further comprise the step of transferring or transmitting information from the device (or sensor) to the reading device. The invention according to the present embodiment will be specifically described below along with schematic embodiments from various viewpoints.

Exemplary MOS RFID Tag / Device [0025] One aspect of the present invention is: (a) an interposer, (b) an antenna and / or inductor on the interposer, and (c) an interposer at a location other than the antenna and / or inductor. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an RFID device including an integrated circuit provided on the top and having a lowermost layer in physical contact with the surface of an interposer. This provides an inexpensive RFID (or EAS) tag with a substrate (eg, interposer), inductor / antenna and RF front end (or a subset of the RF front end and logic circuitry) that is fully operational as per modern RFID standards. (Sensors, certain external changes in the environment [eg, temperature, conductivity of the structure or surface to which the sensor is attached, and others) and generally changing signal activities and active An RFID device may be further provided (eg, a tag having a battery provided on a board).

  [0026] Printed electronic components based on inorganic materials (eg, nanocrystals by laser printing) have an appropriate thermal isolation layer / barrier layer between the substrate (eg, metal film) and the next layer to be laser treated. It has been found that once inserted, it can be formed on certain flexible substrates such as high temperature polyimide or metal films. As described above, the invention according to the present embodiment can effectively use such a material as a substrate or an interposer in a flexible EAS tag or device, an RF tag or device, or an RFID tag or device printed (at least partially). Can be used.

[0027] To produce inexpensive RF circuits, interposers typically have a size that can be processed cost-effectively using conventional thin film processes and / or emerging processes or state-of-the-art printing processes. Have. The integrated circuit can be formed on a flexible interposer substrate such as polyimide, glass / polymer laminate, high temperature polymer or metal film, and the integrated circuit formed on such substrate all has one or more barriers. A layer may further be provided. Such an interposer substrate is substantially less expensive than a conventional Si chip of similar size (but in contrast to a conventional Si RFID chip, which may have an area of about 0.01 cm ² or less) RFID interposers typically have an area on the order of 1 cm ² ).

  [0028] An anodized Al film, Al / Cu film, stainless steel film or similar metal film is used as an interposer substrate, and as an insulator, electrode and interconnector for an IC resonance capacitor or a mass storage device It may be useful to use an inductor and use an inactive or other memory storage element as an electrode for a diode, MOS device or FET or as a WORM / OTP. Examples of such substrates are disclosed in US Patent Nos. 10 / 885,283 and 11 / 104,375 (Attorney Docket No. IDR0121 and No. IDR0312, respectively). Thus, in various embodiments, the antenna and / or inductor is provided on the first surface of the interposer and the integrated circuit is provided on the second surface of the interposer opposite the first surface.

  [0029] Thus, the present invention comprises (a) an interposer, (b) an antenna and / or inductor on the first surface of the interposer, and (c) a second surface of the interposer opposite the first surface. And an integrated circuit provided with a bottom layer in physical contact (and in various embodiments, electrically) with the second surface of the interposer. In one embodiment, the integrated circuit includes one or more printed layers. The printed layer may comprise a semiconductor layer, an intermediate insulator layer, a metal interconnector layer and / or a gate metal layer.

  [0030] Generally, an integrated circuit is doped with a gate metal layer and one or more semiconductor layers (eg, a transistor channel layer, a source / drain terminal layer, and / or a lower or higher concentration). One or more diode layers), a gate insulator layer between the gate metal layer and the semiconductor layer, and one or more capacitor electrodes (each capacitor electrode is generally electrostatically coupled to another capacitor electrode, The additional capacitor electrode may also be part of the integrated circuit or may be integrated together, or may be part of the interposer or antenna / inductor layer), the gate metal layer, the source, Multiple metal conductors electrically connected to the drain terminal and / or the uppermost diode layer or capacitor electrode, and intermediate insulation between the metal conductor and the semiconductor layer And a body layer. The integrated circuit may further comprise one or more resistors, the one or more resistors may include metal and / or lightly or heavily doped polysilicon. In one embodiment, the integrated circuit includes a gate metal layer, a plurality of semiconductor layers (a transistor channel layer in contact with the source / drain terminal layers), a gate between the gate metal layer and the transistor channel layer. An insulator layer and a plurality of metal layers electrically connected to the gate metal layer, the source terminal, and the drain terminal are included. In the following, typical layers of an integrated circuit according to a typical method of manufacturing a MOS RFID tag / device will be described more specifically.

  [0031] Interposers are relatively high temperature processing (eg, 300 ° C., 350 ° C., 400 ° C., 450 ° C. or higher, or temperatures up to 500 ° C., 600 ° C. or 1000 ° C., generally mechanical and / or Or a flexible material that can be employed to withstand temperature treatments that substantially reduce or reduce electrical properties. For example, the interposer can be a thin (50-200 micron) glass sheet or slip, a glass / polymer laminate, a high temperature polymer (eg, polyimide, PES (polyethersulfone), PEN (polyethylene naphthalate) PEEK (polyether ether ketone), etc.), or aluminum Alternatively, a metal film such as stainless steel can be included. Depending on the material, typical thicknesses are generally in the range of about 25 μm to about 250 μm (eg, from about 50 μm to about 100 μm).

  [0032] The antenna and / or inductor may include an antenna, an inductor, or both, and may further include a capacitor electrode connected thereto or a capacitor electrode integrated therewith (July 6, 2004 and (See US patent application Ser. Nos. 10 / 885,283 and 11 / 104,375, each filed on Apr. 11, 2005). Generally, the antenna and / or the inductor is made of metal. In one embodiment, the metal may be commercially available as a film (eg, aluminum, stainless steel, copper, or alloys thereof). In such a case (when the antenna and / or inductor made of metal film is made on one side and the integrated circuit is on the opposite side of the interposer), the RFID device and / or the EAS device (See the description below.) The manufacturing method is under a metal film or an electrically active integrated circuit (eg, a transistor or a diode, but not necessarily a capacitor using a metal film as an electrode or electrode plate). That is, the method may further include removing one or more metal portions located on the opposite side.

  [0033] In one embodiment that includes both an antenna and an inductor, the inductor may function as a pacing inductor (see, eg, US patent application Ser. No. 11 / 104,375). Therefore, the metal forming the antenna and the inductor may not be continuous (that is, it may include an electrically disconnected portion), and the monitoring device and / or the recognition device according to the present invention may include the first capacitor electrode. A first (outer) inductor connected to the plate, a second (inner) inductor connected to the second capacitor electrode plate, an insulator layer on the first (outer) inductor, and a second (inner) And the first and second capacitor electrode plates, the first insulator layer having respective tips of the first and second (eg, outer and inner) inductors therein Has an exposed hole. In alternative embodiments, the capacitor electrode plate may be linear or non-linear, and the monitoring or recognition device may be first and second coupled to the first and second linear capacitor electrode plates, respectively. A non-linear capacitor electrode plate may be further provided on the insulator layer.

  [0034] The device according to the present embodiment may further include a support layer and / or a backing layer (not shown) on the surface of the inductor 110 opposite to the insulator film 20. Support layers and / or backing layers are common and are known in the EAS and RFID fields (eg, US 2002/0163434 and US Pat. No. 5,841,350, Nos. 5,608,379 and 4,063,229). Generally, such support and backing layers are (1) an adhesive surface for mounting or placement of the tag / device on the article to be detected or monitored, and / or (2) the tag / Provides some mechanical support for the device. For example, the device according to the present embodiment is attached to the back of a recognition label or price tag (price tag), and further forms a label or tag suitable for use in a conventional RFID system. It is preferred that the adhesive material be coated or placed on the surface of the device on the opposite side (optionally covered with a conventional release sheet until a label or tag is available).

Typical Manufacturing Method of MOS Tag / Device [0035] In one aspect, the present invention includes (1) forming a bottom layer of an integrated circuit on the surface of the interposer; and (2) on a bottom layer of the integrated circuit. The present invention relates to a method for manufacturing a recognition device, including the step of forming a plurality of layers following the integrated circuit, and the step of (3) connecting a conductive functional layer to the interposer substantially at a position other than the integrated circuit. Alternatively, the manufacturing method according to the present embodiment includes (1) a step of forming a lowermost layer of the integrated circuit on the surface of the interposer, and (2) a step of forming a plurality of layers following the integrated circuit on the lowermost layer. And (3) from an interposer (eg, when the interposer includes a conductive metal such as a metal film) or from a functional layer connected to the interposer (eg, the interposer is anodized on the top surface) Forming a conductive structure (including a laminate of a conductive material and an electrically inert material, such as a metal layer on which an oxide layer is formed or grown). Thus, according to the manufacturing method according to the present embodiment, the RFID device can be manufactured with high cost efficiency.

  [0036] Hereinafter, a first typical manufacturing method of the RFID device according to the present embodiment will be described with reference to FIGS. FIG. 2A shows a tag precursor 100 that includes pads 134 and 136 and an interposer 132 having an integrated circuit 110 on the top surface. In general, the integrated circuit 110 is formed on the first main surface of the interposer 132. Mainly using the techniques disclosed in US patent application Ser. Nos. 10 / 885,283 and 11 / 104,375 filed on Jul. 6, 2004 and Apr. 11, 2005, respectively. Thus, the integrated circuit 110 can be realized as a printed inorganic circuit. Typical steps in the formation of a “bottom gate” device using this method are described below, and partial cross-sectional views of the steps are depicted in FIGS. 3A-H. .

  [0037] Next, as in the formation process of the pads 34 and 36 in FIG. 1A, pads 134 and 136 are formed on the same surface as the surface of the interposer 132 in which the integrated circuit 110 is formed. However, in the exemplary process of FIG. 2A, circuit components present in integrated circuit 110 (generally upper metallization layers or interconnects, eg, (G)-(H ) And the following description) holes or vias present in the top insulator layer of integrated circuit 110 (known as a passivation layer (passivation layer)) There is generally. (In the top insulator layer of the integrated circuit 110 (often known as a passivation layer), holes or vias are generally present. Basically, pads 134 and 136 are shown in FIG. It performs the same function as pads 34 and 36.

  [0038] Next, holes or vias may be formed on the main surface of the interposer 132 opposite the surface on which the pads 134 and 136 and the integrated circuit 110 are formed. In general, and as shown in FIG. 2A, a hole or hole penetrating the interposer 132 that exposes the surfaces of the pads 134 and 136 and allows electrical contact with the terminals of the antenna / inductor 152. There are vias. Generally, mounting methods with relatively high throughput and relatively low resolution (compared to pick-and-place or wire bonding processes used to connect the chip 20 to the inductor substrate 40; FIG. )), Each hole / via exists in a position that allows easy contact between one terminal of the antenna / inductor 152 and the corresponding pad, and the area that enables it is defined as Have. As shown in FIG. 2B, an electrical coupling is formed between pads 134 and 136 and the terminals of antenna / inductor 152 at locations corresponding to holes or vias present in interposer 132. , Inductor and / or antenna 152 (attached or disposed on applicator sheet 150) to or attached to interposer 132. An inductor and / or antenna 152 is fairly reliably secured to the integrated interposer 132 by annealing for a short period of time (and may apply a small pressure to the opposite major surface of the integrated interposer 132 and the application sheet 150). be able to.

  [0039] The process described herein not only reduces the manufacturing cost of active electrical components, but also reduces the number of costly / low-throughput connection steps, thereby reducing costs overall. it can. Inexpensive tags can be produced by printing the circuit directly or otherwise forming the circuit on an interposer that is relatively inexpensively coupled to the inductor / carrier with relatively low precision. This method can be effective in that circuit processing can be performed on flexible substrates such as polyimides, glass / polymer laminates, high temperature polymers or metals (all that further have one or more barrier layers). .

  [0040] For the production of inexpensive RF circuits, interposers typically have a size that can be manufactured cost-effectively using conventional film processes as well as conventional or modern printing processes. These processes include sputtering, evaporation, LPCVD, PECVD, bus etching, dry etching, direct laser printing of equipment components, inkjet printing of any component or layer, spray coating, blade coating, extrusion coating, Photolithography, lithography of any layer using a printed etch mask (such as laser or ink jet), offset printing, gravure printing, embossing, contact printing, schooling printing or combinations thereof and / or other techniques Is included. Almost all layers in the integrated circuit according to the present embodiment can be basically manufactured by any of these techniques. In particular, according to the present invention, RFID tags and / or EAS tags can be manufactured inexpensively by printing or by low cost processes such as a combination of printing and conventional display (eg, flat panel display) processing. It becomes possible. The latter uses an interposer as a substrate for the manufacture of integrated circuits so that active materials can be blanket deposited thereon and / or by equipment / processes commonly used to manufacture integrated circuits. The effective area where active material can be processed can be reduced. Therefore, the manufacturing method according to the present embodiment may further include a step of forming one or more second layers of the integrated circuit by, for example, a conventional display process.

  [0041] As will be apparent from the following description, in the present invention, the antenna and / or the inductor can be formed on the same side or the opposite side of the interposer. Also, a facility for processing substrates based on continuous rolls or spool webs may be used for the manufacture of integrated circuits according to this embodiment on the interposer (and the antennas and / or inductors on the interposer after the integrated circuit is manufactured). In a connected embodiment, can be used to attach an antenna / inductor).

Typical Manufacturing Method of Integrated Circuit [0042] Generally, the integrated circuit is formed directly on the first major surface of the interposer 132. In a top-gated device having an integrated capacitor and an integrated diode, US patent application Ser. No. 11 / 084,448 filed Mar. 18, 2005, Aug. 11, 2005, and Jun. 12, 2006, respectively. No. 11 / 203,563 and 11 / 452,108, the integrated circuit 110 is printed (partially) and essentially using the techniques disclosed in US Pat. It can be realized as a circuit containing an inorganic material.

  [0043] Typical steps in the formation of a bottom gate type device are described below and are shown in FIGS. 3A-H as partial cross-sectional views. U.S. Patent Application Nos. 11 / 084,448, 10 / 885,283 and March 18, 2005, July 6, 2004 and April 11, 2005, respectively. In the 11 / 104,375 specification, many of the techniques described later are also disclosed.

Interposer Substrate Preparation [0044] As shown in FIG. 3A, interposer 210 is flexible or non-flexible (non-flexible), electrically active or insulative capable of the following three points: Any substrate may be provided. (I) physical for an integrated circuit formed on the interposer 210 during formation of the interposer 210 and for an RF transmitter / receiver attached to the interposer 210 during connection of the interposer 210; Support can be provided, (ii) can have (preferably printed) integrated circuits formed on the interposer 210, and (iii) can be electrically coupled through the interposer 210. (Ie, to ensure that signals are transmitted between an integrated circuit formed on one major surface of the interposer and a receiver / transmitter component mounted on the opposite major surface of the interposer) A substrate may be provided. Thus, the interposer 210 may comprise a metal film (preferably a metal film having an insulator film [which may be anodized] thereon), polyimide, thin glass or an inorganic / organic laminate substrate. .

  [0045] Preferably, the interposer 210 is normally cleaned before the next step and coated with a barrier material 220 (such as silicon dioxide or aluminum oxide). The coating step may include oxidizing and / or anodizing the surface material of an interposer substrate (eg, a metal film), depositing a spin-on or fluid-coated barrier film (Honeywell AcuGlass series or other), sputtering, CVD, or spraying. Deposition of a barrier material on the interposer substrate by coating, or any combination thereof may be included. As shown in FIG. 3A, the barrier materials 220 a and 220 b cover at least two main surfaces of the interposer 210. Optionally, the surface of at least one barrier material layer is preferably treated (eg, roughened or activated) and / or cleaned prior to the next step. If the interposer comprises a metal sheet or metal film, US patent application Ser. No. 10 / 885,283 filed on Jul. 6, 2004, Apr. 11, 2005 and Jun. 12, 2006, respectively. 11 / 104,375 and 11 / 452,108, the metal film is etched and / or cut to separate the contact pads of the antenna. Is preferred.

Gate and Gate Layer Interconnector Formation [0046] As shown in FIG. 3B, the gate metal layer 230 can be formed on the barrier material layer 220a by sputtering as is conventional. The gate metal layer 230 is formed of aluminum (Al), titanium (Ti), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (usually used in integrated circuits and / or printed circuits. Fe), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), zinc ( Zn) or any metal such as Al-Ti, Al-Cu, Al-Si, Mo-W, Ti-W, etc., or titanium nitride, titanium silicide, tantalum nitride, tantalum silicide, Electrically active (ie, electrically active) such as molybdenum nitride, molybdenum silicide, tungsten nitride, tungsten silicide, cobalt silicide. It may include sexual) compounds. The gate metal layer 230 preferably has a normal thickness (for example, any value in the range of 50 nm to 5000 nm, preferably 80 nm to 3000 nm, more preferably 100 nm to 2500 nm).

  [0047] A resist layer may then be deposited on the gate metal layer 230. The resist layer may comprise a conventional photoresist or a thermoset resist and may be deposited or formed on the gate metal layer 230 by conventional methods (eg, spin coating or ink jet). As shown in FIG. 3B, the gate and the interconnector on the gate surface (not shown, but located outside the cell or active region of the transistor or other circuit component formed from the gate metal layer 230. In order to leave a patterned resist layer 235 that limits the shape of a conventional “landing pad”, a print / pattern by conventional photolithography or laser irradiation using a conventional developer. Lithography (eg, selectively illuminating a portion of a resist layer and then developing that portion [irradiated or unirradiated portions of the resist layer are removed depending on whether the resist is positive or negative) ]: See US patent application Ser. No. 11 / 203,563 filed on Aug. 11, 2005) obtain. Thereafter, the exposed gate metal 230 is etched and the patterned resist layer 235 is removed to provide an interface on the gate (eg, 232 and 234 shown in FIG. 3C) and the gate surface. A connector is formed. Alternatively, the gate layer 230 may be printed (eg, by inkjet) with a metal precursor ink followed by post-processing and / or metal precursor layers (direct conversion [eg, laser to metal Laser patterning, which may include both direct conversion] or indirect conversion [e.g., both cross-linked to a metal-containing species by a laser followed by annealing to form a conductive metal film]. Can be deposited and patterned.

Gate Insulator Formation [0048] Referring now to FIG. 3D, the gate insulator layer 240 (eg, including nitride and / or silicon oxide, aluminum, etc.) may be sputtered, CVD or other blanket. A deposition process forms on the gates and interconnectors 232 and 234 on the gate surface. The thickness of the gate insulator layer 240 is preferably in the range of 10 nm to 100 nm, preferably 10 nm to 50 nm, and more preferably 10 nm to 40 nm.

  [0049] Alternatively, the gate insulator layer 240 is printed on the interconnector 232 or 234 on the gate surface (eg, inkjet or other US patent application Ser. No. 10 / 885,283 and / or 11 / 104,375 specification). Appropriate layer properties and / or quality can be provided by printing multiple layers for post-processing. Such post processing may include oxidation of the printed insulator precursor material, densification of the insulating material, doping of the insulating material, and the like.

  [0050] As a further alternative, the gate insulator layer may be formed of metal on the gate surface by direct and conventional thermal or electrochemical oxidation (eg, anodic) of the gate metal 232 and / or 234. Structures 232 and / or 234 may be formed. One or more metal structures on the gate surface can be conventionally masked (with a photo or laser patternable resist) if it is not desired to form an insulator film thereon.

Formation of Semiconductor Layer [0051] Subsequently, as shown in FIG. 3D, the semiconductor layer 250 (which may include intrinsic Si or may be doped at a low concentration) may be sputtered, A coating or other gate blanket deposition (eg, by CVD) can be used to form on insulator layer 240. The thickness of the semiconductor layer 250 is preferably in the range of 80 nm to 2000 nm, preferably 100 nm to 1500 nm, and more preferably 150 nm to 1000 nm. The semiconductor layer 250 can be patterned by conventional photolithography or laser patterning (US patent application Ser. No. 11 / 203,563, filed Aug. 11, 2005), generally as a transistor channel. Can function.

  [0052] Optionally, the contact layer can be formed on the semiconductor (channel) layer by conventional masking and ion implantation, or a highly doped Si (source / drain) contact layer can be formed on the semiconductor ( Channel) layer 250 may be formed by sputtering, coating, or other blanket deposition (eg, by CVD). At that time, if the source / drain contact layers are blanket deposited, the source and drain contact structures 252a and 252b can be formed by conventional planarization (eg, polishing (chemical mechanical polishing) or resist and non-selective etchback). Silicon islands can be formed by conventional photolithography, laser irradiation of thermoset resists or printed (eg, ink jet) resists. After lithography patterning, it can be formed by dry or wet etching and removing the resist. The highly doped Si layer portion 255 on the gate may not be formed (eg, by not printing) or removed (eg, by photolithography and By etching or forming the layer 252 as an amorphous layer, the portion 252 is not irradiated with laser light (for example, for crystallization), and the portion not irradiated to the crystallized silicon is selectively etched. By removing).

  [0053] Alternatively, and as shown in FIG. 3E, the semiconductor layer 250 and the heavily doped Si contact layers 252a and 252b are made of semiconductor (eg, doped or undoped silane). Ink can be printed at locations corresponding to silicon islands: for example, February 27, 2004, September 24, 2004, September 24, 2004, October 1, 2004, October 8, 2004 and U.S. Patent Application Nos. 10 / 789,317, 10 / 950,373, 10 / 949,013, and 10 / filed on October 6, 2005, respectively. See U.S. Pat. Nos. 956,714 and 11 / 246,014. In general, the semiconductor layer 250 is printed before the heavily doped Si contact layers 252a and 252b are printed thereon (ie, without the portion of 255 located on the gate), followed by processing. Is made. After printing, the ink is dried, cured and / or heat treated to change the morphology of the ink (eg, at least partially crystallize the dried ink). It is also possible to activate part or all of the ink dopant by heat treatment or laser light irradiation. Printing not only improves the throughput by avoiding resist deposition and removal steps, but also allows the discontinuous source and drain contact layers 252a and 252b to be formed directly.

Formation of Intermediate Insulator Layer and Via [0054] It is known to form an insulator intermediate layer and a via from a semiconductor layer and a gate layer. For example, as shown in FIG. 3F, a relatively thick insulator layer 260 can be deposited on the semiconductor layer 250 (and on the contact layer 252 if present), and thereafter In addition, the via 262 can be formed by performing conventional photolithography, irradiation of a laser beam to a thermosetting resist, or lithography patterning of a printing resist, followed by normal insulator etching. Alternatively, patterned insulator layer 260 (ie, via 262 formed therein) may be formed by printing on semiconductor layer 250 (eg, as described above with respect to gate insulator layer 240, By inkjet method). The thickness of the intermediate insulator layer 260 is, for example, 0.5 μm or more, preferably 1 μm to 25 μm, more preferably 2 μm to 10 μm.

Source / Drain (S / D) and Intermediate Interconnector Formation [0055] If heavily doped semiconductor layers 252a and 252b are not formed (see, eg, FIG. 3E) The S / D layer 270 can be sputtered, coated or otherwise bracket deposited on the intermediate layer 260 and in the via 262. Typically, the S / D layer 270 includes a highly doped semiconductor material similar to the highly doped semiconductor layers 252a and 252b. The thickness of the S / D layer 270 may be in the range of, for example, 20 nm to 1000 nm, preferably 40 nm to 500 nm, and more preferably 50 nm to 100 nm.

  [0056] Referring to FIG. 3G, interconnector metal 280 may be sputtered, coated, or otherwise blanket deposited on S / D layer 270 (including bias 262 therein). The interconnector metal 280, like the gate metal 230, generally comprises a metal, an alloy or an electrically active composite, and its thickness may range from 0.5 μm to 10 μm, preferably 0.75 μm. It is ˜8 μm, more preferably 1 μm to 5 μm. Since interconnector metal 280 may contact a layer comprising silicon, interconnector metal 280 may further include a lower silicon barrier layer (eg, a metal nitride such as TiN).

  [0057] Range of S / D layer and interconnector metal by conventional photolithography, laser irradiation of thermoset resist or resist patterning by blanket deposited S / D layer and intermediate interconnector layer inkjet method The actual interconnector metal is formed by conventional metal (and semiconductor) etching. Similar bonds can be formed at desired locations along the gate metal, but locations other than the location of the silicon island 255 (eg, outside it) are preferred (see FIG. 3E).

  [0058] Alternatively, as shown in FIG. 3H, the S / D structures 272-278 are printed with a semiconductor (eg, doped or undoped silane) ink at locations corresponding to the locations of the vias 262. (See, for example, US patent application Ser. Nos. 10 / 885,283 and / or 11 / 104,375). If undoped ink is used, the process of forming S / D structures 272-278 may further include a doping step (eg, conventional ion implantation or ion shower doping). Thereafter, if necessary, in addition to the lower adhesive layer and / or silicon barrier layer, the interconnector metal structure 280 can be further formed as described above.

[0059] The manufacturing method according to this embodiment may further include the step of passivating the integrated circuit and / or the device after the formation of the integrated circuit is substantially completed (eg, integrated circuit). Etc., and forming a passivation or insulator layer on the interposer or part of the substrate to the extent that it can be exposed). The passivation layer generally suppresses or prevents the ingress of moisture, oxygen and / or other objects that can cause the degradation or failure of the integrated circuit or device, and provides considerable mechanical support to the device, especially during further processing. Can be granted. The passivation layer may be formed on the top surface of the integrated circuit and / or device, with one or more inorganic barrier layers such as polysiloxane, silicon and / or aluminum nitrides or oxides, and / or one or more perylenes, fluorides. It can be formed by coating with an organic barrier layer such as an organic polymer or other barrier material. Alternatively, the passivation layer may further comprise an insulator layer having a lower stress than the passivation layer at the bottom. For example, the insulator layer may include an oxide such as SiO ₂ (eg, CVDTEOS), USG, FSG, BPSG, etc., and the passivation layer may include silicon nitride or silicon oxynitride. Good. The thickness of the passivation layer is preferably slightly larger than the thickness of the insulator layer.

  [0060] At this point in the process (or at any point where material has been added to provide physical or mechanical support to the integrated circuit or device), the interposer's physical or mechanical support function is It is no longer necessary. Thus, the portion of the interposer that supports the integrated circuit may be removed entirely (eg, if the interposer is electrically insulating) or partially removed (eg, the interposer is conductive like a metal film) In some cases, the remainder of the interposer electrically connects the antenna, the one or more inductors, and / or the antenna and / or inductor to the via or [remaining] the interposer through an integrated circuit or a separate wire. To form a contact wire). In such a case, the final device, tag, or sensor interposer may be a dielectric layer or formed on the same surface as the surface on the metal film on which the integrated circuit is formed. An insulator may be used.

Hybrid integrated circuit [0061] As an alternative, the tag precursor (eg, the interposer of FIG. 2A with integrated circuit 110 and pads 132-134 thereon) may take a “hybrid” shape. This enables, for example, relatively inexpensive and easily manufactured and relatively functional organic (digital) logic and / or memory with RF “front ends” based on printed inorganic semiconductors and / or conductors. Circuits or conventional (digital) logic and / or memory circuits based on Si chips can be easily combined. The term “RF front end” refers to inductors, capacitors, diodes, and FETs that operate at and / or modulate the carrier frequency and refer to “IC” in FIGS. Indicated by area 110. These components (and circuit blocks that substantially include or comprise the components) are generally analog in nature (eg, they function or operate in an analog fashion or continuously) and are relatively A device with higher performance than a slow digital logic circuit may be required.

  [0062] This “hybrid” formula can be particularly effectively combined in organic circuits and can be somewhat advantageous in terms of materials and / or manufacturing costs. Organic circuits are suitable for circuit controllers, logic and / or memory sections and often operate at frequencies well below the RF frequency (eg, at 1 MHz or less). However, organic FET circuits may not operate effectively at a carrier frequency (eg, about 13.56 MHz or higher). For example, there are several proven difficulties in the construction and manufacture of diodes based on organic materials with appropriate rectification, leakage, and breakdown characteristics. It may also be difficult to achieve effective organic modulation FETs or organic clock related FETs that operate at the carrier RF frequency. In this case, it can be processed directly on a hybrid circuit and RF front end (acting as an underlying substrate or carrier) with an RF front end that is disclosed herein and can be processed from high performance printed minerals. Organic logic and / or memory circuits can be manufactured.

  [0063] Thus, the present invention comprises: (1) forming a bottom layer of an integrated circuit on a first surface of an interposer; and (2) a plurality of successive integrated circuits on the bottom layer of the integrated circuit. The present invention relates to a method for manufacturing a recognition device or a tag, including a step of forming a layer, and (3) connecting a layer having a conductive function to the second surface of the interposer opposite to the first surface. According to the present invention, an RFID (or EAS) tag including a substrate, an RF front end or a subset of the RF front end, and a logic circuit can be manufactured by an inexpensive process.

Exemplary Methods for Reading RFID Tags [0064] The present invention includes (a) electromagnetic radiation detectable by the device (preferably at a frequency corresponding to an integral multiple or fraction of an applied electromagnetic field). Generating or inducing in the apparatus sufficient current to radiate the light; and (b) detecting detectable electromagnetic radiation (optional, but (c) detectable electromagnetic And a method for detecting an article or object in a detection area further comprising the step of processing information transferred by radiation). Generally speaking, when the device is in a detection region comprised of an oscillating electromagnetic field, sufficient current and voltage are induced in the device to provide electromagnetic radiation that the device can detect. The oscillating electromagnetic field is generated or generated by conventional EAS equipment or systems and / or RFID equipment or systems. As described above, the usage method according to the present embodiment is detected so that (d) the step of transmitting or transferring information from the device (or sensor) to the reading device is reversed or (before step (a)). The apparatus according to the present embodiment is attached to or pasted on an article or object (for example, an ID card, a packaging container for an article to be shipped, etc.), or the article or object is included in the present invention or Therefore, it may further include a step of packaging.

  [0065] The tag according to the present embodiment is designed such that at least a portion of the electrical recognition system and / or security system that detects an obstruction in the RF electromagnetic field operates. In such electrical systems, the control area defined by the entrance through which goods are to be passed when leaving a controlled premises (eg, retail, library, etc.), or read or recognized Thus, an electromagnetic field is formed in the space where the article is placed. A tag having a resonant circuit is attached to each article, and in the controlled area, the presence of the tag circuit is sensed by a receiving system that senses the tag and processes information obtained from the tag (e.g., authorized). Or whether the item in the container labeled with the tag is identified). Most tags that operate according to such rules are single use or single use tags and are therefore designed to be produced in large quantities and at low cost.

  [0066] Alternatively, the tag according to this embodiment may take the form of a sensor whose characteristics or properties of its RF signal modulation can be changed by changing the properties or properties of the attached object or article. For example, the sensor according to this embodiment may be attached to a stainless steel (or other metal) object, structure or surface. When properties of an object, structure or surface change (eg, steel oxidizes, metals with electromagnetic properties are magnetized or threshold current is reduced, or the temperature of the object or surface [regardless of composition] The characteristic or nature of the RF signal emitted, reflected or modulated by the sensor will also change to a detectable level (which varies by a predetermined difference or threshold amount).

[0067] The tag according to this embodiment is utilized (and required) in any commercial EAS application field and / or RFID tag application field, basically in the frequency range used for such application field. And / or reuse if possible). For example, a tag according to this embodiment may be used in the field and / or range at the frequencies shown in the following table.

  [0068] As described above, the present invention relates to a product monitoring technique in which electromagnetic waves are transferred to an area of a premises protected at a fundamental frequency (for example, 13.56 MHz). The presence of non-authenticated items is detected by the reception or detection of typical radiation. This emitted electromagnetic radiation is subject to this device being attached or embedded in an article in a situation where it is not deactivated or modulated in order to legally remove the label or film on the protected premises. A radio wave having a second or subsequent harmonic frequency re-radiated from a sensor emitter component, label, or film comprising:

Conclusion / Summary [0069] Thus, the present invention provides a MOS recognition device including an integrated interposer, a method for manufacturing the same, and a method for using the same. The MOS recognition device is generally provided on (a) an interposer, (b) an antenna and / or inductor on the first surface of the interposer, and (c) a second surface of the interposer opposite to the first surface. Integrated circuit having a bottom layer in physical contact (and electrically in various embodiments) with the second surface of the interposer. The manufacturing method generally includes (1) forming a bottom layer of an integrated circuit on a first surface of an interposer, and (2) a plurality of layers following the integrated circuit on the bottom layer of the integrated circuit. And (3) connecting a conductive layer to the second surface of the interposer opposite the first surface. The method of use generally comprises the steps of (i) generating or inducing current in the device sufficient to radiate a detectable electromagnetic signal; and (ii) detectable electromagnetic. Detecting the irradiance, optionally (iii) processing the information transferred by the detectable electromagnetic radiation, and (iv) information from the device (or sensor) back to the reader. Transmitting or transferring. The present invention provides an inexpensive RF tag and / or RFID tag capable of standard application and operation using conventional RF equipment or systems, RFID equipment or systems, and / or EAS equipment or systems. Circuits on an interposer that not only reduces the manufacturing cost of active electronic components, but also reduces the number of costly and low-throughput connection steps and is relatively inexpensive and relatively low accuracy attached to the inductor / carrier An inexpensive tag can be manufactured by printing directly or by other methods.

  [0070] The novel components of the present invention include (i) direct integration of the steps of manufacturing / processing the circuit on the interposer substrate, and / or (ii) printing directly on the interposer carrier, after which Low cost connection to an inductor formed on or from an inexpensive substrate material such as a metal film may be included. In one embodiment, the inductor has a larger area (and thus can have more than one dimension) than the interposer. Such direct manufacturing / processing steps can be shared with web processing, continuous processing, roll-to-roll processing or sheet processing, and conventional flexible and thin RF labels, and can improve throughput in the tag manufacturing process. . Because the resolution of the pick-and-place process for assembling the interposer and inductor / antenna is low, manufacturing circuit components directly on the interposer allows for inexpensive manufacturing. According to the present invention, it is possible to use an effective / inexpensive device substrate material that is thermally and chemically compatible with RFID manufacturing and / or EAS tag manufacturing or provides suitable barrier properties, When used on an interposer board for the entire tag, it may be too expensive.

  [0071] The present invention has been described and explained based on preferred embodiments. However, the present invention is not limited or limited to the above-described embodiments, and various changes or modifications can be made without departing from the gist of the present invention. This embodiment illustrates the principles of the present invention and the practical application of the present invention so that various modifications can be optimally implemented by those skilled in the art to suit the present invention and the intended specific use. It has been selected and described for optimal explanation. It is intended that the scope of the invention be defined by this and the equivalent claims.

It is a figure which shows each step of the manufacturing method of the conventional RFID tag including the process of attaching the conventional semiconductor chip on an interposer. FIG. 2 schematically illustrates important steps of a method of manufacturing an RFID tag / device having an integrated interposer according to a preferred embodiment. FIG. 6 schematically illustrates important steps for manufacturing an integrated circuit on an interposer substrate of an RFID tag / device according to a preferred embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Tag precursor, 110 ... Integrated circuit, 132 ... Interposer, 134, 136 ... Pad, 150 ... Applicator sheet (applicator sheet), 152 ... Antenna / inductor, 210 ... Interposer, 220a, 220b ... Barrier material layer, 230 ... Gate metal layer, 232, 234 ... Interconnector, 235 ... Resist layer, 250 ... Semiconductor layer, 252a, 252b ... Si contact layer, 260 ... Intermediate layer, 262 ... Via, 270 ... S / D layer, 272,274 276, 278 ... S / D structure, 280 ... interconnector metal structure.

Claims (20)

a) an interposer;
b) an antenna and / or inductor on the interposer;
c) an integrated circuit provided on the interposer at a position other than the antenna and / or the inductor, the integrated circuit having a lowermost layer in physical contact with the surface of the interposer;
A recognition device comprising:   The recognition apparatus according to claim 1, wherein the integrated circuit includes one or more printed layers.   The recognition apparatus according to claim 2, wherein the one or more printed layers include a semiconductor layer.   The recognition apparatus according to claim 2, further comprising a gate metal layer and a gate insulator layer between the gate metal layer and the semiconductor layer.   The recognition device according to claim 4, wherein the integrated circuit further comprises a source and a drain.   The recognition device according to claim 5, wherein the integrated circuit further includes a plurality of metal conductors electrically connected to the gate metal layer, the source terminal, and the drain terminal.   The recognition apparatus according to claim 6, wherein the integrated circuit further includes an intermediate insulator layer between the metal conductor and the semiconductor layer.   The recognition apparatus according to claim 2, wherein the one or more printed layers include at least one of a gate metal layer, an intermediate insulator layer, and an interconnector metal layer.   The recognition device of claim 1, wherein the interposer comprises polyimide, glass / polymer laminate, high temperature polymer or metal film. a) forming a bottom layer of an integrated circuit on the surface of the interposer;
b) forming successive layers of the integrated circuit on the bottom layer of the integrated circuit;
c) connecting a conductive layer to the interposer;
A method for manufacturing a recognition device including:   The method for manufacturing a recognition apparatus according to claim 10, wherein the step of forming the bottom layer of the integrated circuit on the surface of the interposer includes a step of printing the bottom layer of the integrated circuit.   The recognition according to claim 10, wherein forming a plurality of successive layers of the integrated circuit on a bottom layer of the integrated circuit includes printing one or more layers of the successive layers. Device manufacturing method.   The method for manufacturing a recognition device according to claim 12, wherein at least one of the plurality of subsequent layers includes a semiconductor layer.   11. The method of manufacturing a recognition device according to claim 10, wherein the successive layers of the integrated circuit comprise a source / drain layer, a gate insulator layer, a gate metal layer, and an interconnector / metallization. .   The method for manufacturing a recognition device according to claim 10, wherein at least one of the lowermost layer and the plurality of successive layers of the integrated circuit includes a channel layer of a transistor. Forming a bottom layer of an integrated circuit on the surface of the interposer includes printing or displaying the bottom layer;
11. The step of forming a plurality of successive layers of an integrated circuit on a bottom layer of the integrated circuit includes the step of printing or display processing at least one of the successive layers. The manufacturing method of the recognition apparatus of description.   The method for manufacturing a recognition apparatus according to claim 10, wherein the interposer includes an insulator.   The method for manufacturing a recognition device according to claim 10, wherein the conductive layer includes a metal film.   The method of manufacturing a recognition device according to claim 18, further comprising etching the metal film to form an antenna and / or an inductor. a) generating or inducing in the recognition device of claim 1 sufficient current to radiate, reflect or modulate a detectable electromagnetic signal;
b) detecting the detectable electromagnetic signal;
A method for reading a recognition device comprising: