TWI381647B - A digital phase locked loop with self-calibration - Google Patents

Description

Digital self-correcting phase-locked loop

The present invention relates to an electronic circuit, and more particularly to a digital self-correcting phase-locked loop that uses a digital loop filter in conjunction with a low-power digitally controlled oscillator to allow the entire loop to be fully digitized and easier to operate. In the low-voltage working environment, and the overall power can be reduced, in addition, the digital control oscillator gain self-correction unit is added to the system to correct the characteristics of the digitally controlled oscillator to improve the stability of the overall loop. .

The trend of telecommunications liberalization has made wireless communication highly valued. The wireless communication RF module includes a low-noise amplifier, a bandpass filter, a mixer, a voltage oscillator, a frequency synthesizer, and a frequency synthesizer. Power amplifier. In the transmitter, the frequency synthesizer is one of the key components. This component is often used with a phase-looked loop. The analogy is used to realize the phase-locked loop, which is more susceptible to process variation, and as the fabrication progresses, the voltage provided by it decreases, which makes the analog circuit more sensitive and increases the design difficulty. In a general phase-locked loop, the oscillator and the frequency divider account for a significant proportion of the overall power consumption. However, for the FM oscillator, if the voltage or current supplied is reduced, the gain of the oscillator will increase the available voltage or current, which will increase the sensitivity of the oscillator and be susceptible to noise interference.

In order to reduce the power of the phase-locked loop, it is common practice to reduce the output frequency of the oscillator, and then use a phase interpolator or a frequency multiplier to generate an output frequency. However, if the phase of the output of the voltage controlled oscillator is dithered, it will affect the phase noise of the last high frequency signal of the phase locked loop. And if the frequency multiplier is used to generate a high frequency signal, the selection of the frequency multiplier is limited, and it is difficult to make adjustment. In the case of low power, the range of available voltage or current of the phase-locked loop is reduced, the gain of the oscillator is increased, and it is susceptible to noise, which deteriorates the phase noise of the output signal.

A conventional technique can be found in U.S. Patent No. 7,088,154 issued to Hung Cai Ngo, entitled "Method and arrangements for a Low Power Phase-Locked Loop", which discloses a By using a multi-phase voltage controlled oscillator, the output frequency of the voltage controlled oscillator can be reduced, and a high frequency output signal can be generated by a pulse generator using different phases. Although this method can reduce the power of the voltage controlled oscillator, if the output phase of the multi-phase voltage controlled oscillator is jittery, it will directly react to the high frequency output signal, and the phase noise of the high frequency output signal will be poor.

In order to solve the above problems, it is necessary to provide a new phase locked loop to overcome the disadvantages of the prior art. The job is the reason, the applicant is carefully tested and researched, and a perseverance spirit, finally developed a digital self-correcting phase-locked loop. It uses a digital loop filter and a low-power digitally controlled oscillator to make the entire circuit fully digitized, easier to operate in a low-voltage operating environment, and the overall power can be reduced to save wafer area. The goal. In addition, the present invention also adds a digital control oscillator gain self-correction unit to the system to correct the characteristics of the digitally controlled oscillator to improve the stability of the overall loop.

In view of the above problems, the present invention provides a digital self-correcting phase-locked loop that can be applied to a wireless radio frequency transmission interface or a high-speed serial transmission interface.

It is an object of the present invention to provide a digital self-correcting phase-locked loop that allows the entire circuit to be fully digitized, saves power and saves wafer area, and enhances overall circuit stability.

To achieve the above object, the present invention provides a digital self-correcting phase-locked loop having an input terminal including a digitally controlled oscillator; a phase detector; a frequency divider; a digital loop filter; a digitally controlled oscillator gain self-correcting unit; and a dynamic loop gain controller. The digitally controlled oscillator is electrically connected to an adder for providing a signal of frequency f _OUT and a circuit gain K _VCO '; the frequency divider is electrically connected to the digitally controlled oscillator, Dividing the signal whose frequency is f _OUT output by the digital control oscillator by a positive integer N and outputting a signal having a frequency of f _OUT /N; the phase detector is configured to receive the frequency divider The signal with the output frequency f _OUT /N is phase-compared with the signal from the input terminal with a frequency of f _REF to provide a correction signal PDOUT; the digital loop filter is electrically connected to the phase detector. Receiving the correction signal PDOUT and adjusting an output signal of the digitally controlled oscillator; the multiplexer is electrically connected to the digital loop filter for receiving a plurality of control codes (Ctrl) and the digital loop a plurality of digital code outputs by the filter; the digitally controlled oscillator gain self-correcting unit is electrically connected to the digitally controlled oscillator for providing the digitally controlled oscillator, a gain correction signal K, and the adder Offset correction system code signal L; and dynamic loop gain controller, electronically connected to the digital loop filter for controlling the internal parameters of the digital loop filter.

According to a feature of the invention, the digitally controlled oscillator further comprises: a sum and a difference modulator and a frequency modulation oscillator. And the difference modulator receives the plurality of digit codes and the gain correction signal K; and the frequency modulation oscillator is electrically connected to the sum and difference modulator, and is adjusted by the sum and the difference modulator to provide This digitally controls the output signal of the oscillator.

By means of a digital self-correcting phase-locked loop of the invention, the entire circuit can be fully digitized, easier to operate in a low voltage working environment, and the overall power can be reduced to achieve the goal of saving wafer area. In addition, the present invention adds a digitally controlled oscillator gain self-correction unit to the system to correct the characteristics of the digitally controlled oscillator to enhance the stability of the overall loop.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

While the invention may be embodied in various forms, the embodiments illustrated in the drawings It is not intended to limit the invention to the particular embodiments illustrated and/or described.

Please refer to the first figure, which illustrates a preferred embodiment of the digital self-correcting phase-locked loop block diagram of the present invention. According to an embodiment of the invention, a digital self-correcting phase-locked loop 100 has an input terminal 110, which mainly includes a digitally controlled oscillator 200; a phase detector 120; a frequency divider 150; Loop filter 140; a multiplexer 160; a digitally controlled oscillator gain self-correcting unit 180 and a dynamic loop gain controller 130. The input terminal 110 is configured to provide a signal 190 with a frequency of f _REF to the phase detector 120. The digitally controlled oscillator 200 is electrically coupled to an adder 170 for providing a signal 196 having a frequency of f _OUT and a circuit gain K _VCO '195. The frequency divider 150 is electrically connected to the output terminal 111 for providing a signal 196 with a frequency f _OUT of the output terminal 111 divided by a positive integer N and outputting a frequency of f _OUT /N Signal. The phase detector 120 is electrically connected to the input terminal 110 and the frequency divider output 198 for receiving a phase difference between the signal having the frequency f _OUT /N and the signal 190 having the frequency f _REF . A correction signal PDOUT191 is provided. The digital loop filter 140 is electrically connected to the phase detector 120 for receiving the correction signal PDOUT 191 and adjusting the output signal of the digitally controlled oscillator 200. The multiplexer 160 is electrically connected to the digital loop filter 140 for receiving a plurality of control codes (Ctrl) and a plurality of digital code outputs by the digital loop filter 140. The digitally controlled oscillator gain self-correction unit 180 is electrically coupled to the digitally controlled oscillator 200 for providing the digitally controlled oscillator 200 with a gain correction signal K 194 and the adder 170 for control code offset correction. Signal L 193. The dynamic loop gain controller 130 is electrically connected to the digital loop filter 140 for controlling parameters inside the digital loop filter 140.

The digital self-correcting phase-locked loop 100 operates as follows: initially, the digitally controlled oscillator 200 outputs a signal 196 having a frequency of f _{OUT, and} the signal is fed back to the phase via the frequency divider (1/N) 150. a phase detector 120 for comparing the phase detector 120 will send a correction signal PDOUT 191 after the digital loop filter 140 adjusts the digital control oscillator 200, when the stable output frequency f _OUT of the frequency signal 196 It is N times the signal 190 of f _REF . In order to increase the speed of the lock, the digital code 210 corresponding to the central frequency is first sent to the digitally controlled oscillator 200 as an initial value (Dinit), and the dynamic loop gain controller is utilized during the locking process. 130 controls the parameters internal to the digital loop filter 140.

In order to clearly disclose the structure of the digitally controlled oscillator 200, please refer to FIG. 2, which is a block diagram of the digitally controlled oscillator 200 in FIG. The digitally controlled oscillator 200 further includes a sum and difference modulator 220 and a frequency modulation oscillator 230. The sum and difference converter 220 receives the plurality of digit codes and the gain correction signal K194. The frequency modulation oscillator 230 is electrically connected to the sum and difference modulator 220, and is adjusted by the sum and difference modulator 220 to provide an output signal of the digitally controlled oscillator 230. The gain correction signal K 194 can be used to generate the gain Kvco required for loop stabilization, but to multiply a gain, an additional multiplier is required, but the multiplier consumes a large amount of power and area. It is known that the sum and difference modulator 220 has a function of improving the resolution. If the gain reciprocal is generated, the gain correction signal K 194 (K=Kvco'/Kvco) is sent to the difference modulator 220, and the change and the difference modulation are changed. The number of bits of the device 220 can be changed by the equivalent of the division ratio of the difference modulator 220 to obtain a multiplication effect. If the gain correction signal K 194 of the digitally controlled oscillator 200 is used in this manner, the characteristics of the overall circuit can be corrected back to the originally designed transfer function without increasing the area and power consumption of the entire wafer.

As the process evolves, the available voltage range is getting lower and lower, causing the gain of the frequency-modulated oscillator 230 to rise, so that the sensitivity of the frequency-modulated oscillator 230 is increased. In order to reduce the sensitivity of the frequency modulation oscillator 230, the sum and difference modulator 220 is added, and the transmission and difference modulator 220 accurately adjusts the amount of change of the output frequency of the frequency modulation oscillator 230, so that the frequency modulation oscillator 230 can be lowered. Sensitivity to noise, and the overall circuit can operate at a lower supply voltage, achieving low power.

In general, the digitally controlled oscillator 200 is susceptible to process variations, voltage variations, and temperature variations, and its performance is somewhat different from that of the original design, resulting in the characteristics of the entire digital self-correcting phase-locked loop 100 and the original design. different. In order to solve this problem, before the digital self-correcting phase-locked loop 100 starts operating, some control code (Ctrl) 192 is sent to perform the digital control oscillator gain correction operation, and then the lock is started after the correction to compensate for the environmental factors. This digitally controls the variation of the characteristics of the oscillator 200.

When the digitally controlled oscillator gain self-correction unit 180 is activated, two sets of control codes 192 are respectively sent to D1 and D2 through the multiplexer 160 to be sent to the digitally controlled oscillator 200, and self-corrected by the digitally controlled oscillator gain. The unit 180 detects that the frequency 196 output by the digitally controlled oscillator 200 when the control code 192 is D1 and D2 is fout1 and fout2, respectively. From the above information, the circuit gain K _VCO '195 of the actual digitally controlled oscillator 200 can be obtained. Kvco' = (fout2-fout1) / (D2-D1). It is known that the digital control oscillator 200 required to stabilize the loop is Kvco. If the gain Kvco' of the actual digitally controlled oscillator 200 is multiplied by a gain of Kvco/Kvco', the characteristics of the overall loop are the same as the design. .

In addition to the digital control oscillator 200 gain will be different from the original design after implementation, the control code 192 of the digitally controlled oscillator 200 will also have a certain deviation from the frequency range corresponding to the original design. Since the loop is initially operated in this example, an initial value (Dinit) is input through the control code 192 to the digital code 210 control code 192 to cause the digitally controlled oscillator 200 to output as the center frequency, but due to the aforementioned effects, After the wafer is fabricated, the factor bit controls the change in the frequency range of the signal 196 of f _OUT output by the oscillator 200, causing the actual frequency corresponding to the initial value (Dinit) control code 192 to be not the target center frequency fout3. Therefore, in addition to the gain self-correction, the offset between the actual output frequency corresponding to the initial value (Dinit) of the control code 192 and the ideal output frequency also needs to be corrected.

Next, the generation process of the offset correction signal L193 is described. After the gain correction is performed, a set of control codes 192 is sent to D3 to the digitally controlled oscillator 200, and the actual output frequency is measured by the digitally controlled oscillator gain self-correction unit 180. Fout3'. It is known that the relationship between the output frequency fout3 corresponding to D3 and the actually obtained frequency fout3' is as shown in the following equations (1) and (2), where finit is the initial frequency when the control code 192 is 0, The shift correction signal L193 is an offset of the control code 192.

Fout3=D3×Kvco+finit (1)

Fout3'=D3×Kvco+finit'=(D3+L)×Kvco+finit (2)

From the above relationship, the offset correction signal L193 of the control code 192 can be reversed as shown in the following equation (3). The offset correction signal L193 is applied to the multiplexer output 197 by the adder 170 to offset the offset of the initial value (Dinit), and the result is sent to the input 210 of the difference modulator 220. The frequency shift of the digitally controlled oscillator 200 due to the environment can be corrected.

L=(fout3'-fout3)/Kvco (3)

After the above procedure is completed, the digital self-correcting phase-locked loop 100 begins to lock, and the characteristics of the factor-controlled oscillator 200 have been corrected back to the original design, thereby improving the stability and accuracy of the entire loop, thereby The locked feature is more versatile and more accurate. In this example, the digitally controlled oscillator 200 can adjust very fine frequency variations such that the power of the digitally controlled oscillator 200 can be reduced, and with this method the sensitivity can be reduced and operated in a lower voltage environment.

It should be noted that the transistor form of the above active circuit can be realized by a 0.18μm, 0.13μm, 0.09μm, 0.045μm or more advanced process, and the transistor form can be realized in the following types: bi-carrier transistor (BJT), heterogeneous Junction double carrier transistor (HBT), high electron mobility transistor (HEMT), pseudo high electron mobility transistor (PHEMT), complementary metal oxide semiconducting field effect transistor (CMOS) and side diffusion Metal oxidized semiconductive field effect transistor (LDMOS). The semiconductor substrate material for the transistor includes germanium, germanium on insulator (SOI), germanium compound (SiGe), gallium arsenide (GaAs), indium phosphide (InP), and germanium-carbon compound.

In summary, a digital self-correcting phase-locked loop 100 according to the present invention utilizes a digital loop filter in conjunction with a low-power digitally controlled oscillator to enable full digitization of the entire loop, making it easier to operate at low voltages. Under the working environment, the overall power can be reduced to save the wafer use area, and the oscillator gain self-correction unit is used to correct the characteristics of the digitally controlled oscillator, which enhances the stability of the overall loop. Therefore, the present invention can be widely applied to mobile or wireless network systems.

While the present invention has been disclosed in its preferred embodiments, it is not intended to limit the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. The spirit of this invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . Digital self-correcting phase-locked loop

110. . . Input

111. . . Output

120. . . Phase detector

130. . . Dynamic loop gain controller

140. . . Digital loop filter

150. . . Frequency divider (1/N)

160. . . Multiplexer

170. . . Adder

180. . . Digitally controlled oscillator gain self-correction unit

190. . . Signal 191 correction signal PDOUT with frequency f _REF

192. . . Control code (Ctrl)

193. . . Offset correction signal L

194. . . Gain correction signal K

195. . . Circuit gain K _VCO '

196. . . Signal with frequency f _OUT

197. . . Multiplexer output

198. . . Frequency divider output

200. . . Digitally controlled oscillator

210. . . Digital code

220. . . And difference modulator

230. . . Frequency modulated oscillator

The above and other objects, features, and advantages of the present invention will become more apparent from the <RTIgt;

1 is a block diagram of a digital self-correcting phase-locked loop of the present invention;

Figure 2 shows a block diagram of the digitally controlled oscillator in Figure 1.

100. . . Digital self-correcting phase-locked loop

110. . . Input

111. . . Output

120. . . Phase detector

130. . . Dynamic loop gain controller

140. . . Digital loop filter

150. . . Frequency divider (1/N)

160. . . Multiplexer

170. . . Adder

180. . . Digitally controlled oscillator gain self-correction unit

190. . . f _REF signal

191. . . Correction signal PDOUT

192. . . Control code (Ctrl)

193. . . Offset correction signal L

194. . . Gain correction signal K

195. . . Circuit gain K _VCO '

196. . . f _OUT signal

197. . . Multiplexer output

198. . . Frequency divider output

200. . . Digitally controlled oscillator

Claims (6)

A digital self-correcting phase-locked loop having an input terminal comprising: a digitally controlled oscillator electrically coupled to an adder for providing a signal having a frequency of f _OUT and a circuit gain K _VCO '; a frequency divider is electrically connected to the digitally controlled oscillator for dividing the signal of the digital control oscillator output frequency f _OUT by a positive integer N and outputting a frequency of f _OUT / a signal of a phase detector is electrically connected to the input terminal for receiving the signal that the frequency divider outputs the frequency f _OUT /N and the signal from the input terminal with a frequency of f _REF Phase comparison to provide a correction signal PDOUT; a digital loop filter electrically coupled to the phase detector for receiving the correction signal PDOUT and adjusting an output signal of the digitally controlled oscillator; a multiplexer Electrically connected to the digital loop filter for receiving a plurality of control codes (Ctrl) and a plurality of digital code outputs of the digital loop filter; a digitally controlled oscillator gain self-correcting unit, electrically connected Connected to the digitally controlled oscillator for providing the digitally controlled oscillator a gain correction signal K and the adder-control code offset correction signal L; and a dynamic loop gain controller electrically coupled to the digital A loop filter that controls the parameters inside the digital loop filter. The digital self-correcting phase-locked loop of claim 1, wherein the digitally controlled oscillator further comprises: a sum and a difference modulator, receiving the plurality of digit codes and the gain correction signal K; and a frequency modulation The oscillator is electrically connected to the sum and the difference modulator, and is adjusted by the sum and the difference modulator to provide an output signal of the digitally controlled oscillator. For example, the digital self-correcting phase-locked loop described in claim 2, wherein the sum and the difference modulator can change the equivalent division ratio of the sum and the difference modulator by changing the number of bits thereof. The digital self-correcting phase-locked loop of claim 1, wherein the digital control oscillator gain self-correction unit of the gain correction signal K is used to correct the circuit gain of the digitally controlled oscillator K _VCO 'Make it the same as the gain K _VCO required for the original design. The digital self-correcting phase-locked loop of claim 1, wherein the digital control oscillator gain self-correction unit of the control code offset correction signal L is used to correct the plurality of control codes, and further Correct the frequency drift of the digital control oscillator output frequency f _OUT signal. The digital self-correcting phase-locked loop of claim 1, wherein the digital self-correcting phase-locked loop can be implemented by a 0.18 μm, 0.13 μm, 0.09 μm, 0.045 μm or more advanced process.