JP2011023938A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make precise process calibration for a short time without increasing a circuit area required for a process monitor. <P>SOLUTION: After a digital control oscillator 38 selects an arbitrary oscillation band, a control section 25 switches a switch 44 for a signal of a TDC 41 to be inputted to a process monitor control section 40. The TDC 41 converts a period between a rising edge of a signal VREF and a rising edge of the signal VPRE, closest to it, to a digital value, and a period between a rising edge of the signal VREF and a rising edge of the signal VPRE, second closest to it, to another digital value, and calculates a difference between the digital values. The process monitor control section 40 refers to a look-up table, and compares the calculated value with a preset expected value to determine a process value. The process values are outputted, respectively, to an adjustment control section 26 as a process signal, to perform process calibration. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a calibration technique using a process monitor, and more particularly to a technique effective for adjusting electrical characteristics in a semiconductor integrated circuit device having an ADPLL (All Digital Phase-Locked Loop).

  High-frequency semiconductor integrated circuit devices used for wireless communications such as cellular phones and wireless local area networks (LAN) are still expected to grow at a high rate. In recent years, the development flow of a semiconductor integrated circuit device for high frequency processing has progressed to one chip with a semiconductor integrated circuit device for baseband processing, and a demand for higher integration by a miniaturization process has increased.

  However, there are still many analog circuits that cannot be replaced with digital circuits, and such circuits need to be designed in consideration of variations in threshold voltage Vth of MOS transistors.

  Some of these types of semiconductor integrated circuit devices include a process monitor circuit. Each process circuit monitors signal amplitude and bias voltage fluctuations that change as the threshold voltage Vth decreases by the process monitor circuit. A device that corrects characteristics in an analog manner is known.

  As a process monitoring technique for the threshold voltage Vth in the MOS transistor, for example, it is composed of a ring oscillator, a counter, and a comparator whose frequency changes depending on the process, and the frequency is counted and compared with an expected value. A device that detects variations and adjusts the timing of each circuit according to the result is known (see, for example, Patent Document 1).

US Pat. No. 6,853,177

  However, the present inventor has found that the timing adjustment technique using the process monitor circuit as described above has the following problems.

  That is, the process monitor circuit is an analog circuit, and a filter may be added so that the noise of the monitor circuit itself does not affect the main circuit, which is not suitable for miniaturization.

  In addition, since it is necessary to optimize the monitoring method and the correction method together, it takes time and trial and error, which is a big problem in development using a fine process with a short design period and high cost. .

  Furthermore, the technique of Patent Document 1 requires a new oscillator (ring oscillator or the like), which causes a new area increase and makes it difficult to reduce the size of the semiconductor integrated circuit device.

  An object of the present invention is to provide a technique capable of performing highly accurate process calibration in a short time without increasing a circuit area necessary for process monitoring.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a semiconductor integrated circuit device for RF processing having a reception system circuit and a transmission system circuit, which detects a process variation from a process monitor signal and constitutes a reception system circuit and a transmission system circuit. Process monitor that adjusts the electrical characteristics in the functional block of the process, and a clock signal used when the reception system circuit demodulates the reception signal or the transmission system circuit modulates the transmission signal, and process monitor processing And an ADPLL that outputs a process monitor signal based on the control signal.

  Further, according to the present invention, the process monitor unit detects a process variation from a process monitor signal output from the ADPLL, determines a process value for controlling the process variation, and outputs the process value as a process signal; Based on the process signal output from the process monitor control unit and provided in each of the control blocks that output the control signal to the ADPLL and the function blocks constituting the reception system circuit and the transmission system circuit during the process monitor process. And an adjustment control unit that outputs a process control signal for optimizing the electrical characteristics to each functional block.

  Furthermore, the outline | summary of the other invention of this application is shown briefly.

  In the present invention, the process monitor unit detects a process variation from a temperature sensor that detects a temperature during the process monitor process, a process monitor signal output from the ADPLL, and a temperature detected by the temperature sensor, and the process variation is detected. A process monitor control unit that determines a process value to be controlled and outputs it as a process signal; a control unit that outputs a control signal to the ADPLL during process monitor processing; and each of the reception system circuit and transmission system circuit Each of the functional blocks includes an adjustment control unit that outputs a process control signal for optimizing electrical characteristics to the functional block based on the process signal output from the process monitor control unit.

  Further, according to the present invention, the ADPLL outputs from the TDC based on the TDC that converts the phase difference between the clock signal generated by the ADPLL and the reference clock signal into a digital value, and the control signal output from the control unit. And a switching unit for switching the digital value to be output as a process monitor signal to the process monitor control unit.

  Further, according to the present invention, the process monitor control unit includes a first look-up table for converting the process monitor signal into a process signal, and the process monitor signal output from the ADPLL is converted based on the first look-up table. The adjustment control unit includes a second look-up table that converts the process signal into a process control signal, and the process signal output from the process monitor control unit based on the second look-up table. Is converted into a process control signal for adjusting the electrical characteristics of each functional block and set in an adjustment register provided in the functional block.

  In the present invention, the process monitor control unit includes a first look-up table for converting a process monitor signal set for each arbitrary temperature range into a process signal, and based on the first look-up table. The process monitor signal output from the ADPLL corresponding to the temperature range detected by the temperature sensor is converted into a process signal, and the adjustment control unit includes a second lookup table that converts the process signal into a process control signal, Based on the second look-up table, the process signal output from the process monitor control unit is converted into a process control signal for adjusting the electrical characteristics of each functional block, and set in an adjustment register provided in the functional block. To do.

  Further, according to the present invention, the ADPLL includes a delay lock loop that generates a first signal having an arbitrary phase difference and a second signal, and the TDC includes a first signal generated by the delay lock loop and The phase difference with the second signal is converted into a digital value.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) A highly accurate process monitor can be performed without increasing the circuit area.

  (2) According to the above (1), it is possible to provide a low-cost and highly reliable semiconductor integrated circuit device without increasing the chip area.

It is a block diagram which shows an example of the RF process part by Embodiment 1 of this invention. It is a block diagram which shows an example of a structure in the transmission / reception ADPLL provided in the RF process part of FIG. It is a block diagram which shows the structural example of TDC provided in ADPLL of FIG. It is a timing chart of each part signal in TDC of FIG. It is a block diagram which shows an example of the counter provided in transmission / reception ADPLL of FIG. 6 is a timing chart in the counter of FIG. It is a schematic diagram which shows the process of the frequency lock in ADPLL of FIG. 3 is a flowchart showing an example of an operation in the transmission / reception ADPLL of FIG. 2. It is explanatory drawing which shows an example of the lookup table stored in the lookup table storage part of the process monitor control part provided in ADPLL of FIG. It is explanatory drawing which shows the process dependence of the resolution in TDC of FIG. It is explanatory drawing which shows an example of the digital value at the time of measuring the period of a reference clock signal using TDC of FIG. It is explanatory drawing which shows an example of the look-up table with which the adjustment control part of FIG. 2 was equipped. It is explanatory drawing which shows an example of the lookup table with which the adjustment control part following FIG. 12 was equipped. FIG. 3 is an explanatory diagram showing an example of calibration timing of process monitor processing by a process monitor control unit provided in the ADPLL of FIG. 2. It is explanatory drawing which shows the frequency transition at the time of the process monitor process in transmission / reception ADPLL of FIG. It is explanatory drawing which shows the normal lock process in transmission / reception ADPLL of FIG. It is a block diagram which shows an example of the RF process part by Embodiment 2 of this invention. It is a flowchart which shows an example of the operation | movement of the process monitor process in transmission / reception ADPLL provided in the RF process part of FIG. It is a block diagram which shows an example of the RF process part by Embodiment 3 of this invention. It is explanatory drawing which shows an example of the temperature sensor provided in the RF process part of FIG. It is explanatory drawing which shows an example of the lookup table stored in the lookup table storage part of the process monitor control part provided in RF processing part of FIG. It is explanatory drawing which shows the temperature of the resolution in TDC which comprises ADPLL of FIG. 19, and process dependence. It is explanatory drawing which shows an example of the digital value at the time of measuring the period of a reference | standard clock signal using TDC of FIG. It is a block diagram which shows an example of the RF process part by Embodiment 4 of this invention. FIG. 25 is an explanatory diagram illustrating an example of a chip layout in the RF processing unit of FIG. 24. It is explanatory drawing which showed an example of the calibration timing of the process monitor process by the process monitor control part of FIG. It is explanatory drawing which shows an example of the layout in TDC provided in the RF process part by Embodiment 5 of this invention. It is a block diagram which shows an example of RF processing part by Embodiment 6 of this invention, and a baseband circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram illustrating an example of an RF processing unit according to Embodiment 1 of the present invention, FIG. 2 is a block diagram illustrating an example of a configuration of a transmission / reception ADPLL provided in the RF processing unit of FIG. 1, and FIG. 2 is a block diagram showing a configuration example of a TDC provided in the ADPLL in FIG. 2, FIG. 4 is a timing chart of signals at each part in the TDC in FIG. 3, and FIG. 5 is an example of a counter provided in the transmission and reception ADPLL in FIG. FIG. 6 is a timing chart in the counter of FIG. 5, FIG. 7 is a schematic diagram showing a frequency lock process in the ADPLL in FIG. 2, and FIG. 8 is a flowchart showing an example of the operation in the transmission / reception ADPLL in FIG. 9 is an example of a lookup table stored in the lookup table storage unit of the process monitor control unit provided in the ADPLL of FIG. FIG. 10 is an explanatory diagram showing the process dependence of the resolution in the TDC of FIG. 3, and FIG. 11 is an explanation showing an example of a digital value when the period of the reference clock signal is measured using the TDC of FIG. FIG. 12 is an explanatory diagram illustrating an example of a lookup table provided in the adjustment control unit of FIG. 2, and FIG. 13 is an explanatory diagram illustrating an example of the lookup table provided in the adjustment control unit following FIG. 14 is an explanatory diagram showing an example of calibration timing of process monitor processing by the process monitor control unit provided in the ADPLL of FIG. 2, and FIG. 15 is a frequency transition at the time of process monitor processing in the transmission / reception ADPLL of FIG. FIG. 16 is an explanatory diagram showing a normal locking process in the transmission / reception ADPLL of FIG.

  In the first embodiment, the RF processing unit 1 is a semiconductor integrated circuit device provided in a communication mobile system such as a mobile phone. The RF processing unit 1 employs a direct conversion method for transmission and reception, and demodulates a reception signal or modulates a transmission signal.

  As shown in FIG. 1, an antenna switch 2 is connected to the RF processing unit 1, and an antenna 3 is connected to the antenna switch 2. The antenna 3 transmits and receives signal radio waves. The antenna switch 2 switches between transmitted and received signals.

  A baseband circuit 4 is connected to the RF processing unit 1. The baseband circuit 4 converts transmission data into an I signal and a Q signal and controls the RF processing unit 1. The RF processing unit 1 includes, for example, a reception system circuit 5, a transmission system circuit 6, and a process monitor unit 7.

  The reception system circuit 5 includes functional blocks such as a low noise amplifier 8, a phase shifter 9, mixers 10 and 11, filters 12 and 13, and variable gain amplifiers 14 and 15.

  The low noise amplifier 8 is an amplifier that amplifies the received signal. The phase shifter 9 divides the clock signal generated by the transmission / reception ADPLL 24 described later to generate an orthogonal signal. The mixers 10 and 11 are demodulation circuits that perform demodulation by combining the received signal amplified by the low noise amplifier 8 with the orthogonal signal divided by the phase shifter 9.

  The filters 12 and 13 are low-pass filters. The variable gain amplifiers 14 and 15 amplify the demodulated I and Q signals, respectively, and output the amplified signals to the baseband circuit 4.

  The transmission system circuit 6 includes functional blocks such as filters 16 and 17, a phase shifter 18, a quadrature modulator 19, and a power amplifier 20.

  The filters 16 and 17 are, for example, low-pass filters, and the phase shifter 18 generates an orthogonal signal that is 90 ° out of phase with the clock signal generated by the transmission / reception ADPLL 24.

  The quadrature modulator 19 includes multipliers 21 and 22 and an adder 23. The quadrature modulator 19 modulates the generated quadrature signal with the I signal and the Q signal supplied from the baseband circuit 4, and generates a modulated signal. Is synthesized. The power amplifier 20 amplifies the transmission signal output from the quadrature modulator 19.

  The process monitor unit 7 includes a transmission / reception ADPLL 24, a control unit 25, adjustment control units 26 to 35, and the like. The process monitor unit 7 detects a process variation in the MOS transistor and performs a process monitor process for controlling each circuit to have optimum characteristics.

  The transmission / reception ADPLL 24 generates a clock signal used for the phase shifters 9 and 18 on the basis of a clock signal TCXO generated by an externally connected clock oscillator or the like, measures process variation, and responds to the acquired process variation. Output process signal.

  The control unit 25 controls the process monitor unit 7. The adjustment control units 26 to 35 output process control signals from the process signals output from the transmission / reception ADPLL 24. The adjustment control unit 26 optimizes the electrical characteristics of the digitally controlled oscillator 38 provided in the transmission / reception ADPLL 24 by a process control signal. The adjustment control unit 27 optimizes the electrical characteristics of the low noise amplifier 8 based on the process control signal.

  The adjustment control unit 28 optimizes the electrical characteristics of the mixers 10 and 11 by the process control signal, and the adjustment control unit 29 optimizes the electrical characteristic of the phase shifter 9 by the process control signal.

  Similarly, the adjustment control unit 30 includes the filters 12 and 13, the adjustment control unit 31 includes the variable gain amplifiers 14 and 15, the adjustment control unit 32 includes the power amplifier 20, and the adjustment control unit 33 includes the multipliers 21 and 22. The adjustment control unit 34 sets the phase shifter 18, and the adjustment control unit 35 sets the filters 16 and 17 to have optimum electrical characteristics according to the respective process control signals.

  FIG. 2 is a block diagram illustrating a configuration example of the transmission / reception ADPLL 24.

  The transmission / reception ADPLL 24 includes a digital phase comparator 36, a digital loop filter 37, a digital control oscillator 38, a frequency divider 39, and a process monitor control unit 40 as shown in the figure.

  A signal output from the digitally controlled oscillator 38 is divided by a frequency divider 39, and a phase is compared with a reference clock signal TCXO by a digital phase comparator 36. The comparison result is output as a digital signal, and after high frequency noise components are removed by the digital loop filter 37, it is input to the digital control oscillator 38.

  Since feedback is applied until the frequency after frequency division matches the frequency of the reference clock signal TCXO, a clock having a frequency that is twice the frequency division ratio of the frequency of the reference clock signal TCXO is obtained at the output of the transmission / reception ADPLL 24. This state is said to have been locked. The frequency is controlled by changing the frequency division ratio.

  The digital phase comparator 36 includes a TDC (Time to Digital Converter) 41, a counter 42, an adder 43, and a switch 44. The TDC 41 changes the phase difference into a digital value.

  The input signals include a signal VREF (e.g. 26 MHz) which is a reference clock signal TCXO, a signal VDIV (e.g. 26 MHz) "output from the frequency divider 39, and a signal VPRE (e.g. 1 GHz)". The phase difference is coarse by the counter 42, finely detected by the TDC 41, and synthesized by the output.

  The counter 42 receives the signal VREF and the signal VDIV, and the TDC 41 receives the signal VREF and the signal VPRE. Based on the control signal output from the control unit 25, the switch 44 performs switching so that the signal output from the TDC 41 is output to either the adder 43 or the process monitor control unit 40.

  FIG. 3 is a block diagram illustrating a configuration example of the TDC 41.

As shown in FIG. 3, the TDC 41 includes multi-stage delay cells 41a _{1 to} 41a _N , multi-stage flip-flops 41b _{1 to} 41b _N , and a decoder 41c. In this case, the phase difference between the rising edges of the signal VPRE and the signal VREF is detected by detecting an edge where the output signal of the flip-flop 41b changes from “1” to “0”. The phase (time) resolution is determined by the delay amount of the delay cells 41a _{1 to} 41a _N.

  FIG. 4 is a timing chart of each signal in the TDC 41 of FIG.

In FIG. 4, the signal timings of the signal VREF, the signal VPRE, and the output signals D1 to D8 of the delay elements 41a _{1 to} 41a _N from the first stage to the eighth stage are shown from the top to the bottom. In this case, in the TDC 41 having the configuration shown in FIG. 3, as shown in FIG. 4, the resolution is 20 ps and the phase difference is 140 ps.

  FIG. 5 is a block diagram illustrating an example of the counter 42.

  As shown in the figure, the counter 42 includes an inverter 42a, an integrator 42b, latches 42c and 42d, and a subtractor 42e.

  In this case, the edges of the signal VPRE are counted and output by the integrator 42b, latched by the latches 42c and 42d by the signals VREF and VDIV, respectively, and then subtracted by the subtractor 42e and output.

  FIG. 6 is a timing chart of the counter 42 in FIG. 5. The output of the TDC 41 is normalized to the weight of the counter 42 and then combined with the output of the counter 42. FIG. 7 is a schematic diagram showing the frequency lock process. The ABS (Auto Band Selection) period shown in FIG. 7 is a period for selecting the oscillation band of the digitally controlled oscillator 38 close to the desired frequency before the lock operation. Before the ABS, the output of the digital loop filter 37 is fixed, and the loop is open (open loop). After the ABS, the loop is closed.

  Next, the operation of the transmission / reception ADPLL 24 in the process monitoring process according to the first embodiment will be described with reference to the flowchart of FIG.

  The process monitor process is performed in an open loop using the TDC 41. First, when the autoband select signal ABS for starting the process monitoring process is output from the baseband circuit 4, the digitally controlled oscillator 38 generates an oscillation band (about +/− tens of MHz) close to a predetermined frequency. Select (step S101). Here, the allowable circumferential error is determined by the resolution of the TDC 41. A range that does not affect the output of the TDC 41 is required.

  Subsequently, the control unit 25 outputs a control signal for switching the signal output destination of the switch 44. In response to the control signal, the switch 44 switches the output destination of the signal output from the TDC 41 from the adder 43 to the process monitor control unit 40 (step S102).

  Then, the TDC 41 converts the period of the rising edge of the signal VPRE closest to the rising edge of the signal VREF into a digital value N1 (step S103). Subsequently, the period between the rising edge of the signal VREF and the rising edge of the second closest signal VPRE is converted into a digital value N2 (step S104).

  Thereafter, the TDC 41 calculates a digital value difference (N2−N1) between the process of step S103 and the process of step S104 (step S105) and outputs the difference to the process monitor control unit 40. The difference between the digital values (N2−N1) corresponds to a digital value of one cycle of the signal VPRE.

  Alternatively, the processing of steps S103 to S105 may be repeated several times to obtain an average value of the digital values of one cycle of the signal VPRE and output the average value to the process monitor control unit 40.

  Subsequently, the process monitor control unit 40 uses the lookup table (first lookup table) and expects the value obtained in the process of step S105 and the process monitor control unit 40 set in advance. The process value is determined by comparing with the value (step S106).

  For example, if the digital value difference (N2−N1) is smaller than the expected value, the delay amount of the delay cell is large. On the contrary, if the difference (N2−N1) in the digital value is larger than the expected value, the delay amount is small. Judge the process by how big or small it is, not just big or small.

  The process values determined by the process monitor control unit 40 are output as process signals to the adjustment control units 26 to 35, respectively (step S107). Then, each of the adjustment control units 26 to 35 calculates a process control signal for setting the electrical characteristics of each circuit based on the input process signal, and the digital control oscillator 38, the low noise amplifier 8, the mixer 10, 11, phase shifter 9, filters 12 and 13, variable gain amplifiers 14 and 15, power amplifier 20, multipliers 21 and 22, adder 23, phase shifter 18, and processes for optimizing the electrical characteristics of filters 16 and 17 Calibration is performed (step S108).

  Digital control oscillator 38, low noise amplifier 8, mixers 10, 11, phase shifter 9, filters 12, 13, gain variable amplifiers 14, 15, power amplifier 20, multipliers 21, 22, adder 23, phase shifter 18 The filters 16 and 17 are each provided with a register, and the process signal calculated by the adjustment control units 26 to 35 is set in the register, and the power supply voltage and current are switched based on the set value. Optimum characteristics can be obtained.

  Next, detailed operation in the process monitor control unit 40 will be described.

  The process monitor control unit 40 includes a calculation unit and a lookup table storage unit. FIG. 9 is an explanatory diagram illustrating an example of a lookup table stored in the lookup table storage unit.

  As shown in the figure, the lookup table is a table that calculates an arbitrary process control signal from the input digital value. The process signal is composed of, for example, 'slow', 'type1', 'typ2', and 'fast'.

  FIG. 10 is an explanatory diagram showing process dependence of resolution in the TDC 41. FIG. 11 is an explanatory diagram showing an example of a digital value when the period of a 3840 MHz / 4 reference clock signal is measured using the TDC 41, for example. It is.

  10 and 11, “slow” indicates a case where the threshold voltage Vth of the transistor constituting the TDC 41 is high, and “fast” indicates a case where the threshold voltage Vth of the transistor constituting the TDC 41 is low. Is shown.

  Also, 'typ1' has a lower threshold voltage Vth of the transistor constituting the TDC 41 than 'slow', and 'typ2' has a lower threshold voltage Vth of the transistor than 'typ1', and 'fast Is higher than '.

  For example, when the threshold voltage Vth of the transistor of the TDC 41 is “typ2”, the resolution of the TDC 41 is 12.9 psec from FIG. 10, and the digital value output from the TDC 41 is 1 / p from FIG. (3840 MHz / 4) = 81.

  When the digital value “81” output from the TDC 41 is input to the process monitor control unit 40, the calculation unit of the process monitor control unit 40 refers to the lookup table shown in FIG. Output as a process signal.

  In this case, in FIG. 9, since the input digital value “81” is larger than “75” and smaller than “95”, the calculation unit of the process monitor control unit 40 performs adjustment control using “typ2” as a process signal. The data are output to the units 26 to 35, respectively.

  12 and 13 are explanatory diagrams illustrating an example of a lookup table provided in the adjustment control unit 26. FIG.

  Similar to the process monitor control unit 40 described above, the adjustment control unit 26 includes a calculation unit and a lookup table storage unit. The lookup table storage unit includes, for example, those shown in FIGS. A lookup table (second lookup table) is stored.

  12 is a table showing the relationship between the power supply voltage regulator code and the output voltage amplitude in the digitally controlled oscillator 38, and FIG. 13 is a table showing the relationship between the power supply voltage regulator code and the current consumption in the digitally controlled oscillator 38. It is.

  Note that FIGS. 12 and 13 show tables displaying only the case of “type 2” and the case of “slow” as an example.

  For example, when the rated value of the digitally controlled oscillator 38 is defined as 700 mVpps or more, if the input process signal is “typ2”, the arithmetic unit refers to the lookup table of FIG. The power supply voltage regulator code “(or higher)” is calculated, and “0” is set in the register of the digitally controlled oscillator 38. The digitally controlled oscillator 38 corrects the output voltage amplitude based on the power supply voltage regulator code “0” set in the register.

  If the input process signal is, for example, “slow”, the arithmetic unit refers to the lookup table of FIG. 12 and calculates a power supply voltage regulator code of “5” (or higher) to obtain a digital value. “5” is set in the register of the control oscillator 38.

  The digitally controlled oscillator 38 corrects the output voltage amplitude based on the power supply voltage regulator code “5” set in the register.

  Moreover, it is desirable that the current consumption is small. That is, the power supply voltage regulator code in FIG. 13 should be small. Therefore, when the input process signal is “typ2”, the power supply voltage regulator code is set to “0”, and when the process signal is “slow”, the power supply voltage regulator code is set to “5”. Set the register.

  As a result, the current consumption of the digitally controlled oscillator 38 is 12 mA for 'typ2' and 11.4 mA for 'slow'. If there is no switching function depending on the process, '5' determined by 'slow' is always used. In this case, at 'type 2', the current is 13.8 mA, and the current of 1.8 mA increases.

  FIG. 14 is an explanatory diagram showing an example of the calibration timing of the process monitor process performed by the process monitor control unit 40.

  Each state in the RF processing unit 1, the transmission / reception ADPLL 24, the reception RX, and the transmission TX is shown from the upper side to the lower side of FIG.

  In this case, as illustrated, the process monitor process is executed only once after Power-up (power-on). Then, after the process value (process control signal) is determined, the analog circuit reflects this value and process calibration is performed.

  FIG. 15 is an explanatory diagram showing frequency transitions during process monitor processing in the transmission / reception ADPLL 24.

  The transmission / reception ADPLL 24 performs process monitor processing after auto band selection (ABS), and the operation is turned off. The auto-band selection time ends in about several tens of μsec, for example. Time and power consumption can be reduced compared to a normal lock process (for example, about several hundred μsec) of the transmission / reception ADPLL 24.

  FIG. 16 is an explanatory diagram showing a normal lock process in the transmission / reception ADPLL 24 for comparison. In this case, after auto-band selection (ABS), the process proceeds to the lock process.

  Thereby, according to the first embodiment, since the process monitor process can be performed using the transmission / reception ADPLL 24, the process can be monitored while the increase in area is reduced.

(Embodiment 2)
FIG. 17 is a block diagram illustrating an example of an RF processing unit according to the second embodiment of the present invention, and FIG. 18 is a flowchart illustrating an example of an operation of a process monitor process in the transmission / reception ADPLL provided in the RF processing unit of FIG. is there.

  In the second embodiment, as shown in FIG. 17, a DLL (Delay Locked Loop) 45 that is a delay locked loop and switches 46 and 47 are newly provided in the transmission / reception ADPLL 24 of the RF processing unit 1 and input to the TDC 41. As a test signal, a signal VDLL1 (first signal) having an arbitrary phase difference and a signal (second signal) VDLL2 are input from the DLL 45.

  The DLL 45 generates and outputs signals VDLL1 and VDLL2 having an accurate phase difference from the signal VREF. Based on the control signal output from the control unit 25, the switch 46 performs switching so that either the signal VDLL1 output from the DLL 45 or the signal VREF is output to the TDC 41 and the counter 42, respectively.

  Further, the switch 47 switches to output either the signal VDLL2 output from the DLL 45 or the signal VPRE output from the frequency divider 39 to the TDC 41 based on the control signal output from the control unit 25. Since other connection configurations are the same as those in FIG. 2 in the first embodiment, description thereof is omitted.

  FIG. 18 is a flowchart showing an example of operation of process monitor processing in the transmission / reception ADPLL 24.

  Also in this case, the process monitor process is performed in an open loop as in the first embodiment (FIG. 8).

  First, when the control unit 25 operates the DLL 45, the DLL 45 generates a signal VDLL1 and a signal VDLL2 having a predetermined phase difference (step S201). Subsequently, the control unit 25 outputs a control signal for switching the signal output destination of the switches 44, 46 and 47.

  Upon receiving this control signal, the switch 44 switches the output destination of the signal output from the TDC 41 from the adder 43 to the process monitor control unit 40, and the switch 46 receives the signal VDLL 1 output from the DLL 45 as input to the TDC 41. The switch 47 switches so that the signal VDLL2 output from the DLL 45 is input to the TDC 41 (step S202).

  Then, the TDC 41 converts the rising edge period between the signal VDLL1 and the signal VDLL2 into a digital value (step S203). Subsequently, the process monitor control unit 40 compares the value obtained in step S203 with an expected value preset in the process monitor control unit 40, and determines a process value (step S204). ).

  If the value obtained in step S203 is smaller than expected, the delay amount of the delay cell is large. Conversely, if the value is large, the delay amount is small. Judge the process by how big or small it is, not just big or small.

  Alternatively, the process of step S203 may be repeated several times, an average value of the digital values obtained by the process of step S203 may be obtained, and the average value may be output to the process monitor control unit 40.

  Then, the process values determined by the process monitor control unit 40 are output as process signals to the adjustment control units 26 to 35, respectively (step S205). Each adjustment control unit 26 to 35 calculates a process control signal for setting the electrical characteristics of each circuit based on the input process signal, and the digital control oscillator 38, the low noise amplifier 8, the mixers 10 and 11, Process calibration that optimizes the electrical characteristics of the phase shifter 9, filters 12 and 13, variable gain amplifiers 14 and 15, power amplifier 20, multipliers 21 and 22, adder 23, phase shifter 18, and filters 16 and 17. Is performed (step S206).

  As a result, in the second embodiment, by adding the DLL 45, auto band selection (ABS) at the time of process monitoring can be made unnecessary, and the processing time of the process monitoring process can be shortened.

(Embodiment 3)
19 is a block diagram illustrating an example of an RF processing unit according to Embodiment 3 of the present invention, FIG. 20 is an explanatory diagram illustrating an example of a temperature sensor provided in the RF processing unit of FIG. 19, and FIG. FIG. 22 is an explanatory diagram illustrating an example of a lookup table stored in a lookup table storage unit of a process monitor control unit provided in the 19 RF processing unit, and FIG. 22 is a resolution temperature in the TDC constituting the ADPLL of FIG. FIG. 23 is an explanatory diagram showing an example of a digital value when the period of the reference clock signal is measured using the TDC of FIG.

  In the third embodiment, as shown in FIG. 19, a temperature sensor 48 is newly added to the process monitor unit 7 of the RF processing unit 1. A process monitor control unit 40 is connected to the output unit of the temperature sensor 48. Other configurations in the RF processing unit 1 are the same as those in FIGS. 1 and 2 of the first embodiment, and a description thereof will be omitted.

  FIG. 20 is an explanatory diagram showing an example of the configuration of the temperature sensor 48.

  The temperature sensor 48 includes resistors R0 to R8, a diode D1, and comparators CP1 to CP7. One connection part of the resistor R0 is connected so that, for example, a power supply voltage VLD having no temperature dependency generated from the power supply voltage Vb generated by the band gap reference circuit is supplied, and the other end of the resistor R0 is connected. Is connected to the anode of the diode D1.

  The resistors R1 to R8 connected in series are connected between the cathode of the diode D1 and the reference potential VSS. The negative (−) side input terminals of the comparators CP1 to CP7 are respectively connected so that the power supply voltage Vb is input.

  A connecting portion between the resistor R1 and the resistor R2 is connected to the positive (+) side input terminal of the comparator CP1. The connection part of resistors R2 and R3 is connected to the positive (+) side input terminal of the comparator CP2, and the connection part of resistors R3 and R4 is connected to the positive (+) side input terminal of the comparator CP3. Yes.

  The connection portion of resistors R4 and R5 is connected to the positive (+) side input terminal of the comparator CP4, and the connection portion of resistors R5 and R6 is connected to the positive (+) side input terminal of the comparator CP5. Yes.

  Similarly, resistors R6 and R7 are connected to the positive (+) side input terminal of the comparator CP6, and resistors R7 and R8 are connected to the positive (+) side input terminal of the comparator CP7. It is connected.

  The diode D1 has a characteristic that the forward voltage Vd decreases as the temperature increases. Therefore, the divided voltages Vt0 to Vt6 output from the connection portions of the resistors R1 to R8 increase as the temperature increases.

  On the other hand, the power supply voltage Vb generated by the bandgap reference circuit is constant regardless of the temperature. Therefore, the power supply voltage Vb and the divided voltages Vt0 to Vt6 can be used as a temperature sensor by comparing them with the comparators CP1 to CP7, respectively.

  When the temperature is 25 ° C., for example, the outputs of the comparators CP1 to CP4 are high signals, and the outputs of the comparators CP5 to CP7 are low signals. By outputting signals output from the comparators CP1 to CP7 as temperature data to the process monitor control unit 40, more accurate process monitor processing can be performed.

  FIG. 21 is an explanatory diagram illustrating an example of a lookup table stored in the lookup table storage unit of the process monitor control unit 40.

  As shown in the figure, the lookup table is a table for calculating an arbitrary process control signal from the input digital value and temperature data. The range of the temperature data is “−20 ° C. or lower”, “−20 to 0 ° C.”, “0 ° C. to 20 ° C.”, “−20 to 40 ° C.”, “40 ° C. to 60 ° C.”, “−60 to 80”. “C °”, “80 ° C. to 100 ° C.”, and “100 ° C. or higher”, and the process signal includes, for example, “slow”, “typ1”, “typ2”, and “fast”.

  FIG. 22 is an explanatory diagram showing temperature and process dependence of resolution in the TDC 41. FIG. 23 is an example of a digital value when the period of a 3840 MHz / 4 reference clock signal is measured using the TDC 41, for example. It is explanatory drawing shown.

  For example, when the temperature data is 25 ° C. and the threshold voltage Vth of the transistor of the TDC 41 is “typ2”, the resolution of the TDC 41 is 12.9 psec from FIG. 22, and the digital value output from the TDC 41 is From FIG. 23, 1 / (3840 MHz / 4) = 81.

  Therefore, in FIG. 21, since the input digital value “81” is larger than “75” and smaller than “95”, the calculation unit of the process monitor control unit 40 uses “type 2” as a process signal as an adjustment control unit. 26 to 35, respectively.

  Then, the adjustment control units 26 to 35 execute process calibration based on the input process signal “typ2”. In this case, the process calibration is the same as the processing shown in FIGS. 12 and 13 of the first embodiment, and the description thereof is omitted.

  Thus, in the third embodiment, the temperature sensor 48 is provided, so that the environment can be monitored in more detail, and highly accurate process calibration can be performed.

  In addition, since the temperature during the process monitor process can be taken into account, it is not necessary to cover the worst condition, thereby eliminating the need for an overmargin design and reducing power consumption.

(Embodiment 4)
24 is a block diagram showing an example of an RF processing unit according to the fourth embodiment of the present invention, FIG. 25 is an explanatory diagram showing an example of a chip layout in the RF processing unit of FIG. 24, and FIG. 26 is a process of FIG. It is explanatory drawing which shows an example of the calibration timing of the process monitor process by a monitor control part.

  In the first embodiment, a direct conversion method is adopted for transmission and reception, and transmission and reception are alternately performed in a time-sharing manner to share the transmission and reception ADPLL 24 (FIG. 2) as a local oscillator. In the fourth embodiment, a configuration of the RF processing unit 1 that performs transmission and reception at the same time as in the W-CDMA system, for example, will be described.

  In this case, the process monitor unit 7 of the RF processing unit 1 includes a reception ADPLL 24a and a transmission ADPLL 24b, control units 25a and 25b, and adjustment control units 26a and 26b as local oscillators, as shown in FIG.

  The control unit 25a controls the reception ADPLL 24a during the process monitor process, and the control unit 25b controls the transmission ADPLL 24b during the process monitor process.

  The adjustment controllers 26a and 27 to 31 output a process control signal from the process signal output from the reception ADPLL 24a. The adjustment control units 26b and 32 to 35 output a process control signal from the process signal output from the transmission ADPLL 24b.

  The adjustment control unit 26a optimizes the electrical characteristics of the digital control oscillator provided in the reception ADPLL 24a by the process control signal, and the adjustment control unit 26b provides the electrical characteristics of the digital control oscillator provided in the transmission ADPLL 24b by the process control signal. To optimize.

  Since other connection configurations and operations are the same as those in the first embodiment, description thereof will be omitted.

  FIG. 25 is an explanatory diagram showing an example of a chip layout in the RF processing unit 1 shown in FIG.

  A transmission ADPLL 24b is laid out in the upper left of FIG. 25, and a power amplifier 20 is laid out on the right side of the transmission ADPLL 24b. A phase shifter 18 is laid out on the lower left side of the power amplifier 20, and a quadrature modulator 19 is laid out on the right side of the phase shifter 18.

  Filters 16 and 17 are laid out on the right side of the power amplifier 20 and the quadrature modulator 19. Variable gain amplifiers 14 and 15 are laid out below the transmission ADPLL 24 b, the phase shifter 18, and the quadrature modulator 19, and the filters 12 and 13 are laid out below the variable gain amplifiers 14 and 15. .

  Control units 25a and 25b are laid out on the right side of the variable gain amplifiers 14 and 15 and the filters 12 and 13, and a reception ADPLL 24a is laid out below the control units 25a and 25b.

  Mixers 10 and 11 are laid out at the lower left of the filters 12 and 13, and a low noise amplifier 8 is laid out below the mixers 10 and 11. A phase shifter 9 is laid out on the right side of the mixer 10 and the low noise amplifier 8.

  In this case, in order to shorten the wiring length, the reception ADPLL 24a is arranged near the block where the reception system circuit 5 is laid out, and the transmission ADPLL 24b is arranged near the block where the transmission system circuit 6 is laid out. It has become. With this layout, process variations can be corrected more optimally.

  FIG. 26 is an explanatory diagram showing an example of the calibration timing of the process monitor process performed by the process monitor control unit 40.

  Each state in the RF processing unit 1, the ADPLL 24, the reception RX, and the transmission TX is shown from the upper side to the lower side of FIG.

  As shown in the figure, the process monitor process is executed only once after Power-up (power-on). Further, since the reception ADPLL 24a and the transmission ADPLL 24b are provided independently, it is possible to perform process monitor processing at the same time.

  Thereby, also in the fourth embodiment, it is possible to perform highly accurate process calibration while reducing an increase in area.

(Embodiment 5)
FIG. 27 is an explanatory diagram showing an example of the layout in the TDC provided in the RF processing unit according to the fifth embodiment of the present invention.

  In the fifth embodiment, an example of the layout in the TDC 41 (FIG. 2) will be described with reference to FIG.

As shown in FIG. 3 of the first embodiment, the TDC 41 includes delay cells 41a _{1 to} 41a _N , flip-flops 41b _{1 to} 41b _N , and a decoder 41c. Delay cells 41a _{1 to} 41a _N and dummy delay cells 41a _NN are laid out from left to right.

Below these delay cells 41a _{1 to} 41a _NN , flip-flops 41b _{1 to} 41b _N and dummy flip-flops 41b _NN are laid out from left to right. A decoder 41c is laid out below the flip-flops 41b _{1 to} 41b _NN .

In the TDC 41, the linearity of phase difference detection is important. Therefore, the delay cells 41a _{1 to} 41a _N and the flip-flops 41b _{1 to} 41b _N need to be arranged in an orderly manner. In this case, a layout design method using automatic placement and routing that is normally performed by logic is not used.

  In the normal synchronous design, the data flow of the continuous flip-flop and the clock flow are reversed in order to prevent data loss. Since TDC is not a synchronous design, it is input from the same direction.

  In FIG. 27, the influence of the data delay due to the wiring length can be canceled by laying out the wiring length of the data and the wiring length H2 of the clock line substantially the same. On the other hand, since the detected data only needs to be processed by the next clock, the decoder 41c is not greatly limited in layout. Therefore, the decoder 41c performs layout design by automatic placement and routing in order to reduce the area.

(Embodiment 6)
FIG. 28 is a block diagram showing an example of an RF processing unit and a baseband circuit according to the sixth embodiment of the present invention.

  In the first embodiment, the case where the process monitor process is performed every time the power is turned on has been described. However, for example, the process value may be stored after the process value is determined.

  In this case, as shown in FIG. 28, a memory 4a is provided in the baseband circuit 4, and a process value is stored in the memory 4a from the output circuit of the RF processing unit 1 via the input circuit of the baseband circuit 4.

  Then, the process value is distributed from the output circuit of the baseband circuit 4 to the respective adjustment control units 26 to 35 via the input circuit of the RF processing unit 1 at an appropriate timing.

  Thereby, even if the power of the RF processing unit 1 is turned off, the data is stored in the baseband circuit 4, so that the process monitor process can be made unnecessary even when the power is turned on to the RF processing unit 1. .

  Thereby, calibration time and power consumption can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for a process monitor processing technique in a semiconductor integrated circuit device for high frequency processing used for a cellular phone or the like.

DESCRIPTION OF SYMBOLS 1 RF processing part 2 Antenna switch 3 Antenna 4 Baseband circuit 4a Memory 5 Reception system circuit 6 Transmission system circuit 7 Process monitor part 8 Low noise amplifier 9 Phase shifter 10, 11 Mixer 12, 13 Filter 14, 15 Gain variable amplifier 16, 17 Filter 18 Phase shifter 19 Quadrature modulator 20 Power amplifiers 21 and 22 Multiplier 23 Adder 24 Transmission / reception ADPLL
24a Reception ADPLL
24b Transmission ADPLL
25 control unit 25a control unit 25b control unit 26 adjustment control unit 26a adjustment control unit 26b adjustment control unit 27 to 35 adjustment control unit 36 digital phase comparator 37 digital loop filter 38 digital control oscillator 39 frequency divider 40 process monitor control unit 41 TDC
41a _{1 to} 41a _N delay cell 41a _NN delay cell 41b _{1 to} 41b _N flip flop 41b _NN flip flop 41c decoder 42 counter 42a inverter 42b integrator 42c, 42d latch 42e subtractor 43 adder 44 switch 45 DLL
46, 47 Switch 48 Temperature sensor R0-R8 Resistor D1 Diode CP1-CP7 Comparator H1, H2 Wiring length

Claims (10)

A semiconductor integrated circuit device for RF processing having a reception system circuit and a transmission system circuit,
A process monitor unit that detects process variation from a process monitor signal and adjusts electrical characteristics in an arbitrary functional block constituting the reception system circuit and the transmission system circuit;
The reception system circuit generates a clock signal used when the reception system circuit demodulates the reception signal or the transmission system circuit modulates the transmission signal, and the process monitor signal is based on the control signal during the process monitor process. A semiconductor integrated circuit device comprising: The semiconductor integrated circuit device according to claim 1.
The process monitor unit
A process monitor control unit that detects a process variation from a process monitor signal output from the ADPLL, determines a process value for controlling the process variation, and outputs the process value as a process signal;
A control unit that outputs a control signal to the ADPLL during the process monitoring process;
Provided in each functional block constituting the reception system circuit and the transmission system circuit, a process control signal for optimizing electrical characteristics based on a process signal output from the process monitor control unit. A semiconductor integrated circuit device comprising: an adjustment control unit that outputs to each block. The semiconductor integrated circuit device according to claim 1.
The process monitor unit
A temperature sensor that detects the temperature during process monitor processing;
A process monitor control unit that detects a process variation from the process monitor signal output from the ADPLL and the temperature detected by the temperature sensor, determines a process value for controlling the process variation, and outputs the process value as a process signal;
A control unit that outputs a control signal to the ADPLL during the process monitoring process;
Provided in each functional block constituting the reception system circuit and the transmission system circuit, a process control signal for optimizing electrical characteristics based on a process signal output from the process monitor control unit. A semiconductor integrated circuit device comprising: an adjustment control unit that outputs to each block. The semiconductor integrated circuit device according to any one of claims 1 to 3,
The ADPLL is
A TDC for converting a phase difference between the clock signal generated by the ADPLL and a reference clock signal into a digital value;
A semiconductor integrated circuit comprising: a switching unit configured to switch a digital value output from the TDC to be output as a process monitor signal to the process monitor control unit based on a control signal output from the control unit; Circuit device. The semiconductor integrated circuit device according to claim 2 or 4,
The process monitor control unit
A first look-up table for converting the process monitor signal into the process signal, and converting the process monitor signal output from the ADPLL into the process signal based on the first look-up table;
The adjustment control unit
A second look-up table for converting the process signal into the process control signal, and the process signal output from the process monitor control unit based on the second look-up table A semiconductor integrated circuit device, wherein an electrical characteristic is converted into a process control signal and set in an adjustment register provided in the functional block. The semiconductor integrated circuit device according to claim 3 or 4,
The process monitor control unit
A first look-up table for converting the process monitor signal set for each arbitrary temperature range into the process signal; and based on the first look-up table, a temperature range detected by the temperature sensor Converting the process monitor signal output from the corresponding ADPLL into the process signal;
The adjustment control unit
A second look-up table for converting the process signal into the process control signal, and the process signal output from the process monitor control unit based on the second look-up table A semiconductor integrated circuit device, wherein an electrical characteristic is converted into a process control signal and set in an adjustment register provided in the functional block. The semiconductor integrated circuit device according to any one of claims 4 to 6,
The ADPLL is
A delay lock loop that generates a first signal having an arbitrary phase difference and a second signal;
The TDC is
A semiconductor integrated circuit device, wherein a phase difference between a first signal and a second signal generated by the delay lock loop is converted into a digital value. The semiconductor integrated circuit device according to any one of claims 4 to 6,
The ADPLL is
With a digitally controlled oscillator,
The TDC is
A semiconductor integrated circuit device, wherein a period of a signal obtained by dividing the digitally controlled oscillator by a frequency divider inside the ADPLL is converted into a digital value. The semiconductor integrated circuit device according to any one of claims 4 to 6,
A plurality of ADPLLs for outputting each process monitor signal;
Correcting the process variation of the functional block based on the process monitor signal output from the ADPLL laid out in the arrangement closest to the arbitrary functional block constituting the reception system circuit and the transmission system circuit. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to any one of claims 4 to 6,
An output circuit for outputting the process value to a baseband processing unit connected to the outside of the semiconductor integrated circuit;
By distributing the process value from the baseband processing unit, it is possible to omit the process calibration when the RF processing unit is turned on next time even if the RF processing unit including the ADPLL is turned off. A semiconductor integrated circuit device, comprising:

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