JP2014127731A - Semiconductor device and method for controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of accurately and simply performing IM2 correction.SOLUTION: A semiconductor device 100 comprises: a receiving circuit 11 which directly converts a received RF signal to a baseband signal; a correction circuit 12 which corrects secondary intermodulation distortion characteristics of the receiving circuit 11 on the basis of correction parameters; a storage circuit 13 which stores a first correction value set in the correction parameters so as to improve the secondary intermodulation distortion characteristics at a first timing; and a control circuit 14 which sets a second correction value in the correction parameters so as to improve the secondary intermodulation distortion characteristics on the basis of the first correction value at a second timing after the first timing.

Description

  The present invention relates to a semiconductor device and a control method thereof, and can be suitably used for, for example, a semiconductor device including a receiving circuit that receives an RF signal and a control method thereof.

  In recent years, wireless communication terminals such as mobile phone terminals are rapidly spreading, and further, W-CDMA (Wideband Code Division Multiple Access), EDGE (Enhanced Data rates for GSM Evolution), GSM (Global System for Mobile Communication) ( A multi-mode configuration employing a plurality of communication methods such as registered trademark (LTE) and LTE (Long Term Evolution) is being promoted. In order to achieve multimode, a plurality of semiconductor devices (RFICs) that process RF (Radio Frequency) signals of the respective communication methods are required. Therefore, downsizing and low cost of a semiconductor device built in a wireless communication terminal are required. Is desired. In order to respond to such a request, a direct conversion method is adopted in the receiving unit of the wireless communication terminal.

  The direct conversion method is a method for directly down-converting an RF signal in a received RF frequency band to a baseband frequency band. In the direct conversion method, since the RF signal is directly converted into the baseband frequency band, there is no intermediate frequency band, and no image response exists in principle, so that an image removal filter is unnecessary. In addition, since the baseband filter is suitable for semiconductor integration, the size can be reduced.

  On the other hand, it is known that the reception sensitivity of the direct conversion type receiver deteriorates because second order inter-modulation (IM2) occurs in the received signal. For example, Patent Documents 1 and 2 describe techniques related to IM2 correction (IM2 calibration) for correcting the IM2 characteristics of the reception unit so as to reduce the IM2 component (IM2 signal) superimposed on the reception signal.

JP 2011-114752 A Special table 2010-517386

  Conventionally, in a semiconductor device that receives an RF signal, a SAW (Surface Acoustic Wave) filter has been used to reduce the IM2 component. In recent years, as described above, downsizing and cost reduction have been demanded, and research on a semiconductor device capable of removing the SAW filter and reducing the number of components (SAW filter-less) has been advanced.

  The inventor has studied IM2 correction to improve reception sensitivity in a SAW filterless semiconductor device.

  In the prior art such as Patent Document 1, IM2 correction is performed when the semiconductor device is powered on, and the circuit parameters are adjusted to reduce the IM2 component. However, the present inventor has paid attention to the fact that the conventional semiconductor device does not consider the fluctuation of the IM2 characteristic of the semiconductor device after the IM2 correction at the time of power-on. For example, since the IM2 characteristic may fluctuate due to changes in the environment such as temperature, the IM2 component cannot be accurately reduced only by IM2 correction at power-on as in a conventional semiconductor device, and reception sensitivity may deteriorate. The present inventor has found that

  Furthermore, in order to perform IM2 correction in a semiconductor device that receives an RF signal, the inventor has paid attention to the need to suppress the influence on the reception operation of the RF signal. In the conventional semiconductor device, since the IM2 correction is performed only at the time of power-on with sufficient time, the time for performing the IM2 correction is not considered. In the conventional semiconductor device, the present inventor has found that since the IM2 correction can be performed simply and the correction operation cannot be completed in a short time, the reception operation of the RF signal may be affected.

  Thus, the conventional semiconductor device has a problem that IM2 correction cannot be performed accurately and easily.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device includes a receiving circuit, a correction circuit, a memory circuit, and a control circuit. The receiving circuit directly converts the received RF signal into a baseband signal. The correction circuit corrects the second-order intermodulation distortion characteristic of the reception circuit based on the correction parameter. The storage circuit stores the first correction value set in the correction parameter so that the second-order intermodulation distortion characteristic is improved at the first timing. The control circuit sets the second correction value in the correction parameter so that the second-order intermodulation distortion characteristic is improved based on the first correction value at the second timing after the first timing.

  According to the one embodiment, IM2 correction can be performed accurately and easily.

It is a block diagram which shows the main characteristics of the semiconductor device which concerns on embodiment. It is a block diagram which shows the structure of the radio | wireless communication terminal containing the semiconductor device of a reference example. 1 is a configuration diagram illustrating a configuration of a wireless communication terminal including a semiconductor device according to a first embodiment. 3 is a frequency spectrum of a signal processed by the semiconductor device according to the first embodiment. 1 is a configuration diagram showing a main configuration of a semiconductor device according to a first embodiment. 3 is a circuit diagram showing a circuit configuration of a circuit included in the semiconductor device according to the first embodiment. FIG. FIG. 6 is a diagram for explaining an operation timing of the semiconductor device according to the first embodiment. 3 is a graph showing a relationship between IM2 characteristics and temperature by the semiconductor device according to the first embodiment. 3 is a flowchart showing an operation at power-on of the semiconductor device according to the first embodiment. 6 is an explanatory diagram for explaining an operation timing at the time of power-on of the semiconductor device according to the first embodiment; FIG. 4 is a flowchart showing an operation during warm-up of the semiconductor device according to the first embodiment. FIG. 6 is an explanatory diagram for explaining an operation timing during warm-up of the semiconductor device according to the first embodiment. 3 is a graph showing a locking operation of a PLL included in the semiconductor device according to the first embodiment. 6 is a flowchart showing an operation during warm-up of the semiconductor device according to the second embodiment. FIG. 10 is an explanatory diagram for explaining an operation timing at the time of warm-up of the semiconductor device according to the second embodiment. FIG. 10 is a configuration diagram illustrating a main configuration of a semiconductor device according to a third embodiment. FIG. 6 is a circuit diagram showing a circuit configuration of a temperature sensor included in a semiconductor device according to a third embodiment. 10 is a flowchart showing an operation at the time of power-on of the semiconductor device according to the third embodiment. 10 is a flowchart showing an operation during warm-up of the semiconductor device according to the third embodiment. FIG. 10 is a configuration diagram showing a main configuration of a semiconductor device according to a fourth embodiment. FIG. 6 is a circuit diagram showing a circuit configuration of a PMA included in a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram for explaining an operation timing of the semiconductor device according to the fourth embodiment. FIG. 10 is a diagram for explaining an operation timing of the semiconductor device according to the fourth embodiment.

(Outline of the embodiment)
Prior to the description of the embodiment, the outline of the main features of the embodiment will be described with reference to FIG. As shown in FIG. 1, the semiconductor device 100 according to the embodiment includes a reception circuit 11, a correction circuit 12, a storage circuit 13, and a control circuit 14 as main components.

  The receiving circuit 11 directly converts the received RF signal into a baseband signal. The correction circuit 12 corrects the second-order intermodulation distortion (IM2) characteristic of the reception circuit 11 based on the correction parameter. The storage circuit 13 stores the first correction value set as the correction parameter so that the second-order intermodulation distortion characteristic is improved at the first timing. The control circuit 14 sets the second correction value in the correction parameter so that the second-order intermodulation distortion characteristic is improved based on the first correction value at the second timing after the first timing.

  For example, the first timing is a power-on operation of the semiconductor device 100, and the second timing is a warm-up operation until the semiconductor device 100 shifts from a sleep operation to a normal operation. In addition, the second timing may be any timing among repeated warm-up operations.

  As described above, one of the demands for a semiconductor device (RFIC) used in a high-frequency wireless device such as a mobile phone terminal is removal of a SAW filter as an external component (SAW filter-less). In the SAW filterless architecture, the signal output from the transmission unit (TX) leaks into the reception unit (RX). This leak signal generates an interference wave (IM2 component) in the baseband due to second-order intermodulation distortion (IM2), and the IM2 component is superimposed on the desired signal, thereby degrading the reception sensitivity. For this reason, in a semiconductor device without a SAW filter, it is necessary to improve the IM2 characteristics by mounting a correction circuit for correcting the mismatch state of the differential pair in the receiving unit.

  However, even if the even-order distortion of the signal is canceled by controlling the differential circuit in the receiving unit of the semiconductor device, IM2 correction may not be sufficiently performed due to mismatch of circuit devices or parasitic imbalance. The optimum correction point at which the IM2 characteristic is most improved depends on the temperature, and the degree of dependence differs for each semiconductor device (sample). That is, the analog circuit that constitutes the RF signal receiver generally varies in characteristics due to temperature changes and has variations due to the manufacturing process. Therefore, the optimum correction point varies for each temperature and semiconductor device. For this reason, it is difficult to store correction parameters in a table in advance and perform IM2 correction using this table.

  In the conventional semiconductor device, the IM2 characteristic deterioration due to the temperature fluctuation after the IM2 correction may be dealt with by giving a margin to the product specifications of the semiconductor device. That is, only a semiconductor device satisfying the product specification in consideration of a margin for deterioration of the IM2 characteristic due to temperature fluctuation has been determined to be a non-defective product. In this case, the temperature degradation of the IM2 characteristic has a large variation in the semiconductor device. Therefore, when the worst degradation is taken into account, it becomes an over margin and there is a concern that the yield may be reduced.

  In addition, since the IM2 correction circuit for reducing the deterioration of the reception sensitivity due to the IM2 component inputs the test signal (two-tone signal) to the reception unit, reception is performed when IM2 correction is performed at the timing when the reception circuit is actually operating. Affects processing. For this reason, IM2 correction cannot be performed at the timing when the semiconductor device performs the receiving operation. In the conventional semiconductor device, since IM2 correction takes time, IM2 correction is performed only when the RFIC power is on, which has a sufficient time. However, when the mismatch state of the differential circuit changes due to a temperature change as described above, the IM2 characteristic changes. There is a problem of deterioration.

  Therefore, in the embodiment, IM2 correction (IM2 recorrection, IM2 recalibration) is performed at a timing other than the power-on operation (first timing) with the configuration as shown in FIG. The main feature is that it can be shortened.

  That is, in the semiconductor device according to the embodiment, the IM2 characteristic is corrected at the first timing as in the power-on operation, and the IM2 characteristic is corrected again at the second timing as in the warm-up operation. It was. Thereby, even when the IM2 characteristic fluctuates due to a change in the environment such as temperature, the IM2 characteristic can be corrected appropriately and accurately. Further, since the correction is performed at the second timing based on the correction value corrected at the first timing, the correction can be easily and efficiently performed with fewer operations, and the correction time can be shortened.

(Embodiment 1)
The first embodiment will be described below with reference to the drawings. First, the structure of a wireless communication terminal including a semiconductor device (RFIC) according to a reference example before application of the embodiment will be described with reference to FIG.

  As shown in FIG. 2, the wireless communication terminal 2 of the reference example includes an RFIC 900, a baseband processor 200, an antenna 201, a DPX (duplexer) 202, an isolator 203, an HPA (high power amplifier) 204, a transmission SAW filter 211, and a reception SAW. A filter 212 is provided.

  The antenna 201 is connected to the antenna terminal 202 a of the DPX 202. The receiving terminal 202b of the DPX 202 and the RF signal input terminal 900a of the RFIC 900 are connected. The transmission terminal 202 c of the DPX 202 and the RF signal output terminal 900 b of the RFIC 900 are connected via the isolator 203, the HPA 204, and the transmission SAW filter 211. The reception SAW filter 212 is connected to the reception filter connection terminals 900d and 900e of the RFIC 900. The RFIC 900 and the baseband processor 200 are connected to each other via an LVDS (Low Voltage Differential Signaling) interface 900c so that input / output is possible.

  The RFIC 900 of the reference example is a semiconductor device for transmitting and receiving an RF signal of a W-CDMA modulation method. The RFIC 900 is a direct conversion transceiver with a SAW filter and includes a reception block 901 and a transmission block 902 as shown in FIG. In FIG. 2, a part of the configuration of the reception block 901 and the transmission block 902 is illustrated, and illustration of the other configurations is omitted. The reception block 901 includes an LNA (low noise amplifier) 903, a mixer (MIX) 904, and a BE (back end circuit) 905. A reception SAW filter 212 is connected between the LNA 903 and the mixer 904 as an external component. Yes. The transmission block 902 includes a driver 906.

  When the wireless communication terminal 2 performs transmission, the RFIC 900 receives a baseband transmission signal from the baseband processor 200 via the LVDS interface 900c. The transmission block 902 of the RFIC 900 upconverts the input baseband transmission signal to the RF frequency band, and the driver 906 amplifies the upconverted signal and outputs the RF transmission signal. The RF transmission signal output from the RFIC 900 is amplified by the HPA 204 after removing unnecessary frequency components by the transmission SAW filter 211. This amplified RF transmission signal is input to the DPX 202 via the isolator 203, and transmitted from the DPX 202 to the base station or the like via the antenna 201.

  When the wireless communication terminal 2 performs reception, when the antenna 201 receives an RF reception signal from a base station or the like, it is demultiplexed by the DPX 202 and the RF reception signal is input to the RFIC 900. In the RFIC 900, the input RF reception signal is amplified by the LNA 903, and unnecessary frequency components are removed by the reception SAW filter 212. The RF reception signal that has passed through reception SAW filter 212 is down-converted to a baseband reception signal in the baseband frequency band by mixer 904. Further, the baseband received signal is subjected to predetermined signal processing by the BE 905 and then output to the baseband processor 200 via the LVDS interface 900c.

  In the W-CDMA modulation scheme, since the reception block 901 and the transmission block 902 operate simultaneously, the RF transmission signal leaks to the reception block 901, and this leak interference wave signal deteriorates the reception sensitivity. For this reason, in the RFIC 900 of the reference example, the leakage interference wave signal is suppressed by the reception SAW filter 212 arranged as an external component between the LNA 903 and the mixer 904 as shown in FIG.

  On the other hand, in the present embodiment, a configuration in which the SAW filter is removed (SAW filter-less) in order to reduce the number of peripheral components and the mounting chip area in response to the multi-band RFIC (multi-mode). To do.

  FIG. 3 shows a configuration of a wireless communication terminal including the semiconductor device according to this embodiment. The wireless communication terminal 1 according to the present embodiment is a mobile phone terminal, a smartphone, a tablet terminal, or the like. As illustrated in FIG. 3, the wireless communication terminal 1 does not include the transmission SAW filter 211 and the reception SAW filter 212 as compared with the wireless communication terminal 1 of the reference example illustrated in FIG. 2. That is, the wireless communication terminal 1 includes an RFIC 100, a baseband processor 200, an antenna 201, a DPX 202, an isolator 203, and an HPA 204. Note that the RFIC 100 and the baseband processor 200 may be a single semiconductor device.

  The antenna 201 is connected to the antenna terminal 202 a of the DPX 202. The receiving terminal 202b of the DPX 202 and the RF signal input terminal 100a of the RFIC 100 are connected. The transmission terminal 202 c of the DPX 202 and the RF signal output terminal 100 b of the RFIC 100 are connected via an isolator 203 and an HPA 204. The RFIC 100 and the baseband processor 200 are connected to each other via an LVDS interface 100c so that input / output is possible.

  The RFIC 100 according to this embodiment is a one-chip semiconductor device, and is a semiconductor device for transmitting and receiving W-CDMA modulation type RF signals. The RFIC 100 is a SAW filterless direct conversion transceiver, and includes a reception block 101 and a transmission block 102 as shown in FIG. In FIG. 3, some configurations of the reception block 101 and the transmission block 102 are illustrated, and the other configurations are not illustrated. The reception block 101 includes an LNA 103, a mixer 104, and a BE 105. The transmission block 102 includes a driver 106.

  When the wireless communication terminal 1 performs transmission, the baseband processor 200 generates a baseband transmission signal by performing encoding or the like based on transmission data. The RFIC 100 receives a baseband transmission signal from the baseband processor 200 via the LVDS interface 100c. The transmission block 102 of the RFIC 100 upconverts the input baseband transmission signal to an RF frequency band, and the driver 106 amplifies the upconverted signal and outputs an RF transmission signal. The RF transmission signal output from the RFIC 100 is amplified by the HPA 204. This amplified RF transmission signal is input to the DPX 202 via the isolator 203, and transmitted from the DPX 202 to the base station or the like via the antenna 201.

  When the wireless communication terminal 1 performs reception, when the antenna 201 receives an RF reception signal from a base station or the like, it is demultiplexed by the DPX 202 and the RF reception signal is input to the RFIC 100. In the RFIC 100, the input RF reception signal is amplified by the LNA 103 and down-converted to a baseband reception signal in the baseband frequency band by the mixer 104. Further, the baseband received signal is subjected to predetermined signal processing by the BE 105 and then output to the baseband processor 200 via the LVDS interface 100c. The baseband processor 200 generates reception data by performing decoding or the like based on the baseband reception signal.

  FIG. 4 shows a frequency spectrum of a signal processed by the semiconductor device 100. 4A is a frequency spectrum of an input signal input from the LNA 103 to the mixer 104. FIG. 4B is a reception input from the local block (oscillator in the semiconductor device) used by the mixer 104 for multiplication. FIG. 4C shows the frequency spectrum of the local signal, and FIG. 4C shows the frequency spectrum of the output signal output from the mixer 104.

  As described above, in the W-CDMA modulation scheme, since the reception block 101 and the transmission block 102 operate simultaneously, the RF transmission signal leaks to the reception block 101. For this reason, as shown in FIG. 4A, the mixer 104 receives the RF reception signal having the frequency f_RX and the leak interference wave signal having the frequency f_TX superimposed on each other. The RF reception signal of the frequency f_RX has a bandwidth of 2 × f_BB (baseband frequency), and the leak interference wave signal of the frequency f_TX has a bandwidth of f_int.

  Further, as shown in FIG. 4B, the reception local signal having the frequency f_RX is input to the mixer 104. The mixer 104 outputs the signal of FIG. 4C in order to multiply the signal of FIG. 4A by the signal of FIG. 4B. As shown in FIG. 4C, an IM2 signal (IM2 component signal) having a frequency f_int is superimposed on a baseband signal having a bandwidth f_BB (0 to f_BB) and output.

  That is, since the RFIC 100 according to the present embodiment does not have a SAW filter, the leak interference wave signal from the antenna is directly input from the LNA 103 to the mixer 104, and a high-level IM2 signal is generated at the mixer stage. As a result, the reception sensitivity deteriorates. In this embodiment, IM2 correction (IM2 calibration) is performed to reduce the generation of IM2 signals.

  Hereinafter, the configuration and operation for performing IM2 correction in the present embodiment will be described. FIG. 5 mainly shows the configuration of the reception block 101 in the semiconductor device (RFIC) according to the present embodiment. The LNA 103, the mixer 104, and the BE 105 illustrated in FIG. 3 respectively correspond to the LNA 111, the mixer 113, and the logic unit 142 (including the MPU 130) illustrated in FIG.

  As shown in FIG. 5, the RFIC 100 according to the present embodiment includes a reception analog unit 110, an IM2 correction circuit 120, an MPU (Micro Processing Unit) 130, an ADC 141, a logic unit 142, a DCOC control unit 143, a reception DCO (RXDCO: A digitally controlled oscillator 151, a divider 152, a transmission DCO (TXDCO) 153, and a system clock oscillator 154.

  The reception analog unit 110 directly down-converts the received RF reception signal to generate and output an analog baseband reception signal. The reception analog unit 110 includes an LNA 111, a switch circuit 112, a mixer 113, a PMA 114, an LPF 115, and a PGA 116. The IM2 correction circuit 120 includes a test signal generation unit 122 and an IM2 tuning unit 121. The MPU 130 includes a RAM (Random Access Memory) 132 and a CPU (Central Processing Unit) 131.

  The LNA 111 receives an RF reception signal received from the antenna 201 via the DPX 202, amplifies the input RF reception signal with low noise, and outputs the amplified signal. The gain of the LNA 111 is appropriately set by the baseband processor 200.

  The switch circuit 112 switches the signal input to the mixer 113 to either the RF reception signal output from the LNA 111 or the test signal output from the IM2 correction circuit 120 (test signal generation unit 122). The switch circuit 112 switches a signal to be down-converted by the mixer 113 in accordance with a test enable signal input from the logic unit 142 or the baseband processor 200. The switch circuit 112 connects the LNA 111 and the mixer 113 when processing the RF reception signal received by the antenna 201. When performing the IM2 correction using the test signal generated by the IM2 correction circuit 120, the switch circuit 112 connects the IM2 correction circuit 120 and the mixer 113. Connecting.

  During a normal transmission / reception operation, the mixer 113 receives an RF reception signal amplified by the LNA 111 via the switch circuit 112, multiplies the input RF reception signal by the reception local signal, and generates a baseband frequency band. Downconvert to baseband received signal (baseband signal at reception) and output. The mixer 113 is an orthogonal demodulator, and generates Ich and Qch baseband signals based on the RF reception signal and the reception local signal. Hereinafter, baseband signals (baseband received signals) processed by the mixer 113 and later include Ich and Qch signals. Further, the mixer 113 receives the test signal generated by the IM2 correction circuit 120 during the IM2 correction via the switch circuit 112, and multiplies the input test signal by the received local signal to obtain the baseband frequency band. Downconverted to a signal (baseband signal at the time of test) including the IM2 signal and output.

  The mixer 113 corrects the IM2 characteristic according to the tuning signal input from the IM2 correction circuit 120 (IM2 tuning unit 121). By tuning the differential mismatch of the mixer 113 that has the largest contribution to the generation of the IM2 signal in the reception analog unit 110, IM2 correction is effectively performed. That is, generally, the IM2 component is generated by the nonlinearity of the mixer 113, and in particular, the IM2 characteristic is deteriorated by the unbalance of the differential pair constituting the mixer 113. Therefore, the differential pair can be adjusted by adjusting the circuit parameters of the differential pair. Is corrected, and the IM2 component is reduced. In this embodiment, the back gate voltage of the differential pair is adjusted by the tuning signal. Note that the differential pair may be adjusted by other circuit parameters such as a load resistance value and a bias value.

  The reception local signal input to the mixer 113 is generated by dividing the reception clock generated from the reception DCO 151 by the frequency divider 152. The reception DCO 151 includes a reception PLL (Phase Locked Loop) 151 a and outputs a reception clock having a frequency based on the lock frequency of the reception PLL 151 a to the frequency divider 152.

  A PMA (Post mixer Amp) 114 receives a baseband signal at the time of reception or test when the mixer 113 downconverts, and amplifies the input signal. The gain of the PMA 114 is appropriately set by the baseband processor 200. An LPF (Low Path Filter) 115 removes the high frequency component of the baseband signal amplified by the PMA 114 at the time of reception or test and outputs the result.

  A PGA (Programmable Gain Amp) 116 receives a baseband signal that is amplified by the PMA 114 and passes through the LPF 115 and is received or tested, and further amplifies the input signal. The gain of the PGA 116 is appropriately set by the baseband processor 200. Further, the PGA 116 reduces the DC (direct current) offset according to the DC offset control signal input from the DCOC control unit 143. By reducing the DC offset, the output signal of the PGA 116 is set within the dynamic range of the ADC 141 at the subsequent stage.

  The test signal generation unit 122 generates a test signal for performing IM2 correction and outputs the test signal to the switch circuit 112. The test signal is a signal for generating the IM2 signal (baseband signal at the time of test) in the reception analog unit 110 and detecting the IM2 signal in the logic unit 142. The test signal is a two-tone signal corresponding to the leak interference signal (f_TX signal) in FIG. 4A in order to generate the IM2 signal in a pseudo manner for the test. The test signal generation unit 122 includes an ICMIX (IC mixer) 122a, and multiplies the transmission local signal (frequency f_TX) output from the transmission DCO 153 by the system clock (frequency f_int) output from the system clock oscillator 154. A two-tone signal is generated.

  The IM2 tuning unit 121 generates a tuning signal for reducing the IM2 component for the mixer 113. The IM2 tuning unit 121 generates a tuning signal (back gate voltage) for controlling the back gate of the differential pair of the mixer 113 according to the correction parameter input from the logic unit 142. That is, the IM2 tuning unit 121 converts the correction parameter input from the logic unit 142 into a tuning signal for tuning the operation of the mixer 113.

  The DCOC control unit 143 generates a DC offset control signal for reducing the DC offset for the PGA 116. The DCOC control unit 143 generates a DC offset control signal according to the offset parameter input from the logic unit 142. That is, the DCOC control unit 143 converts the offset parameter input from the logic unit 142 into a DC offset control signal for reducing the DC offset.

  The ADC (A / D converter) 141 converts the analog baseband signal (during reception or test) down-converted by the reception analog unit 110 into a digital signal for processing by the logic unit 142 and outputs the digital signal.

  The logic unit 142 receives a digital baseband signal (during reception or test) that is A / D converted by the ADC 141, performs digital signal processing on the input signal, and outputs the digital signal to the baseband processor 200.

  The logic unit 142 detects the level (IM2 value) of the IM2 signal generated by the reception analog unit 110 from the test signal when IM2 is corrected (during testing), and reduces the IM2 signal based on this detection. The correction parameter is calculated, and the calculated correction parameter is set in the IM2 correction circuit 120. The calculation of the correction parameter is performed by the CPU 131 and the RAM 132 of the MPU 130. As described later, a correction parameter for reducing the IM2 signal can be obtained by detecting and comparing a plurality of IM2 values.

  Furthermore, at the time of DC offset correction (at the time of DC offset calibration), the logic unit 142 calculates a correction parameter for reducing the DC offset based on the level of the baseband received signal, and the calculated correction parameter is used as the DCOC control unit. Set to 143. The calculation of this parameter is performed by the CPU 131 and the RAM 132 of the MPU 130.

  FIG. 6 mainly shows an example of the circuit configuration of the mixer 113, the switch circuit 112, and the IM2 tuning unit 121 in the semiconductor device (RFIC) according to the present embodiment.

  As shown in FIG. 6, the mixer 113 includes a first differential pair (differential circuit, differential transistor) 113a and a second differential pair 113b. The first differential pair 113a includes NMOS (N-channel Metal Oxide Semiconductor) transistors N11 and N12, and the second differential pair 113b includes N21 and N22.

  The sources of the NMOS transistors N11 and N12 are commonly connected to the node A11. The node A11 is a first input terminal of the mixer 113 and is connected to the switch circuit 112. Similarly, the sources of the NMOS transistors N21 and N22 are commonly connected to the node A21. The node A 21 is a second input terminal of the mixer 113 and is connected to the switch circuit 112.

  The drains of the NMOS transistors N11 and N22 are commonly connected to the node A12. The node A12 is a first output terminal that outputs a first baseband signal (MIXout_T), and is connected to the PMA 114. Similarly, the drains of the NMOS transistors N12 and N21 are commonly connected to the node A22. The node A22 is a second output terminal that outputs a second baseband signal (MIXout_B), and is connected to the PMA 114.

  The first reception local signal (RX_Local_T) is commonly input from the reception DCO 151 and the frequency divider 152 to the gates of the NMOS transistors N11 and N21. Similarly, the second reception local signal (RX_Local_B) is commonly input from the reception DCO 151 and the frequency divider 152 to the gates of the NMOS transistors N12 and N22.

  By the NMOS transistors N11, N12, N21, and N22, the RF reception signal or test signal (LNAout_B or ICMIXout_T) input to the node A11, the RF reception signal and test signal (LNAout_T or ICMIXout_B) input to the node A21, and reception local Multiplies the signals (RX_Local_T, RX_Local_B) and outputs baseband signals (MXout_T, MXout_B).

  The back gates of the NMOS transistors N11 and N22 are commonly connected to the node A13. The node A13 is a first tuning terminal of the mixer 113 and is connected to the IM2 tuning unit 121 via the capacitor C1. Similarly, the back gates of the NMOS transistors N12 and N21 are commonly connected to the node A23. The node A23 is a second tuning terminal of the mixer 113, and is connected to the IM2 tuning unit 121 via the capacitor C2. In the NMOS transistors N11, N12, N21, and N22, the mismatch (unbalance) of the differential pair is adjusted by a tuning signal (back gate voltage) supplied to the nodes A13 and A23.

  As shown in FIG. 6, the switch circuit 112 includes a first switch input unit 112a that inputs an RF reception signal and a second switch input unit 112b that inputs a test signal. The first switch input unit 112a includes PMOS transistors P31 and P32. The second switch input unit 112b includes NMOS transistors N31 and N32.

  In the PMOS transistor P31, the first RF reception signal (LNAout_T) is input from the LNA 111 to the drain, and the source is connected to the node A21 of the mixer 113. In the PMOS transistor P32, the second RF reception signal (LNAout_B) is input from the LNA 111 to the drain, and the source is connected to the node A11 of the mixer 113.

  In the NMOS transistor N31, the first test signal (ICMIXout_T) is input from the ICMIX 122a to the source, and the drain is connected to the node A11 of the mixer 113. In the NMOS transistor N32, the second test signal (ICMIXout_B) is input from the ICMIX 122a to the source, and the drain is connected to the node A21 of the mixer 113.

  A test enable signal (test signal enable bit) is commonly input from the logic unit 142 or the baseband processor 200 to the gates of the PMOS transistors P31 and P32 and the NMOS transistors N31 and N32. The test enable bit is a bit for switching a signal input to the mixer 113, and is also a bit for inputting a test signal to the mixer 113 for IM2 correction. In this example, the test signal enable bit is 1 bit, and the PMOS transistors P31 and P32 and the NMOS transistors N31 and N32 are turned on / off according to the test signal enable bit “0” (low) or “1” (high). The signal to be input to the mixer 113 is switched off.

  When the test signal enable bit is “0”, the PMOS transistors P31 and P32 are turned on and the NMOS transistors N31 and N32 are turned off, so that the first RF reception signal (LNAout_T) is input to the node A21 of the mixer 113, and 2 RF reception signals (LNAout_B) are input to the node A 11 of the mixer 113. When the test signal enable bit is “1”, the PMOS transistors P31 and P32 are turned off and the NMOS transistors N31 and N32 are turned on. Therefore, the first test signal (ICMIXout_T) is input to the node A11 of the mixer 113, and the second Test signal (ICMIXout_B) is input to the node A21 of the mixer 113.

  As shown in FIG. 6, the IM2 tuning unit 121 includes a back gate pair selection unit 121a and a back gate tuning unit 121b. The back gate pair selection unit 121a includes NMOS transistors N41 and N42 and PMOS transistors P41 and P42. The back gate tuning unit 121b includes NMOS transistors N101 to N116 and resistors R101 to R116.

  In the back gate pair selection unit 121a, the drain of the NMOS transistor N41 and the source of the PMOS transistor P41 are commonly connected to the node A13 of the mixer 113 via the capacitor C1, the source of the NMOS transistor N41 is connected to GND, and the PMOS transistor P41. Are connected to the node A30. The node A30 is an output terminal for outputting a back gate voltage to the mixer 113. The drain of the NMOS transistor N42 and the source of the PMOS transistor P42 are commonly connected to the node A23 of the mixer 113 via the capacitor C2, the source of the NMOS transistor N42 is connected to the node A30, and the drain of the PMOS transistor P42 is connected to GND. The

  A back gate pair control signal (back gate pair control bit) is commonly input from the logic unit 142 to the gates of the NMOS transistors N41 and N42 and the PMOS transistors P41 and P42. The back gate pair control bit is a bit for selecting a transistor for tuning the back gate voltage, and is also a bit indicating positive / negative of a correction parameter set by the logic unit 142. In this example, the back gate pair control bit is 1 bit, and the NMOS transistors N41 and N42 and the PMOS transistors P41 and P42 are turned on according to “0” (low) or “1” (high) of the back gate pair control bit. Turn on / off and switch transistor to tune back gate voltage.

  When the back gate pair control bit is “0”, the NMOS transistors N41 and N42 are turned off and the PMOS transistors P41 and P42 are turned on. Therefore, the node A13 of the mixer 113 is connected to the node A30, and the node A23 of the mixer 113 is connected to the GND. Connected to. For this reason, the back gates of the NMOS transistors N11 and N22 of the mixer 113 are controlled by the voltage generated by the back gate tuning unit 121b.

  When the back gate pair control bit is “1”, the NMOS transistors N41 and N42 are turned on and the PMOS transistors P41 and P42 are turned off. Therefore, the node A23 of the mixer 113 is connected to the node A30, and the node A13 of the mixer 113 is connected to the GND. Connected to. For this reason, the back gates of the NMOS transistors N12 and N21 of the mixer 113 are controlled by the voltage generated by the back gate tuning unit 121b.

  In the back gate tuning unit 121b, resistors R11 to R26 are connected in series between the power supply (VDD) and GND. NMOS transistors N101 to N116 are connected between each node between the resistors R11 to R26 and the node A30, respectively. That is, the drains of the NMOS transistors N101 to N116 are commonly connected to the node A30. The source of the NMOS transistor N101 is connected to GND, the source of the NMOS transistor N102 is connected between the resistors R11 and R12, and the source of the NMOS transistor N103 is connected between the resistors R12 and R13. Similarly, the sources of the NMOS transistors N104 to N116 are connected between the resistors R13 to R26, respectively.

  A back gate tuning signal (back gate tuning bit) is commonly input from the logic unit 142 to the gates of the NMOS transistors N101 to N116. The back gate tuning bit is a bit for setting the back gate voltage output to the mixer 113 and is a correction parameter set by the logic unit 142. In this example, the back gate tuning bits are 4 bits, and the values “0” to “15” represented by these 4 bits correspond to the NMOS transistors N101 to N116, respectively. For example, correction parameters of “−15” to “+15” can be set by 5 bits including a 1-bit back gate pair control bit and a 4-bit back gate tuning bit.

  When the back gate tuning bit is “0”, the NMOS transistor N101 is turned on and the other NMOS transistors are turned off, so that the node A30 is connected to GND. Therefore, the back gate voltage supplied to the node A13 or A23 is 0V.

  When the back gate tuning bit is “1”, the NMOS transistor N102 is turned on and the other NMOS transistors are turned off, so that the node A30 is connected between the resistor R11 and the resistor R12. Therefore, the back gate voltage supplied to the node A13 or A23 is 0.03125V by dividing the power supply voltage 1.2V by the resistor R11 and the resistors R12 to R26.

  When the back gate tuning bit is “2”, the NMOS transistor N103 is turned on and the other NMOS transistors are turned off, so that the node A30 is connected between the resistor R12 and the resistor R13. Therefore, the back gate voltage supplied to the node A13 or A23 is 0.0625V by dividing the power supply voltage 1.2V by the resistors R11 to R12 and the resistors R13 to R26. Similarly, when the back gate tuning bit is “3”, only the NMOS transistor N104 is turned on, and the power supply voltage 1.2V is divided by the resistors R11 to R13 and the resistors R14 to R26 to become 0. 09375V. When the back gate tuning bit is “15”, only the NMOS transistor N116 is turned on, and the back gate voltage becomes 0.5 V by dividing the power supply voltage 1.2V by the resistors R11 to R25 and the resistor R26.

  FIG. 7 shows the IM2 correction timing of the semiconductor device (RFIC) according to this embodiment. First, when the power of the wireless communication terminal 1 (RFIC 100) is turned on at time T0, the RFIC 100 performs a power-on operation. Within this power-on operation, the RFIC 100 performs IM2 correction (S11). The switch circuit 112 switches to connect the mixer 113 and the test signal generation unit 122 in accordance with an instruction from the baseband processor 200, and supplies the test signal generated by the test signal generation unit 122 to the mixer 113. The logic unit 142 detects the IM2 signal output from the reception analog unit 110 according to the test signal, calculates the optimum value of the correction parameter, sets it in the IM2 tuning unit 121, and stores the optimum value in the RAM 132.

  When the IM2 correction in the power-on operation is completed, the RFIC 100 performs a normal transmission / reception operation (normal operation) with the base station or the like at times T1 to T2. The switch circuit 112 switches so that the mixer 113 and the LNA 111 are connected in accordance with an instruction from the baseband processor 200, and supplies an RF reception signal from the LNA 111 to the mixer 113. The mixer 113 outputs a baseband received signal in which the differential pair is appropriately tuned by the correction parameter set in S11 and the IM2 component is reduced. The logic unit 142 performs predetermined signal processing on the baseband received signal with the IM2 component reduced, and outputs the signal to the baseband processor 200.

  The warm-up operation is performed at time T3 when the sleep time elapses after time T2. Within this warm-up operation, the RFIC 100 further performs IM2 correction (IM2 re-correction, IM2 recalibration) (S12).

  When the transmission / reception operation is completed, the RFIC 100 enters a sleep state according to an instruction from the baseband processor 200 at time T2. For example, the RFIC 100 stops a predetermined circuit operation in order to reduce power consumption. Thereafter, when the sleep time elapses, the RFIC 100 is released from the sleep state in accordance with an instruction from the baseband processor 200 at time T2, and performs a warm-up operation to start a transmission / reception operation. The warm-up operation is an operation for the RFIC to transition from a sleep state to a normal transmission / reception operation (normal operation), and activates a circuit that has been stopped in the sleep state.

  In the warm-up operation, the switch circuit 112 switches to connect the mixer 113 and the test signal generation unit 122 according to an instruction from the baseband processor 200 and supplies the test signal generated by the test signal generation unit 122 to the mixer 113. . The logic unit 142 detects the IM2 signal output from the reception analog unit 110 according to the test signal, recorrects the correction parameter based on the optimum value stored in S11 at the time of power-on, and sets the IM2 tuning unit 121. The correction value is stored in the RAM 132.

  When the IM2 correction in the warm-up operation is completed, a normal transmission / reception operation is performed with the base station or the like at times T4 to T5. Thereafter, the RFIC 100 repeatedly executes a sleep operation, a warm-up operation, and a transmission / reception operation, and repeats IM2 correction during the warm-up operation (S13). In S13, the logic unit 142 detects the IM2 signal output from the reception analog unit 110 in response to the test signal, re-corrects the correction parameter based on the correction value stored in S12 at the previous warm-up, and then IM2 The correction value is set in the tuning unit 121 and stored in the RAM 132.

  As shown in FIG. 7, in the present embodiment, IM2 correction is performed at power-on, and IM2 correction (IM2 re-correction) is also performed during subsequent warm-up. Thereby, even when the IM2 characteristics fluctuate due to changes in the environment such as temperature, the IM2 correction can be performed appropriately.

  The graph of FIG. 8 shows the temperature dependence of the IM2 characteristic. In the IM2 characteristic graph of FIG. 8, the vertical axis indicates the level of the IM2 signal (IM2 component) generated by the RFIC, and the horizontal axis indicates the value of the correction bit (correction parameter) given to the IM2 tuning unit. This correction bit is the back gate tuning bit (including the back gate pair control bit) of FIG.

  As shown in FIG. 8, the IM2 characteristic for the correction bit is a substantially V-shaped curve, and the point with the lowest IM2 signal level is the optimal point for correction. In the high temperature characteristic 301, the point 304 is the optimum correction point because the IM2 signal is the lowest, and S1 at this time is the optimum correction value. The reference value 303 is a product specification value, and the IM2 signal needs to be equal to or less than the reference value 303 in order to satisfy the product specification. When the correction is performed with the correction value S1 at a high temperature, the IM2 signal is the reference value 303, which satisfies the product specification.

  On the other hand, the characteristic 302 at the low temperature is a characteristic shifted to the left side (the side where the correction parameter becomes smaller) on the characteristic graph as compared with the characteristic 301 at the high temperature. In the low temperature characteristic 302, the point 306 is the optimum correction point because the IM2 signal is the lowest, and S2 at this time is the optimum correction point. That is, when the temperature decreases, the characteristic curve moves in a direction in which the correction bit becomes smaller than at the high temperature as in the characteristic 302, so that the correction optimum point moves from S1 to S2.

  Therefore, after the IM2 correction is performed with the correction value S1 in the high temperature state, when the temperature decreases, the IM2 characteristic changes from the characteristic 301 to the characteristic 302, so that the level of the IM2 signal rises to the point 305. For this reason, the reception sensitivity is deteriorated by the IM2 signal, and the IM2 signal is larger than the reference value 303, so that the product specification is not satisfied.

  In this embodiment, after performing IM2 correction at power-on, IM2 correction is also performed during warm-up. Thereby, even if the IM2 characteristic changes due to the temperature, the correction value is changed from S1 to S2 so that the IM2 signal decreases from the point 305 to the point 306. Therefore, since the IM2 correction is appropriately performed, the reception sensitivity is improved and the product specification is satisfied.

  Even when the temperature changes from a low temperature to a high temperature, similarly, the correction value can be appropriately set by performing the IM2 correction again. Further, since the IM2 characteristics vary from one semiconductor device to another, there is no regularity in the direction and degree of temperature dependence. Therefore, depending on the temperature, the amount of characteristic variation differs depending on the temperature and the direction of characteristic variation differs depending on the temperature depending on the semiconductor device. Even in this case, the IM2 signal is appropriately corrected by performing IM2 correction again. Can be reduced.

  FIG. 9 shows an IM2 correction operation at power-on in the semiconductor device (RFIC) according to the present embodiment. This operation is mainly executed by the logic unit 142 and the MPU 130 of the RFIC 100. The RFIC 100 includes a storage unit that stores a program for IM2 correction. The CPU 131 loads this program into the RAM 132, and the CPU 131 executes the program loaded into the RAM 132, thereby realizing the following operations. FIG. 9 shows the operation of S11 shown in FIG. 7, and the RFIC 100 starts the IM2 correction operation as follows during the power-on operation.

  First, the CPU 131 sets the correction parameter (X) to a default value (m = 0) in order to tune the IM2 signal to the minimum value (S101). As shown in FIG. 8, since the IM2 characteristic is substantially V-shaped with respect to the correction parameter, the correction parameter (correction bit) is initialized to 0 (minimum value) and sequentially increased to obtain the optimum point. By detecting the IM2 value from the minimum value toward the maximum value, the most appropriate correction parameter can be obtained. Note that the correction parameter may be initialized to the maximum value and sequentially decreased to obtain the optimum point.

  Here, the correction parameter (X) is a correction bit (back gate tuning bit) set from the logic unit 142 to the IM2 tuning unit 121. “m” is a variable that is stored in the RAM 132 and is set to the correction parameter (X).

  Next, the IM2 value (the magnitude of the IM2 signal) at each of the set points X (= m) and X + 1 is detected by the logic unit 142, and the CPU 131 compares the two IM2 values (S102). Here, the IM2 value in the case of the correction parameter (X) is represented as IM2 (X).

  In order to generate the IM2 signal of the set point X (m = 0), the CPU 131 notifies the logic unit 142 of the set point X, and the logic unit 142 sets the correction parameter (X = 0) in the IM2 tuning unit 121. The back gate of the differential pair of the mixer 113 is controlled from the IM2 tuning unit 121 by this correction parameter (X = 0). Then, the logic unit 142 detects IM2 (X = 0) of the IM2 signal generated in the reception analog unit 110 corresponding to the correction parameter (X = 0). Next, the CPU 131 shifts m = 0 by 1 LSB (bit) to increase by 1 to m = 1, sets a correction parameter (X = 1) from the logic unit 142, and sets the correction parameter (X = 1). Detect IM2 (X = 1) of the corresponding IM2 signal. Further, the CPU 131 compares the detected IM2 (X = 0) with IM2 (X = 1).

  As a result of comparing IM2 (X) and IM2 (X + 1) in S102, if IM2 (X)> IM2 (X + 1) (S103), the CPU 131 updates (increments) to m = m + 1 (S104). . Thereafter, in S102, IM2 (X) in which the updated m is set is compared with IM2 (X + 1), and the correction parameter is swept (changed) until IM2 (X) <IM2 (X + 1).

  As a result of comparing IM2 (X) and IM2 (X + 1) in S102, if IM2 (X) <IM2 (X + 1) (S105), the IM2 correction parameter is set to X (S106), and m is stored in the RAM 132. (S107). The CPU 131 notifies the current m to the logic unit 142 as the optimum point X, and the logic unit 142 sets the correction parameter (X = m) in the IM2 tuning unit 121. By this correction parameter (X = m), the back gate of the differential pair of the mixer 113 is controlled from the IM2 tuning unit 121, and the IM2 signal is set to be the lowest. Further, the CPU 131 stores m in the RAM 132 when IM2 (X) <IM2 (X + 1), so that it can be used for IM2 correction during warm-up.

  Note that when IM2 (X) = IM2 (X + 1), the minimum values are considered to be continuous, so the operations of S103 to S104 may be performed, or the operations of S105 to S107 may be performed.

  FIG. 10 shows the detailed timing of the IM2 correction operation at the time of power-on shown in FIG. As shown in FIG. 10, in the IM2 correction operation at power-on, DC offset correction (DCOC), IM2 setting (setting of the IM2 correction circuit 120), and IM2 detection are performed. Further, since it is necessary to correct two channels of Ich and Qch for one frequency band, IM2 setting and IM2 detection are performed twice. Note that the IM2 detection time in FIG. 10 is the time for detecting the IM2 signal in order to perform IM2 correction in FIG. That is, the operation in FIG. 9 is executed at the timing of IM2 detection in FIG.

  Here, IM2 setting time = digital setting time (10 usec) for initial setting of the digital circuit of the IM2 correction circuit 120 + rise time (20 usec) of the IM2 correction circuit 120 = 30 usec, and DC offset correction time = 25 usec.

  The correction time at power-on depends on the number of bits of the correction parameter and the number of averages when IM2 is detected, but if the correction parameter is 6 bits (= 64 LSB) and the number of averages is 60 times (about 4 usec), IM2 detection of 1ch (IM2 correction) time is 4 usec * 64 = 256 usec.

  Therefore, as shown in FIG. 10, DC offset time + (IM2 setting time + IM2 detection time) * 2 = 25 + (30 + 256) * 2 = 597, and the IM2 correction time at the time of power-on for one band is about 600 usec as a whole. It becomes.

  FIG. 11 shows an IM2 correction operation during warm-up in the semiconductor device (RFIC) according to the present embodiment. This operation is executed mainly by the logic unit 142 and the MPU 130 of the RFIC 100 as in FIG. 9, and the following operation is realized by the CPU 131 executing the IM2 correction program. FIG. 11 shows operations in S12 and S13 shown in FIG. As shown in FIG. 7, after the power-on operation, the transmission / reception operation and the sleep operation are repeated, and the RFIC 100 starts the IM2 correction operation at the time of the warm-up operation between the sleep operation and the transmission / reception operation as follows.

  First, the CPU 131 sets the stored value m of the RAM 132 as the correction parameter (X) (S201). It is possible to simplify the correction operation by setting the optimum value m stored when the IM2 correction is performed at the time of power-on or the previous warm-up to the initial value.

  Next, the IM2 values of the set points X (= m) and X + 1 are detected by the logic unit 142, and the CPU 131 compares the two IM2 values (S202). In order to generate the IM2 signal of the set point (X = m), the CPU 131 notifies the logic unit 142 of the set point X, and the logic unit 142 sets the correction parameter (X) in the IM2 tuning unit 121. The back gate of the differential pair of the mixer 113 is controlled from the IM2 tuning unit 121 by the correction parameter (X). Then, the logic unit 142 detects IM2 (X = m) of the IM2 signal generated in the reception analog unit 110 corresponding to the correction parameter (X = m). Next, the CPU 131 shifts m by 1 LSB (bit) to increase by 1 to m = m + 1, sets the correction parameter (X + 1) from the logic unit 142, and sets the IM2 signal IM2 corresponding to the correction parameter (X + 1) (X + 1) is detected. Further, the CPU 131 compares the detected IM2 (X) with IM2 (X + 1).

  In this example, IM2 (X) and IM2 (X + 1) are compared, but IM2 (X) and IM2 (X-1) may be compared. Further, not limited to X + 1, it may be X + 2 or X + n (arbitrary integer). n is a correction unit for performing correction according to the correction parameter. For example, n may be set according to the interval and frequency of correction. When n = 1 is set as in the present embodiment, the fine adjustment can be performed in the finest units, so that IM2 correction can be performed with high accuracy.

  As a result of comparing IM2 (X) and IM2 (X + 1) in S202, if IM2 (X)> IM2 (X + 1) (S203), the IM2 correction parameter is set to X + 1 (S204), and m + 1 is stored in the RAM 132. (S205). Here, when IM2 (X + 1) is smaller than IM2 (X), X + 1 is set as the optimum point (correction point).

  The CPU 131 notifies the logic unit 142 of X + 1 as the optimum point, and the logic unit 142 sets the correction parameter (X + 1) in the IM2 tuning unit 121. By this correction parameter (X + 1), the back gate of the differential pair of the mixer 113 is controlled from the IM2 tuning unit 121, and the IM2 signal is set to be lower than IM2 (X). Further, the CPU 131 stores m + 1 corresponding to IM2 (X + 1) in the RAM 132 for use in IM2 correction at the next warm-up.

  As a result of comparing IM2 (X) and IM2 (X + 1) in S202, if IM2 (X) <IM2 (X + 1) (S206), the IM2 correction parameter is set to X (S207), and m−1. Is stored in the RAM 132 (S208). Here, when IM2 (X) is smaller than IM2 (X + 1), X is set as the optimum point (correction point).

  The CPU 131 notifies the logic unit 142 of X as the optimum point, and the logic unit 142 sets the correction parameter (X) in the IM2 tuning unit 121. Accordingly, the IM2 signal is set to be lower than IM2 (X + 1). Further, the CPU 131 stores m−1 in the RAM 132 for use in IM2 correction at the next warm-up. M corresponding to IM2 (X) may be stored in the RAM 132. However, by storing m-1, correction is performed from the point of m-1 at the next warm-up, so the correction parameter is further reduced. It becomes possible.

  When IM2 (X) = IM2 (X + 1), since the same value is set, the operations from S203 to S205 may be performed, or the operations from S206 to S08 may be performed.

  FIG. 12 shows the detailed timing of the IM2 correction operation during warm-up shown in FIG. As shown in FIG. 12, in the IM2 correction operation during warm-up, DC offset correction (DCOC), IM2 setting (setting of the IM2 correction circuit 120), and IM2 detection are performed. Note that the IM2 detection time in FIG. 12 is the time for detecting the IM2 signal in order to perform IM2 correction in FIG. That is, the operation in FIG. 11 is executed at the timing of IM2 detection in FIG.

  Here, the IM2 setting time and the DC offset time are 30 usec and 25 usec, as in FIG. As shown in FIG. 11, at the time of warm-up, the optimum correction value m stored in the RAM 132 is read, and IM2 (X) based on the correction parameter (X = m) and IM2 (X + 1) based on the correction parameter (X + 1). Therefore, the IM2 detection (IM2 correction) time is 8 usec (= 4 usec * 2). Accordingly, the total IM2 correction time during warm-up is IM2 setting time + DC offset time + IM2 detection time = 30 + 25 + 8 = 63 usec. By simplifying the IM2 detection to two points, the IM2 correction time can be shortened to about 1/10 compared to 600 usec during warm-up in FIG.

  Also, as shown in FIG. 12, at the time of warm-up, the reception PLL 151a in the reception DCO 151 performs a lock-up operation and locks to a desired lock frequency. In order to receive and down-convert the RF reception signal, the reception PLL 151a that generates the reception local signal needs to be locked. For this reason, after the reception PLL lockup time necessary for locking the reception PLL has elapsed, the signal processing of the reception signal is started in the logic unit 142 and the baseband processor 200.

  The timing for starting IM2 detection (IM2 correction) is preferably after the reception PLL 151a is locked (after completion of locking). If the reception PLL 151a is locked, the IM2 signal can be detected in the same state as when the RF reception signal is received, so that IM2 correction can be performed with high accuracy. By starting IM2 detection immediately before the start of transmission / reception operation (normal operation), IM2 correction can be performed with the reception PLL locked as much as possible.

  For example, the reception PLL lockup time is a time set in advance according to the specification of the PLL, and includes a predetermined margin. Then, since the reception PLL 151a is generally locked before the reception PLL lockup time elapses, IM2 detection may be started before the reception PLL lockup time elapses. In this case, since the reception PLL is locked or almost locked, IM2 correction can be performed with high accuracy. In addition, by making the reception PLL lockup time (warmup time) and the IM2 detection time end at the same timing or almost the same timing, useless time until the transmission / reception operation is started can be reduced.

  Further, as shown in FIG. 13, the reception PLL 151a locks the frequency with the passage of time. That is, when the reception PLL 151a starts operation (power supply), the reception PLL 151a starts a lock-up operation and brings the local frequency (PLL output frequency) closer to the lock frequency. Here, assuming that the lock-up time of the reception PLL 151a is 160 usec, the local frequency rises to the vicinity of the lock frequency after 25 usec has elapsed since the start of the operation of the reception PLL 151a.

  After the elapse of 100 usec from the start of the operation of the reception PLL 151a, the frequency difference (frequency deviation) from the lock frequency is as very small as 1 / million (1 ppm). Even if IM2 detection is performed at this timing, the lockup time ( The difference from the IM2 correction result after elapse of 160 usec) is small. For this reason, it is preferable to start IM2 detection after the elapse of 100 usec (62.5% of the lock-up time) from the start of operation of the reception PLL 151a, or when the frequency difference is about 1 / million (1 ppm).

  Furthermore, after 152 usec has elapsed since the start of the operation of the reception PLL 151a, the frequency difference from the lock frequency is as small as about 0.15 ppm, and even if IM2 detection is performed at this timing, the influence on the IM2 correction result is very small. For this reason, it is more preferable to start IM2 detection after 152 usec has elapsed (95% of the lock-up time) from the start of operation of the reception PLL 151a, or when the frequency difference is about 0.15 ppm.

  For this reason, in the present embodiment, IM2 detection is started 152 usec after the start of operation of the reception PLL 151a as shown in FIG. Note that even if the setting of the IM2 correction circuit 120 and the DC offset correction are performed when the reception PLL is not sufficiently locked, the IM2 correction result is not affected.

  As shown in FIG. 12, IM2 setting (digital setting of IM2 correction circuit 120 and circuit startup operation) is started up after 97 usec from the start of operation of reception PLL 151a. After 30 usec, the IM2 setting is completed, and the differential DC offset value generated by connecting (switching on) the path between the IM2 correction circuit 120 and the reception analog unit 110 is corrected. After 25 usec, the DC offset operation ends and IM2 detection (IM2 correction) is performed. As described above, IM2 detection (IM2 correction) ends after 8 usec. At this timing, the reception PLL lock-up time is also ended, and signal processing is started.

  As described above, since the IM2 characteristic varies depending on the temperature, the IM2 correction is performed again in accordance with the variation of the optimum point. However, since the test signal is input to the reception analog unit 110 during the IM2 correction, the IM2 correction and the actual operation of receiving the RF reception signal cannot be performed in parallel. For this reason, in this embodiment, IM2 correction is performed during warm-up before the start of normal transmission / reception operation.

  Further, if IM2 correction is performed strictly, 600 usec / band is required as shown in FIG. 10, and it is difficult to secure such a time other than when the power is turned on. For this reason, in this embodiment, IM2 correction time is shortened by simplifying IM2 detection to two points, and IM2 correction is performed during reception PLL lockup during warm-up.

  As described above, in the present embodiment, IM2 correction is performed at power-on, and IM2 correction is performed again at warm-up. Therefore, the IM2 correction parameter is appropriately updated at each warm-up. For this reason, since it is possible to follow fluctuations in the optimum correction point due to temperature changes, it is possible to perform IM2 correction with high accuracy and prevent deterioration in reception sensitivity. Therefore, unlike the conventional case, it is not necessary to consider the margin for the temperature characteristic deterioration in the IM2 specification, and it is possible to prevent the yield from being lowered. Furthermore, as described above, the IM2 correction time can be shortened by simplifying the IM2 correction operation during warm-up, so that IM2 correction can be performed effectively without affecting the reception operation.

(Embodiment 2)
The second embodiment will be described below with reference to the drawings. In the present embodiment, compared with the first embodiment, three IM2 values are detected in the IM2 correction operation during warm-up. Others are the same as those in the first embodiment, and thus description thereof will be omitted as appropriate.

  FIG. 14 shows an IM2 correction operation during warm-up in the semiconductor device (RFIC) according to the present embodiment. This operation is mainly executed by the logic unit 142 and the MPU 130 of the RFIC 100 as in FIG. 11, and the following operation is realized by the CPU 131 executing the IM2 correction program. The RFIC 100 starts the IM2 correction operation as follows during the warm-up operation (S12, S13) of FIG.

  First, the CPU 131 sets the stored value m of the RAM 132 as the correction parameter (X) (S301). Next, the IM2 values of the set point X (= m) and X + 1, X−1 are detected by the logic unit 142, and the CPU 131 compares the three IM2 values (S302). In order to generate the IM2 signal of the set point (X = m), the CPU 131 notifies the logic unit 142 of the set point X, and the logic unit 142 sets the correction parameter (X) in the IM2 tuning unit 121. The back gate of the differential pair of the mixer 113 is controlled from the IM2 tuning unit 121 by the correction parameter (X). Then, the logic unit 142 detects IM2 (X) of the IM2 signal generated in the reception analog unit 110 corresponding to the correction parameter (X = m). Next, the CPU 131 shifts m to 1 LSB (bit) plus side to increase by 1 to m = m + 1, sets the correction parameter (X + 1) from the logic unit 142, and sets IM2 corresponding to the correction parameter (X + 1). The signal IM2 (X + 1) is detected. Next, the CPU 131 shifts m to 1 LSB (bit) minus side to decrease by 1 to m = m−1, sets the correction parameter (X−1) from the logic unit 142, and sets the correction parameter (X− IM2 (X-1) of the IM2 signal corresponding to 1) is detected. Further, the CPU 131 compares IM2 (X), IM2 (X + 1), and IM2 (X−1). As in the first embodiment, not only X + 1 / X-1, but other X + n / X-n may be used.

  As a result of comparing IM2 (X), IM2 (X + 1), and IM2 (X-1) in S302, if IM2 (X + 1) is minimum (S303), the IM2 correction parameter is set to X + 1 (S304), m + 1 Is stored in the RAM 132 (S304). Here, when IM2 (X + 1) is the smallest among the three IM2 values, X + 1 is set as the optimum point (correction point).

  The CPU 131 notifies the logic unit 142 of X + 1 as the optimum point, and the logic unit 142 sets the correction parameter (X + 1) in the IM2 tuning unit 121. By this correction parameter (X + 1), the back gate of the differential pair of the mixer 113 is controlled from the IM2 tuning unit 121, and the IM2 signal is set to be lower than IM2 (X-1) and IM2 (X). Further, the CPU 131 stores m + 1 corresponding to IM2 (X + 1) in the RAM 132 for use in IM2 correction at the next warm-up.

  As a result of comparing IM2 (X), IM2 (X + 1), and IM2 (X-1) in S302, if IM2 (X) is minimum (S306), the IM2 correction parameter is set to X (S307), m Is stored in the RAM 132 (S308). Here, when IM2 (X) is the smallest among the three IM2 values, X is the optimum point (correction point).

  The CPU 131 notifies the logic unit 142 of X as the optimum point, and the logic unit 142 sets the correction parameter (X) in the IM2 tuning unit 121. Thereby, the IM2 signal is set to be lower than IM2 (X-1) and IM2 (X-1). Further, the CPU 131 stores m corresponding to IM2 (X) in the RAM 132 for use in IM2 correction at the next warm-up.

  In S302, if IM2 (X-1) is the minimum as a result of comparing IM2 (X), IM2 (X + 1), and IM2 (X-1) (S309), the IM2 correction parameter is set to X-1 ( S310), m-1 is stored in the RAM 132 (S311). Here, when IM2 (X-1) is the smallest among the three IM2 values, X-1 is set as the optimum point (correction point).

  The CPU 131 notifies the logic unit 142 of X-1 as the optimum point, and the logic unit 142 sets the correction parameter (X-1) in the IM2 tuning unit 121. Thereby, the IM2 signal is set to be lower than IM2 (X) and IM2 (X-1). Further, the CPU 131 stores m-1 corresponding to IM2 (X-1) in the RAM 132 for use in IM2 correction at the next warm-up.

  Note that when IM2 (X) = IM2 (X-1) = IM2 (X + 1), the same value is set, and therefore any operation of S303 to S305, S306 to S308, and S309 to S311 may be performed. .

  FIG. 15 shows the detailed timing of the IM2 correction operation during warm-up shown in FIG. As shown in FIG. 14, in the present embodiment, at the time of IM2 correction, IM2 (X) based on the correction parameter (X = m), IM2 (X + 1) based on the correction parameter (X + 1), and IM2 (X-1) based on the correction parameter (X-1) Since the three points X-1) are detected and compared, the IM2 detection (IM2 correction) time is 12 usec (= 4 usec * 3). Therefore, the total IM2 correction time during warm-up is IM2 setting time + DC offset time + IM2 detection time = 30 + 25 + 12 = 67 usec. Although it is longer than that in FIG. 12 of the first embodiment, the IM2 correction time can be greatly shortened by simplifying the IM2 detection to two points as compared with the warm-up in FIG.

  Further, in the present embodiment, IM2 detection is started after 148 usec from the start of operation of the reception PLL 151a as shown in FIG. As shown in FIG. 13, if 100 usec has elapsed after the operation of the reception PLL 151a has started, the reception PLL 151a is almost locked, and the IM2 correction result is not affected.

  As shown in FIG. 12, the IM2 setting (digital setting of the IM2 correction circuit 120 and the circuit rising operation) is started up after 93 usec from the start of the operation of the reception PLL 151a. After 30 usec, the IM2 setting is completed, and the differential DC offset value generated by connecting (switching on) the path between the IM2 correction circuit 120 and the reception analog unit 110 is corrected. After 25 usec, the DC offset operation ends and IM2 detection (IM2 correction) is performed. As described above, IM2 detection (IM2 correction) ends after 12 usec. At this timing, the reception PLL lock-up time is also ended, and signal processing is started.

  As described above, in the present embodiment, three points IM2 (X-1), IM2 (X), and IM2 (X + 1) are detected in IM2 correction during warm-up. Thereby, IM2 correction can be performed more accurately than in the first embodiment. That is, in the first embodiment, since only two IM2 values are detected, the IM2 correction time is the shortest. However, when the IM2 characteristic changes greatly, the number of warm-ups until the correction parameter is set to the optimum value. (Number of IM2 correction operations) increases. In the present embodiment, by detecting three IM2 values, the number of warm-ups (the number of IM2 correction operations) until the correction parameter is set to the optimum value when the IM2 characteristics fluctuate greatly is further reduced. be able to.

  In this embodiment, three IM2 values are detected. However, the correction accuracy may be further improved by detecting more IM2 values than three points and performing IM2 correction. That is, the IM2 detection may be started within a time period that does not affect the IM2 correction result within the lock-up time of the reception PLL, and therefore, for example, between 3 and 100 usec after the start of the operation of the reception PLL 151a. You may detect IM2 value more than a point.

(Embodiment 3)
The third embodiment will be described below with reference to the drawings. In the present embodiment, the semiconductor device further includes a temperature sensor as compared with the first and second embodiments. Since others are the same as those in the first and second embodiments, description thereof will be omitted as appropriate.

  FIG. 16 mainly shows the configuration of the reception block 101 in the semiconductor device (RFIC) according to the present embodiment. 16 further includes a temperature sensor 155 in addition to the RFIC 100 of FIG. 5 of the first embodiment.

  The temperature sensor 155 is an on-chip temperature sensor mounted on the RFIC 100. The temperature sensor 155 detects the temperature of the RFIC 100 and outputs the detected temperature (temperature data) to the logic unit 142. The logic unit 142 performs IM2 correction according to the detected temperature. In the present embodiment, the temperature change from the temperature when IM2 correction is performed at the time of power-on is monitored by the temperature sensor, and IM2 correction is performed again when a temperature change occurs.

  FIG. 17 shows an example of the configuration of the temperature sensor according to the present embodiment. As shown in FIG. 17, the temperature sensor 155 includes resistors R0 to R8, a diode D1, and comparators CP1 to CP7.

  One connection portion of the resistor R0 is connected so that, for example, the power supply voltage VDL0 generated from the power supply voltage Vb generated by the bandgap reference circuit and having no temperature dependency is supplied, and the other end of the resistor R0 is connected. Is connected to the anode of the diode D1.

  The resistors R1 to R8 connected in series are connected between the cathode of the diode D1 and the reference potential VSS. The negative (−) side input terminals of the comparators CP1 to CP7 are respectively connected so that the power supply voltage Vb is input.

  A connecting portion between the resistor R1 and the resistor R2 is connected to the positive (+) side input terminal of the comparator CP1. The connection part of resistors R2 and R3 is connected to the positive (+) side input terminal of the comparator CP2, and the connection part of resistors R3 and R4 is connected to the positive (+) side input terminal of the comparator CP3. Yes. The connection portion of resistors R4 and R5 is connected to the positive (+) side input terminal of the comparator CP4, and the connection portion of resistors R5 and R6 is connected to the positive (+) side input terminal of the comparator CP5. Yes. Similarly, resistors R6 and R7 are connected to the positive (+) side input terminal of the comparator CP6, and resistors R7 and R8 are connected to the positive (+) side input terminal of the comparator CP7. It is connected.

  The diode D1 has a characteristic that the forward voltage Vd decreases as the temperature increases. Therefore, the divided voltages Vt0 to Vt6 output from the connection portions of the resistors R1 to R8 increase as the temperature increases.

  On the other hand, the power supply voltage Vb generated by the bandgap reference circuit is constant regardless of the temperature. Therefore, the power supply voltage Vb and the divided voltages Vt0 to Vt6 can be used as a temperature sensor by comparing them with the comparators CP1 to CP7, respectively. The comparators CP1 to CP7 output high to the detection signals To0 to To6, respectively, when the divided voltages Vt0 to Vt6 are higher than the power supply voltage Vb.

  When the temperature is 25 ° C., for example, the outputs of the comparators CP1 to CP4 are high signals, and the outputs of the comparators CP5 to CP7 are low signals. The signals output from the comparators CP1 to CP7 are output to the logic unit 142 as temperature data. The logic unit 142 performs IM2 correction based on the temperature data.

  FIG. 18 shows an IM2 correction operation at power-on in the semiconductor device (RFIC) according to the present embodiment.

  As in FIG. 9 of the first embodiment, the correction parameter (X) is set to m = 0 (S101), IM2 (X) and IM2 (X + 1) are compared (S102), and IM2 (X)> IM2 ( X + 1) (S103), m + 1 is set (S104), and the comparison between IM2 (X) and IM2 (X + 1) is repeated. If IM2 (X) <IM2 (X + 1) at S102 (S105), the IM2 correction parameter is set to X (S106), and m is stored in the RAM 132 (S107).

  Further, in the present embodiment, the temperature (temperature data) is stored in the RAM 132 (S108). In order to detect a change in temperature during warm-up, the temperature when the correction parameter is set is detected by the temperature sensor 155 and the detected temperature is stored in the RAM 132.

  FIG. 19 shows an IM2 correction operation during warm-up in the semiconductor device (RFIC) according to the present embodiment.

  In the present embodiment, at the time of warm-up, first, it is determined whether or not there is a temperature change (S209). The current temperature is detected by the temperature sensor 155, and the CPU 131 compares the detected temperature with the temperature stored in the RAM 132. If the detected temperature and the temperature stored in the RAM 132 are the same, it is determined that there is no temperature change. If the detected temperature and the temperature stored in the RAM 132 are different, it is determined that there is a temperature change.

  Note that a value obtained by adding a margin to the temperature stored in the RAM 132 may be compared with the detected temperature. For example, the IM2 correction operation can be further omitted by including a margin so as to detect a temperature change that causes at least the fluctuation of the IM2 characteristic.

  If it is determined in S209 that there is no temperature change, the IM2 characteristics have not changed, and the operation is terminated without performing IM2 correction.

  When it is determined that there is a temperature change in S209, IM2 correction is performed as in FIG. 11 of the first embodiment. Note that IM2 correction may be performed similarly to FIG. 14 of the second embodiment.

  That is, the correction parameter (X) is set to the stored value m of the RAM 132 (S201), IM2 (X) and IM2 (X + 1) are compared (S202), and IM2 (X)> IM2 (X + 1) is satisfied (S203). ), The IM2 correction parameter is set to X + 1 (S204), and m + 1 is stored in the RAM 132 (S205). If IM2 (X) <IM2 (X + 1) (S206), the IM2 correction parameter is set to X (S207), and m-1 is stored in the RAM 132 (S208).

  In addition, you may change according to the temperature change which detected n in X + n which correct | amends. For example, when the temperature change is small, the fluctuation of the IM2 characteristic is also small, so n is set small. When the temperature change is large, the fluctuation of the IM2 characteristic is also large, and n is set large.

  Furthermore, in this embodiment, the temperature is stored in the RAM 132 (S210). In order to detect a change in temperature at the next warm-up, the temperature when the correction parameter is set is detected by the temperature sensor 155, and the detected temperature is stored in the RAM 132.

  As described above, in the present embodiment, IM2 correction is performed again only when a temperature change is detected in IM2 correction during warm-up. As a result, unnecessary execution of the IM2 correction operation can be omitted. The operating load of the RFIC can be reduced and power consumption can be suppressed. For example, when IM2 correction is performed after the lock-up time of the reception PLL, the warm-up time can be shortened.

  In the present embodiment, the temperature change is detected during warm-up, but the temperature change may be detected during power-on. For example, when the temperature at the time of the previous IM2 correction is stored in a ROM such as a flash memory and a temperature change from the temperature stored at the time of power-on is detected, the IM2 correction in FIG. 18 is performed. May be. By omitting the IM2 correction at power-on, the operation load of the RFIC can be greatly reduced.

(Embodiment 4)
The fourth embodiment will be described below with reference to the drawings. In the present embodiment, the PMA 114 is tuned in addition to the tuning of the mixer 113 in the IM2 correction operation as compared with the first to third embodiments. Since others are the same as in the first to third embodiments, the description thereof will be omitted as appropriate.

  FIG. 20 mainly shows the configuration of the reception block 101 in the semiconductor device (RFIC) according to the present embodiment. The RFIC 100 of FIG. 20 is different from the RFIC 100 of FIG. 20 of Embodiment 3 in that the IM2 tuning unit 121 of the IM2 correction circuit 120 includes two blocks. The IM2 tuning unit 121 includes a mixer tuning unit 123 that tunes the mixer 113 and a PMA tuning unit 124 that tunes the PMA 114.

  The mixer tuning unit 123 corresponds to the IM2 tuning unit 121 of the first to third embodiments, and generates a tuning signal for reducing the IM2 component to the mixer 113. The mixer tuning unit 123 outputs a tuning signal (back gate voltage) for controlling the back gate of the differential pair of the mixer 113 according to the correction parameter input from the logic unit 142.

  The PMA tuning unit 124 generates a tuning signal for reducing the IM2 component for the PMA 114. For the PMA 114, a parameter having a lower IM2 correction sensitivity (allowing fine adjustment) than the back gate voltage of the mixer 113 is set. In the present embodiment, the PMA 114 is adjusted by the bias current of the differential pair as a parameter with low IM2 correction sensitivity. That is, the PMA tuning unit 124 outputs a tuning signal (bias current control signal) for controlling the bias current of the differential pair of the PMA 114 according to the correction parameter input from the logic unit 142.

  FIG. 21 shows an example of the circuit configuration of the PMA according to the present embodiment. As shown in FIG. 21, the PMA 114 includes NMOS transistors N201 to N204, resistors R201 to R206, current sources I201 to I203, and capacitors C201 to C202. NMOS transistors N201 to N204 form a differential pair. It can be said that the NMOS transistors N201 and N203 form a differential pair, and the NMOS transistors N202 and N204 form a differential pair.

  The drains of the NMOS transistors N201 to N204 are connected to the power supply Vdd via resistors R201 to R204, respectively. The drain of the NMOS transistor N202 is connected to the first output terminal (output_p), and the drain of the NMOS transistor N204 is connected to the second output terminal (output_p).

  The sources of the NMOS transistors N201 and N203 are connected in common, and a current source I203 is connected between the common node and GND. Current sources I201 and I202 are connected between the sources of the NMOS transistors N202 and N204, respectively, and GND.

  The gate of the NMOS transistor N201 is connected to the first input terminal (Input_p), and the gate of the NMOS transistor N202 is connected to the drain of the NMOS transistor N201. The gate of the NMOS transistor N203 is connected to the second input terminal (Input_m), and the gate of the NMOS transistor N204 is connected to the drain of the NMOS transistor N203.

  A resistor R205 and a capacitor C201 are connected in parallel between the first input terminal (Input_p) and the second output terminal (output_m). A resistor R206 and a capacitor C202 are connected in parallel between the second input terminal (Input_m) and the first output terminal (output_p).

  Current sources I201 and I202 generate a bias current for the differential pair of NMOS transistors N202 and N204. In this example, the current source I201 is a variable current source, and the current source I202 is a fixed current source. The current source I201 is a variable current source and generates a current corresponding to a tuning signal from the PMA tuning unit 124. The current source I201 may be a fixed current source, and the current source I202 may be a variable current source. Similarly to FIG. 6 of the first embodiment, the current source for controlling the current may be switched according to the positive / negative of the correction parameter.

  The PMA tuning unit 124 adjusts the bias current only on one side of the differential circuit of the PMA 114, and generates an amplitude mismatch between the differentials of the output signal level. IM2 correction is performed by adjusting the bias current so that the IM2 component in the entire circuit of the reception analog unit 110 is minimized.

  22 and 23 show an example of IM2 correction timing of the semiconductor device (RFIC) according to this embodiment.

  In the example of FIG. 22, when the power of the wireless communication terminal 1 (RFIC 100) is turned on at time T0, the RFIC 100 performs a power-on operation. Within this power-on operation, the RFIC 100 performs IM2 correction (S21).

  In S21, the mixer 113 is tuned by the mixer tuning unit 123, and the PMA 114 is tuned by the PMA tuning unit 124. That is, as in the first to third embodiments, the logic unit 142 detects the IM2 signal output from the reception analog unit 110 according to the test signal, and sets the optimum correction parameter value of the mixer 113 according to the IM2 signal. The optimum value is calculated and set in the mixer tuning unit 123 and stored in the RAM 132. Further, the logic unit 142 detects the IM2 signal output from the reception analog unit 110 according to the test signal, calculates the optimum value of the correction parameter of the PMA 114 according to the IM2 signal, and uses this optimum value as the PMA tuning unit 124. And stored in the RAM 132.

  IM2 correction at power-on uses the bag gate voltage of a mixer with high IM2 correction sensitivity as a correction parameter in order to detect the optimum correction point from a wide range of mismatch states.

  When the IM2 correction in the power-on operation is completed, the RFIC 100 performs a normal transmission / reception operation (normal operation) with the base station or the like at times T1 to T2.

  The warm-up operation is performed at time T3 when the sleep time elapses after time T2. Within this warm-up operation, the RFIC 100 further performs IM2 correction (S22). In S22, the PMA tuning unit 124 tunes only the PMA 114 without tuning the mixer 113. The logic unit 142 detects the IM2 signal output from the reception analog unit 110 according to the test signal, re-corrects the correction parameter of the PMA 114 based on the optimum value stored in S21 at power-on, and the PMA tuning unit 124. The correction value is stored in the RAM 132.

  In IM2 re-correction at the time of warm-up, in order to finely adjust the optimal correction point for temperature fluctuation, the differential current value of PMA having IM2 correction sensitivity lower than the mixer's bag gate voltage is used as a correction parameter, and IM2 correction is performed. Do.

  When the IM2 correction in the warm-up operation is completed, a normal transmission / reception operation is performed with the base station or the like at times T4 to T5. Thereafter, the RFIC 100 repeatedly executes the sleep operation, the warm-up operation, and the transmission / reception operation, and repeats the IM2 correction during the warm-up operation (S23). In S23, similar to S22, the correction parameter of the PMA 114 is re-corrected based on the correction value stored in the previous IM2 correction and set in the PMA tuning unit 124, and this correction value is stored in the RAM 132.

  In the example of FIG. 23, only the mixer 113 is tuned by the mixer tuning unit 123 in the IM2 correction at power-on (S31). That is, as in the first to third embodiments, the optimum value of the correction parameter of the mixer 113 is calculated, and this optimum value is set in the mixer tuning unit 123 and stored in the RAM 132. By performing IM2 correction at power-on only on the mixer, the IM2 correction operation can be simplified as compared with FIG.

  In the IM2 correction (S32, S33) at the time of warm-up, only the PMA 114 is tuned by the PMA tuning unit 124 as in FIG. Since PMA is not corrected at power-on, in S32, the correction parameter of PMA 114 is corrected based on the default value (initial value) and set in PMA tuning unit 124, and this correction value is stored in RAM 132. In S33, the correction parameter of the PMA 114 is re-corrected based on the correction value stored in the previous IM2 correction and set in the PMA tuning unit 124, and this correction value is stored in the RAM 132.

  As described above, in the present embodiment, in the IM2 correction, in addition to the correction by the mixer back gate, the correction by the PMA bias current is performed. In the correction by the back gate of the mixer, since the correction sensitivity (correction width) is large, fine adjustment may be difficult. For this reason, by performing correction with the bias current of the PMA, which has lower correction sensitivity than the correction by the back gate of the mixer, the IM2 correction can be performed with higher accuracy that enables fine adjustment.

  In particular, since the IM2 correction is set to an optimum value at the time of power-on, the IM2 correction at the time of warm-up often requires a minute correction compared with the time of power-on. For this reason, correction can be performed efficiently by correcting by the back gate of the mixer at power-on and by correcting by the bias current of the PMA at warm-up.

  Note that the correction target may be switched according to the temperature change. For example, when the temperature change is small, the fluctuation of the IM2 characteristic is also small, so correction is performed by the bias current of the PMA. When the temperature change is large, the fluctuation of the IM2 characteristic is also large, and correction is performed by the back gate of the mixer.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 Wireless communication terminal 11 Reception circuit 12 Correction circuit 13 Memory circuit 14 Control circuit 100 Semiconductor device 100a RF signal input terminal 100b RF signal output terminal 100c LVDS interface 101 Reception block 102 Transmission block 103 LNA (low noise amplifier)
104 Mixer 105 BE (Back-end circuit)
106 Driver 110 Reception Analog Unit 111 LNA
112 Switch circuit 112a, 112b Switch input part 113 Mixer 113a, 113b Differential pair 114 PMA (mixer latter stage amplifier)
115 LPF (low pass filter)
116 PGA (variable gain amplifier)
120 IM2 Correction Circuit 121 IM2 Tuning Unit 121a Back Gate Pair Selection Unit 121b Back Gate Tuning Unit 122 Test Signal Generation Unit 122a ICMIX
123 Mixer tuning unit 124 PMA tuning unit 130 MPU
131 CPU
132 RAM
141 ADC (A / D converter)
142 Logic Unit 143 DCOC (DC Offset) Control Unit 151 Reception DCO (Digitally Controlled Oscillator)
151a Receive PLL
152 Divider 153 Transmit DCO
154 System Clock Oscillator 155 Temperature Sensor 200 Baseband Processor 201 Antenna 202a Antenna Terminal 202b Reception Terminal 202c Transmission Terminal 203 Isolator 204 HPA (High Power Amplifier)
211 Transmission SAW filter 212 Reception SAW filter

Claims (20)

A receiving circuit that directly converts the received RF signal into a baseband signal;
A correction circuit for correcting second-order intermodulation distortion characteristics of the receiving circuit based on a correction parameter;
A storage circuit for storing a first correction value set in the correction parameter so that the second-order intermodulation distortion characteristic is improved at a first timing;
A control circuit that sets a second correction value to the correction parameter so that the second-order intermodulation distortion characteristic is improved based on the first correction value at a second timing after the first timing; ,
A semiconductor device comprising: The first timing is a power-on operation of the semiconductor device;
The second timing is during a warm-up operation until the semiconductor device shifts from a sleep operation to a normal operation.
The semiconductor device according to claim 1. The semiconductor device repeatedly operates in the order of sleep operation, warm-up operation, normal operation,
The first timing is during the warm-up operation,
The second timing is during the warm-up operation after the warm-up operation of the first timing.
The semiconductor device according to claim 1. The control circuit detects a second-order intermodulation distortion component included in an output signal output from the reception circuit, and sets the correction parameter based on the detected second-order intermodulation distortion component;
The semiconductor device according to claim 1. The control circuit sets the correction parameters by sequentially changing from the initial values at the first timing, and includes a plurality of output signals included in the plurality of output signals output by the receiving circuit according to the set correction parameters. Detecting the second-order intermodulation distortion component of
The semiconductor device according to claim 4. The control circuit determines a value of the correction parameter set corresponding to the lowest second-order intermodulation distortion component among the plurality of second-order intermodulation distortion components to be detected as the first correction value.
The semiconductor device according to claim 5. The control circuit uses, as the correction parameter, the first correction value and an increase value and / or a decrease value obtained by increasing and / or decreasing the first correction value by a predetermined value at the second timing. Setting and detecting a plurality of second order intermodulation distortion components included in the plurality of output signals output by the receiving circuit according to the set correction parameter;
The semiconductor device according to claim 4. The control circuit determines, as the second correction value, the correction parameter set corresponding to the lowest second-order intermodulation distortion component among the plurality of second-order intermodulation distortion components to be detected.
The semiconductor device according to claim 7. When the increase value or the decrease value is determined as the second correction value, the increase value or the decrease value is stored in the storage circuit as the first correction value;
When the first correction value is determined as the second correction value, a value obtained by increasing or decreasing the first correction value by a predetermined value is stored in the storage circuit as the first correction value.
The semiconductor device according to claim 8. The second timing is immediately before the normal operation state is started.
The semiconductor device according to claim 2. A PLL circuit for generating a local signal used for the direct conversion;
The second timing is immediately before the end of the lock-up time necessary for the PLL circuit to lock,
The semiconductor device according to claim 2. The lock-up time and the setting operation of the second timing end at substantially the same timing,
The semiconductor device according to claim 11. A PLL circuit for generating a local signal used for the direct conversion;
The second timing is a timing at which the lock of the PLL circuit is almost completed.
The semiconductor device according to claim 2. A temperature sensor for measuring the temperature of the semiconductor device;
When a change in temperature is detected by the temperature sensor, the control circuit performs the second timing setting operation.
The semiconductor device according to claim 1. The receiving circuit includes a mixer that performs the direct conversion,
The correction circuit controls a back gate voltage of a differential pair transistor constituting the mixer according to the correction parameter.
The semiconductor device according to claim 1. The receiving circuit further includes an amplifier connected to a subsequent stage of the mixer,
The correction circuit controls a bias current of a differential pair transistor constituting the amplifier according to the correction parameter.
The semiconductor device according to claim 15. At the first timing, the correction circuit controls the mixer and the amplifier,
At the second timing, the correction circuit controls only the amplifier.
The semiconductor device according to claim 16. At the first timing, the correction circuit controls only the mixer,
At the second timing, the correction circuit controls only the amplifier.
The semiconductor device according to claim 16. A method for controlling a semiconductor device including a receiving circuit that directly converts a received RF signal into a baseband signal,
Correcting the second-order intermodulation distortion characteristics of the receiving circuit based on a correction parameter;
Storing a first correction value set in the correction parameter so that the second-order intermodulation distortion characteristic is improved at a first timing;
A second correction value is set in the correction parameter so that the second-order intermodulation distortion characteristic is improved based on the first correction value at a second timing after the first timing;
A method for controlling a semiconductor device. Semiconductor devices including:
(A) a receiving circuit that directly converts a received RF signal into a baseband signal;
(B) a correction circuit for correcting second-order intermodulation distortion characteristics of the receiving circuit based on a correction parameter;
(C) a storage circuit that stores a first correction value set in the correction parameter so that the second-order intermodulation distortion characteristic is improved at a first timing;
(D) A second correction value is set in the correction parameter so that the second-order intermodulation distortion characteristic is improved based on the first correction value at a second timing after the first timing. Control circuit.

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