TWI381174B - A testing system and method of the peripheral component interconnect express - Google Patents

Description

New generation generation peripheral interface test system and test method thereof

A test system and a test method thereof, in particular, a test system for a new generation peripheral connection interface and a test method thereof.

In order to solve the bandwidth requirement of various devices in personal computers, a new generation peripheral connection interface bus has recently been released. This technology was originally designed for high-speed data transmission. Among them, the new generation peripheral connection interface provides each device with its own dedicated bus. The data is serially transmitted as a packet through a pair of transmit and receive signals called lanes, with a single direction of 250 Gigabits/sec per channel in the first generation of the new generation perimeter connection interface. . Multiple channels can be combined to form the channel bandwidth of X1, X2, X4, X8, X12, X16, X24, and X32 to increase the bandwidth of the slot.

In response to the needs of users, many motherboard manufacturers have joined the new generation peripheral connection interface bus. At present, the test method for the new generation peripheral connection interface is usually to insert a new generation peripheral connection interface card into the new generation peripheral connection interface slot. If the card can be operated correctly, the new generation peripheral connection interface slot is considered normal. . However, the testing process requires the communication of all levels of information developed by the new generation peripheral connection interface to achieve communication purposes.

Please refer to "Figure 1" for a schematic diagram of the structure of the prior art. From "top 1", the top, bottom, and bottom are the application, operating system, transport protocol, data link, and physical transport. When the application wants to drive the new generation peripheral connection interface At the time of the application, the application will call the corresponding transport protocol through the operating system and transmit the signal to the new generation peripheral connection interface device through the data link and physical transmission. For example, there are generally two methods for testing the peripheral interface of the new generation: the first is the memory read and write mode test, and the second is the DMA (direct memory access, DMA) read and write mode test. The memory read/write mode requires time for the processing unit executed by the application; in the case of the DMA read/write mode test, it also occupies a certain amount of physical memory, which leads to consumption of system resources. In order to maintain the continuity of data transmission during the test, it is necessary to use intensive data requests to improve.

In this way, when the test signal is transmitted in each level of the new generation peripheral connection interface, the test result will be significantly affected. After the data is passed in, the data is also analyzed by the communication protocol above the physical layer to resolve the specific packet requirements. Therefore, how to achieve the purpose of testing without the complicated communication level of information exchange is what the manufacturer needs.

In view of the above problems, the main object of the present invention is to provide a test system for a new generation peripheral connection interface for testing a device under test having a new generation peripheral connection interface.

To achieve the above objective, a test system for a new generation peripheral connection interface disclosed by the present invention includes: a switch, a device to be tested, and a test host. The switch includes a register and a check unit; the device to be tested is used to connect the switch; the test host is electrically connected to the switch, and the test host further includes a processing order The test program and the storage unit, the storage unit stores the test program, and the processing unit is configured to execute the test program. The test program includes the following steps: setting the register to the loop state, so that the switch is set to the master mode ( Master), and the device to be tested is set to slave mode; set the test parameters of the switch; send the test signal to the switch for testing the device to be tested; record each test result of the device under test to Check unit; the test result is counted by the check unit and then returned to the test host.

From another aspect of the present invention, the present invention provides a test method for a new generation peripheral connection interface for testing devices having a new generation peripheral connection interface.

In order to achieve the above objective, a test method for a new generation peripheral connection interface disclosed in the present invention includes the following steps: electrically connecting a switch to a device under test and a test host, and the switch includes a register. And the verification unit; setting the register to the loop state; setting the plurality of test parameters of the switch; sending the test signal to the switch by the test host to test the device to be tested, and until all test items or times are completed Record each test result of the device to be tested to the check unit; the test result is counted by the check unit and then returned to the test host.

The invention provides a test system and a method for a new generation peripheral connection interface, which directly exchanges information with a new generation peripheral connection interface through a switch. The invention does not need to exchange information between the test host and each level in the device under test, and can more correctly detect the transmission speed of the device to be tested.

The features and implementations of the present invention are described in detail below with reference to the preferred embodiments.

Please refer to "Figure 2" for a schematic diagram of the system architecture of the present invention. The test system 200 of the present invention includes: a test host 210, a switch 220, and a device under test 230. The switch 220 is electrically connected between the device under test 230 and the test host 210. The switch 220 further includes a register 221 and a check unit 222. The test host 210 further includes a processing unit 211, a storage unit 212, and a test program 212. The storage unit 212 stores the test program 213, and the processing unit 211 is configured to execute the test program 213. A buffer 231 is further included in the device under test 230. The switch 220 and the device under test 230 use 8/10b encoding for message delivery. The buffer 231 receives the test signal from the switch 220, and the buffer 231 is used to stabilize the integrity of the received test signal.

The test program 213 further includes a plurality of test items, which may be interface version test, power test, System Management Bus (SMB), JTAG (Joint Test Action Group, JTAG for short) test, wake-up test, advance Reset any of the test, differential clock, and data test and/or bandwidth tests. The bandwidth test is to test the bandwidth of X1, X4, X8, X16, X24 or X32 of the connection interface of the new generation.

The way to test the link speed includes the following categories:

1. Bandwidth transmission rate = number of transmitted bits/number of bandwidths/transmission time, and the calculation result is the transmission rate of each bandwidth.

2. Connection 埠 transmission rate = number of transmissions / transmission time, the calculation result is the transmission rate of the connection ,, the rate will be compared with the preset value after calculation.

3. Bandwidth error rate = error count / (bandwidth transmission rate * transmission time * number of bandwidths).

Please refer to "Figure 3" for a schematic diagram of the operational flow of the present invention. The switch is electrically connected between the device under test and the test host (step S310). Next, the register is set to the loop state (step S320), so that the switch 220 is set to the master mode, and the device under test 230 is set to the slave mode. The plurality of test parameters of the switch are set (step S330), which are used to set the test environment parameters in the switch 220: test time, number of single transmission bits, number of transmission pins.

The test host sends a test signal to the switch for instructing the switch to test the device under test (step S340). The switch transmits the test data to the device under test, and stores the data returned by the device under test in the register (step S350). Each test result of the device to be tested is recorded to the check unit (step S360), and is replied after each execution. The test result is counted by the check unit and then returned to the test host (step S370). It is judged whether or not the test result is correct (step S380). If the test result is wrong, the test host executes a warning message (step S381) to remind the tester that the hardware structure of the test device is wrong.

The invention provides a test system 200 for a new generation peripheral connection interface and a method thereof, which exchanges information directly with a new generation peripheral connection interface through a switch 220. The present invention does not need to exchange information between the test host 210 and the various levels in the device under test 230, so that the transmission speed of the device under test 230 can be detected more correctly. Minimize system consumption during testing, such as memory and central processing unit occupancy.

While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The patent protection scope of the invention is subject to the definition of the scope of the patent application attached to the specification.

200‧‧‧Test System

210‧‧‧Test host

211‧‧‧Processing unit

212‧‧‧ storage unit

213‧‧‧Test procedure

220‧‧‧Switch

221‧‧‧ register

222‧‧‧Check unit

230‧‧‧Device under test

231‧‧‧ buffer zone

Figure 1 is a schematic diagram of the architecture of the prior art.

Figure 2 is a schematic diagram of the system architecture of the present invention.

Figure 3 is a schematic diagram of the operational flow of the present invention.

Claims (7)

A test system for a new generation peripheral connection interface for testing a device under test with a new generation peripheral connection interface, the test system comprising: a switch including a register and a check unit; and a device to be tested, The device to be tested is electrically connected to the switch; and a test host is electrically connected to the switch, and the check unit directly establishes a physical layer link with the test host, and transmits the test to the test host. Data, and storing the data returned by the test host in the register, the test host further includes a processing unit, a test program and a storage unit, the storage unit stores the test program, and the processing unit is configured to execute The test program includes the following steps: setting the communication between the switch and the device to be tested as a loop state of a physical layer link, setting the switch to a master control mode, and setting the device to be tested to Slave mode; set the test parameters of the switch, which are interface version test, power test, system management bus (System Manageme Nt Bus, SMB), JTAG (Joint Test Action Group) test, wake-up test, pre-reset test, differential clock and data test and / or bandwidth test; send a test signal to the device under test to The switch instructs the switch to test the device to be tested; the switch transmits test data to the device to be tested, and the test is to be tested The data returned by the device is stored in the register; and the test unit is logged back to the test host after the test unit counts the test result. A test system for a new generation peripheral connection interface as claimed in claim 1, wherein the bandwidth test comprises the step of switching the bandwidth of X1, X4, X8, X16, X24 or X32 of the new generation peripheral connection interface, respectively. A test system for a new generation peripheral connection interface as claimed in claim 1, wherein the device under test further includes a buffer for receiving a test signal from the switch. The test system of the new generation peripheral connection interface according to claim 1, wherein before recording the test result of the device to be tested to the verification unit, the method further comprises the following steps: switching the switch from the master mode The slave mode; and the device to be tested is set to the master mode. The test system of the new generation peripheral connection interface as claimed in claim 1, wherein the switch and the device under test utilize 8/10b coding for message transmission. A test method for a new generation peripheral connection interface for testing a device having a new generation peripheral connection interface, the test method comprising the steps of: electrically connecting a switch to a device under test and a test host, the exchange The device includes a register and a check unit; the register is set to a loop state, so that the switch is set to the master mode; Set the test parameters of the switch. These test items are interface version test, power test, System Management Bus (SMB), JTAG (Joint Test Action Group) test, wake-up test, pre-reset test. Testing, and/or bandwidth testing of differential clocks and data; sending a test signal to the switch by the test host for testing the device to be tested; recording each time of the device under test The test result is sent to the verification unit; and the test result is counted by the verification unit and then replied to the test host. The method for testing a new generation peripheral connection interface according to claim 6, wherein before recording the test result of the device to be tested to the verification unit, the method further includes the following steps: switching the switch from the master mode The slave mode; and the device to be tested is set to the master mode.