200813445 九、發明說明： •【發明所屬之技術領域】 ， 本發明係關於一種測試卡，尤指一種介面功率消耗測 試卡。 【先前技術】 在電子系統之研發過程中’可靠度測試係確保産品品 質之重要關卡’其中一項即係系統介面之功率滿載測試。 φ 下面以PCI Express介面爲例說明。 PCIExpress係新一代匯流排介面。英代爾公司於2〇〇1 年提出要用新一代技術取代PCI匯流排及多種晶片之内1 連接，並稱之爲第三代I/O匯流排技術。隨後在2001年底， 包括Inte卜AMD、DELL、IBM在内20多家業界主導公司 開始起草新技術之規範，並於2002年完成，對其正式命名 爲 PCI Express 〇 PCI Express採用了業内流行之點對點串列連接，比起 PCI以及更早期之電腦匯流排之共用並行架構，每_机備 都有專用連接，不需要向整個匯流排請求帶寬，且可把二責 料傳輸率提高到一很高之頻率，達到PCI所不能提供之高 帶寬。相對于傳統PCI匯流排在單一時間周期内只能實現 單向傳輸，PCIExpress之雙單工連接能提供更高之傳輸速 率及質量。 PCI Express之介面根據匯流排位元寬不同而有戶斤差 異，包括XI、X4、X8以及X16 ( X2模式將用於内部介面 而非插槽模式）。較短之PCI Express卡可插入較長之pC][ 6 200813445200813445 IX. Description of the invention: • [Technical field to which the invention pertains] The present invention relates to a test card, and more particularly to an interface power consumption test card. [Prior Art] In the development of electronic systems, 'reliability testing is an important level to ensure product quality'. One of them is the power full load test of the system interface. φ The following is an example of the PCI Express interface. PCI Express is the next-generation bus interface. In 2001, Intel Corporation proposed to replace the PCI bus and one of the multiple wafers with a new generation of technology, and called it the third-generation I/O bus technology. Then at the end of 2001, more than 20 industry-leading companies including Inte Bu AMD, DELL, and IBM began drafting specifications for new technologies, which were completed in 2002. They were officially named PCI Express 〇PCI Express. Point-to-point serial connection, compared to the shared parallel architecture of PCI and earlier computer bus, each network has a dedicated connection, does not need to request bandwidth to the entire bus, and can increase the two transfer rate to a very High frequency, reaching the high bandwidth that PCI can't provide. Compared to traditional PCI buss, which can only achieve one-way transmission in a single time period, PCI Express's dual simplex connection can provide higher transmission rate and quality. The PCI Express interface varies depending on the busbar width, including XI, X4, X8, and X16 (X2 mode will be used for the internal interface instead of the slot mode). A shorter PCI Express card can be inserted into a longer pC][ 6 200813445
Express插槽中使用。PCI Express介面能夠支援熱拔插。 • PCI Express卡支援之三種電壓分別爲+3.3V、3.3Vaux (輔 ，助電源）以及+12V。用於取代AGP介面之pci Express 介面位元寬爲X16 ’將能夠提供5 GB/s之帶寬，即便有編 碼上之損耗但仍能夠提供約爲4GB/s左右之實際帶寬，遠 退超過AGP X8之2· 1 GB/s之帶寬。PCI Express不僅可用 於南橋及其他設備之連接，亦可延伸到晶片組間之連接， 鲁甚至亦可用於連接圖形晶片。這樣整個PC之I/O系統將 重新統一起來，將更進一步簡化PC系統，增加PC之可攜 性及模組化。 習知PCI Express多用於伺服器及個人電腦上，在産 品測試過程中有一項壓力測試，需要將PCI Express介面 .插接上PCI Express測試卡進行功率滿截測試。習知技術 係用符合PCI Express規範之繪圖卡、網路卡等作爲測試 卡來進行功率滿載測試，但由於這些繪圖卡、網路卡等産 着品之功率都係預先設定，而PCI Express具有多個介面規 範，各個介面規範之最大額度功率係不同的，所以在實際 測試過程中PCI Express介面並不能達到真正的滿載測 試，造成測試不準確；而且測試不同的PCI Express介面 需要換插上不同的PCI Express測試卡，造成測試不便。 因是，實有必要對習知之介面功率消耗測試卡進行改 良’以消除上述缺失。 【發明内容】 鑒於以上内容，有必要提供一種介面功率消耗測試卡。 200813445 一種介面功率消耗測試卡，包括一符合相應介面規格 •之電路板及一設於該電路板之負載模擬裝置，該負載模擬 _裝置包括一提供輸出電壓之穩壓裝置及一接收該輸出電壓 並用於消耗功率之負載裝置，該穩壓裝置輸出之輸出電壓 與該負載裝置之負載至少之一可調以滿足待測介面所需之 最大功率。 相較習知技術，該介面功率消耗測試卡可透過該負載 Φ模擬裝置模擬待測介面所需之最大功率，測試準確且方便。 【實施方式】 請參閱圖1及圖2，本發明介面功率消耗測試卡之較 佳實施方式以PCI Express介面爲例進行說明，其包括一 符合 PCI Express 介面規格之 PCB ( Printed Circuit Board， .印刷電路板）1〇及一設於該PCB10内之負載模擬裝置20。 該介面功率消耗測試卡可插置於一電路板上之PCI Express插槽12對其消耗功率進行模擬測試。 # 該負載模擬裝置20包括一穩壓裝置22及一負載裝置 24。該穩壓裝置22包括一穩壓器26及一電晶體Q1，本實 施方式中該穩壓器26係由美國LINEAR公司生産之型號 爲LM338之可調三端穩壓器。該穩壓器26包括一輸入端 Vin、一輸出端V〇ut及一調節端ADJ。 該穩壓器26之輸入端Vin及輸出端V〇ut之間接入一 第一穩壓二極體D1，該第一穩壓二極體D1之正極與該輸 出端V0UT連接，負極與該輸入端VIN連接。該穩壓器26 之輸出端V0UT及調節端AD J之間並聯一電阻R1及一第二 8 200813445 穩壓二極體D2。該第二穩壓二極體D2之正極與該調節端 • ADJ連接，負極與該輸出端V0UT連接。該穩壓器26之輸 ^ 入端VIN接入一直流電源VI之正極，該直流電源VI由一 待測PCI Express介面12提供。該直流電源VI並聯接入 一第一電容C1用於濾除雜訊。該穩壓器26之調節端ADJ 透過一第二電容C2接入該直流電源VI之負極。該穩壓器 26之調節端ADJ還連接複數並聯之第一電阻Rn之共同連 φ 接端，每一第一電阻Rn之另一端爲觸點，且每一第一電 阻Rn之阻值不相同。該直流電源VI之負極連接一第一開 關K1，當該第一開關K1之擲刀與其中一第一電阻Rn之 另一端連接時，該第一電阻Rn即被接入電路。該穩壓器 26之輸出端V0UT透過一第三電容C3接入該直流電源VI 之負極。該第二電容C2及該第三電容C3用於進行充放 電，可提高紋波抑制比。該第一穩壓二極體D1及該第二 穩壓二極體D2用於防止該第二電容C2及該第三電容C3 _在放電過程中損壞該穩壓器26。該電晶體Q1之集極與該 直流電源VI之正極連接，基極與該穩壓器26之輸出端 V〇uT連接。 該負載裝置24包括一第四電容C4、複數並聯之第二 電阻Rm及一第二開關K2。該電晶體Q1之射極透過該第 四電容C4接入該直流電源VI之負極，該第四電容C4用 於濾波。該電晶體Q1之射極還接入該等第二電阻Rm之 共同連接端，每一第二電阻Rm之另一端爲觸點，且每一 第二電阻Rm之阻值不相同。該直流電源VI之負極連接 200813445 該第二開關Κ2 ’當該第二開關K2之擲刀與其中一第二電 阻Rm之另一端連接時，該第二電阻Rmm被接入電路。 根據該穩壓器26之工作特點，該穩壓器26之輸入端 vIN在接入該直流電源¥1後，該輸出端ν〇υτ及該調節端 ADJ之間産生1.25伏之參考電壓。假設該第一開關將 其中一第一電阻Rn接入電路，該輸出端ν〇υτ此時之電壓 爲V2，則根據分壓電路特點有下列等式：Used in the Express slot. The PCI Express interface supports hot plugging. • The three voltages supported by the PCI Express card are +3.3V, 3.3Vaux (auxiliary, auxiliary power) and +12V. The pci Express interface used to replace the AGP interface is X16' wide and will provide a bandwidth of 5 GB/s. Even with the loss of coding, it can still provide an actual bandwidth of about 4GB/s, far back beyond AGP X8. 2·1 GB/s bandwidth. PCI Express can be used not only for the connection between the South Bridge and other devices, but also for the connection between the chipsets. Lu can even be used to connect graphics chips. In this way, the entire PC I/O system will be re-unified, which will further simplify the PC system and increase the portability and modularization of the PC. Conventional PCI Express is mostly used on servers and personal computers. There is a stress test during product testing. The PCI Express interface needs to be plugged into a PCI Express test card for power full-cut test. The conventional technology uses a PCI Express-compliant graphics card, network card, etc. as a test card for power full load testing, but since the power of the graphics cards, network cards, etc. are pre-set, PCI Express has Multiple interface specifications, the maximum power of each interface specification is different, so the PCI Express interface does not achieve true full load test during the actual test, resulting in inaccurate testing; and testing different PCI Express interfaces requires different plug-ins The PCI Express test card caused inconvenience in testing. Therefore, it is necessary to improve the conventional interface power consumption test card to eliminate the above-mentioned deficiency. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide an interface power consumption test card. 200813445 An interface power consumption test card includes a circuit board conforming to a corresponding interface specification and a load simulation device disposed on the circuit board, the load simulation device includes a voltage stabilizing device for providing an output voltage and receiving the output voltage And for the power consumption load device, at least one of the output voltage of the voltage regulator device and the load of the load device is adjustable to meet the maximum power required for the interface to be tested. Compared with the prior art, the interface power consumption test card can simulate the maximum power required by the interface to be tested through the load Φ simulation device, and the test is accurate and convenient. [Embodiment] Referring to FIG. 1 and FIG. 2, a preferred embodiment of the interface power consumption test card of the present invention is described by taking a PCI Express interface as an example, which includes a PCB (Printed Circuit Board) conforming to the PCI Express interface specification. The circuit board) 1 and a load simulation device 20 disposed in the PCB 10. The interface power consumption test card can be plugged into a PCI Express slot 12 on a circuit board for analog testing of its power consumption. # The load simulation device 20 includes a voltage stabilization device 22 and a load device 24. The voltage regulator device 22 includes a voltage regulator 26 and a transistor Q1. In this embodiment, the voltage regulator 26 is an adjustable three-terminal voltage regulator of the type LM338 manufactured by LINEAR Corporation of the United States. The regulator 26 includes an input terminal Vin, an output terminal V〇ut and an adjustment terminal ADJ. A first voltage stabilizing diode D1 is connected between the input terminal Vin and the output terminal V〇ut of the voltage regulator 26, and the anode of the first voltage stabilizing diode D1 is connected to the output terminal VOUT, the negative pole and the input Terminal VIN connection. A resistor R1 and a second 8 200813445 voltage stabilizing diode D2 are connected in parallel between the output terminal V0UT of the voltage regulator 26 and the regulating terminal AD J . The anode of the second regulator diode D2 is connected to the regulation terminal • ADJ, and the cathode is connected to the output terminal VOUT. The input terminal VIN of the regulator 26 is connected to the anode of the DC power supply VI, which is provided by a PCI Express interface 12 to be tested. The DC power supply VI is connected in parallel to a first capacitor C1 for filtering noise. The regulator terminal ADJ of the regulator 26 is connected to the cathode of the DC power source VI through a second capacitor C2. The regulating terminal ADJ of the voltage regulator 26 is further connected to the common φ terminal of the plurality of parallel connected first resistors Rn, and the other end of each first resistor Rn is a contact, and the resistance of each first resistor Rn is different. . The negative pole of the DC power source VI is connected to a first switch K1. When the throwing knife of the first switch K1 is connected to the other end of one of the first resistors Rn, the first resistor Rn is connected to the circuit. The output terminal V0UT of the voltage regulator 26 is connected to the cathode of the DC power source VI through a third capacitor C3. The second capacitor C2 and the third capacitor C3 are used for charge and discharge to increase the ripple rejection ratio. The first Zener diode D1 and the second Zener diode D2 are used to prevent the second capacitor C2 and the third capacitor C3_ from damaging the regulator 26 during discharge. The collector of the transistor Q1 is connected to the anode of the DC power source VI, and the base is connected to the output terminal V〇uT of the regulator 26. The load device 24 includes a fourth capacitor C4, a plurality of parallel parallel resistors Rm, and a second switch K2. The emitter of the transistor Q1 is connected to the cathode of the DC power source VI through the fourth capacitor C4, and the fourth capacitor C4 is used for filtering. The emitter of the transistor Q1 is also connected to the common connection terminal of the second resistors Rm, and the other end of each of the second resistors Rm is a contact, and the resistance of each of the second resistors Rm is different. The negative connection of the DC power supply VI 200813445 The second switch Κ2' is connected to the circuit when the throwing knife of the second switch K2 is connected to the other end of one of the second resistors Rm. According to the operating characteristics of the voltage regulator 26, after the input terminal vIN of the voltage regulator 26 is connected to the DC power source ¥1, a reference voltage of 1.25 volts is generated between the output terminal ν〇υτ and the regulation terminal ADJ. Assuming that the first switch connects one of the first resistors Rn to the circuit, and the voltage of the output terminal ν 〇υ τ is V2, the following equation is obtained according to the characteristics of the voltage dividing circuit:
Vr2xi?l/(i?l + /?n)=1.25 ( 1 ) 根據等式（1 )變形有： F2 = 1*25x(l+i?/z/i?l) ( 2 ) 即該穩壓器26提供一穩定之輸出電壓。 着 假没該電晶體Q1之射極電壓爲V3，此時該電晶體 Q1之基極與該穩壓器26之輸出端ν〇υτ連接，所以該電晶 體Q1之基極電壓爲V2，此時該電晶體Q1導通，則根據 電晶體之工作特點並結合等式（2 ): F3 = 1.25x(l + i?n/i?l) —〇·7 ( 3 ) 假設第二開關K2將其中一第二電阻Rm接入電路， 則該第二電阻Rm即爲輸出負載，加在該第二電阻—上 之負載電壓即爲V3。當某種原因（譬如該第二開關以切 換接入另-第二電阻Rn^，由於負載電流不變而負載電 阻發生變化）導致該負载電壓V3下降（或升高）時，該 電晶體Q1之基極、射極間之電壓升高（或下降），從而導 致該電晶體Q1之集極、射極間之電壓下降（或升高），由 於該電晶體Q1之集極與該直流電源V1連接，即該電 200813445Vr2xi?l/(i?l + /?n)=1.25 ( 1 ) According to the equation (1), there are: F2 = 1*25x(l+i?/z/i?l) ( 2 ) Voltage regulator 26 provides a stable output voltage. The emitter voltage of the transistor Q1 is V3, and the base of the transistor Q1 is connected to the output terminal ν〇υτ of the voltage regulator 26, so the base voltage of the transistor Q1 is V2. When the transistor Q1 is turned on, according to the working characteristics of the transistor and combined with the equation (2): F3 = 1.25x (l + i?n / i?l) - 〇 · 7 ( 3 ) Assuming that the second switch K2 will When a second resistor Rm is connected to the circuit, the second resistor Rm is an output load, and the load voltage applied to the second resistor is V3. The transistor Q1 is used when the load voltage V3 drops (or rises) for some reason (for example, the second switch switches to the other-second resistor Rn^, the load resistance changes due to the load current constant). The voltage between the base and the emitter rises (or falls), causing the voltage between the collector and the emitter of the transistor Q1 to drop (or rise) due to the collector of the transistor Q1 and the DC power supply. V1 connection, that is, the electricity 200813445
Qi之集極電壓恒定，導致該負载電壓V3升高（或下降）， ‘從而達到穩定輸出負載電壓V3之目的。 ^ 假設該第二電阻Rm在電壓V3時産生之功率爲p，則 根據功率公式並結合等式（3)，有： p = (V3)2/Rm = [1.25 x (1 + Rn/Rl) - 〇jf ( 4 ) 由於該電阻R1之阻值恒定，待測pci Express介面之 最大功率已知，該第二電阻Rm、第一電阻Rn之阻值即 •可根據公式（4)換算出來（可預先設定該第二電阻Rm之 =值爲500歐姆，再計算該第一電阻Rn之阻值）。透過該 第一開關κι及該第二開關K2將所需之第二電阻Rm、第 一電阻Rn接入電路即可得到所需之功率p。 將所需之第二電阻Rm、第一電阻Rn接入電路即可滿 足測試時不同之PCI Express介面所需之最大功率，且不 用另外換插測試卡，測試準確且方便。 纟實施方式罐裝置22亦可不包括該電晶體⑴， 罾即該穩壓器26之輸出端V〇UT直接與該等第二電阻如之 共同連接端連接，此時該輸出端ν〇υτ之電壓v2即爲 之輸出電壓。 、秋 本實施方切第二電阻Rm、第—電阻Rn之數量 據需要設定’例如可只接入一第二電阻Rm及複數第乂 阻Rn’亦可接入-第一電阻Rn及複數第二電阻心。 綜上所述，本發明符合發明專利要件，爰依法提 利申請。惟，以上所述者僅為本發明之較佳實施方式，汽 凡热悉本案技藝之人士，在爰依本發明精神所作之等效ς 11 200813445 飾或變化，皆應涵蓋於以下之申請專利 【圖式簡單說明】 係本發明介面功率消耗測試卡 乾圍内 圖 立體圖 之較佳實施方式 之 置之 圖2係本發明介面功率消耗測試卡之負载模擬裝 電路圖。Qi's collector voltage is constant, causing the load voltage V3 to rise (or fall), and thus achieve the purpose of stabilizing the output load voltage V3. ^ Assuming that the power generated by the second resistor Rm at the voltage V3 is p, according to the power formula and in conjunction with equation (3), there are: p = (V3)2/Rm = [1.25 x (1 + Rn/Rl) - 〇jf ( 4 ) Since the resistance of the resistor R1 is constant, the maximum power of the pci Express interface to be tested is known, and the resistance of the second resistor Rm and the first resistor Rn can be converted according to the formula (4) ( The value of the second resistor Rm is set to be 500 ohms, and the resistance of the first resistor Rn is calculated. The required power p is obtained by connecting the required second resistor Rm and the first resistor Rn to the circuit through the first switch κι and the second switch K2. By connecting the required second resistor Rm and the first resistor Rn into the circuit, the maximum power required for the different PCI Express interfaces at the time of testing can be satisfied, and the test card is not replaced by another test, and the test is accurate and convenient. The implementation tank device 22 may also not include the transistor (1), that is, the output terminal V〇UT of the voltage regulator 26 is directly connected to the second resistors, for example, the common terminal, and the output terminal ν〇υτ The voltage v2 is the output voltage. The implementation of the second resistor Rm and the first resistor Rn according to the implementation of the autumn implementation may be set as needed, for example, only a second resistor Rm and a plurality of resistors Rn' may be connected to the first resistor Rn and the second plurality. Resistance heart. In summary, the present invention complies with the requirements of the invention patent, and applies for an application in accordance with the law. However, the above description is only a preferred embodiment of the present invention, and those who are interested in the art of the present invention, in accordance with the spirit of the present invention, may be included in the following patent applications. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a diagram of a load simulation circuit diagram of an interface power consumption test card of the present invention. FIG. 2 is a schematic diagram of a preferred embodiment of the interface power consumption test card.
【主要元件符號說明】 PCB 10 負載模擬裝置 20 負載裝置 24 電晶體 Q1 輸出端 V〇ut 第一穩壓二極體 D1 第二穩壓二極體 D2 第一開關 Κ1 苐二開關 Κ2 第一電阻 Rn 第一電阻 Rm[Main component symbol description] PCB 10 load simulation device 20 load device 24 transistor Q1 output terminal V〇ut first voltage regulator diode D1 second voltage regulator diode D2 first switch Κ1 苐2 switch Κ2 first resistor Rn first resistance Rm
PCI Express 插槽 12 穩壓裝置 22 穩壓器 26 輸入端 VlN 調節端 ADJ 第一電容 Cl 第二電容 C2 第三電容 C3 第四電容 C4 電阻 R1 直流電源 VIPCI Express slot 12 Regulator 22 Regulator 26 Input VlN Adjuster ADJ First Capacitor Cl Second Capacitor C2 Third Capacitor C3 Fourth Capacitor C4 Resistor R1 DC Power Supply VI
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