TWI379353B - Method for grinding a wafer - Google Patents

Description

1379353.

TW4532PA IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a wafer polishing method, and more particularly to a wafer polishing method for thinning wafer thickness. [Prior Art] In a wafer polishing process, wafers are often subjected to stress and cracks are formed at the edges of the wafer. Especially at the notch or the flat edge, the situation is more serious. The wafer at the crack will not be reworked and must be scrapped directly, resulting in a reduced grain yield after grinding. If the crack grows too much, it can even lead to the scrapping of the entire wafer. Therefore, how to improve the phenomenon of cracks in the process of grinding wafers is an important direction of the current research and development. SUMMARY OF THE INVENTION In view of the above, the present invention provides a wafer polishing method by forming a trench on a wafer to prevent the crack from continuing to grow. During the grinding process, the crack growth is blocked by the groove and stops, so that the crack growth is limited between the edge of the wafer and the groove. In this way, the quality of the polished wafer is not affected by the growth of cracks. According to an aspect of the invention, a wafer grinding method is proposed. The wafer* polishing method includes providing a wafer having a first surface opposite to the first surface and a second surface; forming at least one trench on the first surface, the depth of the trench being greater than or equal to a predetermined thickness; The second surface grinds the wafer until the wafer is ground to a predetermined thickness. 1379353

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TW4532PA In order to make the above-mentioned contents of the present invention more comprehensible, the following description of the preferred embodiment and the accompanying drawings will be described in detail as follows: [Embodiment] Please refer to FIG. A flow chart of a wafer polishing method in accordance with a preferred embodiment of the invention. The wafer polishing method includes: first, please refer to FIG. 2A and FIG. 2B, FIG. 2A is a schematic view of the wafer of the embodiment, and FIG. 2B is a second wafer of FIG. 2A along the 2B-2B' Cutaway view. As shown in FIG. 2B, in step S101, a wafer 200 is provided. The wafer 200 has a first surface 202 and a second surface 204. Among them, the first surface 202 is, for example, an active surface, and the second surface 204 is, for example, a non-main surface. In addition, as shown in FIG. 2A, the wafer further has a notch 201 at the edge 205 of the wafer 200. Next, please refer to FIG. 3A, which is a schematic view showing the wafer in which the groove is formed in the embodiment. In step S103, at least one trench 206 is formed on the first surface 202, and the trench 206 is adjacent to the edge 205 of the wafer 200. • Preferably, the trench 206 is between the recess 201 and the center of the wafer 200. That is, all of the edges 205 (including the edges of the notches 201) are located outside of the grooves 206. Therefore, the crack grown by the edge 205 can be blocked at the groove 206. In particular, in areas where the shape of the outer edge 205 varies greatly (e.g., the recess 201), the groove 206 can also achieve the effect of preventing the crack from becoming long. In addition, please refer to FIG. 3B, which shows a cross-sectional view of the wafer along FIG. 3A along 3B-3B'. The depth D1 of one of the trenches 206 is greater than or equal to one pre- 1379353.

TW4532PA is set to a thickness of D2. In the present embodiment, the depth D1 is described as being larger than a predetermined thickness 卯. For example, the phenomenon of cracks is most likely to occur when the wafer 2 is scheduled to be ground to a predetermined thickness D2 of less than 5 filaments or less than i. Further, referring to Figures 4A to 4C, there is shown a schematic diagram of a method of fabricating a trench in the present embodiment. In the step of step sl3, as shown in FIG. 4A, the wafer polishing method further includes forming a photoresist layer 21 on the first surface 202. Then, as shown in Fig. 4B, the photoresist layer 21 is patterned such that the patterned photoresist layer has a surname opening 212. The rice opening 212 exposes a portion of the first surface 2〇2 that is intended to form the groove 206. Next, as shown in Fig. 4C, the patterned photoresist layer 21 is used as a mask to form a first surface 2〇2 to form trenches 2〇6. Thus, the groove 2〇6 of this embodiment is formed. Although the manufacturing method of the trench 2G6 in this embodiment is in the off mode, the method of fabricating the trench can also be performed by using a laser processing branch or a green image as shown in FIGS. 5A to 5B. A schematic diagram of another way of making a trench. As shown in FIG. 5A, in the step of measuring the step, the wafer polishing side (four) is wide, firstly, a protective thin layer 214 is attached to the first surface 2〇2' 矣, 臈 214 has an opening 216, and the opening 216 A portion of the first surface 202 is exposed. As shown in Fig. 5B, a portion of the first surface 202 of the open path is cut by a laser (not shown). At this point, a groove win is formed. 1379353

TW4532PA Please refer to FIG. 6A and FIG. 6B , FIG. 6A is a schematic diagram showing the crack growth of the trench in the embodiment during the grinding process, and FIG. 6B is a diagram showing the wafer of FIG. 6A along the 6B-6B′. Cutaway view. As shown in Fig. 6B, in step S105, the wafer 200 is polished from the second surface 206 until the wafer 200 is ground to a predetermined thickness D2. As shown in Fig. 6A, during the grinding process, the cracks 218 often occur at locations where stress is concentrated, such as the notches 201. The trench 206 of the present embodiment prevents the growth of the crack 218, so that the growth of the crack 218 is confined between the edge 205 of the wafer 200 and the trench 206, so that the wafer 200 can ensure the trench 206 after the polishing is completed. Grain yield between the center of the wafer 200. Further, although this embodiment is described by taking the groove form of Fig. 3A as an example. However, the form of the grooves is not limited by Figure 3A. Please refer to FIG. 7 , which illustrates a second form of the trench of the embodiment. The shape of a trench 208 is substantially similar to the shape of the edge 205 of the wafer 200 , that is, adjacent to the recess 201 . The groove 208 is formed around the shape of the recess 201. This 'j is well formed in the form of the edge 205 closest to the wafer 200 so that the wafer 200 can have a greater grain yield after grinding. Alternatively, please refer to Fig. 8, which is a schematic view showing a third form of the groove of the embodiment. In step S103, a groove 220 may also be adjacent only to the recess 201. The trench 220 is not provided adjacent to the remaining edge 205 to increase the throughput of the wafer 200. Designers can choose the appropriate design between the grain yield and the wafer 200 usage based on the actual situation. 1379353 • »

TW4532PA Although there are only one groove number in this embodiment, in other embodiments, please refer to FIG. 9, which shows a schematic view of the fourth form of the groove of the embodiment. In step S103, two or more grooves 224 may be formed on the first surface 202. Also, the grooves 224 may be surrounded by a plurality of closed paths. The grooves 224 have a double barrier to the occurrence of cracks. That is to say, if the crack grows too intensely, a plurality of grooves can be formed to alleviate the fierce growth of the crack. Although the present embodiment is exemplified by a wafer in which a notch is formed, in other embodiments, the trench may be formed on a wafer having no recess or flat. Because the wafer has no notches or flat edges, the wafer may still have a large change in the shape of the wafer during the grinding process, such as the crack at the edge of the wafer. Furthermore, as long as the wafer is subjected to a grinding operation, cracks may occur. Therefore, the present invention can be applied to prevent the growth of cracks as long as it is a wafer to be polished. The wafer polishing method disclosed in the above embodiments of the present invention prevents the growth of cracks during the grinding process by the formation of grooves on the wafer. The growth of the crack during the polishing process is limited between the edge of the wafer and the trench. Therefore, the quality of the wafer is not affected by cracks. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. Those skilled in the art having the knowledge of the present invention can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 1379353

TW4532PA [Simple Description of the Drawings] Fig. 1 is a flow chart showing a method of polishing a wafer in accordance with a preferred embodiment of the present invention. FIG. 2A is a schematic view showing the wafer of the embodiment. Figure 2B is a cross-sectional view of the wafer of Figure 2A taken along line 2B-2B'. Fig. 3A is a schematic view showing the wafer on which the trench is formed in the embodiment. Figure 3B is a cross-sectional view of the wafer of Figure 3A taken along line 3B-3B'. • Figs. 4A to 4C are views showing a manner of making a groove in the present embodiment. 5A to 5B are views showing another mode of fabricating the trenches of the present embodiment. Fig. 6A is a view showing the growth of the groove of the embodiment to prevent crack growth during the grinding process. Figure 6B is a cross-sectional view of the wafer of Figure 6A taken along line 6B-6B'. Fig. 7 is a schematic view showing the second form of the groove of this embodiment. • Fig. 8 is a schematic view showing a third form of the groove of the embodiment. Figure 9 is a schematic view showing the fourth form of the groove of the embodiment. [Main component symbol description] 200: Wafer. 201: Notch 202: First surface 204: Second surface 1379353

TW4532PA 205: edge 206, 208, 220, 224: trench 210: photoresist layer 212: etching opening 214: protective film 216: opening 218: crack D1: depth D2: predetermined thickness

Claims (1)

1379353 May 17, 101 Nuclear replacement page 曰Revision and replacement page 2012/5/17_la Application & Amendment 10, patent application scope: 1. A wafer grinding method includes: providing a wafer with relative a first surface and a second surface; forming at least one trench on the first surface, the trench having a depth greater than or equal to a predetermined thickness, wherein the trench has a shape substantially similar to an edge of the wafer Shape; and grinding the wafer from the second surface until the wafer is ground to the predetermined thickness. 2. The wafer polishing method of claim 1, wherein in the step of forming the trench, the trench is adjacent to a edge of the wafer. 3. The wafer polishing method of claim 1, wherein in the step of forming the trench, the trench is surrounded by a closed path. 4. The wafer polishing method of claim 1, wherein the wafer further has a notch, the notch being located at an edge of the wafer, in the step of forming the trench The trench is located between the recess and the center of the wafer. 5. The wafer polishing method of claim 1, wherein the step of forming the trench further comprises: forming a photoresist layer on the first surface; patterning the photoresist layer to pattern The photoresist layer has an etch opening that exposes a portion of the trench that is intended to form the trench. The first table 097119662 1013185704-0 1379353 [ϊ〇1, May 17th, according to the replacement ϋ 2012/5/n_Jst Complex & Correction Surface; - I f —— - '月丨η日修正 replacement page with the patterned photoresist layer as a mask, etched the first surface to form the trench. The heart should be 6. If you apply for the patent scope! The step of forming the trench in the crystal of the item further comprises: attaching a protective film to the first surface, the protective film having a mouth π-exposed portion of the first surface; and a laser A portion of the first surface exposed by the opening is cut. 7. The crystal according to claim i: the step of forming the trench is to form two or more trenches in the table, and the wafer polishing method according to claim 7 of claim 7 The grooves are surrounded by a plurality of closed paths. 9. If you apply for a patent scope! The predetermined thickness in the wafer grinding described in the item is less than 5 mils. 4 10. The thickness of the pre-tanning is less than 1 inch (mi 1 ) in the wafer research described in item 1 of the patent application. Lh, as in the wafer grinding described in claim 1, the first surface is an active surface 'the second surface is an inactive surface straight 097119662 1013185704-0 13