1379300 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種程式化一記憶胞的方法及一種記 憶體’特別是指一種多階（multi-level )程式化一相變化記 憶胞的方法及一種相變化記憶體（phase_change random access memory，PRAM)。 【先前技術】 相變化記憶體是一種非揮發性記憶體（n〇n_v〇latile memory)，其所儲存的資料不會因電源移除而消失。由於相 變化s己’〖思體的切換速度相當快，且可相容於互補式金屬氧 化物半導體（CMOS)製程，被看好有機會取代快閃記憶體 (flash memory)成為非揮發性記憶體的主流。 相變化記憶體使用可藉由加熱而在結晶相（以丫他川狀 phase )和非晶相（amorph〇us phase )之間切換的相變化材 料（例如硫屬合金（chalCOgenide aU〇y))來儲存資料。相 變化材料在結晶相下具有低電阻係、數（resisUvity)和高反 射率（reflectance)，@在非晶才目下具有冑冑阻係數和低反 射率。相變化記憶體利用電信號來加熱相變化材料，並利 $相變&材料|結晶相與非晶相之間的電阻係數差異來辨 別所儲存的資料1重寫光學媒體（例如cd_rw和謂_ RW)也使用相變化材料來儲存資料，但利用雷射光來加熱 相變化材料，並利用相變化材料在結 反射率差異來辨別所儲存的資料。 晶相與非晶相之間的 在相變化記憶體中 藉由將相變化材料先加熱到超過 1379300 其結晶溫度，但低於其熔融溫度，再冷卻下來，可使其從 非晶相轉變成結晶相，一般稱此過程為設定（set) *而错由 將相變化材料先加熱到超過其熔融溫度，再冷卻下來，可 使其從結晶相轉變成非晶相，一般稱此過程為重設（reset) 〇 當相變化記憶體採用二元（binary)儲存時，是使相變 化記憶胞的記錄區中的相變化材料在二種不同狀態（例如 :完全結晶及完全非晶）間轉換，因此每一相變化記憶胞 能儲存一位元的資料。當相變化記憶體採用多階儲存時， 是使相變化記憶胞的記錄區中的相變化材料在更多種不同 狀態（例如：完全結晶、完全非晶及介於這二者之間的部 分結晶）間轉換，以提高每一相變化記憶胞的資料儲存量 。例如：若相變化記憶胞的記錄區中的相變化材料在四種 不同狀態間轉換的話，則每一相變化記憶胞能儲存二位元 的資料。 參閱圖 1，2006 年 1 月 IEEE TRANSACTIONS ON ELECTRON DEVICES 第 53 卷第 1 期第 56 頁’’HSPICE Macromodel of PCRAM for Binary and Multilevel Storage”論 文揭露了一種多階程式化一相變化記憶胞的方法，適用於 採用多階儲存的相變化記憶體。首先，施加一重設電流脈 衝11到相變化記憶胞的相變化材料，以使記錄.區中的相變 化材料實質上完全非晶（即結晶程度接近〇% )。接著，施 加一設定電流脈衝12到相變化記憶胞的相變化材料，以使 記錄區中的相變化材料具有期望的結晶程度（例如：100% 6 1379300 ' 第097124699號專利申錄補充、修正後無畫線之說明書替換·頁 修i曰期：1〇1年8月 、65%或40。/。），其中，設定電流脈衝的寬度與期望的結晶 程度對應。然而，這種方法所需的重設電流脈衝的振幅很 大，超過奈米級M〇s或類似元件所能提供的最大電流因 此不利於實現《另外，每次程式化都要將相變化記憶胞的 相變化材料加熱到超過其熔融溫度，且形成很大的熔融區 域，這樣报容易損壞相變化記憶胞而降低其重覆次數且 ' 可此使附近相變化記憶胞的相變化材料非預期地達到其結 晶溫度而局部結晶，造成熱串號（thermal cross-talk)問題 〇 【發明内容】 因此本發明之目的即在提供一種多階程式化一相變 化記憶胞的方法，容易實現’且可以提高重覆次數及減輕 熱串號問題。 於疋本發明多階程式化一相變化記憶胞的方法適用 於一相變化記憶胞，該相變化記憶胞包括依序電連接的一 第一電極、一相變化材料層及一第二電極，該相變化材料 層與》亥第電極的接觸面積實質上小於該相變化材料層與 該第二電極的接觸面積，該方法包含以下步驟： .’i由。玄苐電極及該第二電極施加一設定電流脈衝到 該相變化材料層，以使該相變化材料層實質上完全結晶； 及 根據一寫入資料，經由該第一電極及該第二電極施加 至少一重設電壓脈衝到該相變化材料層，以在該相變化材 料層中產生-大小與該寫入資料對應的非晶區域，其中， 7 1379300 第__糊申鞠充侧嫩之說嘯顧 修正日期：料8月 該重設電！脈衝的振幅、寬度及數量中的至少一者是可調 寫入寅料對應，該重設電壓脈衝使該第一電極 的電壓減去該第二電極的電壓所得到的電壓差與該相變化 材料層的席貝克係數異號。 而本發明之另-目的即在提供一種相變化記憶體，容 易實現’且可以提高重覆次數及減輕熱串號問題。 於疋’本發明相變化記憶體包含複數相變化記憶胞及 一寫入電路。每一相變化記憶胞包括依序電連接的一第一 電極 相是化材料層及一第二電極，該相變化材料層與 該第一電極的接觸面積實質上小於該相變化材料層與該第 二電極的接觸面積。該寫人電路經由該等相.變化記憶胞中 被選定的一者的第一電極及第二電極，施加一設定電流脈 衝到該被選定的相變化記憶胞的相變化材料層，以使該被 選定的相變化記憶胞的相變化材料層實質上完全結晶及 根據一寫入資料，施加至少一重設電壓脈衝到該被選定的 相變化記憶胞的相變化材料層’以在該被選定的相變化記 憶胞的相變化材料層中產生一大小與該寫入資料對應的非 晶區域’其中’該重設電壓脈衝的振幅、寬度及數量中的 至少一者是可調的’且與該寫入資料對應，該重設電壓脈 衝使該被選定的相變化記憶胞的第一電極的電壓減去該被 選定的相變化δ己憶胞的第·一電極的電壓所得到的電壓差與 該被選定的相變化記憶胞的相變化材料層的席貝克係數異 號。 【實施方式】 1379300 第097124699號專利申請案補充、 修正日期_· 1〇】年8月 修正從無畫線之說明書替換黃 有關本發明之刖述及其他技術内容、特點與功效，在 以下配合參考圖式之_個較佳實施例的詳細說明中，將可 清楚地呈現。 >閱圖2與圖3 ’本發明相變化記憶體之較佳實施例包 含複數相變化記憶胞2、-寫入電路3及一讀取電路4。 每-相變化記憶胞2包括依序電連接的一第一電極接 觸21、一第一電極22、—相變化材料層23、一第二電極 24與一第二電極接觸25’以及-圍繞上述構件21〜25的介 電部26。如目3(a)所示’當相變化記憶胞2採用垂直結構 時’第一電極接觸21、第-電極22、相變化材料層23、第 二電極24及第二電極接觸25沿垂直方向排列。如圖3⑻所 示’當相變化記憶胞2採用線型結構時，第一電極22、相 變化材料層23及第二電極24沿水平方向排列。相變化記 隐月L 2也可以採用其它結構，不以垂直結構及線型結構為 限。 參閱圖4及圖5 ’寫入電路3多階程式化相變化記憶體 胞2中被選定的一者之方法包含以下步驟： 步驟51疋經由第一電極接觸21與第二電極接觸施 加一設定電流脈衝到相變化材料層23，以使相變化材料層 23貫質上完全結晶（即相變化材料層23中實質上沒有形成 '一非晶區域23 1 )。 在步驟51中，設定電流脈衝使相變化材料層23的最 冋咖·度丁⑺以貫質上介於其結晶溫度Te與其熔融溫度丁⑺之 間（即Tc<Tmax<Tm)，以使相變化材料層23從非晶相轉變 9 1379300 修正曰期：101年8月 第 _24699 號專利 成結晶相。 ，步驟52是根據一寫入資料，經由第一電極接觸η與 第一電極接觸25施加至少—重設電壓脈衝到相變化材 2曰3 ’以在相變化材料層23中形成大小與寫人資料對應的非 =區域23卜其中，重設電壓脈衝的振巾昌ν_、寬度及數 里中的至少—者是可調的，且與寫入資料對應。 藉由改邊重設電壓脈衝的振幅、寬度、數量或其等的 任意組合，例如：寬度固定，數量為！，只改變振幅，或者 例如：振幅固定’數量為1，只改變寬度，或者例如：數量 =1 ’改變振幅及寬度二者’或者例如：振幅固定，寬度固 定’只改變數量，可以在實質上完全結晶的相變化材料層 23中形成不同大小的非晶區域23工，如圖5⑷〜⑷所示（圖 5中只晝出相變化記憶胞2採用垂直結構的情況），其中， 若非晶區域231足以包覆第一電極22與相變化材料層23 的接觸面的話，則稱相變化材料層23實質上完全非晶。 一在步驟52中，重設電壓脈衝使相變化材料層23的最 局溫度τ_實質上超過其炫融溫度Tm (即τ舰八），以使 相變化材料層23從結晶相轉變成非晶相。較佳地，重設電 壓脈衝使相變化材料層23的最高溫度Τ隨實質上低於介電 部26的熔融溫度，以避免介電部26熔融。較佳地，在相 邊化材料層23與第-電極22之接觸面積實f上小於相變 化材料層23與第二電極24之接觸面積的情況下，重設電 壓脈衝使第—電極接觸21的電壓減去第二電極接觸25的 電壓所得到的電壓差與相變化材料層23㈣貝克係數（ 10 1379300 ‘ 第097124699號專利申諳案補充、修正後無畫線之說明書替換頁修正日期：101年8月1379300 IX. Description of the Invention: [Technical Field] The present invention relates to a method of staging a memory cell and a memory 'in particular to a multi-level stylized one-phase change memory cell Method and a phase change memory (PRAM). [Prior Art] Phase change memory is a non-volatile memory (n〇n_v〇latile memory) whose stored data does not disappear due to power removal. Since the phase change is quite fast and compatible with complementary metal oxide semiconductor (CMOS) processes, it is expected to have the opportunity to replace flash memory into non-volatile memory. Mainstream. The phase change memory uses a phase change material (for example, chaalCOgenide aU〇y) which can be switched between a crystalline phase (in a sultaneous phase) and an amorph 〇us phase by heating. To store the data. The phase change material has a low resistance system, a resisUvity, and a high reflectance under the crystal phase, and a resistivity coefficient and a low reflectance under the amorphous state. The phase change memory uses an electrical signal to heat the phase change material and distinguishes the stored data by the difference in resistivity between the crystalline phase and the amorphous phase. 1 Rewrite optical media (eg cd_rw and _ RW) also uses phase change materials to store data, but uses laser light to heat the phase change material and uses the phase change material to discern the stored data at the junction reflectance difference. The phase change material between the crystal phase and the amorphous phase is heated from the amorphous phase to the crystalline phase by heating the phase change material to a temperature exceeding 1379300, but below its melting temperature. The crystal phase, generally referred to as the process of setting * is wrong by heating the phase change material above its melting temperature and then cooling it down to convert it from a crystalline phase to an amorphous phase. This process is generally referred to as resetting. (reset) When the phase change memory is binary, the phase change material in the recording area of the phase change memory cell is converted between two different states (for example, completely crystalline and completely amorphous). Therefore, each phase change memory cell can store one dollar of data. When the phase change memory adopts multi-stage storage, the phase change material in the recording area of the phase change memory cell is in a plurality of different states (for example, completely crystalline, completely amorphous, and a portion between the two). Conversion between crystallizations to increase the amount of data stored in each phase of the memory cells. For example, if the phase change material in the recording area of the phase change memory cell is switched between four different states, then each phase change memory cell can store the data of the two bits. Referring to Figure 1, the January 2006 IEEE TRANSACTIONS ON ELECTRON DEVICES, Volume 53, Number 1, page 56, ''HSPICE Macromodel of PCRAM for Binary and Multilevel Storage') discloses a multi-stage, stylized, phase-change memory cell method. It is suitable for phase change memory using multi-stage storage. First, a reset current pulse 11 is applied to the phase change material of the phase change memory cell, so that the phase change material in the recording region is substantially completely amorphous (ie, the degree of crystallization is close to 〇%). Next, a phase change material for setting the current pulse 12 to the phase change memory cell is applied to make the phase change material in the recording region have a desired degree of crystallization (for example: 100% 6 1379300 ' patent application No. 097124699 After the addition and correction, there is no line drawing instructions to replace the page repair period: 1〇1 month, 65% or 40%.), where the width of the current pulse is set to correspond to the desired degree of crystallization. However, this The amplitude of the reset current pulse required by the method is large, and the maximum current that can be provided by the nanometer M〇s or the like is not conducive to achieving "in addition, each Stylization is to heat the phase change material of the phase change memory cell beyond its melting temperature and form a large melting area, so that it is easy to damage the phase change memory cell and reduce the number of repetitions and 'can change the nearby phase The phase change material of the memory cell undesirably reaches its crystallization temperature and is partially crystallized, causing a thermal cross-talk problem. [The present invention] Therefore, the object of the present invention is to provide a multi-stage stylized one-phase change memory. The cell method is easy to implement 'and can increase the number of repetitions and reduce the hot serial number problem. The method of multi-stage stylized one-phase change memory cells of the present invention is applicable to one-phase change memory cells, and the phase change memory cells include a first electrode, a phase change material layer and a second electrode electrically connected, wherein a contact area of the phase change material layer and the first electrode is substantially smaller than a contact area between the phase change material layer and the second electrode, The method comprises the steps of: 'i from the Xuanzan electrode and the second electrode applying a set current pulse to the phase change material layer to make the phase change material The material layer is substantially completely crystallized; and according to a writing data, at least one reset voltage pulse is applied to the phase change material layer via the first electrode and the second electrode to generate a size in the phase change material layer Write the data corresponding to the amorphous region, wherein, 7 1379300 __ paste 鞠 侧 侧 之 啸 啸 啸 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正The adjustable write buffer corresponds to a voltage difference obtained by subtracting the voltage of the second electrode from the voltage of the first electrode and a Scheib coefficient of the phase change material layer. Another object of the present invention is to provide a phase change memory which is easy to implement and which can increase the number of repetitions and reduce the number of hot strings. The phase change memory of the present invention comprises a plurality of phase change memory cells and a write circuit. Each phase change memory cell includes a first electrode phase sequentially electrically connected to the material layer and a second electrode, and the contact area of the phase change material layer and the first electrode is substantially smaller than the phase change material layer and the The contact area of the second electrode. The write circuit applies a set current pulse to the phase change material layer of the selected phase change memory cell via the first electrode and the second electrode of the selected one of the phase change memory cells to enable the The phase change material layer of the selected phase change memory cell is substantially completely crystallized and, according to a write data, at least one reset voltage pulse is applied to the phase change material layer of the selected phase change memory cell to be selected Forming, in the phase change material layer of the phase change memory cell, an amorphous region corresponding to the written data, wherein at least one of amplitude, width and number of the reset voltage pulse is adjustable and Corresponding to the write data, the reset voltage pulse subtracts the voltage difference between the voltage of the first electrode of the selected phase change memory cell and the voltage of the first electrode of the selected phase change δ cell The Sibeck coefficient of the phase change material layer of the selected phase change memory cell is different. [Embodiment] 1379300 Patent application No. 097124699, date of revision _·1〇] In August, the amendment replaces the description of the invention from the description of the invention and other technical contents, features and effects, in the following The detailed description of the preferred embodiment with reference to the drawings will be clearly presented. <Reading Figures 2 and 3' The preferred embodiment of the phase change memory of the present invention comprises a plurality of phase change memory cells 2, a write circuit 3 and a read circuit 4. The per-phase change memory cell 2 includes a first electrode contact 21 electrically connected in sequence, a first electrode 22, a phase change material layer 23, a second electrode 24 and a second electrode contact 25', and - surrounding The dielectric portion 26 of the members 21 to 25. As shown in FIG. 3(a), when the phase change memory cell 2 adopts a vertical structure, the first electrode contact 21, the first electrode 22, the phase change material layer 23, the second electrode 24, and the second electrode contact 25 are vertically oriented. arrangement. As shown in Fig. 3 (8), when the phase change memory cell 2 has a linear structure, the first electrode 22, the phase change material layer 23, and the second electrode 24 are arranged in the horizontal direction. Phase change Hidden moon L 2 can also adopt other structures, not limited by vertical structure and linear structure. Referring to FIG. 4 and FIG. 5, the method of selecting one of the multi-stage stylized phase change memory cells 2 of the write circuit 3 includes the following steps: Step 51: applying a setting by contacting the second electrode via the first electrode contact 21 The current is pulsed to the phase change material layer 23 such that the phase change material layer 23 is completely crystallized completely (i.e., substantially no 'amorphous region 23 1 ' is formed in the phase change material layer 23). In step 51, the current pulse is set such that the most gradual change (7) of the phase change material layer 23 is between the crystallization temperature Te and its melting temperature D (7) (ie, Tc < Tmax < Tm). Phase change material layer 23 is transformed from amorphous phase 9 1379300. Modified period: August 2011, No. _24699 patented into a crystalline phase. Step 52 is to apply at least a reset voltage pulse to the phase change material 2曰3' via the first electrode contact η and the first electrode contact 25 to form a size and write in the phase change material layer 23 according to a write data. The non-region 23 corresponding to the data, wherein the vibrating wiper ν_, the width and the number of the voltage pulses are adjustable, and corresponds to the written data. By changing the edge, reset the amplitude, width, number, or any combination of voltage pulses, for example, the width is fixed, the quantity is! , only change the amplitude, or for example: the amplitude is fixed 'the number is 1, only the width is changed, or for example: number = 1 'change both amplitude and width' or for example: fixed amplitude, fixed width 'only changes the number, can be in essence Amorphous regions 23 of different sizes are formed in the completely crystallized phase change material layer 23, as shown in Figs. 5(4) to (4) (in the case where only the phase change memory cell 2 adopts a vertical structure in Fig. 5), wherein an amorphous region is used. When the 231 is sufficient to cover the contact surface of the first electrode 22 and the phase change material layer 23, the phase change material layer 23 is said to be substantially completely amorphous. In step 52, the voltage pulse is reset such that the most local temperature τ_ of the phase change material layer 23 substantially exceeds its smelting temperature Tm (ie, τ ship eight) to cause the phase change material layer 23 to change from the crystalline phase to the non-phase. Crystal phase. Preferably, the voltage pulse is reset such that the highest temperature Τ of the phase change material layer 23 is substantially lower than the melting temperature of the dielectric portion 26 to avoid melting of the dielectric portion 26. Preferably, in the case where the contact area of the phase-cutting material layer 23 and the first electrode 22 is smaller than the contact area of the phase change material layer 23 and the second electrode 24, the voltage pulse is reset to make the first electrode contact 21 The voltage difference obtained by subtracting the voltage of the second electrode contact 25 and the phase change material layer 23 (4) Becker coefficient (10 1379300 ' Patent No. 097124699 Supplementary, revised no-line specification replacement page Revision date: 101 August
Seebeck coefficient)(即熱電係數）異號。 參閱圖6、圖7與表1，當相變化記憶胞2分別採用垂 直結構（以V表示）與線型結構（以L表示）、相變化材料 層 23 分別由 Ge22Sb24Te54 (以 GST 表不）與 Se2Sb7〇Te28 ( 以SST表示）製成、相變化記憶胞2的特徵尺寸（feature size)(以F表示）為65 nm，以及脈衝寬度為50ns時，根 據模擬結果，重設電壓脈衝的振幅Vreset與在結晶祖下的相 變化材料層23的最高溫度Tmaxi間的關係如圖6(a)所示， 設定電壓脈衝的振幅Vset與在非晶相下的相變化材料層23 的最高溫度Tmax之間的關係如圖6(b)所示，重設電流脈衝 的振幅Ireset與在結晶相下的相變化材料層23的最高溫度 Tmax之間的關係如圖7(a)所示，設定電流脈衝的振幅Iset與 在非晶相下的相變化材料層23的最高溫度Tmax之間的關係 如圖7(b)所示，以及相變化記憶胞2所需的重設電壓脈衝的 最小振幅（使在結晶相下的相變化材料層23的最高溫度 Tmax實質上達到其熔融溫度Tm)、設定電壓服衝的最小振幅 (使在非晶相下的相變化材料層23的最高溫度Tmax實質上 達到其結晶溫度Tc)、重設電流脈衝的最小振幅（使在結晶 相下的相變化材料層23的最高溫度Tmax實質上達到其熔融 溫度Tm)與設定電流脈衝的最小振幅（使在非晶相下的相 變化材料層23的最高溫度Tmax實質上達到其結晶溫度Tc) 如表1所示。由這些數據可知，利用電流脈衝來進行設定 而利用電壓脈衝來進行重設，可以降低脈衝振幅。 表1 11 1379300 ‘ 第097124699號專利申請案補充、修正後無畫線之說明書替換頁修正日期：101年8月 相變化記憶 重設電壓脈 設定電壓脈 重設電流 設定電流 胞的類型 衝的最小振 衝的最小振 脈衝的最 脈衝的最 幅 幅 小振幅 小振幅 SST-V 0.17V 3V 4261μΑ 35μΑ GST-V 0.27V 45V 2675μΑ 3μΑ SST-L 0.49V 7V 2937μΑ 16μΑ GST-L 0.60V 93V 1297μΑ 1 μΑ 參閱圖8，當相變化記憶胞2採用垂直結構（以V表示 )、相變化材料層23由Se2Sb70Te28 (以SST表示）製成、' 相變化記憶胞2的特徵尺寸（以F表示）分別為35nm、 65nm與150nm，以及脈衝寬度為50ns時，根據模擬結果， 重設電壓脈衝的振幅Vreset與在結晶相下的相變化材料層23 的最高溫度Tmax之間的關係如圖8(a)所示，設定電流脈衝 的振幅Iset與在非晶相下的相變化材料層23的.最向溫度 Tmax之間的關係如圖8(b)所示，以及相變化記憶胞2所需的 重設電壓脈衝與設定電流脈衝的最小振幅如表2所示。由 這些數據可知，即使特徵尺寸改變，仍可利用電流脈衝來 進行設定而利用電壓脈衝來進行重設。 表2 相變化記憶胞的特 重設電壓脈衝的最 設定電流脈衝的最 徵尺寸 小振中S 小振幅 35nm 0.13V 52μΑ 65nm 0.17V 3 5μΑ 150nm 0.21V 27μΑ 12 1379300 第___魏侧_驗爾麵 _仙年8月 另外根據域結果，在相變化材料層η⑨第 U之接觸面積實質上小於相變化材料層23肖第、 之接觸面積的情況下，無論相變化記憶胞2採 ’當相變化材料層23的席貝克係數實質上大於〇時，2 P壓脈衝使第—電極接觸21的電壓實質上大於第二電極 接觸25的電壓（即第_電極接觸21的電 接觸25的電壓所得到的電壓差與相變化材料層2 = =同號’二者皆是實質上大於。)，因為席貝克及： : ⑷4熱電效應的影響，相變化材料層23中的熱 旎集中位置會往第二電極24的方向移動，導致操作效 幅降低:甚一至無法操作，若重設電厂堅脈衝使第—電極接觸 21的電壓實質上小於第二電極接觸25的電壓（即第 接觸21的電壓減去第二電極接觸25的電厂堅所得到的電壓 差與相變一化材料I 23的席貝克係數異號，前者實質上小於 〇’後者實質上大於0)，相變化材料層23中的熱能集中位 置會往第一電極22的方向移動’導致操作效率提高，甚至 可以降低相變化記憶胞2所需的重設電壓脈衝的最小振幅 而當相變化材料層23的席貝克係數實質上小於〇時，若 重設電壓脈衝使第-電極接觸21的㈣實質上大於第二電 極接觸25的電| (即第—電極接觸21的電_去第二電 極接觸25的電塵所得到的電壓差與相變化材料層^的席 貝克係數異號，前者實質上大於Q，後者實質上小於〇)， 相變化材料層23中的熱能集中位置會往第一電極22的方 向移動，若重設電壓脈衝使第—電極接觸21的電壓實質上 13 1379300 第097124699利申補充 '修正畫線之說明書替換頁 修正日期：101年8月 小於第二電極接觸25的電壓（即 減去第二電極接觸25的電壓所得 ^接觸21的電壓 層23的席貝克係數同號，二者 文化材枓 苓舍疋貫質上小於〇) 材料層23中的熱能集中位置合往 相支化 。因此，在相變化材料層23與第—電極22之接觸夕= 質上小於相變化材料層23與第-雨 積貝 ^ ^ ^極24之接觸面積的情 況下，重設電壓脈衝使第-電極接觸21的電壓減去第二； 極接觸25的電壓所得到的電壓差與相變化材料層w 貝克係數異號，以提高操作效率。 值得注意較’在相變化材料層23與第—電極^之 接觸面積實質上小於相變化材料層23與第二電極Μ之接 觸面積的情況下，無論相變化記憶胞2採用何種結構，杂 重設電壓脈衝使第··電極接觸21的電壓減去第：電極接二 25的電壓所得到的電壓差與相變化材料層23的席貝克係數 異號時’在相變化材料層23中會形成呈圓頂形的非晶區域 231 (如圖5(a)〜⑷所示）’而當重設電壓脈衝使第一電極接 觸21力電塵減去第二電極接觸25的電壓所得到的電壓差 與相變化材料層23的席貝克係數同號時，在相變化材料層 23中會形成呈u形的非晶區域 231。 由於相變化3己憶胞2所需的設定電流脈衝的最小振幅 达小於所耗的重没電流脈衝的最小振幅，藉由使設定電流 脈衝的振幅Iset介於所需的設定電流脈衝的最小振幅與所需 的重設電流脈衝的最小振幅之間，可以使相變化記憶層B 從非晶相轉變成結晶相，但不會使相變化記憶層23從結晶 14 1379300 第097124699乾|·利申請案補充、修i後無畫線明書替換頁修正曰期：1〇1年8月 相轉變成非晶相，因此可以直接覆寫。再者，由於相變化 記憶胞2所需的重設電壓脈衝的最小振幅很小，即使將重 設電壓脈衝的振幅Vreset選取為大於所需的重設電壓脈衝的 最小振幅’仍可以小於奈米級MOS或類似元件所能提供的 最大電壓，因此容易實現。另外，相變化記憶胞2的相變 化材料層23不會在每次程式化時都形成很大的熔融區域， • 這樣較不容易損壞相變化記憶胞2，可以提高其重覆次數， 且較不會使附近的相變化記憶胞2的相變化材料層23非預 期地達到其結晶溫度而局部結晶，可以減輕熱串號問題。 參閱圖2與圖3，讀取電路4讀取相變化記憶體胞2中 被選定的一者所儲存的資料之方式是：經由第一電極接觸 21及第二電極接觸25，施加一讀取電壓脈衝到相變化材料 層23，並偵測流過相變化材料層23的電流，其中，讀取電Seebeck coefficient) (ie thermoelectric coefficient). Referring to FIG. 6, FIG. 7 and Table 1, when the phase change memory cell 2 adopts a vertical structure (indicated by V) and a linear structure (indicated by L), the phase change material layer 23 is respectively composed of Ge22Sb24Te54 (in GST) and Se2Sb7. 〇Te28 (represented by SST), the characteristic size of the phase change memory cell 2 (indicated by F) is 65 nm, and the pulse width is 50 ns, according to the simulation result, the amplitude Vreset of the voltage pulse is reset and The relationship between the highest temperature Tmaxi of the phase change material layer 23 under the crystal ancestors is as shown in Fig. 6(a), and the amplitude Vset of the set voltage pulse is set to the highest temperature Tmax of the phase change material layer 23 under the amorphous phase. The relationship between the amplitude Ireset of the reset current pulse and the highest temperature Tmax of the phase change material layer 23 under the crystal phase is as shown in Fig. 7(a), and the current pulse is set as shown in Fig. 6(b). The relationship between the amplitude Iset and the highest temperature Tmax of the phase change material layer 23 in the amorphous phase is as shown in Fig. 7(b), and the minimum amplitude of the reset voltage pulse required for the phase change memory cell 2 The highest temperature Tm of the phase change material layer 23 under the crystalline phase Ax substantially reaches its melting temperature Tm), sets the minimum amplitude of the voltage impulse (so that the highest temperature Tmax of the phase change material layer 23 in the amorphous phase substantially reaches its crystallization temperature Tc), and resets the minimum amplitude of the current pulse (the maximum temperature Tmax of the phase change material layer 23 under the crystal phase is substantially reached to its melting temperature Tm) and the minimum amplitude of the set current pulse (the maximum temperature Tmax of the phase change material layer 23 in the amorphous phase is substantially The crystallization temperature Tc) is reached as shown in Table 1. From these data, it can be seen that the pulse amplitude can be reduced by setting with a current pulse and resetting with a voltage pulse. Table 1 11 1379300 'Patent Application No. 097124699 Supplementary, Corrected No Line Drawing Instructions Replacement Page Revision Date: August 101 Phase Change Memory Reset Voltage Pulse Setting Voltage Pulse Reset Current Setting Current Cell Type Minimum Minimum amplitude of the minimum pulse of the vibration pulse Small amplitude Small amplitude SST-V 0.17V 3V 4261μΑ 35μΑ GST-V 0.27V 45V 2675μΑ 3μΑ SST-L 0.49V 7V 2937μΑ 16μΑ GST-L 0.60V 93V 1297μΑ 1 μΑ Referring to FIG. 8, when the phase change memory cell 2 adopts a vertical structure (indicated by V), the phase change material layer 23 is made of Se2Sb70Te28 (represented by SST), and the characteristic size of the phase change memory cell 2 (indicated by F) is respectively 35nm, 65nm and 150nm, and a pulse width of 50ns, according to the simulation results, the relationship between the amplitude Vreset of the reset voltage pulse and the maximum temperature Tmax of the phase change material layer 23 under the crystal phase is as shown in Fig. 8(a). It is shown that the relationship between the amplitude Iset of the current pulse and the maximum temperature Tmax of the phase change material layer 23 in the amorphous phase is as shown in FIG. 8(b), and the reset required for the phase change memory cell 2 is shown. Electricity And setting the minimum amplitude of the pulse current pulse as shown in Table 2. From these data, it can be seen that even if the feature size is changed, the current pulse can be used to set and the voltage pulse is used for resetting. Table 2 The most set current pulse of the phase change memory cell is set to the maximum value of the current pulse. Small amplitude S1 small amplitude 35nm 0.13V 52μΑ 65nm 0.17V 3 5μΑ 150nm 0.21V 27μΑ 12 1379300 ___魏侧_验In addition, according to the domain result, in the case where the contact area of the U-phase of the phase change material layer η9 is substantially smaller than the contact area of the phase change material layer 23, regardless of the phase change memory cell 2 When the Sibeck coefficient of the phase change material layer 23 is substantially larger than 〇, the 2 P pressure pulse causes the voltage of the first electrode contact 21 to be substantially greater than the voltage of the second electrode contact 25 (ie, the voltage of the electrical contact 25 of the _ electrode contact 21). The resulting voltage difference is substantially greater than the phase change material layer 2 = = the same number '. Both, because of the effect of the thermoelectric effect, the heat enthalpy concentration in the phase change material layer 23 will Moving in the direction of the second electrode 24 causes the operation efficiency to decrease: even to the inoperability, if the power plant is reset, the voltage of the first electrode contact 21 is substantially smaller than the voltage of the second electrode contact 25 (ie, the contact 21) Voltage The voltage difference obtained by the power plant to the second electrode contact 25 is different from the Sibeck coefficient of the phase change material I 23 , the former being substantially smaller than 〇 'the latter is substantially greater than 0), and the phase change material layer 23 The position at which the heat energy is concentrated will move toward the direction of the first electrode 22, resulting in an increase in operational efficiency, and may even reduce the minimum amplitude of the reset voltage pulse required for the phase change memory cell 2 while the Sibeck coefficient of the phase change material layer 23 is substantially smaller. In the case of 〇, if the voltage pulse is reset, (4) of the first electrode contact 21 is substantially larger than the electric current of the second electrode contact 25 (ie, the voltage obtained by the electric current of the first electrode contact 21 to the second electrode contact 25) The Sibeck coefficient of the difference and the phase change material layer is substantially larger than Q, and the latter is substantially smaller than 〇), and the heat energy concentration position in the phase change material layer 23 is moved toward the first electrode 22, if reset The voltage pulse causes the voltage of the first electrode contact 21 to be substantially 13 1379300. The 097124699 supplements the 'correction line specification' replacement page correction date: the August 101 month is less than the voltage of the second electrode contact 25 (ie minus the first The voltage of the two-electrode contact 25 is obtained. The voltage of the contact layer 21 is the same as the Sbeck coefficient of the layer 23, and the two materials are less than 〇. The thermal energy concentration in the material layer 23 is combined with the phase branching. Therefore, in the case where the contact between the phase change material layer 23 and the first electrode 22 is qualitatively smaller than the contact area of the phase change material layer 23 and the first rain product layer, the voltage pulse is reset to the first The voltage of the electrode contact 21 is subtracted from the second; the voltage difference obtained by the voltage of the pole contact 25 is different from the phase change material layer w Beck coefficient to improve the operation efficiency. It is worth noting that, in the case where the contact area of the phase change material layer 23 and the first electrode is substantially smaller than the contact area of the phase change material layer 23 and the second electrode ,, regardless of the structure of the phase change memory cell 2, When the voltage pulse is reset, the voltage difference obtained by subtracting the voltage of the first electrode contact 21 from the voltage of the second electrode 25 is different from the Scheib coefficient of the phase change material layer 23, 'will be in the phase change material layer 23 Forming a dome-shaped amorphous region 231 (shown in FIGS. 5(a) to (4))' and resetting the voltage of the first electrode contact 21 to subtract the voltage of the second electrode contact 25 When the voltage difference is the same as the Sibeck coefficient of the phase change material layer 23, an amorphous region 231 having a u shape is formed in the phase change material layer 23. Since the minimum amplitude of the set current pulse required for phase change 3 has less than the minimum amplitude of the consumed heavy current pulse, by setting the amplitude Iset of the set current pulse to the minimum amplitude of the desired set current pulse Between the minimum amplitude of the desired reset current pulse, the phase change memory layer B can be converted from the amorphous phase to the crystalline phase, but the phase change memory layer 23 is not made from the crystal 14 1379300 097124699 dry | After the case is added, after the repair, there is no line to replace the book to replace the page. The period is changed: 1 to 1 year, the phase is transformed into an amorphous phase, so it can be directly overwritten. Furthermore, since the minimum amplitude of the reset voltage pulse required for the phase change memory cell 2 is small, even if the amplitude Vreset of the reset voltage pulse is selected to be larger than the minimum amplitude of the desired reset voltage pulse, it can be smaller than the nanometer. The maximum voltage that a MOS or similar component can provide is therefore easy to implement. In addition, the phase change material layer 23 of the phase change memory cell 2 does not form a large melting region every time it is programmed, and it is less likely to damage the phase change memory cell 2, which can increase the number of repetitions, and The phase change material layer 23 of the nearby phase change memory cell 2 is not expected to reach its crystallization temperature and is partially crystallized, which can alleviate the heat serial number problem. Referring to FIG. 2 and FIG. 3, the reading circuit 4 reads the data stored by the selected one of the phase change memory cells 2 by applying a read through the first electrode contact 21 and the second electrode contact 25. The voltage pulse is applied to the phase change material layer 23, and the current flowing through the phase change material layer 23 is detected, wherein the read current
壓脈衝使相變化材料層23的最高溫度實質上低於其結 晶溫度 tc (即 Tmax<Tc)。 、D 當相變化記憶胞2採用垂直結構（以v表示）' 相變化 材料層23由GhSbaTe54 (以GS丁表示）製成、相變化記 隐胞2的特徵尺寸（以F表示）&丨5()腿，以及非晶區域 231的半徑（以r表示）分別為25nm、50nm、70nm與 80nm時，根據模擬結果，若讀取電路4施加電壓脈衝到相 變化材料層23並偵測流過相變化材料層23的電流以讀取 資料的活，由於偵測到的電流會有很大的差異，可以用來 辨別不同大小的非晶區域231 (如圖9所示），而若讀取電 路4施加電流脈衝到相變化材料層23並_相變化材料層 15 1379300 綱廳細擔槪、織綱纖麵胃 細㈣年8月 23的跨壓以讀取資料的話，在非晶區域231不足以包覆第 -電極22與相變化材料層23的接觸面之情況下（例如· 非晶區域23i呈圓頂形’但不夠大’或者非晶區域231呈^ 形）’由於相變化材料層23中會有漏電流路徑，使得谓測 到的㈣沒有差異，無法用來辨別不同大小的非晶區域231 。因此，利用電歷脈衝來讀取資料，可以避免訊號無法辨 別。 較佳地，在相變化材料層23與第一電極22之接觸面 積實質上小於相變化材料層23與第二電極24之接觸面積 的情況下，讀取電壓脈衝使第一電極接觸21的電壓減去第 二電極接觸25的電麼所得到的㈣差與相變化材料層η 的席貝克係數同號，如此一來，相變化材料層23中的熱能 集中位置會往第二電極24的方向移動，導致散熱效果較好 〇 綜上所述，本實施例藉由先利用設定電流脈衝以使相 文化材料層23貫g上完全結晶，再利用重設電壓脈衝以在 相變化材料層23中形成期望大小的非晶區域231，容易實 現’且可以提尚重覆次數及減輕熱串號問題，因此確實可 以達到本發明之目的。 准以上所述者’僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 16 1379300 修正曰期：1〇1年8月 第09Ή24699號專利申綠補充胃 圖 化記憶胞的方法； 疋一模擬圖，說明習知的一種多階程式化—相變 圖2疋一方塊圖，說明本發明相變化記憶體之較佳實 施例； 圖3是一剖面圖，說明較佳實施例的相變化記憶胞， (a)採用垂直結構，或（b)採用線型結構； 圖4是一流程圖，說明較佳實施例多階程式化相變化 記憶胞的方法； 圖5是一剖面圖，說明相變化記憶胞在相變化材料層 中形成不同大小的非晶區域’⑷非晶區域最小，⑻次之， (c)再次之’及（d)非晶區域最大； 圖6疋一模擬圖，說明在相變化記憶胞的類型不同時 ，（a)重設電壓脈衝的振幅與在結晶相下的相變化材料層的 最兩溫度之間的關係，及（b)設定電壓脈衝的振幅與在非晶 相下的相變化材料層的最高溫度之間的關係； 圖7疋一模擬圖，說明在相變化記憶胞的類型不同時 ，（a)重設電流脈衝的振幅與在結晶松下的相變化材料層的 最向溫度之間的關係，及（1?)設定電流脈衝的振幅與在非晶 相下的相變化材料層的最高溫度之間的關係； 圖8是一模擬圖’說明在相變化記憶胞的特徵尺寸不 同時’（a)重設電壓脈衝的振幅與在結晶相下的相變化材料 層的最尚溫度之間的關係，及（b)設定電流脈衝的振幅與在 非晶相下的相變化材料層的最高溫度之間的關係；及 圖9是一模擬圖，說明不同大小的非晶區域所導致的 17 1379300 ' 第097124699號專利申諳案補充、修正後無畫線之說明書替換頁修正日期：ιοί年8月 電流差異。 18 1379300 ' 第097124699號專利申請案補充、修正後無畫線之說明書替換頁修正日期：101年8月 【主要元件符號說明】 2…… •…相變化記憶胞 25........ •第二電極接觸 21 ··... •…第一電極接觸 26........ •介電部 22·...· •…第一電極 3 ......... •寫入電路 23…·. •…相變化材料層 4 ......... •讀取電路 231 ··· …·非晶區域 51 ' 52 · •步驟 24···.· •…第二電極 19The pressure pulse causes the highest temperature of the phase change material layer 23 to be substantially lower than its crystal temperature tc (i.e., Tmax < Tc). D When the phase change memory cell 2 adopts a vertical structure (indicated by v) 'The phase change material layer 23 is made of GhSbaTe54 (represented by GS dice), and the characteristic size of the phase change cell 2 (indicated by F) & When the 5() leg and the radius of the amorphous region 231 (indicated by r) are 25 nm, 50 nm, 70 nm, and 80 nm, respectively, according to the simulation result, if the reading circuit 4 applies a voltage pulse to the phase change material layer 23 and detects the flow. The current of the phase change material layer 23 is read to read the data. Since the detected current has a large difference, it can be used to distinguish amorphous regions 231 of different sizes (as shown in FIG. 9), and if read Take the circuit 4 to apply a current pulse to the phase change material layer 23 and _ phase change material layer 15 1379300 纲 细 细 槪 槪 织 织 织 织 织 槪 织 织 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 231 is insufficient to coat the contact surface of the first electrode 22 and the phase change material layer 23 (for example, the amorphous region 23i is dome-shaped but not large enough or the amorphous region 231 is shaped). There is a leakage current path in the material layer 23, so that there is no difference in the measured (four). Method used to identify the amorphous region 231 of different sizes. Therefore, using the electrical calendar pulse to read the data can avoid the signal being unrecognizable. Preferably, in the case where the contact area of the phase change material layer 23 and the first electrode 22 is substantially smaller than the contact area of the phase change material layer 23 and the second electrode 24, the voltage of the first electrode contact 21 is read by the voltage pulse. The difference between the (four) difference obtained by subtracting the electric power of the second electrode contact 25 and the Sibeck coefficient of the phase change material layer η is such that the heat energy concentration position in the phase change material layer 23 is directed to the second electrode 24. Moving, resulting in better heat dissipation. In summary, in the present embodiment, the set current pulse is used to completely crystallize the phase material layer 23, and then the reset voltage pulse is used in the phase change material layer 23. Forming the amorphous region 231 of a desired size is easy to achieve and can raise the number of repetitions and reduce the number of hot strings, so that the object of the present invention can be achieved. The above-mentioned ones are only the preferred embodiments of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are all It is still within the scope of the invention patent. [Simple description of the diagram] 16 1379300 Correction period: 1〇August, August 09Ή24699 Patent Shen Green supplements the method of gastric image memory; 疋一模拟图, illustrating a multi-level stylization-phase transition Figure 2 is a block diagram showing a preferred embodiment of the phase change memory of the present invention; Figure 3 is a cross-sectional view showing the phase change memory cell of the preferred embodiment, (a) using a vertical structure, or (b) employing Figure 4 is a flow chart illustrating a preferred embodiment of a multi-step programmed phase change memory cell; Figure 5 is a cross-sectional view showing phase change memory cells forming different sizes of amorphous in a phase change material layer The region '(4) amorphous region is the smallest, (8) is the second, (c) again 'and (d) the amorphous region is the largest; Figure 6 is a simulation diagram showing that when the type of phase change memory cell is different, (a) reset The relationship between the amplitude of the voltage pulse and the two temperatures of the phase change material layer under the crystalline phase, and (b) the relationship between the amplitude of the set voltage pulse and the maximum temperature of the phase change material layer in the amorphous phase Figure 7疋A simulation diagram illustrating the phase change When the type of the cell is different, (a) reset the relationship between the amplitude of the current pulse and the temperature of the phase change material layer in the crystal Panasonic, and (1?) set the amplitude of the current pulse and the amorphous phase The relationship between the highest temperature of the phase change material layer; Figure 8 is a simulation diagram 'Describes the difference in the characteristic size of the phase change memory cell' (a) the amplitude of the reset voltage pulse and the phase change material under the crystalline phase The relationship between the most extreme temperatures of the layers, and (b) the relationship between the amplitude of the current pulse and the maximum temperature of the phase change material layer in the amorphous phase; and Figure 9 is a simulated diagram illustrating different sizes 17 1379300 'After the amorphous area, the patent application No. 097124699 is added, and the revised line is replaced by the instruction sheet. Correction date: ιοί year August current difference. 18 1379300 'The patent application No. 097124699 is added, the specification of the no-line after the correction is replaced. The date of revision: August, August [Description of main component symbols] 2... •...phase change memory cell 25.... • Second electrode contact 21 ··... •...First electrode contact 26.........Dielectric part 22·...·......first electrode 3 ....... .. • Write circuit 23...·.•...phase change material layer 4 .......... read circuit 231 ····· amorphous region 51 ' 52 · • Step 24···. · •...second electrode 19