1377682 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種陣列基板的製造方法，特別是關於 一種可減少接觸窗關鍵尺寸損失之陣列基板的製造方法。 【先前技術】 隨著科技進步，具有省電、無幅射、體積小、低耗電 量、。平面直角、高解析度、畫質穩定等多概勢的液晶顯 示器，為原先處獨佔地位之傳統映像管螢幕(簡稱CRT)帶 來了莫大的衝擊’尤其是現今各式資訊產品如：手機、筆 記型電腦、數位相機、PDA、液晶螢幕等產品越來越普及，BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating an array substrate, and more particularly to a method of fabricating an array substrate capable of reducing the critical dimension loss of a contact window. [Prior Art] With the advancement of technology, it has power saving, no radiation, small size, and low power consumption. The liquid crystal display with a flat right angle, high resolution, stable image quality, etc., has brought a great impact to the original traditional image tube screen (CRT). Especially today's various information products such as mobile phones, Notebook computers, digital cameras, PDAs, LCD screens and other products are becoming more and more popular.
亦使得液晶顯示器(LCD)的需求量大大提升。 液晶顯示器主要係包括一液晶顯示面板以及一背光 模組(backlight moduie)，其中液晶顯示面板是由一彩色遽 光片基板(color filter)、一薄膜電晶體陣列基板(TFT町# substrate)以及配置於此兩基板之間的液晶層所構成而背 光模組是_提供此液晶面板所需之面光源，以使液晶顯 示器達到顯示的效果。 請參閱圖―’係為f知技術之薄膜電晶體之結構俯視 ，。液晶顯示H具有複數個㈣歸的_錢素單元， 每-個像素單元係由-像素電極1()和_細電晶體以斤 構成’其中薄膜電晶體12包含有-閘極(未圖示）、一通道 一源極124與-_126。其中’通道層係覆蓋於 間極上方’且源極124與沒極126之間具有-通道128。雖 閘極未以圖示顯示，但其係與掃爾14電性連接自不待 5 (S ) 1377682 言，而源極124電性連接資料線10，沒極U6與像素電極⑴ 做-電性連接。其中電晶體來做為液晶顯示器 但是，在薄膜電晶體製作過程中，常會因為汲極與源 極通道(SD channel)製程殘留等問題，使得一些金屬微粒 或者是導電的污染物在完成侧及清洗製程後，仍殘留在 薄膜電晶體的通道處’產生點缺陷，造成薄膜電晶體中源 極與/及極之間的通道發生短路情況，破壞舰電晶體控制 開關的作用。 請參閱圖二A至圖二η，係為習知陣列基板對應製程 之流程圖。目前’於主動式陣列基板之製作，—般係經由 五道或四道微影製程之製程，以下係以薄膜電晶體區、晝 素區以及配置於掃描線周邊電路之電極端子區的截面圖 做為說明。It also greatly increases the demand for liquid crystal displays (LCDs). The liquid crystal display mainly comprises a liquid crystal display panel and a backlight moduie, wherein the liquid crystal display panel is composed of a color filter, a thin film transistor array substrate and a configuration. The liquid crystal layer is formed between the two substrates, and the backlight module is a surface light source required for the liquid crystal panel to achieve the display effect of the liquid crystal display. Please refer to the figure "' for the structure of the thin film transistor of the technology. The liquid crystal display H has a plurality of (four) returned _ 素 单元 cells, each pixel unit is composed of - pixel electrode 1 () and _ fine transistor jin "where the thin film transistor 12 includes a - gate (not shown ), one channel and one source 124 and -_126. Wherein the 'channel layer is over the interpole' and the source 124 and the dipole 126 have a - channel 128. Although the gate is not shown in the figure, it is electrically connected to the Sieel 14 and is not connected to 5 (S) 1377682. The source 124 is electrically connected to the data line 10, and the U6 and the pixel electrode (1) are electrically-charged. connection. Among them, the transistor is used as a liquid crystal display. However, in the process of fabricating a thin film transistor, problems such as draining of the drain and source channel (SD channel) are often caused, and some metal particles or conductive contaminants are on the finished side and cleaned. After the process, it still remains in the channel of the thin film transistor to generate a point defect, which causes a short circuit between the source and/or the pole in the thin film transistor, and destroys the function of the ship's transistor control switch. Please refer to FIG. 2A to FIG. 2n, which are flowcharts of a corresponding process for a conventional array substrate. At present, the fabrication of the active array substrate is generally performed by a five- or four-channel lithography process, and the following is a sectional view of the thin film transistor region, the halogen region, and the electrode terminal region disposed on the peripheral circuit of the scan line. As an explanation.
像素單元之開關元件 首先’如圖一Α所示，使用濺鍵(SpUtter)等鑛膜方式且 使用第一道光罩(未圖示)將絡、鋇、矩、紹、銅、翻或其 合金，選擇性形成複數個金屬區塊於玻璃基板2之表面 上，作為第一金屬層21，以做為掃描線與閘極。 接著使用電漿化學汽相沈積(CVD)、濺鍍等鍍膜方 式’如圖二B所示，依序形成一絕緣層22、一半導體層23、 一第二金屬層24以及一光阻層PR。然後，利用第二道光罩 HM將光阻層PR曝光以形成未曝光部分、完全曝光部分以 及半色調曝光部分之不同膜厚的第一光阻圖案PRl，如圖 二C所示。 接著，以第一光阻圖案PRl為遮罩，利用電漿進行光 阻的灰化(Ashing)及一般之乾式蝕刻方式以蝕刻半導體 6 1377682 • 層’接著施以濕蝕刻製程蝕刻第二金屬層而依序形成源 極、汲極’亦即，進行源極與汲極之分離。然後，除去第 一光阻圖案PR,，如圖二D所示。 接著，如圖二E所示，利用塗佈感光性丙烯酸系有機 光阻25，為一平坦層，用以使陣列基板之表面變成平坦。 如圖二F所示，然後，使用第三道光罩(未圖示），灰化 (ashing)部分感光性丙烯酸系有機光阻25與絕緣層22以到 達第一金屬層21、第二金屬層24，令第一金屬層21和第二 • 金屬層24部分露出。接著，利用濺鍍法或塗佈法等在破璃 基板之整面被覆形成透明導電膜26。透明導電膜26—般係 使用氧化銦錫(ITO)等金屬氧化膜。 然後，使用第四光罩(未圖示）’形成如圖二G所示， 第二光阻圖案PR2為遮罩選擇性蝕刻透明導電膜26，進行 畫素電極之圖案化。然後，如圖所示，除去不要之第 光阻圖案PR2，玻璃基板2就成為主動式陣列基板。 ，將依此方式得到之陣列基板和彩色濾光片基板貼合 • 而製作成液晶面板’接著組裝背光模組以及驅動電路以構 成各種液晶顯示裝置。 “為了製作主動式陣列基板’上述之製作方法需要四道 光罩，使得製程前置時間(lead time)拉長，又因作為晝素 • ，極之底層的平坦化膜曝露灰化反應中，會有較大的^厚 知失，所以接觸窗會有較大的關鍵尺寸損失，且在製作接 =洞時，由於第二金屬層在平坦層的微影_中，於顯 〜凡成後已經露出’再覆蓋透明導電膜之前若在經歷一乾 ，刻製程’沒極與源極表面將遭受長時間的電漿義擊，而 容易造纽極與源極(第二金屬層)的表面缺陷，將影響第 7 c S ) 梅微娜_，使成為良率 因此本發明提供-_基板之製作方法，利用 ”並相對應改變製作流程，使陣列基板可以減少 製程時間’並減低接職關鍵尺寸之損失。 【發明内容】 、本發明之主要目的係在於提供一種陣列基板之 法制利用一半色調光罩製程並相對應改變製作流程， 製程_ ’錢低綱S驗財之損失。 ^ 本發明提供了-種陣列基板的製造方法，其步驟至少 匕括·形成複數個金屬區塊於—基底上之—第—區域 :第二區域内；在基底上依序形成—絕緣層以及一 層’並覆蓋於上述之複數個金屬區塊上；塗佈—第 ^於^上’並覆蓋半導體層及其下方之金屬區塊上 ;:土色調光罩在金屬區塊上方形成-第-光阻圖案與一 絕緣層，用以曝露出第二區域内之金屬區塊二Π 除!r第一光阻層;移除未被第-光二 半導體層上 因此本發明所提供的液晶顯示器之 製作流程做—變更且利用半色調光罩進= 電膜不需再經過蝕刻，及可直接鍍上透明導 電膜，使良率k向；另外，本發明之製程皆在同一個真空 腔體中進行，不需破真空移至另一真空腔體中進行反應， 故減少搬運時間可縮短整體製程時間。 【實施方式】 本發明之技術内容結合元件之相對位置關係與顯示面 板之'、>〇構特徵，係以陣列基板上其薄膜電晶體區與其端子 區之戴面圖來做介紹如下’其餘乃與現有技術相同，故不 多加贅述。 δ月參照圖三A至圖三I，係為本發明一實施例陣列基 板橫截面的製程流程圖。首先，如圖三A所示，係先提供 一基底3 ,其基底3係為一透明絕緣基板，其材質可為玻 璃、石英或塑膠等。接著濺鍍一金屬材料於基底3上，形 成一第一金屬層31於基底3上表面，然後，塗佈一光阻層 並利用一第一光罩做曝光、蝕刻，以圖案化第一金屬層 31，形成一共通電極31〇與一閘極312等複數個金屬區塊 於基底3之上表面。 而共通電極310與閘極312之材質可為導電單層或多 層金屬或其合金，如鋁(A1)、鉻(Cr)、鈦(Ti)、鉬鎢(MoW) 或其合金等。如圖中所示，以下將以第一區域為薄膜電晶 體區，第二區域為端子區做為說明；其中第二區域更可以 包含電容結構、一内部靜電防護環(inner sh〇rt_ring)或是一 外部防護靜電環(outer short-ring)結構，即第二區域中之金 屬區塊共通電極310 (第一金屬層31)係可以利用後續製程 以形成不同元件達到各自功效。 1377682 如圖三B所示’一絕緣層32係形成於共通電極31〇 與閘極線312等複數金屬區塊上。接著，一通道層別沈 積於絕緣層32上…歐姆接觸層说沈積於通道層别 上；其中’通道層331與歐姆接觸層332係可視為一半導 體層33，設置於絕緣層32上方。 接著’如圖二（：所示’一光阻層PR形成於半導體層 33上。其中，光阻層PR可藉由旋轉塗佈(spin coating)或非 旋轉塗佈(Spinlessc〇ating)等方式形成。隨後，以一半色調 光罩HM](亦可稱為半透膜光罩)進行曝光、_，以圖案 化光阻層PR，依半色罩_之雜可將曝光區分為 第一曝光區、第二曝光區與第三曝光區。 依照上述所區分之第一曝光區、第二曝光區與第三曝 光區，對照®SD所示，其巾第—曝光區係泛指薄膜電晶 體區域，其所對應之半色調光罩ΗΜι係為遮避區，故圖案 化後所形成之第-光阻圖案PRi絲曝光部分，具有突起 較厚之光阻層PR。 第二曝光區係泛指第二區域，即端子部、電容結構、 内部靜電防護環或是外部防護靜電環區域結構，其所對應 之半色調光罩HM〗係為穿透區，故圖案化後所形成之第二 光阻圖案PR2為完全曝光部份’形成一下凹且較薄之光阻 層PR 〇 第三曝光區係泛指第一區域及第二區域以外之處，即 晝素區域，其所對應之半色調光罩HM,係為半穿透區，故 圖案化後所形成之第三光阻圖案為一半色調曝光部分，形 成一中間厚度(相較於第一光阻圖案PRl&第二光阻圖案 10 1377682 PR2之厚度)之光阻層PR。 如圖三E所示，於後續製程中侧已曝光之光阻層 PR，並移除第二光阻圖案PR:及其下方部分之半導體層& 及絕緣層32，以路出第二區域中之共通電極“ο。 接著’如圖二F所示，利用灰化製程，將第一光阻圖 案PRl之外的剩餘紐層PR移除，即將第三光阻圖案^ _灰化反應將其移除n續將未被光阻_所覆蓋的3 部分半導體層33蝕刻移除，形成如圖三G所示。 隨後，將光阻圖案移除，並於第一區域中沈積一第二 金屬層34’利用一第二光罩(未圖示)將其第二金屬層^ 圖案化，以形成一源極341與一汲極342 ;其中，在形成 源極341以及汲極342時，位於源極341與汲極342之間 的歐姆接觸層332會被移除。 如圖三Η所示，於基底3塗佈一平坦層35，其中平坦 層35係可用丙烯酸系有機材料製成。再利用一第三光罩 • Μ3將其平坦層35目案化，並利用微雜成以形成複數個 接觸孔貫穿平坦層35,以暴露出共通電極31〇與汲極342; 其中，在微影製成中更依序進行一漂白步驟(Wine bleaching)以及一交聯反應(Curing)，可使得平坦層％内部 形成三維網狀結構，可大幅提昇其機械強度、耐酸鹼能力 及耐候性等。 再者，如圖三I所示，在此平坦層35凹凸的表面結構 上，塗佈一透明導電膜，例如：氧化銦等金屬氧化物，並 利用一第四光罩將透明導電膜圖案化，形成晝素電極36 ; 11 (S ) 1377682 其中，畫素電極36藉由接觸孔與共通電極31()與汲極342 電性連接。至此為止，液晶顯示器之陣列基板的基本元件 已大致構築完成。 隨後，透過與彩色濾光片基板貼合而製作成液晶面 板，接著組裝背光模組以及驅動電路以構成各種液晶顯示 裝置。 根擄上述之說明，可以瞭解本發明的技術特徵在於：The switching element of the pixel unit firstly uses the first film mask (not shown) to use the first film mask (not shown) to use the mineral film method such as SpUtter to display the network, the 钡, the moment, the 、, the copper, or the The alloy selectively forms a plurality of metal blocks on the surface of the glass substrate 2 as the first metal layer 21 as a scan line and a gate. Then, using a plasma chemical vapor deposition (CVD), sputtering, or the like, as shown in FIG. 2B, an insulating layer 22, a semiconductor layer 23, a second metal layer 24, and a photoresist layer PR are sequentially formed. . Then, the photoresist layer PR is exposed by the second mask HM to form first photoresist patterns PR1 of different film thicknesses of the unexposed portion, the fully exposed portion, and the halftone exposed portion, as shown in Fig. 2C. Next, the first photoresist pattern PR1 is used as a mask, the photoresist is ashed by a plasma and a general dry etching method is used to etch the semiconductor 6 1377682. The layer is then subjected to a wet etching process to etch the second metal layer. The source and the drain are formed in sequence, that is, the source and the drain are separated. Then, the first photoresist pattern PR is removed as shown in Fig. 2D. Next, as shown in Fig. 2E, a photosensitive acrylic organic resist 25 is applied as a flat layer for flattening the surface of the array substrate. As shown in FIG. 2F, a third photomask (not shown) is then used to ash a portion of the photosensitive acrylic organic photoresist 25 and the insulating layer 22 to reach the first metal layer 21 and the second metal layer. 24. The first metal layer 21 and the second metal layer 24 are partially exposed. Next, the transparent conductive film 26 is formed on the entire surface of the glass substrate by a sputtering method, a coating method, or the like. As the transparent conductive film 26, a metal oxide film such as indium tin oxide (ITO) is used. Then, a fourth photomask (not shown) is formed as shown in Fig. 2G, and the second photoresist pattern PR2 selectively etches the transparent conductive film 26 as a mask to pattern the pixel electrodes. Then, as shown in the figure, the unnecessary photoresist pattern PR2 is removed, and the glass substrate 2 becomes an active array substrate. The array substrate and the color filter substrate obtained in this manner are bonded together to form a liquid crystal panel. Then, the backlight module and the driving circuit are assembled to constitute various liquid crystal display devices. "In order to make an active array substrate, the above-mentioned manufacturing method requires four masks, so that the lead time of the process is elongated, and the ashing reaction of the flattening film as the bottom layer of the substrate is There is a large thickness, so the contact window will have a large critical dimension loss, and when the connection is made, because the second metal layer is in the lithography of the flat layer, Excluding the fact that if it is subjected to a dry process before the transparent conductive film is covered, the immersion process and the source surface will suffer from long-term plasma stimuli, and the surface defects of the kiln and the source (second metal layer) are easily formed. Will affect the 7th c S) Mewina _, making it a yield. Therefore, the present invention provides a method for manufacturing a substrate, which utilizes "and correspondingly changes the manufacturing process so that the array substrate can reduce the processing time" and reduces the key size of the replacement. Loss. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for fabricating an array substrate by using a halftone mask process and correspondingly changing the production process, and the process _ _ 钱 低纲 S financial loss. The present invention provides a method for fabricating an array substrate, the steps of which at least include forming a plurality of metal blocks on a substrate - a region: a second region; sequentially forming an insulating layer on the substrate; a layer 'overlying the plurality of metal blocks described above; coating - on the ^' and covering the semiconductor layer and the metal block below it; the earth tone mask is formed over the metal block - the first a photoresist pattern and an insulating layer for exposing the metal block in the second region to remove the first photoresist layer; and removing the liquid crystal display provided by the present invention The manufacturing process is done-changing and using a halftone mask. The electric film does not need to be etched, and the transparent conductive film can be directly plated to make the yield k-direction. In addition, the processes of the present invention are all in the same vacuum chamber. It is carried out without moving the vacuum to another vacuum chamber for reaction, so reducing the handling time can shorten the overall process time. [Embodiment] The technical position of the present invention combines the relative positional relationship of the components with the ',> features of the display panel, and the wear surface diagram of the thin film transistor region and its terminal region on the array substrate is described as follows. It is the same as the prior art, so it will not be repeated. Referring to Figures 3A to 3I, a process flow chart of a cross section of an array substrate according to an embodiment of the present invention is shown. First, as shown in Fig. 3A, a substrate 3 is provided, and the substrate 3 is a transparent insulating substrate made of glass, quartz or plastic. Then, a metal material is sputtered on the substrate 3 to form a first metal layer 31 on the upper surface of the substrate 3. Then, a photoresist layer is coated and exposed and etched by a first mask to pattern the first metal. The layer 31 forms a plurality of metal blocks, such as a common electrode 31A and a gate 312, on the upper surface of the substrate 3. The material of the common electrode 310 and the gate 312 may be a conductive single layer or a plurality of layers of metal or an alloy thereof, such as aluminum (A1), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW) or alloys thereof. As shown in the figure, the first region is a thin film transistor region, and the second region is a terminal region; wherein the second region may further include a capacitor structure, an internal electrostatic protection ring (inner sh〇rt_ring) or It is an outer shield short-ring structure, that is, the metal block common electrode 310 (first metal layer 31) in the second region can utilize subsequent processes to form different components to achieve respective functions. 1377682 As shown in FIG. 3B, an insulating layer 32 is formed on a plurality of metal blocks such as the common electrode 31A and the gate line 312. Next, a channel layer is deposited on the insulating layer 32. The ohmic contact layer is deposited on the channel layer; wherein the channel layer 331 and the ohmic contact layer 332 can be regarded as a half of the conductor layer 33, disposed above the insulating layer 32. Then, as shown in FIG. 2 (: a photoresist layer PR is formed on the semiconductor layer 33. The photoresist layer PR may be spin-coated or spin-less coated. Forming. Subsequently, the half-tone mask HM] (also referred to as a semi-transmissive film mask) is exposed, _, to pattern the photoresist layer PR, according to the half-color mask _ the impurity can be divided into the first exposure a region, a second exposure region and a third exposure region. According to the first exposure region, the second exposure region and the third exposure region distinguished by the above, the first exposure region of the towel is generally referred to as a thin film transistor according to the reference of the ®SD. The halftone mask ΗΜι corresponding to the region is an occlusion region, so that the exposed portion of the first photoresist pattern PRi formed after patterning has a photoresist layer PR having a relatively large protrusion. Refers to the second area, that is, the terminal part, the capacitor structure, the internal static protection ring or the external protection electrostatic ring area structure, and the corresponding halftone mask HM is a penetration area, so the second formed after patterning The photoresist pattern PR2 is a fully exposed portion 'forming a concave and thin photoresist layer P The third exposure region of R 泛 generally refers to the region outside the first region and the second region, that is, the pixel region, and the corresponding halftone mask HM is a semi-transparent region, so the pattern formed after the patterning The three-resistance pattern is a half-tone exposed portion, and a photoresist layer PR having an intermediate thickness (compared to the thickness of the first photoresist pattern PR1 & the second photoresist pattern 10 1377682 PR2) is formed. As shown in FIG. 3E, The photoresist layer PR that has been exposed on the side of the subsequent process, and the second photoresist pattern PR and the underlying portion of the semiconductor layer & and the insulating layer 32 are removed to exit the common electrode in the second region. As shown in FIG. 2F, the remaining layer PR except the first photoresist pattern PR1 is removed by the ashing process, that is, the third photoresist pattern is removed by the ashing reaction. The three portions of the semiconductor layer 33 covered by the photoresist etch are removed by etching to form as shown in FIG. 3G. Subsequently, the photoresist pattern is removed, and a second metal layer 34' is deposited in the first region using a second A photomask (not shown) patterns its second metal layer to form a source 341 and a drain 342; When the source 341 and the drain 342 are removed, the ohmic contact layer 332 between the source 341 and the drain 342 is removed. As shown in FIG. 3, a flat layer 35 is coated on the substrate 3, wherein the flat layer 35 is provided. It can be made of an acrylic organic material. The flat layer 35 is visualized by a third mask Μ3, and a plurality of contact holes are formed through the flat layer 35 to expose the common electrode 31. And the bungee 342; wherein, in the lithography process, a bleaching step (Wine bleaching) and a cross-linking reaction (Curing) are performed to form a three-dimensional network structure inside the flat layer %, which can greatly enhance the mechanical structure thereof. Strength, acid and alkali resistance and weather resistance. Further, as shown in FIG. 3I, a transparent conductive film such as a metal oxide such as indium oxide is applied to the surface structure of the uneven layer 35, and the transparent conductive film is patterned by a fourth mask. The pixel electrode 36 is formed; 11 (S) 1377682 wherein the pixel electrode 36 is electrically connected to the drain electrode 342 through the contact hole and the common electrode 31 (). Up to this point, the basic components of the array substrate of the liquid crystal display have been substantially constructed. Subsequently, a liquid crystal panel is formed by bonding to a color filter substrate, and then a backlight module and a driving circuit are assembled to constitute various liquid crystal display devices. Based on the above description, it can be understood that the technical features of the present invention are as follows:
(1)係因本發明之平坦層不需長時間曝露灰化反應 中，且其不需在經過一道乾蝕刻製程，故可以減少平坦膜 之膜f損失，可減少接觸窗的關鍵尺寸損失以及影響鄰近 區域免度的現象發生(crosstalk)。 (2) 另外，可以避免第二金屬層被離子轟擊而造成之 表面缺1¾ ’使㈣二金屬層與透明導魏之間的接觸阻抗 與附著性可有效控制。(1) Since the flat layer of the present invention does not need to be exposed to the ashing reaction for a long time, and it does not need to undergo a dry etching process, the film f loss of the flat film can be reduced, and the critical dimension loss of the contact window can be reduced and A phenomenon that affects the exemption of neighboring areas (crosstalk). (2) In addition, it is possible to prevent the surface of the second metal layer from being bombarded by ions, and the contact resistance and adhesion between the (four) two metal layer and the transparent conductive layer can be effectively controlled.
(3) 對於整體陣列基板製程而言，可以減少製作接觸 =的爛製程，縮短產㈣間。本發明之製程皆在同一個 二腔體中進行’不需破真空移至另-真空腔體中進行反 應，故減少搬運時間可縮短整體製程時間。 本發明雖以較佳實例闡明如上，然其並非用以限定本 =神與發明實體僅止於上述實施例。對所属技術領域 2有通常知識者，當可_ 了解並其它元件或方式 目3功效。是以，在不脫離本發明之精神與範圍 乜改，均應包含在下述之申請專利範圍内。 1377682 【圖式簡單說明j 圖一係為習知技術之薄膜電晶體之結構示意圖 程流程 圖二A至圖二Η係為習知陣列基板截面的製 圖；以及 圖二Α至圖三I係為本發明一實施例陣列基板戴面的 製程流程圖。 鲁 【主要元件符號說明】 像素電極 12薄膜電晶體 14掃瞄線 16資料線 312閘極 122、331通道層 124、341 源極 ® 126、342 汲極 128通道 2玻璃基板 21、 31第一金屬層 22、 32絕緣層 23、 33半導體層 24、 34第二金屬層 25感光性丙烯酸系有機光阻 (S ) 13 1377682 26透明導電膜 3基底 35平坦層 36畫素電極 310共通電極 332歐姆接觸層 ΗΜι半色調光罩 M3第三光罩 PR光阻層 PR!第一光阻圖案 PR2第二光阻圖案 PR3第三光阻圖案 < S ) 14(3) For the overall array substrate process, it is possible to reduce the rotten process of making contact = and shorten the production (four). The process of the present invention is carried out in the same two chambers without the need to break the vacuum to another vacuum chamber, so that reducing the handling time can shorten the overall process time. The present invention has been described above by way of preferred examples, but it is not intended to limit the present invention to the invention and only to the above embodiments. Those who have a general knowledge of the technical field 2 can understand and use other components or methods. Therefore, it should be included in the scope of the following claims without departing from the spirit and scope of the invention. 1377682 [Simplified illustration of the drawing Figure 1 is a schematic diagram of the structure of a thin film transistor of the prior art. Flowchart 2A to Fig. 2 is a drawing of a conventional array substrate section; and Fig. 2 to Fig. 3I are A process flow diagram of an array substrate wearing surface according to an embodiment of the present invention. Lu [Major component symbol description] Pixel electrode 12 Thin film transistor 14 Scan line 16 Data line 312 Gate 122, 331 channel layer 124, 341 Source 126, 342 Bungee 128 channel 2 glass substrate 21, 31 first metal Layer 22, 32 insulating layer 23, 33 semiconductor layer 24, 34 second metal layer 25 photosensitive acrylic organic photoresist (S) 13 1377682 26 transparent conductive film 3 substrate 35 flat layer 36 pixel electrode 310 common electrode 332 ohmic contact Layer 半 halftone mask M3 third reticle PR photoresist layer PR! first photoresist pattern PR2 second photoresist pattern PR3 third photoresist pattern < S ) 14