TWI376755B - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

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Publication number
TWI376755B
TWI376755B TW97102713A TW97102713A TWI376755B TW I376755 B TWI376755 B TW I376755B TW 97102713 A TW97102713 A TW 97102713A TW 97102713 A TW97102713 A TW 97102713A TW I376755 B TWI376755 B TW I376755B
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Taiwan
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metal
substrate
manufacturing
glue
metal frame
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TW97102713A
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Chinese (zh)
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TW200933767A (en
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Wei Min Hsiao
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Description

13767551376755

TW4169PA 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體封裝結構及其製造方 法，且特別是有關於一種晶圓級（wafer level)製程之半 導體封裝結構及其製造方法。 【先前技術】 近年來，隨著電子技術的日新月異，輕薄短小、多功 • 能、高速度之電子產品相繼問世。以半導體封裝產業的使 命而言，簡單來說就是支援電子產品開發之需求。因此， 現今半導體封裝產業的主要發展趨勢’包括有·（一）南輸 入/高輸出；（二）高密集度；（三）可靠性表現；（四）低成本、 高生產效率。然而，這種高密集度、高輸入/高輸出之半導 體封裝結構引腳多、接線密度高，尤其在裝置運作期間， 產生之電磁力往往會干擾其他裝置的運作性能，即所謂的 電磁干擾（Electromagnetic Interference，EMI)效應。因此， * 如何克服電磁干擾的問題，讓半導體封裝結構、甚或封裝 製程，更具有優勢與競爭力，乃業界所致力的課題之一。 【發明内容】 本發明係有關於一種半導體封裝結構及其製造方 法，係利用晶圓級製程將半導體晶粒設置於一氣密空間 内，使封裝結構具有良好的遮蔽電磁干擾之特性，並具有 結構堅固、穩定性高之優點。而且，此封裝結構及其製造 1376755TW4169PA IX. OBJECTS OF THE INVENTION: TECHNICAL FIELD The present invention relates to a semiconductor package structure and a method of fabricating the same, and more particularly to a semiconductor package structure of a wafer level process and a method of fabricating the same. [Prior Art] In recent years, with the rapid development of electronic technology, electronic products with lightness, thinness, versatility, and high speed have come out one after another. In terms of the mission of the semiconductor packaging industry, it is simply to support the needs of electronic product development. Therefore, the main development trends of the semiconductor packaging industry today include: (1) South input/high output; (2) high intensity; (3) reliability performance; (4) low cost and high production efficiency. However, this high-density, high-input/high-output semiconductor package has many pins and high wiring density. Especially during the operation of the device, the electromagnetic force generated often interferes with the operation performance of other devices, so-called electromagnetic interference ( Electromagnetic Interference (EMI) effect. Therefore, how to overcome the problem of electromagnetic interference and make the semiconductor package structure and even the packaging process more advantageous and competitive is one of the topics that the industry is working on. SUMMARY OF THE INVENTION The present invention relates to a semiconductor package structure and a method of fabricating the same, which uses a wafer level process to place a semiconductor die in an airtight space, so that the package structure has good shielding electromagnetic interference characteristics and has a structure. Strong and stable. Moreover, this package structure and its manufacture 1376755

TW4169PA 方法對於半導體晶粒的尺寸、以及欲封裝之半導體晶粒的 數量，具有很高的相容性。 根據本發明之第一方面，提出一種半導體封裝結構之 製造方法，其包括下列步驟。首先，提供一基材。然後， 形成數個金屬框於基材上，其中每個金屬框係相互分隔。 接著，配置數個半導體晶粒於基材上且分別位於金屬框之 内。之後，設置一金屬蓋板於金屬框上，使得每個金屬框、 金屬蓋板與基材之間係形成一氣密空間，半導體晶粒係密 •封於氣密空間内。 根據本發明之第二方面，提出一種半導體封裝結構， 其包括一基板、至少一半導體晶粒、一金屬框、以及一金 屬蓋板。半導體晶粒設置於基板上。金屬框設置於基板 上，此金屬框係部分地嵌入於基板内且圍繞半導體晶粒。 金屬蓋板設置於金屬框上。其中，金屬框、金屬蓋板與基 材之間係形成一氣密空間，半導體晶粒係密封於氣密空間 内。 * 為讓本發明之上述内容能更明顯易懂，下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 根據本發明之實施例之封裝結構，至少包括一基板、 至少一個半導體晶粒、一金屬框、以及一金屬蓋板。半導 體晶粒設置於基板上。金屬框設置於基板上，此金屬框係 部分地嵌入基板内且圍繞半導體晶粒。金屬蓋板設置於金 1376755The TW4169PA method has high compatibility with the size of the semiconductor die and the number of semiconductor dies to be packaged. According to a first aspect of the present invention, a method of fabricating a semiconductor package structure is provided, which comprises the following steps. First, a substrate is provided. Then, a plurality of metal frames are formed on the substrate, wherein each of the metal frames is separated from each other. Next, a plurality of semiconductor dies are disposed on the substrate and are respectively located within the metal frame. Thereafter, a metal cover plate is disposed on the metal frame such that an airtight space is formed between each of the metal frame, the metal cover plate and the substrate, and the semiconductor die is tightly sealed in the airtight space. According to a second aspect of the present invention, a semiconductor package structure is provided comprising a substrate, at least one semiconductor die, a metal frame, and a metal cover. The semiconductor die is disposed on the substrate. The metal frame is disposed on the substrate, the metal frame being partially embedded in the substrate and surrounding the semiconductor die. The metal cover is placed on the metal frame. Wherein, the metal frame, the metal cover plate and the substrate form an airtight space, and the semiconductor die is sealed in the airtight space. In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below in detail with reference to the accompanying drawings, which are described below as follows: [Embodiment] A package structure according to an embodiment of the present invention, at least A substrate, at least one semiconductor die, a metal frame, and a metal cover are included. The semiconductor body grains are disposed on the substrate. The metal frame is disposed on the substrate, and the metal frame is partially embedded in the substrate and surrounds the semiconductor die. Metal cover plate set in gold 1376755

TW4169PA 屬框上其中’金屬框、金屬蓋板與基材之間係形成氣密 空間’半導體晶粒係密封於氣密空間内。 以下係輔以第1圖詳細說明本實施例之半導體封裝 、’·β構的方’、月參知、第1圖，其繪示依照本發明實施例之 半導體封裝結構之製造方法的流程圖。本實施例之製造方 法主要包括以下步驟。首先，如步驟 S11所示，提供一基 材。然後，如步驟S12所示，形成金屬框於基材上。接著，On the TW4169PA frame, the 'metal frame, the metal cover and the substrate form an airtight space'. The semiconductor die is sealed in the airtight space. Hereinafter, the semiconductor package of the present embodiment, the 'square structure', the monthly reference, and the first drawing will be described in detail with reference to FIG. 1, which is a flow chart showing a method of manufacturing a semiconductor package structure according to an embodiment of the present invention. . The manufacturing method of this embodiment mainly includes the following steps. First, as shown in step S11, a substrate is provided. Then, as shown in step S12, a metal frame is formed on the substrate. then,

v驟 斤示配置半導體晶粒於基材上且位於金屬框 之内，後如步驟Sl4所示，設置一金屬蓋板於金屬框 上’使付金屬框、金屬蓋板與基材之間係形成一氣密空間 (air-tight caV1ty)，半導體晶粒係密封於氣密空間内。 由於 導體的封裝技術之中’可用來接合半導體 晶粒的技術不勝枚舉。其中，較為著名的例如有打線接合 技術(wire bonding)以及覆晶接合技術（叫_比屮匕⑽仙幻。 然而，為了使本發明之揭露能更加徹底和完整，以下係以 ^發明實施例之製造方法，搭配其中—種打線接合技術， 來做進一步的說明。因此，具通常知識者當知，在以下的 實施例巾㈣於彳了線接合技術之步驟、製程僅係為舉例說 明之用，以作為熟習此領域者據以實施之參考並非對本 發明欲保護之範圍做限縮。並且，在實際應㈣，也應依 照應用之技術需要作適度之調整’故其中製程得由熟習此 技術領域者任施匠思，而為諸般修飾。再者，實施例中之 圖示亦省略不必要之元件，以利凊楚顯示本發明之技術特 1376755v squeezing the semiconductor die on the substrate and located inside the metal frame, and then, as shown in step S14, providing a metal cover plate on the metal frame to make the metal frame, the metal cover plate and the substrate An air-tight caV1ty is formed, and the semiconductor crystal grains are sealed in the airtight space. Among the conductor packaging techniques, the technology that can be used to bond semiconductor dies is endless. Among them, more famous ones are wire bonding and flip chip bonding technology (called _ 屮匕 (10) singular. However, in order to make the disclosure of the present invention more thorough and complete, the following is an embodiment of the invention. The manufacturing method is further described with the above-mentioned wire bonding technology. Therefore, those skilled in the art know that in the following embodiments, the steps (4) of the wire bonding technique are only illustrated by way of example. The use of this reference as a person skilled in the art is not intended to limit the scope of the invention to be protected. Moreover, in practice (4), it should be adjusted according to the technical needs of the application. Therefore, the process is familiar to the process. The technical field has been modified and modified. In addition, the illustrations in the embodiments also omit unnecessary elements, so as to show the technical specialties of the present invention 1376755

TW4169PA 請參照第2圖，其繪示依照本發明實施例之應用打線 接合技術之製造方法的流程圖。並請同時參照第3a〜3h 圖，其繪示對應第2圖的步驟依序形成半導體封裝結構的 剖面圖。 首先，如步驟S21及第3a圖所示，提供一基材110。 此基材11 〇較佳地係為一石夕晶圓（silicon wafer )。 然後，如步驟S22及第3b圖所示，形成數個金屬框 120於基材110上。在第3b圖中，金屬框120係部分地嵌 • 入基材110内。請同時參照第4圖，其繪示第3b圖中具 有金屬框之基材的俯視圖。每個金屬框120係相互分隔， 且例如是方形或矩形之金屬框120。 在此步騾S22中，例如是利用下述方式形成此些金屬 框120。請參照第5a〜5b圖，其繪示依照本發明實施例之 依序形成金屬框於基材上的示意圖。首先，如第5a圖所 示，圖案化基材110,以形成數個框形凹槽ll〇c於基材110 上。請同時參照第6圖，其繪示第5a圖中具有凹槽之基 ® 材的俯視圖。此些框形凹槽ll〇c例如是方形或矩形。接 著，如第5b圖所示，填充一金屬材料Μ於框形凹槽110c 中。較佳地，此金屬材料Μ係藉由電鍍技術填充於框形凹 槽110c中。之後，如第5c圖所示，薄化（thinning)基材 110,使填充於框形凹槽ll〇c中之金屬材料Μ曝露出一高 度h，以形金屬框120。本實施例中，金屬框120之材質 例如包括銅（Cu)，且基材110例如是利用蝕刻之方式來 進行薄化。 1376755TW4169PA Please refer to FIG. 2, which is a flow chart showing a manufacturing method of applying a wire bonding technique according to an embodiment of the present invention. Please also refer to FIGS. 3a to 3h, which illustrate a cross-sectional view of the semiconductor package structure sequentially formed in accordance with the steps of FIG. First, as shown in steps S21 and 3a, a substrate 110 is provided. The substrate 11 is preferably a silicon wafer. Then, as shown in steps S22 and 3b, a plurality of metal frames 120 are formed on the substrate 110. In Fig. 3b, the metal frame 120 is partially embedded in the substrate 110. Please also refer to Fig. 4, which shows a top view of the substrate having the metal frame in Fig. 3b. Each of the metal frames 120 is separated from each other and is, for example, a square or rectangular metal frame 120. In this step S22, for example, the metal frames 120 are formed in the following manner. Referring to Figures 5a to 5b, there are shown schematic views of sequentially forming a metal frame on a substrate in accordance with an embodiment of the present invention. First, as shown in Fig. 5a, the substrate 110 is patterned to form a plurality of frame-shaped grooves 11c on the substrate 110. Please also refer to Figure 6, which shows a top view of the base material with grooves in Figure 5a. These frame-shaped grooves 11c are, for example, square or rectangular. Next, as shown in Fig. 5b, a metal material is filled in the frame-shaped recess 110c. Preferably, the metal material is filled in the frame-shaped recess 110c by a plating technique. Thereafter, as shown in Fig. 5c, the substrate 110 is thinned to expose the metal material filled in the frame-shaped recess 11c to a height h to shape the metal frame 120. In the present embodiment, the material of the metal frame 120 includes, for example, copper (Cu), and the substrate 110 is thinned by etching, for example. 1376755

TW4169PA 接著，本實施例之製造方法進入第2圖之步驟S23, 如第3c圖所示，形成數個貫穿基材110之導電通道13〇 (延伸箭頭，如圖式）。導電通道13〇係用以電性連接基 材110之上下兩表面，且每個導電通道130係分別位於對 應之金屬框120之内（即位於金屬框120内側）。在實際 應用上，於步驟S23中形成之導電通道130可隨著半導體 晶粒的電路設計而改變其數量、位置’本發明對此並不多 作限制。 然後，進行步驟S24，如第3d _所示’配置數個半 導體晶粒140於基材11〇上且分別位於各金屬框120之 内。本實施例中，係將半導體晶粒14〇之主動面140a (用 以打線接合之表面）朝上，並以一底# 141貼覆固定於基 材110上。另外，雖然本實施例中係以每個金屬框120内 僅配置一個半導體晶粒14〇為例，然而實際應用上’係可 依照不同之產品需求在每個金屬框12〇内配置多個半導體 晶粒140。本發明對於金屬框120中配ί之半導體晶粒 數目不加以限制。 接著，如步驟S25及第3e圖所系，利用打線接合技 術電性連接半導體晶粒140及導電通道130。在此步驟S25 中’主要是透過一金屬線142 (比如金線）’將半導體晶粒 140之主動面140a電性連接於導電通道130。在實際應用 上，打線接合技術可例如更包括超音波接合（Ultrasonic bonding ’ U/S)、熱壓接合（Thermo-compression Bonding， T/C)、熱超音波接合（Thermo-sonic Bonding，T/S)或其他 1376755TW4169PA Next, the manufacturing method of this embodiment proceeds to step S23 of Fig. 2, and as shown in Fig. 3c, a plurality of conductive vias 13 贯穿 (extended arrows, as shown) are formed through the substrate 110. The conductive vias 13 are electrically connected to the upper and lower surfaces of the substrate 110, and each of the conductive vias 130 is located within the corresponding metal frame 120 (ie, inside the metal frame 120). In practical applications, the conductive vias 130 formed in step S23 may vary in number and position with the circuit design of the semiconductor die. The present invention is not limited in this regard. Then, step S24 is performed, and a plurality of semiconductor dies 140 are disposed on the substrate 11A as shown in Fig. 3d_ and are respectively located in the respective metal frames 120. In this embodiment, the active surface 140a of the semiconductor die 14 (the surface joined by wire bonding) faces upward, and is attached to the substrate 110 by a bottom #141. In addition, although in this embodiment, only one semiconductor die 14 is disposed in each metal frame 120 as an example, in practice, a plurality of semiconductors may be disposed in each metal frame 12〇 according to different product requirements. Grain 140. The present invention does not limit the number of semiconductor dies in the metal frame 120. Next, as shown in steps S25 and 3e, the semiconductor die 140 and the conductive via 130 are electrically connected by wire bonding techniques. In this step S25, the active surface 140a of the semiconductor die 140 is electrically connected to the conductive via 130 through a metal line 142 (such as a gold wire). In practical applications, wire bonding techniques may include, for example, Ultrasonic bonding 'U/S, Thermo-compression Bonding (T/C), and Thermo-sonic Bonding (T/). S) or other 1376755

TW4169PA 習用之打線連接技術，本發明對此並不多作限制。 然後’如步驟S26及第3f圖所示，形成一膠材150 於金屬框120之間以及金屬框12〇之頂部。此膠材15〇較 佳地係為一金屬膠。 一 之後，進行步驟S27，如第3g圖所系，設置一金屬 蓋板160於金屬框丨2〇上。本實施例中，每個金屬框12〇、 屬蓋板160與基材Π 〇之間係形成一氣密空間（air-tight 鲁屬—） 而半導體晶粒140係密封於氣密空間Z内。金 ώ现板160較佳地係藉由膠材150固定於金屬框120之頂 丨】用金屬框120、金屬膠15〇以及金屬蓋板160 等之金屬分肪 、’ /何質’有效地遮蔽電磁干擾，以及提高支撐強度。 ^ 然後’如步驟S28及第3h圖所示，切割（sawing) ιοα。 7之基材110，以形成數個半導體封裝結構 於此切割基材110之步驟中，較佳地係使每個半導 $裝匕掮"100包括一個金屬框120。 • 匕外在上述應用打線接合技術之製造過程中，步驟 S24以及步驄A + 少外 鄉S25係會隨著應用之接合技術而變化。因 此，如欲以士由 ^ 可調敕舟本實施例之製造方法搭配其它接合技術時，係 製造二^驟S24以及步驟S25。舉例來說，當本實施例之 止邮备係搭配覆晶接合技術時’係省略掉步驟S24以及 步驟S25，私 14〇 坟以透過覆晶接合技術(FC)來配置半導體晶粒 人；，_板11 〇上。然而’不論是打線接合技術或是覆晶 S技術之製程，皆已為本發明技術領域之通常知識，而 '、中步驟、製程得由熟習此技術領域者任施匠思，而為 1376755 ·. *The TW4169PA conventional wire bonding technology, the present invention does not limit this. Then, as shown in steps S26 and 3f, a glue 150 is formed between the metal frames 120 and the top of the metal frame 12〇. Preferably, the rubber material 15 is a metal glue. Thereafter, step S27 is performed, and as shown in Fig. 3g, a metal cover 160 is disposed on the metal frame 丨2〇. In this embodiment, each of the metal frame 12, the cover plate 160 and the substrate 形成 形成 form an airtight space (air-tight), and the semiconductor die 140 is sealed in the airtight space Z. The metal plate 160 is preferably fixed to the top of the metal frame 120 by the glue 150. The metal frame 120, the metal glue 15 and the metal cover 160 are used to effectively separate the metal. Mask electromagnetic interference and increase support strength. ^ Then 'sawing ιοα as shown in steps S28 and 3h. The substrate 110 of 7 is formed to form a plurality of semiconductor package structures. In the step of cutting the substrate 110, it is preferred that each of the semiconductor packages comprises a metal frame 120. • In the manufacturing process of the above-mentioned application of wire bonding technology, step S24 and step A + less foreign S25 will change with the application bonding technology. Therefore, if it is desired to use the manufacturing method of the present embodiment in combination with other bonding techniques, the process S24 and the step S25 are performed. For example, when the postal processing system of the present embodiment is combined with the flip chip bonding technology, the steps S24 and S25 are omitted, and the semiconductor die is configured by the flip chip bonding technology (FC); _ board 11 〇. However, 'whether it is the wire bonding technology or the process of flip chip S technology, it is the general knowledge of the technical field of the invention, and the 'steps and processes' are made by those skilled in the art, and the number is 1376755. . *

TW4169PA 諸般修飾。故此*再贅述有關接合半導體晶粒的技術，以 • 避免混淆本發明之精神。 另外，在步驟S26中，雖然係應用金屬膠作為固定蓋 板160之踢材150 ’以與金屬框12〇以及金屬材質之蓋板 160形成良好的電磁干擾遮蔽效果。然而，在本實施例中， 也可以在包圍金屬框12〇外側處使用一般習用之底勝，並 在其上塗覆一層金屬膠來固定蓋板160,以代替完全使用 金屬膠的膠材150。如此一來，半導體封裝結構仍可且有 零良好的電磁干擾遮蔽效果，尤其是在大量生產時，更^以 節省整體的生產成本。 - 舉例來說，在步驟S20中，如欲在包圍金屬框12〇外 側處使用了般的底膠來代替膠材15〇時，可以以下列步驟 來進行。首先，填充第一膠材於金屬框120之間。接著， .形成第二膠材在金屬框120之頂部以及第一膠材上方。如 此一來，金屬蓋板160可藉由第二膠材固定於金屬框12〇 籲之頂部以及第-膠材上。請參照第7圖，其緣示依照本發 月實％例之半導體封裝結構之另一種實施方式的示意 圖。在第7圖令’半導體封裝結構100,係使用第一膠材251 ，第二膠材252，來取代原本半導體封裝結構100的單一 夕材150第一膠材251包圍金屬框120之外側。第二勝 材252设置在金屬框12〇之頂部與金屬蓋板16〇之間以 及第膠材251與金屬蓋板160之間，藉以將金屬蓋板16〇 固1於金屬框120之頂部以及第一膠材251上。其中，第 膠材251例如為一般的底膠，第二膠材252例如為金屬 1376755TW4169PA is all decorated. Therefore, the technique for bonding semiconductor dies will be repeated to avoid confusion with the spirit of the present invention. Further, in step S26, the metal glue is applied as the kick member 150' of the fixed cover plate 160 to form a good electromagnetic interference shielding effect with the metal frame 12A and the metal cover plate 160. However, in the present embodiment, it is also possible to use a conventional bottom sill at the outer side of the metal frame 12, and apply a layer of metal glue thereon to fix the cover plate 160 instead of the glue 150 completely using the metal glue. As a result, the semiconductor package structure can still have zero good electromagnetic interference shielding effect, especially in mass production, to save overall production cost. - For example, in step S20, if a primer is used instead of the glue 15 at the outer side of the metal frame 12, the following steps can be performed. First, the first glue is filled between the metal frames 120. Next, a second glue is formed on top of the metal frame 120 and above the first glue. As a result, the metal cover 160 can be fixed to the top of the metal frame 12 and the first glue by the second glue. Please refer to Fig. 7, which is a schematic view showing another embodiment of the semiconductor package structure according to the present embodiment. In the seventh embodiment, the semiconductor package structure 100 uses a first adhesive material 251 and a second adhesive material 252 instead of the single material 150 of the original semiconductor package structure 100 to surround the outer side of the metal frame 120. The second winning material 252 is disposed between the top of the metal frame 12〇 and the metal cover 16〇 and between the first rubber material 251 and the metal cover 160, thereby securing the metal cover 16 to the top of the metal frame 120 and The first glue 251 is on. Wherein, the first rubber material 251 is, for example, a general primer, and the second rubber material 252 is, for example, metal 1376755

TW4169PA 膠。如此係可依照不同製程需求選用不同成本及材料之膠 材，係可增加製程之應用彈性。 上述依照本發明實施例所揭露之半導體封裝結構及 其製造方法，係從晶圓内部長出方形之金屬框，做為支撐 上蓋之元件，具有較佳之支撐強度。再者，較佳地利用金 屬框、金屬膠以及金屬上蓋等之金屬材質密封半導體晶 粒，來遮蔽電磁干擾。依照本發明實施例之半導體封裝結 構除了結構堅固（支撐強度佳）、穩定性高（抗電磁干擾）之 • 外，對於半導體晶粒的尺寸、以及欲封裝之半導體晶粒的 數量，係具有很高的相容性。另外，此封裝結構的製造方 法係相容於現行製程，故可省下新製程設備之開發成本、 購置成本，從而能在節省生產成本之條件下，有效地提升 產品優勢與競爭力。 綜上所述，雖然本發明已以實施例揭露如上，然其並 非用以限定本發明。本發明所屬技術領域中具有通常知識 者，在不脫離本發明之精神和範圍内，當可作各種之更動 ® 與潤飾。因此，本發明之保護範圍當視後附之申請專利範 圍所界定者為準。 1376755TW4169PA glue. In this way, different cost and material glues can be selected according to different process requirements, which can increase the application flexibility of the process. The semiconductor package structure and the manufacturing method thereof disclosed in the embodiments of the present invention are formed by extending a square metal frame from the inside of the wafer as an element for supporting the upper cover, and have better support strength. Further, it is preferable to use a metal material such as a metal frame, a metal paste or a metal cover to seal the semiconductor crystal grains to shield electromagnetic interference. The semiconductor package structure according to the embodiment of the present invention has a strong structure (good support strength) and high stability (anti-electromagnetic interference), and has a very large size for the semiconductor die and the number of semiconductor grains to be packaged. High compatibility. In addition, the manufacturing method of the package structure is compatible with the current process, so that the development cost and the acquisition cost of the new process equipment can be saved, thereby effectively improving product advantages and competitiveness under the condition of saving production cost. In summary, although the invention has been disclosed above by way of example, it is not intended to limit the invention. It will be apparent to those skilled in the art that various modifications and refinements can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 1376755

TW4169PA 【圖式簡單說明】 第1圖繪示依照本發明實施例之半導體封裝結構之 製造方法的流程圖。 第2圖繪示依照本發明實施例之半導體封裝結構搭 配打線接合技術之製造方法的流程圖。 第3a〜3h圖繪示對應第2圖的步驟依序形成半導體封 裝結構的剖面圖。 第4圖繪示第3b圖中具有金屬框之基材的俯視圖。 • 第5a〜5c圖繪示依照本發明實施例之依序形成金屬 框於基材上的示意圖。 第6圖繪示第5a圖中具有凹槽之基材的俯視圖。 第7圖繪示依照本發明實施例之半導體封裝結構搭 配兩種膠材的示意圖。 【主要元件符號說明】 100、100’ ：半導體封裝結構 ® 110 :基材 110c :凹槽 120 :金屬框 130 :導電通道 140 :半導體晶粒 140a :主動面 141 :底膠 142 :金屬線 1376755TW4169PA BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing a method of fabricating a semiconductor package structure in accordance with an embodiment of the present invention. 2 is a flow chart showing a manufacturing method of a semiconductor package structure in accordance with an embodiment of the present invention. 3a to 3h are cross-sectional views showing the semiconductor package structure sequentially formed in accordance with the steps of Fig. 2. Fig. 4 is a plan view showing a substrate having a metal frame in Fig. 3b. • Figures 5a to 5c are schematic views showing the sequential formation of a metal frame on a substrate in accordance with an embodiment of the present invention. Figure 6 is a plan view showing a substrate having a groove in Figure 5a. FIG. 7 is a schematic view showing the assembly of two kinds of adhesive materials in a semiconductor package structure according to an embodiment of the invention. [Description of main component symbols] 100, 100': semiconductor package structure ® 110 : substrate 110c : recess 120 : metal frame 130 : conductive path 140 : semiconductor die 140a : active surface 141 : primer 142 : metal wire 1376755

TW4169PA 150、251、252 :膠材 160 :金屬蓋板 h :高度 Μ:金屬材料 Ζ :氣密空間TW4169PA 150, 251, 252: glue material 160: metal cover h: height Μ: metal material Ζ: airtight space

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Claims (1)

IT76755 月β曰修正本 [101年.05月18日核正替換頁 2012/5/18」a申復&修正 十、申請專利範圍： 1. 一種半導體封裝結構之製造方法，包括： (a) 提供一基材； (b) 形成複數個金屬框於該基材上，其中各該些金屬 框係相互分隔，包括： (bl)圖案化該基材，以形成複數個框形凹槽於該 基材上； (b2)填充一金屬材料於該些框形凹槽中；以及 (b3)薄化（thinning)該基材，使填充於該些框 形凹槽中之該金屬材料曝露出一高度以形成該些金屬框； (c) 配置複數個半導體晶粒於該基材上且分別位於 該些金屬框之内；以及 (d) 設置一金屬蓋板於該些金屬框上，各該金屬框、 該金屬蓋板與該基材之間係形成一氣密空間（air-tight cavity)，各該半導體晶粒係密封於該氣密空間内。 2. 如申請專利範圍第1項所述之製造方法，其中在 該步驟（d)之前，該製造方法更包括： (e) 形成一膠材於該些金屬框之間以及該些金屬框 之頂部，藉以將該金屬蓋板固定於該些金屬框之頂部。 3. 如申請專利範圍第2項所述之製造方法，其中該 膠材為一金屬膠。 4. 如申請專利範圍第1項所述之製造方法，其中在 該步驟(d)之前，該製造方法更包括： (Π)填充一第一膠材於該些金屬框之間；以及 097.102713； 1013.192160-0 1376755 101年05月18日梭正替换頁 2012/5/18_la 申復 & 修正 (f2)形成一第二膠材在該些金屬框之頂部以及該第 一膠材上方，藉以將該金屬蓋板固定於該些金屬框之頂部 以及該第一膠材上。 5. 如申請專利範圍第4項所述之製造方法，其中該 第二膠材為一金屬膠。 6. 如申請專利範圍第1項所述之製造方法，其中在 該步驟(b2)之中，該金屬材料係藉由一電鍍技術填充於該 些框形凹槽中。 7. 如申請專利範圍第1項所述之製造方法，其中在 該步驟(c)之前，該製造方法更包括： (g) 形成複數個導電通道，該些導電通道係貫穿該基 材，用以電性連接該基材之上下兩表面，各該導電通道分 別對應位於各該金屬框内。 8. 如申請專利範圍第7項所述之製造方法，其中在 該步驟（c)之後，該製造方法更包括： (h) 以一打線接合技術電性連接該些半導體晶粒及 該些導電通道。 9. 如申請專利範圍第1項所述之製造方法，其中該 步驟(c)包括： (i) 以一覆晶接合技術配置該些半導體晶粒於該基材 上。 10. 如申請專利範圍第1項所述之製造方法，其中在 該步驟(d)之後，該製造方法更包括： (j) 切單（singulation)完成該步驟（d)後之該基材， 097102713 1013192160-0 16 1376755 101年05月18日修正替换頁 2012/5/18_la 申復 & 修正 以形成複數個半導體封裝結構，其中各該些半導體封裝結 構包括一個該金屬框。 11. 如申請專利範圍第1項所述之製造方法，其中該 些金屬框之材質包括銅（Cu)。 12. 如申請專利範圍第1項所述之製造方法，其中該 基材為一石夕晶圓（silicon wafer )。 13. —種半導體封裝結構，包括： 一基板； 至少一半導體晶粒，設置於該基板上； 一金屬框，設置於該基板上，該金屬框係部分地嵌入 於該基板内且圍繞該半導體晶粒；以及 一金屬蓋板，設置於該金屬框上，該金屬框、該金屬 蓋板與該基板之間係形成一氣密空間，該半導體晶粒係密 封於該氣密空間内； 其中該基板具有至少一導電通道，該導電通道係貫穿 該基板，用以電性連接該基板之上下兩表面，該導電通道 係位於該金屬框内側。 14. 如申請專利範圍第13項所述之封裝結構，更包 括： 。 一膠材，包圍該金屬框外側以及位在該金屬框之頂部 與該金屬蓋板之間，藉以將該金屬蓋板固定於該金屬框之 頂部。 15. 如申請專利範圍第14項所述之封裝結構，其中 該膠材為一金屬膠。 097102713 · » 1013.192160-0 17 1376755 101年05月18日梭正替換頁 2012/5/18_la 申復 & 修正 16. 如申請專利範圍第13項所述之封裝結構，更包 括： 一第一膠材，包圍該金屬框之外側；以及 一第二膠材，設置在該金屬框之頂部與該金屬蓋板之 間，以及該第一膠材與該金屬蓋板之間，藉以將該金屬蓋 板固定於該金屬框之頂部以及該第一膠材上。 17. 如申請專利範圍第16項所述之封裝結構，其中 該第二膠材為一金屬膠。 18. 如申請專利範圍第13項所述之封裝結構，其中 該半導體晶粒係透過一打線接合技術電性連接於該導電 通道。 19. 如申請專利範圍第13項所述之封裝結構，其中 該半導體晶粒係透過一覆晶接合技術配置於該基板上。 20. 如申請專利範圍第13項所述之封裝結構，其中 該金屬框之材質包括銅（Cu)。 21. 如申請專利範圍第13項所述之封裝結構，其中 該基板為一石夕基板（silicon substrate)。 097102713 1013192160-0 18IT76755 month beta revision [101.05.18 nuclear replacement page 2012/5/18" a application & amendment 10, the scope of application for patent: 1. A method of manufacturing a semiconductor package structure, including: Providing a substrate; (b) forming a plurality of metal frames on the substrate, wherein each of the metal frames is separated from each other, comprising: (bl) patterning the substrate to form a plurality of frame-shaped grooves (b2) filling a metal material in the frame-shaped recesses; and (b3) thinning the substrate to expose the metal material filled in the frame-shaped recesses a height to form the metal frame; (c) arranging a plurality of semiconductor dies on the substrate and respectively located within the metal frames; and (d) providing a metal cover on the metal frames, each The metal frame, the metal cover plate and the substrate form an air-tight cavity, and each of the semiconductor die is sealed in the airtight space. 2. The manufacturing method according to claim 1, wherein before the step (d), the manufacturing method further comprises: (e) forming a rubber material between the metal frames and the metal frame The top portion is used to fix the metal cover to the top of the metal frames. 3. The method of manufacture of claim 2, wherein the glue is a metal glue. 4. The manufacturing method of claim 1, wherein before the step (d), the manufacturing method further comprises: (Π) filling a first glue between the metal frames; and 097.102713; 1013.192160-0 1376755 May 18th, 2011 Shuttle replacement page 2012/5/18_la Application & Amendment (f2) to form a second glue on top of the metal frame and above the first glue, so that The metal cover is fixed on the top of the metal frame and the first glue. 5. The manufacturing method of claim 4, wherein the second adhesive material is a metal glue. 6. The manufacturing method according to claim 1, wherein in the step (b2), the metal material is filled in the frame-shaped grooves by a plating technique. 7. The manufacturing method according to claim 1, wherein before the step (c), the manufacturing method further comprises: (g) forming a plurality of conductive channels, the conductive channels extending through the substrate, The upper and lower surfaces of the substrate are electrically connected, and each of the conductive channels is correspondingly located in each of the metal frames. 8. The manufacturing method according to claim 7, wherein after the step (c), the manufacturing method further comprises: (h) electrically connecting the semiconductor dies and the conductive materials by a wire bonding technique; aisle. 9. The method of manufacturing of claim 1, wherein the step (c) comprises: (i) disposing the semiconductor dies on the substrate by a flip chip bonding technique. 10. The manufacturing method according to claim 1, wherein after the step (d), the manufacturing method further comprises: (j) singulation of the substrate after the step (d) is completed, 097102713 1013192160-0 16 1376755 Modified on May 18, 2011, the replacement page 2012/5/18_la, the application of the present invention, to form a plurality of semiconductor package structures, wherein each of the semiconductor package structures includes one of the metal frames. 11. The manufacturing method of claim 1, wherein the metal frame material comprises copper (Cu). 12. The method of manufacturing of claim 1, wherein the substrate is a silicon wafer. 13. A semiconductor package structure comprising: a substrate; at least one semiconductor die disposed on the substrate; a metal frame disposed on the substrate, the metal frame partially embedded in the substrate and surrounding the semiconductor a metal cover plate is disposed on the metal frame, the metal frame, the metal cover plate and the substrate form an airtight space, and the semiconductor die is sealed in the airtight space; The substrate has at least one conductive channel extending through the substrate for electrically connecting the upper and lower surfaces of the substrate, and the conductive channel is located inside the metal frame. 14. The package structure as described in claim 13 of the patent scope further includes: A rubber material is disposed around the outer side of the metal frame and between the top of the metal frame and the metal cover to fix the metal cover to the top of the metal frame. 15. The package structure of claim 14, wherein the glue is a metal glue. 097102713 · » 1013.192160-0 17 1376755 May 18th, 2011 Shuttle replacement page 2012/5/18_la Application & Amendment 16. The package structure as described in claim 13 of the patent application, further includes: a first glue And surrounding the outer side of the metal frame; and a second adhesive material disposed between the top of the metal frame and the metal cover plate, and between the first rubber material and the metal cover plate, thereby the metal cover A plate is fixed on the top of the metal frame and on the first glue. 17. The package structure of claim 16, wherein the second glue is a metal glue. 18. The package structure of claim 13, wherein the semiconductor die is electrically connected to the conductive via through a wire bonding technique. 19. The package structure of claim 13, wherein the semiconductor die is disposed on the substrate by a flip chip bonding technique. 20. The package structure of claim 13, wherein the metal frame material comprises copper (Cu). 21. The package structure of claim 13, wherein the substrate is a silicon substrate. 097102713 1013192160-0 18
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