CN109087896B - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
CN109087896B
CN109087896B CN201710507311.0A CN201710507311A CN109087896B CN 109087896 B CN109087896 B CN 109087896B CN 201710507311 A CN201710507311 A CN 201710507311A CN 109087896 B CN109087896 B CN 109087896B
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China
Prior art keywords
circuit structure
conductive
layer
electronic
block
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CN201710507311.0A
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CN109087896A (en
Inventor
廖俊明
江政嘉
王隆源
王愉博
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN109087896A publication Critical patent/CN109087896A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An electronic package and a manufacturing method thereof are provided, wherein an electronic element and a plurality of conductive columns and support members with different heights are arranged on a first circuit structure, a block body is arranged on the support member, and then a coating layer for coating the electronic element, the block body, the support member and the conductive columns is formed, so that the block body and the support member are covered on the periphery of the electronic element, and the electronic element is prevented from being subjected to external electromagnetic interference when the electronic package operates.

Description

Electronic package and manufacturing method thereof
Technical Field
The present invention relates to a packaging technology, and more particularly, to a semiconductor package capable of avoiding electromagnetic interference and a method for fabricating the same.
Background
With the rapid development of the electronic industry, electronic products are also gradually moving toward multi-function and high-performance. In order to meet the demand for miniaturization (miniaturization) of electronic products and electronic packages disposed therein, a Chip Scale Package (CSP) technology has been developed, wherein the CSP technology is characterized by having a size equal to or slightly larger than the Chip size.
Fig. 1A to 1E are schematic cross-sectional views illustrating a method for manufacturing a conventional chip-scale package 1.
As shown in fig. 1A, a thermal release tape (thermal release tape)100 is formed on a carrier 10.
Next, a plurality of semiconductor devices 11 are disposed on the thermal release adhesive layer 100, the semiconductor devices 11 have an active surface 11a and a non-active surface 11b opposite to each other, each of the active surfaces 11a has a plurality of electrode pads 110 thereon, and each of the active surfaces 11a is adhered to the thermal release adhesive layer 100.
As shown in fig. 1B, an encapsulant 14 is formed on the thermal release layer 100 to encapsulate the semiconductor device 11.
As shown in fig. 1C, the encapsulant 14 is baked to harden the thermal release layer 100 and remove the thermal release layer 100 and the carrier 10 to expose the active surface 11a of the semiconductor device 11.
As shown in fig. 1D, a circuit structure 16 is formed on the encapsulant 14 and the active surface 11a of the semiconductor device 11, such that the circuit structure 16 is electrically connected to the electrode pad 110. Next, an insulating passivation layer 18 is formed on the circuit structure 16, and the insulating passivation layer 18 exposes a portion of the surface of the circuit structure 16 for bonding with the conductive elements 17 such as solder balls.
As shown in fig. 1E, a singulation process is performed along a cutting path L as shown in fig. 1D to obtain a plurality of chip scale packages 1.
However, the conventional chip-scale package 1 can only place the semiconductor devices 11 in a single layer, and thus the application of the end product is greatly limited. Accordingly, a three-dimensional Wafer Level System In Package (WLSiP) structure is developed to meet the requirements of the current end product application.
Fig. 2A to fig. 2E are schematic cross-sectional views illustrating a manufacturing method of a conventional WLSiP type electronic package 2.
As shown in fig. 2A, a first circuit structure 20 is bonded on a carrier board 9 having a release layer 90 and a bonding layer 91, the first circuit structure 20 has a first side 20a and a second side 20b opposite to each other and is bonded to the bonding layer 91 by the second side 20b, and the first circuit structure 20 includes a first insulating layer 200 and a first redistribution layer (RDL) 201 disposed on the first insulating layer 200.
Next, a plurality of conductive pillars 23 electrically connected to the first circuit structure 20 are formed on the first side 20a, and a first electronic element 21 is disposed on the first side 20a of the first circuit structure 20. The first electronic element 21 has an active surface 21a and an inactive surface 21b opposite to each other, the inactive surface 21b of the first electronic element 21 is adhered to the first side 20a of the first circuit structure 20 through a bonding layer 214, the active surface 21a has a plurality of electrode pads 210 on which conductive bodies 212 are formed, and an insulating layer 211 is formed on the active surface 21a, so that the insulating layer 211 covers the electrode pads 220 and the conductive bodies 212.
As shown in fig. 2B, a cladding layer 25 is formed on the first side 20a of the first circuit structure 20 to encapsulate the first electronic element 21 and the conductive pillars 23, and the surface of the cladding layer 25 is flush with the surface of the insulating layer 211, the end surfaces of the conductive pillars 23 and the end surfaces of the conductive body 212, so that the surface of the insulating layer 211, the end surfaces of the conductive pillars 23 and the end surfaces of the conductive body 212 are exposed out of the cladding layer 25.
As shown in fig. 2C, a second circuit structure 26 is formed on the cladding layer 25, and the second circuit structure 26 electrically connects the conductive pillars 23 and the conductive body 212, wherein the second circuit structure 26 includes a plurality of second insulating layers 260,260 ' and a plurality of second redistribution layers (RDLs) 261,261 ' disposed on the second insulating layers 260,260 '.
As shown in fig. 2D, the carrier 9 and the release layer 90 thereon are removed. Next, an insulating passivation layer 28 is formed on the bonding layer 91, and a plurality of openings are formed in the insulating passivation layer 28 and the bonding layer 91, so that a portion of the surface of the first redistribution layer 201 is exposed to the openings, so as to bond a plurality of conductive elements 27, such as solder balls, on the second side 20b of the first circuit structure 20, and to connect a second electronic element 22.
As shown in fig. 2E, an encapsulation layer 24 is formed on the second side 20b of the first circuit structure 20 to encapsulate the second electronic elements 22. Next, an Under Bump Metallurgy (UBM) 270 is formed on the outermost second redistribution layer 261 'to form a plurality of conductive elements 27' such as solder balls for mounting electronic devices (not shown) such as package structures or chips.
However, when the conventional electronic package 2 is in operation, the first electronic element 21 located between the first and second circuit structures 20 and 26 is very sensitive to external electromagnetic waves, which not only makes the first electronic element 21 unable to operate normally, but also may damage the first electronic element 21.
Therefore, how to overcome the various problems of the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides an electronic package and a method for fabricating the same, which can prevent the electronic device from being subjected to external electromagnetic interference.
The electronic package of the present invention includes: a first line structure having opposite first and second sides; a plurality of conductive posts disposed on the first side and electrically connected to the first circuit structure; a plurality of support members disposed on a first side of the first circuit structure; an electronic component coupled to and electrically connected to the first side of the first circuit structure; the block body is arranged on the support piece to cover the electronic element; a coating layer formed on the first side of the first circuit structure to coat the electronic element, the block body, the support member and the conductive pillar; and a second circuit structure formed on the cladding layer and electrically connected to the conductive pillar.
The invention also provides a method for manufacturing the electronic package, which comprises the following steps: providing a first circuit structure having a first side and a second side opposite to the first side, wherein a plurality of conductive pillars and a plurality of supporting members are formed on the first side, and at least one electronic element is disposed thereon; arranging a block on the support member so that the block covers the electronic element; forming a coating layer on the first side of the first circuit structure so that the coating layer coats the electronic element, the block body, the support member and the conductive column; and forming a second circuit structure on the coating layer, wherein the second circuit structure is electrically connected with the conductive column.
In the above method, the step of disposing the block includes: combining a conductive cover member on the conductive post and the support member, wherein the conductive cover member comprises the block body disposed on the support member and a frame connected to the block body by a plurality of brackets, and the frame is disposed on the conductive post; and removing the frame after forming the coating layer. Further, the stent may be removed after the coating layer is formed.
In the electronic package and the method for fabricating the same, the electronic component is disposed on the first circuit structure in a flip chip manner.
In an embodiment, the height of the supporting element relative to the first side is less than the height of the conductive pillar relative to the first side.
In an embodiment, the support is located between the electronic element and the conductive pillar.
In the electronic package and the method for fabricating the same, the supporting member is used for grounding.
In the electronic package and the method for manufacturing the same, the supporting member and the block are made of a conductive material.
In the electronic package and the method for fabricating the same, the top surface of the block is exposed out of the encapsulation layer.
In the electronic package and the method for fabricating the same, the second circuit structure is connected to the block.
In the electronic package and the method for manufacturing the same, a plurality of conductive elements are formed on the second side of the first circuit structure.
In the electronic package and the method for fabricating the same, a plurality of conductive elements are formed on the second circuit structure.
In view of the above, the electronic package and the method for manufacturing the same of the present invention mainly use the design of the block and the supporting member to cover the shielding structure on the periphery of the electronic component, so that the electronic component is not subjected to external electromagnetic interference when the electronic package is operated.
Furthermore, the invention uses the metal frame as the shielding block, so that the metal shielding layer is not required to be formed by electroplating or sputtering, thereby not only reducing the manufacturing cost, but also maintaining the consistency of the electronic product.
Drawings
Fig. 1A to 1E are schematic cross-sectional views illustrating a method for fabricating a conventional chip-scale package;
fig. 2A to fig. 2E are schematic cross-sectional views illustrating a manufacturing method of a conventional WLSiP type electronic package;
fig. 3A to 3G are schematic cross-sectional views illustrating a method for fabricating an electronic package according to the present invention;
FIG. 3C' is a partial top plan view corresponding to FIG. 3C; and
fig. 3D' is a schematic cross-sectional view of another embodiment corresponding to fig. 3D.
Description of the symbols:
1 chip size package
10 bearing part
100 thermalization shape-separated adhesive layer
11 semiconductor element
11a,21a,31a action surface
11b,21b,31b non-active surface
110,210,310 electrode pad
14 packaging adhesive
16-circuit structure
17,27,27 ', 37, 37' conductive element
18,28,38 insulating protective layer
2,3 electronic package
20,30 first line structure
20a,30a first side
20b,30b second side
200,300 first insulating layer
201,301 first wire redistribution layer
21 first electronic component
211,311 insulating layer
212,312 Electrical conductor
214,91 bonding layer
22 second electronic component
23,33 conductive column
24 encapsulation layer
25,35 coating layer
26,36 second circuit structure
260,260 ', 360,360' second insulating layer
261,261 ', 361,361' second wire redistribution layer
270,370 under bump metal layer
31 electronic component
32 conductive cover member
320 block
321 framework
321' bracket
34 support piece
4 electronic device
40 chip
9 bearing plate
90 from type layer
L, S cutting path.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for clarity of description only, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a substantial technical change or modification.
Fig. 3A to 3G are schematic cross-sectional views illustrating a method for manufacturing an electronic package 3 according to the present invention.
As shown in fig. 3A, a first circuit structure 30 having a first side 30a and a second side 30b opposite to each other is formed on a carrier 9, and a plurality of conductive pillars 33 and a plurality of supporting members 34 are formed on the first side 30a and are bonded to the carrier 9 through the second side 30 b.
In the embodiment, the carrier 9 is a circular plate made of a semiconductor material such as glass, and a release layer 90 and a bonding layer 91 are sequentially formed thereon by, for example, coating, so that the first circuit structure 30 is disposed on the bonding layer 91.
Furthermore, the first circuit structure 30 includes at least a first insulating layer 300 and a first redistribution layer (RDL) 301 disposed on the first insulating layer 300. Specifically, the first redistribution layer 301 is made of copper, for example, and the first insulating layer 300 is made of a dielectric material, for example, Polyoxadiazole (PBO), Polyimide (PI), or Prepreg (PP).
The conductive posts 33 are disposed on the first redistribution layer 301 to electrically connect to the first redistribution layer 301, and the material forming the conductive posts 33 is a metal material such as copper or a solder material.
In addition, the supporting element 34 is disposed on the first redistribution layer 301 for grounding, the supporting element 34 is made of a metal material such as copper or a solder material, and the conductive posts 33 surround the supporting element 34, wherein a height H of the supporting element 34 relative to the first side 30a is smaller than a height H of the conductive posts 33 relative to the first side 30 a.
Specifically, in the embodiment, the supporting member 34 is a column (or a sheet), which can be fabricated together with the conductive pillar 33, for example, by a Double image process. In detail, the conductive pillar 33 and the supporting member 34 can be fabricated separately, for example, the photoresist for fabricating the supporting member 34 can be directly formed without removing the photoresist for fabricating the conductive pillar 33 to form the high-low pillar, and then the two layers of photoresist are removed; alternatively, the lower pillars (the support members 34) are formed first and the photoresist used therefor is removed, and then the upper pillars (the conductive pillars 33) are formed and the photoresist used therefor is removed; or removing the photoresist used to fabricate the conductive post 33 and disposing another photoresist to form the supporting member 34. Therefore, the manufacturing methods of the conductive pillar 33 and the supporting member 34 are various, and not limited to the above.
As shown in fig. 3B, at least one electronic component 31 is bonded to the first side 30a of the first circuit structure 30, the electronic component 31 is electrically connected to the first circuit structure 30, and the supporting members 34 surround the electronic component 31, so that the supporting members 34 are located between the electronic component 31 and the conductive pillars 33.
In the present embodiment, the electronic component 31 is a semiconductor component, such as a semiconductor chip, an active component, such as a resistor, a capacitor, or an inductor, or a combination thereof. For example, the electronic component 31 is a semiconductor chip having an active surface 31a and an inactive surface 31b opposite to each other, the active surface 31a has a plurality of electrode pads 310, and the electronic component 31 electrically connects the first redistribution layer 301 and the electrode pads 310 in a flip-chip manner (e.g., via a plurality of solder bumps 311 having copper bumps 311 a).
As shown in fig. 3C, a conductive cover 32 is bonded to the conductive pillar 33 and the supporting member 34, such that the conductive cover 32 covers the electronic element 30.
In the embodiment, the conductive lid 32 is a metal body, which includes a frame 321 and a block 320, the frame 321 is connected to the block 320 through a plurality of brackets 321 ', as shown in fig. 3C', the frame 321 is connected to the conductive pillar 33, and the block 320 is connected to the support 34 to cover the electronic component 30.
As shown in fig. 3D, a cladding layer 35 is formed on the first side 30a of the first circuit structure 30, so that the cladding layer 35 encapsulates the electronic element 31, the conductive cover 32, the conductive pillars 33 and the supporting members 34, and then a planarization process is performed to expose the end surfaces of the conductive pillars 33 and the block 320 out of the cladding layer 35.
In the present embodiment, the cladding layer 35 is an insulating material, such as an epoxy encapsulant, and may be formed on the first side 30a of the first circuit structure 30 by pressing (laminating) or molding (molding).
Furthermore, the planarization process removes portions of the conductive post 33, the frame 321 (including the stand 321') of the conductive lid 32, and portions of the cladding layer 35 by polishing, such that the end surface of the conductive post 33 is flush with the top surface of the block 320 and the surface of the cladding layer 35.
Also, the block 320 may not be exposed to the surface of the cladding 35. As shown in fig. 3D ', the frame 321 can be bent to press the block 320, so that a height difference (stand off high) is formed between the frame 321 and the block 320, after the cladding layer 35 is formed on the first side 30a of the first circuit structure 30, the frame 321 is protruded out of the cladding layer 35, and then the frame 321 is removed by a leveling process, so that the frame 321' and the block 320 are embedded in the cladding layer 35.
As shown in fig. 3E, a second circuit structure 36 is formed on the cladding layer 35, and the second circuit structure 36 is electrically connected to the conductive pillars 33 and the bulk 320.
In the embodiment, the second circuit structure 36 includes a plurality of second insulating layers 360 and a plurality of second redistribution layers 361 disposed on the second insulating layers 360, and the outermost second insulating layer 360 'can be used as a solder mask layer, so that the outermost second redistribution layers 361' are exposed on the solder mask layer. Alternatively, the second circuit structure 36 may only include a single second insulating layer 360 and a single second redistribution layer 361.
The second redistribution layer 361,361 'is made of copper, and the second insulating layer 360,360' is made of a dielectric material such as poly-p-xylylene (PBO), Polyimide (PI), or Prepreg (PP).
As shown in fig. 3F, the carrier 9 and the release layer 90 thereon are removed. Next, an insulating passivation layer 38, such as a solder mask, is formed on the bonding layer 91 on the second side 30b of the first circuit structure 30.
As shown in fig. 3G, a singulation process is performed along the dicing path S shown in fig. 3F to complete the electronic package 3 of the present invention.
In this embodiment, an Under Bump Metallurgy (UBM)370 may be formed on the outermost second redistribution layer 361 'to combine a plurality of conductive elements 37, such as solder balls, on the outermost second redistribution layer 361' for connecting other electronic structures (such as another package or a chip such as the conventional second electronic element 22).
In addition, a plurality of openings may be formed on the insulating passivation layer 38 and the bonding layer 91, such that the first redistribution layer 301 is exposed to the openings, so as to form a plurality of conductive elements 37', such as solder balls, on the second side 30b of the first circuit structure 30, for connecting an electronic device 4, such as a package structure including a chip 40 or other electronic structure (such as another package or a chip).
Therefore, the manufacturing method of the electronic package 3 of the present invention uses the block 320 of the conductive lid 32 as a shielding structure to block the interference of the external electromagnetic wave to the electronic component 31 between the first and second circuit structures 30 and 36, so that the electronic component 31 of the present invention can operate normally and the external electromagnetic wave can be prevented from damaging the electronic component 31.
Furthermore, the method of the present invention uses the simple metal block 320 on the metal frame 321 as a shielding structure, so that there is no need to form a metal shielding layer by electroplating or sputtering, thereby reducing the manufacturing cost.
In addition, the manufacturing method of the present invention keeps the appearance of the electronic package 3 substantially unchanged, thereby maintaining the consistency of the electronic product.
The present invention also provides an electronic package 3, which includes: a first circuit structure 30, a plurality of conductive pillars 33, an electronic component 31, a block 320, a plurality of supporting members 34, a covering layer 35, and a second circuit structure 36.
The first circuit structure 30 has a first side 30a and a second side 30b opposite to each other.
The conductive pillars 33 are disposed on the first side 30a and electrically connected to the first circuit structure 30.
The support member 34 is disposed on the first side 30a of the first circuit structure 30.
The first electronic component 31 is coupled and electrically connected to the first circuit structure 30.
The block 320 is disposed on the supporting member 34 and covers the first electronic component 31.
The cladding layer 35 is formed on the first side 30a of the first circuit structure 30 to encapsulate the electronic element 31, the block 320, the supporting element 340 and the conductive pillars 33, and the end surfaces of the conductive pillars 33 are exposed out of the cladding layer 35.
The second circuit structure 36 is formed on the cladding layer 35 and electrically connected to the conductive pillar 33.
In one embodiment, the electronic component 31 is disposed on the first side 30a of the first circuit structure 30 in a flip-chip manner.
In one embodiment, the height H of the supporting element 34 relative to the first side 30a is less than the height H of the conductive pillar 33 relative to the first side 30 a.
In one embodiment, the supporting member 34 is located between the electronic element 31 and the conductive pillar 33.
In one embodiment, the supporting member 34 is a conductive material.
In one embodiment, the bulk 320 is a conductive material.
In one embodiment, the block 320 is exposed to the cladding 35.
In one embodiment, the second circuit structure 36 is connected to the block 320.
In one embodiment, the electronic package 3 further includes a plurality of conductive elements 37' formed on the second side 30b of the first circuit structure 30.
In one embodiment, the electronic package 3 further includes a plurality of conductive elements 37 formed on the second circuit structure 36.
In summary, the electronic package and the fabrication method thereof of the present invention use the block and the supporting member as a shielding structure of the electronic component to prevent the electronic component from being subjected to external electromagnetic interference, so that the electrical function of the electronic package can be normally operated.
In addition, the invention uses the block on the simple metal frame as the shielding structure, so that a metal shielding layer is not required to be formed in an electroplating or sputtering way, the manufacturing cost can be reduced, and the consistency of the electronic product can be maintained.
The foregoing embodiments are illustrative of the principles and utilities of the present invention and are not intended to be limiting. Modifications to the above would be obvious to those of ordinary skill in the art, but would not bring the invention so modified beyond the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (10)

1. A method of fabricating an electronic package, the method comprising:
providing a first circuit structure having a first side and a second side opposite to the first side, wherein a plurality of conductive pillars and a plurality of supporting members are formed on the first side, and at least one electronic element is connected to the first side, wherein the first circuit structure includes a first circuit redistribution layer, and the plurality of conductive pillars are electrically connected to the first circuit redistribution layer of the first circuit structure;
combining a conductive cover member on the conductive pillar and the support member, wherein the conductive cover member includes a block body disposed on the support member and a frame connected to the block body through a plurality of brackets, and the frame is disposed on the conductive pillar so that the block body covers the electronic element, wherein a height of the support member relative to the first side is less than a height of the conductive pillar relative to the first side;
forming a coating layer on the first side of the first circuit structure so that the coating layer coats the electronic element, the block body, the support member and the conductive column;
removing the frame after forming the cladding layer; and
forming a second circuit structure having a second redistribution layer on the cladding layer, wherein the second redistribution layer of the second circuit structure is electrically connected to the conductive pillar.
2. The method of claim 1, wherein the electronic component is flip-chip mounted on the first circuit structure.
3. The method of claim 1, wherein the supporting member is located between the electronic component and the conductive pillar.
4. The method of claim 1, wherein the supporting member and the block are made of conductive material.
5. The method of claim 1, wherein the support member is configured to be grounded.
6. The method of claim 1, wherein the top surface of the block is exposed from the encapsulation layer.
7. The method of claim 1, wherein the second circuit structure is connected to the block.
8. The method of claim 1, further comprising forming a plurality of conductive elements on a second side of the first circuit structure.
9. The method of claim 1, further comprising forming a plurality of conductive elements on the second circuit structure.
10. The method of claim 1, further comprising removing the support after forming the encapsulation layer.
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TWI712149B (en) * 2019-08-13 2020-12-01 矽品精密工業股份有限公司 Electronic package and method for fabricating the same
TWI796180B (en) * 2022-03-24 2023-03-11 矽品精密工業股份有限公司 Electronic packaging and manufacturing method thereof
TWI823618B (en) * 2022-10-14 2023-11-21 矽品精密工業股份有限公司 Electronic package

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