TWI367430B - Circuit-design-modifying method executable in computer system - Google Patents

Circuit-design-modifying method executable in computer system

Info

Publication number
TWI367430B
TWI367430B TW097108153A TW97108153A TWI367430B TW I367430 B TWI367430 B TW I367430B TW 097108153 A TW097108153 A TW 097108153A TW 97108153 A TW97108153 A TW 97108153A TW I367430 B TWI367430 B TW I367430B
Authority
TW
Taiwan
Prior art keywords
design
circuit
computer system
modifying method
method executable
Prior art date
Application number
TW097108153A
Other languages
English (en)
Other versions
TW200837591A (en
Inventor
Chien Jung Hsin
Original Assignee
Dorado Design Automation Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dorado Design Automation Inc filed Critical Dorado Design Automation Inc
Publication of TW200837591A publication Critical patent/TW200837591A/zh
Application granted granted Critical
Publication of TWI367430B publication Critical patent/TWI367430B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/06—Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW097108153A 2007-03-09 2008-03-07 Circuit-design-modifying method executable in computer system TWI367430B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US89388907P 2007-03-09 2007-03-09

Publications (2)

Publication Number Publication Date
TW200837591A TW200837591A (en) 2008-09-16
TWI367430B true TWI367430B (en) 2012-07-01

Family

ID=39742929

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097108153A TWI367430B (en) 2007-03-09 2008-03-07 Circuit-design-modifying method executable in computer system

Country Status (3)

Country Link
US (1) US7992123B2 (zh)
CN (1) CN101246516B (zh)
TW (1) TWI367430B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5229834B2 (ja) * 2008-09-30 2013-07-03 株式会社アドバンテスト 回路設計方法、回路設計システム及び記録媒体
JP4831375B2 (ja) * 2009-06-26 2011-12-07 日本電気株式会社 検証装置、検証方法、及びプログラム
US8122400B2 (en) * 2009-07-02 2012-02-21 International Business Machines Corporation Logic difference synthesis
KR20120117774A (ko) * 2009-11-16 2012-10-24 프로엑터 슈츠레츠스베르발퉁스 게엠베하 반탄화 및 파쇄에 의하여 고체 또는 페이스트형 에너지 원료로부터 미립 연료를 생성하는 장치 및 방법
US8271920B2 (en) * 2010-08-25 2012-09-18 International Business Machines Corporation Converged large block and structured synthesis for high performance microprocessor designs
US8266566B2 (en) * 2010-09-10 2012-09-11 International Business Machines Corporation Stability-dependent spare cell insertion
US8316335B2 (en) * 2010-12-09 2012-11-20 International Business Machines Corporation Multistage, hybrid synthesis processing facilitating integrated circuit layout
CN102033772A (zh) * 2010-12-28 2011-04-27 复旦大学 用于fpga映射的电路改写指令系统
US8924896B2 (en) * 2013-01-31 2014-12-30 Globalfoundries Inc. Automated design layout pattern correction based on context-aware patterns
US8966418B2 (en) * 2013-03-15 2015-02-24 Globalfoundries Inc. Priority based layout versus schematic (LVS)
US10460060B2 (en) * 2017-11-27 2019-10-29 Mellanox Technologies, Ltd. Checking equivalence between changes made in a circuit definition language and changes in post-synthesis nets
US10599802B2 (en) 2018-06-18 2020-03-24 Mellanox Technologies, Ltd. Methods for automatic engineering change order (ECO) bug fixing in integrated circuit design
CN112100972B (zh) * 2019-05-31 2024-02-13 创意电子股份有限公司 电路校正系统与增加扫描测试涵盖率的方法
CN113822007A (zh) * 2021-11-22 2021-12-21 北京芯愿景软件技术股份有限公司 电路生成方法、装置、设备及介质

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6484292B1 (en) 2000-02-07 2002-11-19 Xilinx, Inc. Incremental logic synthesis system for revisions of logic circuit designs
JP2002259477A (ja) 2001-03-06 2002-09-13 Mitsubishi Electric Corp 半導体回路設計変更方法
US6530073B2 (en) * 2001-04-30 2003-03-04 Lsi Logic Corporation RTL annotation tool for layout induced netlist changes
JP4147842B2 (ja) * 2002-07-04 2008-09-10 日本電気株式会社 論理検証システム及び方法、論理コーン抽出装置及び方法、論理検証及び論理コーン抽出プログラム

Also Published As

Publication number Publication date
CN101246516B (zh) 2010-06-02
US7992123B2 (en) 2011-08-02
CN101246516A (zh) 2008-08-20
US20080222595A1 (en) 2008-09-11
TW200837591A (en) 2008-09-16

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