1364097 九、發明說明： ，【發明所屬之技術領域】 I發明係關於-種半導體封裝件製法’尤指一種覆晶 .式半導體封裝件製法。 【先前技術】 …覆晶式球柵陣列（FliP-ChiPBall Grid Array，FCBGA) 半導體封裝件係為一種同時具有覆晶與球栅陣列之封裝 結構，以使至少一晶片的作用表面（ActiveSurface)可藉 >由多數凸塊（Solder Bumps)而電性連接至基板 (^Substrate)之一表面上，並於該基板之另一表面上植設 多數作為輸入/輸出（1/0)端之銲球（Solder Ball);此一 封裝結構可大幅縮減體積，同時亦省去習知銲線⑶“幻 之二计，而可降低阻抗提昇電性，以避免訊號於傳輸過程 中衰退，因此確已成為下一世代晶片與電子元件的主流封 裝技術。 | 然而，由於該種半導體封裝件於運作時所產生之熱量 ，向，若不即時將半導體晶片之熱量快速釋除，積存的熱 里會嚴重影響半導體晶片的電性功能與產品穩定度。另一 方面，為避免封裝件内部電路受到外界水塵污染，半導體 晶片表面必須外覆一封裝膠體予以隔絕，惟構成該封裝膠 體之封裝樹脂卻係一熱傳導性甚差之材質，其熱導係數僅 〇.8w/m-K’是以’半導體晶片舖設多數電路之主動面上產 生之熱量無法有效藉該封裝膠體傳遞到大氣外，而往往導 致熱積存現象產生’使晶片性能及使用壽命備受考驗。因 110801 1364097 遂有於封裝件中增 此，為提高半導體封裝件之散熱效率 設散熱件之構想應運而生。 惟若散熱件亦為封裝膠體所完全包覆時，半導體 =熱量的散熱途徑仍須通過封裝膠體，散熱效果：提 甚而無法符合散熱之需求，因而，為有 二曰片熱！，其-方式係使散熱件充分顯露出該封裝膠1364097 IX. Description of the invention: [Technical field to which the invention pertains] The invention of the invention relates to a method of manufacturing a semiconductor package, in particular, a method of fabricating a semiconductor package. [Prior Art] A FliP-ChiPBall Grid Array (FCBGA) semiconductor package is a package structure having both a flip chip and a ball grid array so that at least one active surface of the wafer can be used. Borrowing > is electrically connected to one surface of the substrate by a plurality of bumps, and implanting a majority of the input/output (1/0) end on the other surface of the substrate Ball (Solder Ball); this package structure can greatly reduce the volume, and also eliminates the conventional wire (3) "magic illusion, but can reduce the impedance to improve the electrical, to avoid signal degradation during transmission, so it is indeed Becoming the mainstream packaging technology for the next generation of wafers and electronic components. | However, due to the heat generated by the operation of such semiconductor packages, if the heat of the semiconductor wafer is not immediately released, the accumulated heat will be severe. Affecting the electrical function and product stability of the semiconductor wafer. On the other hand, in order to avoid the internal circuit of the package being contaminated by external water and dust, the surface of the semiconductor wafer must be covered with a package of colloids. Isolation, but the encapsulating resin that constitutes the encapsulant is a material with poor thermal conductivity, and its thermal conductivity is only 88w/m-K'. The heat generated on the active surface of most semiconductor circuits cannot be effective. By transferring the encapsulant to the atmosphere, it often leads to the phenomenon of heat accumulation, which makes the performance and service life of the wafer highly tested. Since 110801 1364097 is added to the package, the heat sink is improved to improve the heat dissipation efficiency of the semiconductor package. The idea came into being. However, if the heat sink is completely covered by the encapsulant, the heat dissipation path of the semiconductor=heat must still pass through the encapsulant, and the heat dissipation effect can not meet the heat dissipation requirement. Therefore, there are two films. Hot!, the way it is to make the heat sink fully reveal the package adhesive
…請參閱第1A至1C圖，鑑此，美國專利第675 號遂揭示一具散埶件之胃， _ 、月又…什之覆日日式+導體封裝件製法； •所不，將一覆晶式半導體晶片12透過 電性連接至純Η，並形成包覆該覆晶式半束1 =装膠體如第1Β圖所示，利用機械研磨或化= ^方式移除位於該覆晶式半導體晶片12上方之封裝腰 體16及薄化部分覆晶式半導 、少 式半導體晶片12;如第1C= I:外露出該覆晶 弥弟1L圖所不，之後於該覆晶式 ίί ^、12上#置散熱件13 ’藉以透過該散熱件13逸散 覆a曰式半導體晶片12運作時所產生之熱量。 前述製法令，由於為使散熱件充分顯露出封裝膠體， 軸磨或化學㈣等方式移除位於覆晶式 +導體曰曰片上方之封装膠體及部分覆晶式半導體晶 可將散熱件接置於該覆晶式半導體晶片上，然而，在利用 機械研磨或化學—等方式移除位於覆晶式半導體 上方之封裝膠體及部分覆晶式半導體晶片，極易導致晶 毀損；另外透賴械研磨方式亦^造成晶片或晶片與基 110801 ( 6 1364097 板連接之導電凸塊因外力而發生損壞。 為此，請參閱第2A至2C圖，盖\击 遂揭示一種可避免晶片毀損之半^專利第6: 444,彻 2A圖所示，首先在散執件 / v 4 H如第 瓜驮…1干以奴外露於大 成一介面層230，再將該散熱件 、形 21之半導體晶片22上，繼而進二=-接置在基板 體26包覆該散熱件23及、^ ’以使封農膠 Μ覆蓋於散熱件23之介面/H22,並使封裝朦體 垃芏 > 上$ _ 層230上，如第2Β圖所示， 接者按+導體封裝件預定長寬尺寸進行 切割路徑係通過該介面請、散熱件：其中; 及基板21 ;如第2C圖所示，將散…上=體26 體=去除，其中該介面層訓（例如為聚亞醯胺樹脂製^ 與散熱件23間之黏結性小於其與封裝膠體26 黏、，·。性’因此將封裝膠體26剝除時，該介面層23〇 =附於封裝膠體26上而隨之去除，藉以使該散熱件23 顯露出封裝膠體26。 然而於刖述製法中不僅須增設介面層而增加製程成 本與複祕’同時在進行切割作業時’ 士刀割刀具之切割路 桎會通過該散熱件，導致刀具磨損嚴重。 綜上所述，如何開發出一種可提升半導體封裝件之散 熱效月b，同時無須使用介面層以簡化製程步驟及成本並 可減少切割刀具磨損，及避免使用機械研磨或化學蝕刻封 裝膠體所導致晶片或導電凸塊毁損問題，以提高製程良 率’確已為此相關研發領域所迫切待解之課題。 7 110801 ( 1364097 【發明内容】 • 有鑑於前述問題，本發明之—目的即在於提供-種提 升散熱效能之半導體封裝件製法。 〜本發明之另-目的在於提供一種無須使用介面層以 簡化製程步驟及降低成本之半導體封裝件製法。 本發明之又-目的在於提供一種減少切割刀具磨損 之半導體封裝件製法。 、 本發明之復-目的在於提供—種避免在移除封裝膠 癱體時，因外力作用導致損壞晶片或導電凸塊之半導體封裝 本發明之再—目的在於提供—種提高製程良率及汚 低製程成本之半導體封裝件製法。 為達上述目的，本發明所提出之半導體封裝件製法 ^包括：提供—承餅與複數基板，該承㈣具有多㈣ =口以容置各該基板，該基板上接置有覆晶式半導⑸ |:二該覆晶式半導體晶片上接置有散熱件，其中該基相 ^長寬尺寸健近料㈣封裝件之敎長寬尺寸，該韵 板:d見尺寸小於该基板之長寬尺寸，以將該複數個基 ι;=於該承載件之多數個開口中，同時封蓋該基板 ^玄承載件間之間隙；進行模璧製程，以於每—開口上八 Γ么用，？覆該覆晶式半導體晶片及散熱件的封裝: 口的封轉體所覆蓋面積的長寬尺寸係A於該開 埶=寬尺寸；進行脫模步驟；利用雷射移除覆蓋於該散 熱件上之封裝膠體’以外露出該散熱件;以及依該半導體 110801 8 1J64097 _ 件之預定長寬尺寸而沿該基板邊緣進行切割，以製得 .夕數個半導體封裝件。 緣材料、之承載件材料係選自FR4、FR5、或BT等有機絕 _ * 、二本發明亦可以一金屬承載件而製得所需之低成本 件盘複數ir’其製法係包括以下步驟：提供一金屬承載 /、星數基板，該承載件具有多數個 板，該基板上接置有覆曰切墓辦曰y 乂合置各-亥基 赢雕旻日日式'^導體日日片，且該覆晶式半導 置有散熱件’其中該基板之長寬尺寸接近該半 基板之=之預定長寬尺寸’該散熱件之長寬尺寸小於該 -二多數二尺Γ以將該複數個基板分別定位於該承載件 •進二 =同時封蓋該基板與該承载件間之間隙； 式半導；:=,:開°上分別形成用以包覆該覆晶 = 的封裝膠體，俾使該基板、覆晶式 件與封裝膠體形成—㈣單元，其中， 尺η™ 於該開σ的長寬 、 ^驟，利用雷射移除覆蓋於該散轨件上之 =膠體，以外露出該散熱件，·分離該封裝單元愈該金屬 承载件；以及依該半導體封裝件之預定長寬尺寸而μ基 板邊緣進行切割，以製得多數個半導體封裝件。^ 前述之金屬承載件係為一銅⑽材料，且其 與該封裝膠體不易點著的金屬鍍層，該金屬鑛層係； Λ自金㈤、鎳⑹、或鉻⑹等金屬材料，進而可，由 該金屬鑛層不與該封裝膠體黏著之特性，輕易 = 110801 S ) 9 1364097 早兀與金屬承載件，更兼顧得製程之便利性。 靜曰由本發明前述之製法’係直接於覆晶式半導 =上接置散熱件，並使封裝谬體同時包覆該覆晶式半 導體明片及散熱件，再利用雷射移除該覆蓋於該散孰件上 體’以外露出該散熱件，進而有效逸散覆晶式 半‘體晶片運作時產；备I旦 α , ‘，，、里，且由於本發明並未直接在 =曰曰式半導體晶片上移除覆蓋其上之封裝膠體，且未以機 學，方式移除封裝膠體，藉以避免毀損覆晶 : ΒΒ片及‘電凸塊’再者’本發明亦省去習知在散 …、件上覆蓋介電層’而得簡化製程步驟及降低成本。 另外本《明所提供之基板長寬尺寸約略等於封裳件 的預定長寬尺寸而不致過大，並封蓋該基板與該承載件間 之間隙，同時令形成封裝膠體之模穴的投影長寬尺寸大於 该開口的長寬尺寸，以供後續沿該基板邊緣切割後即可 件預定長寬尺寸之半導體封裝件’減少基板之製備尺寸出 現不必要的浪費；且由於本發明中所形成之封裝膠體之投 影長寬尺寸係大於半導體封裝件之預定長寬尺寸，因此在 沿該基板邊緣進行切割時，將同時切割移除掉該半導體封 襄件之預定長寬尺寸外之封裝„及形成於該封裝勝體 側邊之氣泡’藉以提高製程良率；同時本發明中設於覆 晶式半導體晶片上之散熱件長寬尺寸係小於該基板之長 寬尺寸，如此在沿該基板邊緣切割時，切割刀具將不致娘 過該散熱件’以減少刀具磨損問題；以及本發明復藉由2 承載件開設多數開口以利用批次方式大量製程，進而降低 110801 ( 1364097 -尺寸之膠片（未圖示）封蓋於該基板與該承載件之間隙 •上，以減省膠片材料之使用量；亦或以點膠方式而於該基 板與玄承載件間之間隙中填充滿一例如拒銲劑（S〇ider Mask)之膠料，以同時定位該基板並封蓋該間隙，或者， 邊膠料亦可選用例如環氧樹脂等高分子材料。 如第3D圖所示’進行模壓製程，將該承載件3〇置入 模具35，以令該覆晶式半導體晶片32及散熱件33容嗖 於其所對應之模穴（Cavity)35〇中，並於每一開口 3〇〇: #分別形成用以包覆該覆晶式半導體晶片32及散執件33 的封裝膠體36。 另外，本發明中用以形成該封裝膠體36之模穴350 的投影長寬尺寸係大於該開口 3〇〇的長寬尺寸亦即所形 成之封裳膠體36之投影長寬尺寸M係大於半導體 之預定長寬尺寸P(約為基板31之尺寸），如此，在封裝 模壓製程中填入封裝樹脂時，模具35之模穴35〇中的空'...please refer to Figures 1A to 1C. For this reason, U.S. Patent No. 675 discloses a stomach of a dilated piece, _, and a month... a method of making a Japanese-style + conductor package; The flip-chip semiconductor wafer 12 is electrically connected to the pure germanium, and is formed to cover the flip-chip half-beam 1 = the colloid is as shown in FIG. 1 , and is removed by mechanical grinding or chemical conversion. a packaged waist body 16 above the wafer 12 and a thinned portion of the flip-chip semi-conductive semiconductor wafer 12; as shown in the first C=I: the exposed crystal chip is not exposed, and then the flip chip type ίί ^, The heat dissipation member 13 is configured to dissipate heat generated by the operation of the a-type semiconductor wafer 12 through the heat dissipation member 13. The above-mentioned manufacturing method can remove the heat dissipating component by removing the encapsulant and the partially flip-chip semiconductor crystal located above the flip-chip+conductor chip in order to make the heat sink fully expose the encapsulant, shaft grinding or chemical (4). On the flip-chip semiconductor wafer, however, the removal of the encapsulant and the partially flip-chip semiconductor wafer over the flip-chip semiconductor by mechanical grinding or chemical-chemical means is liable to cause crystal damage; The method also causes the wafer or wafer to be damaged by the external force of the conductive bumps connected to the base 110801 (6 1364097 board. For this, please refer to Figures 2A to 2C, the cover \ 遂 reveals a half of the patent that can avoid wafer damage ^ patent No. 6: 444, as shown in FIG. 2A, first in the loose piece / v 4 H such as the first melon ... 1 dry slave exposed to the large interface layer 230, and then the heat sink, the shape 21 of the semiconductor wafer 22 Then, the second substrate is attached to the substrate body 26 to cover the heat dissipating member 23 and the cover member to cover the interface of the heat dissipating member 23/H22, and the package body is smashed > On layer 230, as shown in Figure 2, the receiver presses + The predetermined length and width dimensions of the body package are passed through the interface, the heat sink: wherein; and the substrate 21; as shown in FIG. 2C, the body is removed, wherein the interface layer is trained (for example, The adhesive property between the polyimide resin and the heat sink 23 is less than that of the adhesive body 26, and thus the interface layer 23 is attached to the encapsulant 26 when the encapsulant 26 is peeled off. And then removed, so that the heat sink 23 reveals the encapsulant 26. However, in the method of describing the method, not only the interface layer needs to be added, but also the process cost and the re-creation 'while cutting the cutter' The heat sink will pass through the heat sink, causing serious tool wear. In summary, how to improve the heat dissipation effect of the semiconductor package can be improved, and the interface layer is not needed to simplify the process steps and cost and reduce the wear of the cutting tool. And avoiding the problem of wafer or conductive bump damage caused by mechanical grinding or chemical etching of the encapsulant to improve the process yield has indeed been an urgent issue for this related research and development field. 7 11080 1 (1364097) SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a method of fabricating a semiconductor package that enhances heat dissipation performance. Another object of the present invention is to provide an interface layer that is simplified without requiring an interface layer. And a method for manufacturing a semiconductor package with reduced cost. A further object of the present invention is to provide a method for fabricating a semiconductor package that reduces wear of a cutting tool. The present invention is directed to providing a method for avoiding removal of a packaged body. Semiconductor package with external force causing damage to the wafer or conductive bumps. The present invention has been made in an effort to provide a method of fabricating a semiconductor package that improves process yield and low process cost. In order to achieve the above object, the semiconductor package manufacturing method of the present invention comprises: providing a carrier and a plurality of substrates, the carrier (4) having a plurality of (4) ports for accommodating the substrates, and the substrate is covered with a flip chip Guide (5) |: 2, the flip-chip semiconductor wafer is provided with a heat dissipating member, wherein the base phase is long and wide, and the length and width dimensions of the package (4) package are: the d panel is smaller than the length of the substrate. a wide size, in the plurality of openings; in a plurality of openings of the carrier, simultaneously covering the gap between the substrate and the substrate; performing a molding process for each of the openings ,? The package covering the flip-chip semiconductor chip and the heat sink: the length and width of the area covered by the sealing body of the mouth is A in the opening=width dimension; the demoulding step is performed; and the heat sink is covered by the laser removing The heat dissipating member is exposed outside the encapsulating body; and cutting along the edge of the substrate according to a predetermined length and width dimension of the semiconductor 110801 8 1J64097 _ to obtain a plurality of semiconductor packages. The edge material and the carrier material are selected from the group consisting of FR4, FR5, or BT, etc., and the second invention can also be used as a metal carrier to obtain the required low-cost component disk ir'. Providing a metal-bearing/star-numbered substrate, the carrier has a plurality of plates, and the substrate is covered with a cover-cut 墓 曰 乂 乂 各 各 亥 亥 亥 亥 亥 亥 亥 亥 ' ' ' ' ^ ^ ^ ^ ^ ^ 导体And the flip-chip semi-conductor is provided with a heat dissipating member, wherein the length and width dimensions of the substrate are close to a predetermined length and width dimension of the semi-substrate, and the length and width dimensions of the heat dissipating member are smaller than the -two majority Positioning the plurality of substrates on the carrier respectively; entering the second = simultaneously covering the gap between the substrate and the carrier; the semi-conducting;:=,: opening ° is respectively formed to cover the flip chip = Encapsulating the colloid, so that the substrate, the flip-chip and the encapsulant form a (four) unit, wherein the ruler ηTM is over the width and width of the opening σ, and the laser is used to cover the loose track member. a colloid that exposes the heat sink, and separates the package unit from the metal carrier; and according to the semiconductor A predetermined length and width dimensions of the package substrate μ cutting edge, to obtain a plurality of semiconductor packages. ^ The foregoing metal carrier is a copper (10) material, and the metal plating layer which is not easily attached to the encapsulant, the metal ore layer; the metal material such as gold (5), nickel (6), or chromium (6), and then, Since the metal ore layer does not adhere to the encapsulant, it is easy to = 110801 S) 9 1364097, and the metal carrier is used for the convenience of the process. The static method of the present invention is directly attached to the flip-chip semi-conductor=upper heat sink, and the packaged body is simultaneously coated with the flip-chip semiconductor chip and the heat sink, and the cover is removed by laser. Exposing the heat dissipating member to the upper body of the diverging member, thereby effectively dissipating the operation of the flip-chip type semi-body wafer; preparing I, α, ',,, and, since the present invention is not directly at =曰The encapsulation colloid covering the germanium semiconductor wafer is removed, and the encapsulation colloid is not removed mechanically, so as to avoid damage to the flip chip: the crucible and the 'electric bump' are further omitted from the present invention. Covering the dielectric layer on the parts, the process steps are simplified and the cost is reduced. In addition, the length and width of the substrate provided by the present invention are approximately equal to the predetermined length and width of the sealing member without being too large, and cover the gap between the substrate and the carrier, and at the same time, the projection length and width of the cavity forming the encapsulant are formed. The semiconductor package having a size larger than the length and width of the opening for subsequent cutting along the edge of the substrate, which can be a predetermined length and width dimension, reduces unnecessary preparation waste of the substrate; and the package formed by the present invention The projected length and width dimension of the colloid is greater than the predetermined length and width dimension of the semiconductor package, so that when cutting along the edge of the substrate, the package of the predetermined length and width of the semiconductor package is simultaneously cut and removed. The encapsulating bubble on the side of the body is used to improve the process yield; at the same time, the length dimension of the heat sink disposed on the flip chip semiconductor wafer is smaller than the length and width of the substrate, so that when cutting along the edge of the substrate , the cutting tool will not pass the heat sink 'to reduce the problem of tool wear; and the present invention utilizes 2 carriers to open a plurality of openings to utilize Sub-process a large number of processes, thereby reducing 110801 (1364097 - size film (not shown) cover the gap between the substrate and the carrier to reduce the amount of film material used; or by dispensing The gap between the substrate and the meta-support member is filled with a compound such as a solder mask to simultaneously position the substrate and cover the gap, or the epoxy resin may be selected, for example, an epoxy resin. The polymer material is subjected to a molding process as shown in FIG. 3D, and the carrier member 3 is placed in the mold 35 so that the flip chip semiconductor wafer 32 and the heat sink 33 are accommodated in the corresponding cavity (Cavity). 35 〇, and at each opening 3 #: # separately form an encapsulant 36 for covering the flip-chip semiconductor wafer 32 and the loose member 33. In addition, the encapsulant 36 is formed in the present invention. The projection length and width dimension of the cavity 350 is greater than the length and width dimension of the opening 3〇〇, that is, the projection length and width dimension M of the formed sealing body 36 is larger than the predetermined length and width dimension P of the semiconductor (about the substrate 31). Size), so, fill in the package molding process When the sealing resin, the mold cavity 35 is empty 35〇 '
亂將被往側邊推擠而於該側邊上形成氣泡_，其中應注 思該氣泡3 6 0形成位晋| •、上_ 尺寸外。 W位置録斜導體封裝件之預定長寬 填二Γ去 製程前，亦可先以一例如樹脂之底部 膠，再進行前述之模壓製程， ：，”真 體封裝件之電性。 Μ 4化且確保半導 =Ε圖所示，進行脫模程序並移除該踢片34。 如弟3F圖所示，於該基板31上未設置覆晶式半導體 110801 (S) 12 1364097 •有多數個開口 400’其中，該承載件4〇係選用一例如銅 .(Cu)之金屬材料，且該承載件4〇之表面係預先鍍上一例 如金（An)、鎳（Ni)、鉻（Cr)等與封裝膠體黏著不佳的金屬 鐘層（未圖示）。 同時，提供複數基板4卜以供覆晶式半導體晶片42 透過導電凸塊420而接置並電性連接至該基板4卜且於 該覆晶式半導體晶片42上接置有散熱件43，以將該些承 載有晶片42及散熱件43之基板41嵌合定位於該承載件 # 40之開口 400中’並以一勝片44封蓋該基板41與該承 載件40間之間隙，而使該間隙不致貫通該承載件，其 •中該基板41之長寬尺寸約等於該半導體封裝件之預定長 寬尺寸，該散熱件43之長寬尺寸小於該基板41之長寬尺、 寸。 如第4B圖所示，進行模壓製程，將該承載件40置入 模具45，以令該覆晶式半導體晶片42及散熱件43容設 於其所對應之模穴4 ίΐ Φ，"if "t/v > Ββ • 俱八450中，並於母一開口 400上分別形成 用以包覆該覆晶式半導體晶片42及散熱件43的封裝谬體 46 ° 、同樣地，在形成封裝膠體46時，模穴45〇中的空教 將被往側邊推擠而於該側邊上形成氣泡，且該氣=在 該半導體封裝件之敎長寬尺寸外，⑽彳㈣沿 ^ 切割時’同時移除多餘之封裝膝體及形成其中之氣泡/ 、=4(：11所不’於該基板41下表面植接多數個鲜球 以以田射切割移除覆蓋於該散熱件43上之封裝膠 Π0801 ( 15 1364097 如Γ使錢熱件43頂面外露出該封轉體46。 \4D圖所示，進行脫模與膠片44去除步驟此 於5亥金屬承載件40上已預先鍍有盥哕封f 黏著不佳的合属絲s 兀溉啕〃、4封裝膠體46 之接著㈣二 而該封裝膠體46與該承裁件4〇 ，取出由該基板41、覆晶V半自導 件43及封裝膠體46 _ 散熱 利與待進行切割之封;：t封裝早"分離該承載件 如第4E圖所示’進行切割步驟，以沿該基板μ邊緣 仃幻卜進而製得預定長寬尺寸之半導體封裝件。 本實施例可在切割步驟前即先行分離該封襄單元盘 2件’故而於切割步驟時將無需對該承載件進行^ 2載件可重複❹，以提升製程上之便利性及節省製 成本。 以上所述僅為本發明之較佳實施方式而已，並非用以 限定本發明之範圍’亦即’本發明事實上仍可做其他改 變’因此’舉凡熟習該項技術者在未脫離本發明所揭示之 精神與技術思想下所完成之—切等效修飾或改變仍應由 後述之申請專利範圍所涵蓋。 〜 【圖式簡單說明】 第1A至1C圖係為美國專利第號所揭示之 具散熱件之覆晶式半導體封裝件製法示意圖； 第2A至2C圖係為美國專利第6 444 498號所揭示之 具散熱件之覆晶式半導體封裝件製法示音圖. 110801 ( § 16 1364097 - 第3A至3G圖係為本發明之半導體封裝件製法的第一 . 實施例不意圖，以及 第4A至4E圖係為本發明之半導體封裝件製法的第二 貫施例不意圖。 【主要元件符號說明】 '11 基板 12 覆晶式羊導體晶片 13 散熱件 φ 120 導電凸塊 16 封裝膠體 21 基板 22 半導體晶片 "23 散熱件 230 介面層 26 封裝膠體 30 承載件 ® 300 開口 31 基板 32 覆晶式半導體晶片 320 導電凸塊 33 散熱件 34 膠片 35 模具 350 模穴 17 110801 封裝膠體 氣泡 鲜球 承載件 開口 基板 覆晶式半導體晶片 導電凸塊 散熱件 膠片 模具 模穴 封裝膠體 鲜·球 封裝膠體之投影長寬尺寸 半導體封裝件之預定長寬尺寸 18 110801 ( S )The chaos will be pushed to the side to form a bubble _ on the side, which should be noted that the bubble 306 forms a position outside the | Before the predetermined length and width of the W-position oblique conductor package is filled in, the resin may be first glued to the bottom of the resin, and then the above-mentioned molding process is performed: ", the electrical properties of the true package. And ensuring the semi-conductance=Ε图, performing the demolding process and removing the kick piece 34. As shown in the figure 3F, the flip-chip semiconductor 110801 (S) 12 1364097 is not disposed on the substrate 31. • There are a plurality of The opening 400' is characterized in that the carrier member 4 is made of a metal material such as copper (Cu), and the surface of the carrier member 4 is pre-plated with, for example, gold (An), nickel (Ni), chromium (Cr). And a metal clock layer (not shown) which is poorly adhered to the encapsulant. Meanwhile, a plurality of substrates 4 are provided for the flip-chip semiconductor wafer 42 to be connected through the conductive bumps 420 and electrically connected to the substrate 4 And a heat dissipating member 43 is disposed on the flip chip semiconductor wafer 42 to fit the substrate 41 carrying the wafer 42 and the heat sink 43 into the opening 400 of the carrier #40 and wins The sheet 44 covers the gap between the substrate 41 and the carrier 40, so that the gap does not penetrate the carrier The length and width of the substrate 41 are approximately equal to the predetermined length and width of the semiconductor package, and the length and width of the heat sink 43 are smaller than the length and width of the substrate 41. As shown in FIG. 4B, molding is performed. In the process, the carrier 40 is placed in the mold 45 so that the flip-chip semiconductor chip 42 and the heat sink 43 are accommodated in the corresponding cavity 4 ΐ ,, "if "t/v > Ββ • In the eighth socket 450, a package body 46° for covering the flip chip semiconductor wafer 42 and the heat sink 43 is formed on the mother opening 400, and similarly, when the package colloid 46 is formed, the cavity 45〇 The airborne teaching will be pushed to the side to form a bubble on the side, and the gas = outside the length and width dimensions of the semiconductor package, (10) 彳 (4) along the ^ cutting while 'removing the excess package The knee body and the bubble formed therein/, =4 (:11 is not 'planted on the lower surface of the substrate 41, a plurality of fresh balls are implanted to remove the encapsulating plastic cover 0801 covering the heat sink 43 by field cutting (15 1364097 For example, if the top of the money heating member 43 is exposed, the sealing body 46 is exposed. As shown in the figure 4D, the demoulding and film 44 are performed. In addition to the step, the 5 gal metal carrier 40 is pre-plated with a 黏 f 黏 黏 啕〃 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4〇, take out the substrate 41, the flip-chip V semi-self-guide 43 and the encapsulant 46 _ heat dissipation and the seal to be cut; t package early " separate the carrier as shown in Figure 4E 'cutting a step of manufacturing a semiconductor package having a predetermined length and width along the edge of the substrate μ. In this embodiment, the sealing unit disk 2 can be separated before the cutting step, so that the cutting step is not required. The carrier can be repeatedly twisted to improve the convenience of the process and save the cost. The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the present invention may in fact still make other changes, so that those skilled in the art can The equivalent modifications or changes made under the spirit and technical thought of the disclosure should be covered by the scope of the patent application described below. ~ [Simplified Schematic Description] Figures 1A to 1C are schematic diagrams of a method for fabricating a flip-chip semiconductor package having a heat sink disclosed in U.S. Patent No. 2A to 2C, which is disclosed in U.S. Patent No. 6,444,498. Photovoltaic diagram of a flip-chip semiconductor package having a heat sink. 110801 (§16 1364097 - Figures 3A to 3G are the first method of manufacturing a semiconductor package of the present invention. Embodiments are not intended, and 4A to 4E The drawings are not intended to be the second embodiment of the semiconductor package manufacturing method of the present invention. [Main component symbol description] '11 Substrate 12 Flip-chip type sheep conductor wafer 13 Heat sink φ 120 Conductive bump 16 Package colloid 21 Substrate 22 Semiconductor Wafer"23 heat sink 230 interface layer 26 encapsulant 30 carrier® 300 opening 31 substrate 32 flip-chip semiconductor wafer 320 conductive bump 33 heat sink 34 film 35 mold 350 cavity 17 110801 package colloid bubble fresh ball carrier opening Substrate flip-chip semiconductor wafer conductive bump heat sink film mold cavity encapsulation colloid fresh · ball encapsulation colloid projection length and width size semiconductor package pre Length and width dimensions 18 110801 (S)