1362094 九、發明說明： 【發明所屬之技術領域】 +發明係有關於 種半導體元件之承載基板與其應 =^別是有關於可提升半導體元衫位精度之承載基板 興具應用。 【先前技術】 。現今的電子玉業中’光電半導^件已成為—般電子 產。《必備之基本元件’卩發光：極體（Light Emi出叫 D1〇de;LED)為例，發光二極體具有工作電壓低耗電量小， 發光效率高，反應時間短，％色純，結構牢固抗衝擊， 耐振動，性能穩定可靠’重量輕，體積小及成本低等特點。 隨著技術的進步，發光二極體可展現的亮度等級越來越 高，其應用領域也越來越歧，例如：大面積圖文顯示全 彩屏，狀態指示、標該照明、信號顯示、液晶顯示器的背 光源或車内照明。 習知的發光二極體封裝結構係以金屬導電支架（Lead Frame)配合塑料射出成形方式製作出封裝基座。導電支架 係用以電性連接發光二極體晶片 <電極。封裝基座係以射 出成形方式形成，藉以使封裝材料包覆及固定住導電支 架。封裝基座内形成一凹口區域用以放置發光二極體晶 片。在發光二極體晶片置入封裝基座内後，接著，填入一 透明封裝材料（例如環氧樹脂）於封裝基座内，並結合光學透 鏡於封裝基座上，以提高發光效率。在發光二極體完成封 裝後，可利用表面黏著技術（Surface Mount Technology; 5 1362094 , SMT)將發光二極體之正負極焊合於基板上形成電性通 \ 路，以形成發光二極體模組，其中基板通常為印刷電路板 (Printed Circuit Board ; PCB)。 . 請參照第1A圖和第1B圖，第1Λ圖係繪示依照習知 技術一種發光二極體焊合於基板的側視示意圖，第圖係 繪示依照習知技術之焊墊的俯視示意圖。一般當發光二極 體910焊合於基板920時，基板920設有焊墊921，而發光 二極體910的電極接腳91丨係藉由焊錫9〇1來焊接於焊墊 • 921上’通常基板920的焊塾921係呈矩形，且其面積通常 需大於電極接腳911與焊墊921的實際接觸面積3，藉以預 留熔融焊錫901的流動空間。然而極接腳91丄择技 於焊墊921上時， 二極體910容易發生在焊墊921上浮動的情形，進而導致 發光二極體91〇在焊接後具有偏移、旋轉、前傾、後赵或 左右洋立等定位問題，嚴重地影響組裝精度。 # 【發明内容】 因此，本發明之一方面係在於提供一種半導體元件的 承載基板及其應用，藉以在進行焊接時限制半導體元件的 移動^^並避免半導體元件在焊塾上的浮動情形，因而 • 可減少定位偏差問題。 _ 1據本發a月之實施例，此承載基板係用以承載半導體 \ 〃中承载基板至少包含有基板主體和焊墊，焊墊係 形^於基板主體的一側表面上，其中焊塾在一方向上具有 第寬度和第—寬度，第一寬度係大於第二寬度’且谭塾 i^r-實際接合區域，用以直接承載半導體元件， 、不接5區域在此方向上的寬度係實質接近於第二寬度。 又’根據本發明之實施例，此半導體元件模組至少包 =少：半！體元件和承載基板。承載基板係用以承载 焊墊：中承載基板至少包含有基板主體和焊墊， 上=成=板主體的一側表面上，其中焊塾在一方向 且焊塾至少寬度’第一寬度係大於第二寬度， 元件，二直接承載半導體 寬度。 域在此方向上的寬度係實質接近於第 發光:極=發明之實施例，上述半導體元件模組係-=本發明之半導體元件的承龜板及其應用可在途 焊㈣::=::r:r 一 *㈣性與 m 于疋位半導體凡件於承載基板的焊墊上， 因而可大幅地提升半導體元件的μ準確度。 【實施方式】 為讓本發明之上述和其他目的、特徵、優點 ::更::：易懂’本說明書將特舉出一系列實加 =Γ主意的是’此些實施例只是用以說明本發明之 貫施方式’而非用以限定本發明。 體元，其緣示依照本發明第-實施例之半導 載某板〔0(W:、基板上時的剖面示意圖。本實施例之薄 G係用以承載至少—半導體元件·，例如可選自 由雙極性電晶體卿）、金氧半電晶體（M〇s) :電⑽s)、高功率電晶體'異質接面電晶體⑽: 及尚電子移動率電晶體（HEMT)所組成之n或 電兀件，例如可選自於由發光二極體、雷射二 ‘ 能電池、以及光檢測玆所紐# + 體、太陽 乂及先檢測益所組成之一族群，藉以形成 Μ模組（例如發光二極體模組）。其中此光電元件。在另一 些實施例中，半導體元件亦可為積體電路晶片。1362094 IX. Description of the invention: [Technical field to which the invention pertains] + The invention relates to a carrier substrate for a semiconductor component, and a carrier substrate for which the accuracy of the semiconductor device can be improved. [Prior Art]. In today's electronic jade industry, the photoelectric photoconductor has become a general electronic product. "Basic essential components" 卩 illuminating: polar body (Light Emi called D1 〇 de; LED) as an example, the light-emitting diode has a low operating voltage, low power consumption, high luminous efficiency, short reaction time, and pure color. The structure is firm and impact resistant, vibration resistant, stable and reliable. 'Light weight, small size and low cost. With the advancement of technology, the brightness level of LEDs can be displayed more and more, and its application fields are becoming more and more different. For example, large-area graphic display full color screen, status indication, standard illumination, signal display, LCD The backlight of the display or the interior lighting. The conventional LED package structure is formed by a metal conductive bracket (Lead Frame) and a plastic injection molding method. The conductive support is used to electrically connect the light-emitting diode wafer <electrode. The package base is formed by injection molding so that the package material covers and holds the conductive support. A recessed region is formed in the package base for placing the LED wafer. After the LED chip is placed in the package base, a transparent encapsulating material (such as epoxy) is then filled in the package base and combined with the optical lens on the package base to improve luminous efficiency. After the LED is packaged, the surface mount technology (Surface Mount Technology; 5 1362094, SMT) can be used to solder the positive and negative electrodes of the LED to the substrate to form an electrical path to form a light-emitting diode. The module, wherein the substrate is usually a printed circuit board (PCB). Referring to FIG. 1A and FIG. 1B , FIG. 1 is a side view showing a light-emitting diode soldered to a substrate according to a prior art, and FIG. 1 is a schematic top view of a solder pad according to a conventional technique. . Generally, when the LED 910 is soldered to the substrate 920, the substrate 920 is provided with a pad 921, and the electrode pins 91 of the LED 910 are soldered to the pad 921 by solder 9〇1. Generally, the pad 921 of the substrate 920 has a rectangular shape, and its area generally needs to be larger than the actual contact area 3 of the electrode pin 911 and the pad 921, thereby preserving the flow space of the molten solder 901. However, when the pin 91 is selected on the pad 921, the diode 910 is likely to float on the pad 921, which causes the LED 91 to be offset, rotated, and tilted after soldering. Positioning problems such as post-Zhao or left-right yangli seriously affect assembly accuracy. [Invention] Therefore, an aspect of the present invention is to provide a carrier substrate of a semiconductor element and an application thereof, thereby limiting the movement of the semiconductor element during soldering and avoiding floating of the semiconductor element on the solder bump, thereby • Reduces positioning deviation problems. According to the embodiment of the present invention, the carrier substrate is used to carry the semiconductor. The carrier substrate includes at least a substrate body and a pad, and the pad is formed on one side surface of the substrate body. Having a first width and a first width in one direction, the first width is greater than the second width 'and the actual joint area is used to directly carry the semiconductor component, and the width of the 5 region in this direction is not Substantially close to the second width. Further, according to an embodiment of the present invention, the semiconductor component module is at least packaged with less: half! Body element and carrier substrate. The carrier substrate is used to carry the bonding pad: the middle carrier substrate comprises at least the substrate body and the bonding pad, and the upper surface is formed on one side surface of the board body, wherein the soldering iron is in one direction and the soldering bead has at least a width 'the first width is greater than The second width, the component, two directly carries the semiconductor width. The width of the domain in this direction is substantially close to the first luminescence: pole = embodiment of the invention, the above-mentioned semiconductor component module is - the carrier of the semiconductor component of the invention and its application can be welded in the way (4)::=::r :r a * (four) and m in the semiconductor semiconductor on the pad of the carrier substrate, so that the μ accuracy of the semiconductor device can be greatly improved. [Embodiment] The above and other objects, features and advantages of the present invention are as follows: more::: understandable 'This specification will cite a series of actual additions = the idea is that 'these embodiments are only for illustration The present invention is not intended to limit the invention. A voxel, the edge of which is a semi-conductive substrate in accordance with the first embodiment of the present invention (W: a schematic cross-sectional view on the substrate. The thin G of the present embodiment is used to carry at least a semiconductor component, for example, Free bipolar transistor crystal, gold oxide semi-transistor (M〇s): electric (10) s), high-power transistor 'heterojunction transistor (10): monk electron mobility transistor (HEMT) Or an electric component, for example, may be selected from a group consisting of a light-emitting diode, a laser two-energy battery, and a light-detecting device, a solar ray, and a first detection benefit, thereby forming a Μ module (for example, a light-emitting diode module). Among them, this photoelectric element. In other embodiments, the semiconductor component can also be an integrated circuit die.
如第2圖所示，在本實施例中半導體元件扇可預 先進行封裝，再結合（焊接）於承載基板1〇〇上，亦即半導體 7L件200可預先形成半導體元件封襄結構（例如發光二極體 封裝結構），再結合於承載基板刚上。當半導體元件2〇〇 形成+導體元件封裝結構時’半導體元件晶片21〇(例如發 光二極體晶片)可設置於承載器22〇上，承載器22〇例如為 導電支架（Lead Frame)，且承載n 22〇可藉由—體成型的方 式（例如射出成型或共燒成型）來結合一座體23〇，而形成封As shown in FIG. 2, in the present embodiment, the semiconductor element fan can be packaged in advance and then bonded (welded) to the carrier substrate 1 , that is, the semiconductor 7L device 200 can be pre-formed into a semiconductor device package structure (for example, light emission). The diode package structure) is then bonded to the carrier substrate just above. When the semiconductor device 2 is formed into a +conductor device package structure, the semiconductor device chip 21 (for example, a light-emitting diode wafer) may be disposed on the carrier 22, and the carrier 22 is, for example, a conductive frame (Lead Frame), and Carrying n 22 〇 can be combined by body molding (such as injection molding or co-firing) to form a body 23 〇, forming a seal
裝基座’並外露出二個電極接腳24〇，以提供電性連接路徑。 如第2圖所不’本實施例之承載基板1〇〇例如為印刷 電路板（Printed Circuit board ; pCB)或軟性印刷電路板 (Flexible printed Circuiis ; Fpc)，以提供半導體元件 2⑼ 可電性連接之電路（未繪示）。承載基板l〇〇至少包含有基板 主體110、焊墊120及防焊層13〇。基板主體11〇的材質係 由電性絕緣材料所製成，例如為：BT(Bismaleimide Triazine) 熱固性樹脂材料、環氧樹脂、陶竞或有機玻璃纖維，其中 基板主體110可設有貫孔（未繪示），用以埋設被動元件。再 者，基板主體11〇亦可為複合結構，其中此複合結構可由 1362094 導電材料與電性絕緣材料所組成，例如具有金屬核心的印 =路板（M咖Core pcB ; McpCB)，且此導電材料係選自 ;金屬材料、陶莞材料'半導體材料及上述材料之任意 ^合所組狀—族群。焊墊120係形成於基板主體11〇 -表面上’藉以使半導體元件2〇〇的電極(未繪示)或電極接 腳240可焊接結合於承載基板100的焊塾120上，其中當 焊接結合時可藉由料1G1來作為接著材料，例如為錯錫 (Pb-Sn)合金、錫銀合金、錫銅合金或其他無鉛焊料。焊墊 120係以金屬材料（例如銅）所圖案化形成，其中焊墊工汕可 具有表面處理，例如：表面塗佈有機保焊劑（〇rganic Solderability Preservatives)或表面電鍍鎳金，以避免焊墊 120發生表面氧化情形，防焊層13〇係形成於基板主體 的一側表面上，且形成於焊墊12〇之外，用以避免在進行 知接結合時所使用之焊料1 01可能因高溫而任意流動，導 致短路情形。防焊層130的材料例如為綠漆（s〇ldermask〇r Solder Resist) ’ 其可利用網印（screen printing)、簾幕塗佈 (Curtain Coating)、喷霧塗佈（Spray c〇ating)、靜電喷塗 (Electrostatic Spraying)或滾輪塗佈（R〇Uer c〇ating)等方式 來形成於基板主體110上。由於防焊層13〇係形成於焊墊 120之外的區域，因此，當進行焊接時，熔融狀態的焊料 101僅能在焊墊120的區域内流動。 值得注意的是，在另一些實施例中，本實施例的半導 體元件200亦可在封裝前直接結合於承載基板1〇〇上，此 時，半導體元件200的二電極可接合於承載基板1〇〇的焊 墊120;或者，半導體元件200的一電極係直接接合於焊墊 1362094 :而半導體元件2°°的另-電極係藉由打線方式來連接 墊的=照：3圖’其繪示依照本發明之第-實施例之焊 第圖:t實施例的焊墊120在-方向上具有第 焊塾m至少包含有於第二寬度t’且 122。眘軟位人 貝牙'接&區域121及焊料流動區域 極式。雷：姓s區域121係用以直接承載半導體元件200電 m上的區域，”實件200實際接合於焊墊 /、中貫際接合區域121在平行於第一寬度τ 第：寬度t之方向上的寬度係實質接近於第二寬度 塾可例如在本㈣例中，焊 t十面、.·"構，因而在實際接合區域121 Π料流動區域122之外自然地具有-寬度縮減區域b，亦 p在-方向上縮減焊墊的第一寬度τ至第二寬度t。且至少 =實際接合區域121係位於由第二寬度t所構成的輝 塾區域内’而受到第二寬度t的限制，使得半導體元件· 之電極與浑墊的接合不致偏出第二寬度t之外，亦即不致 偏-出”寒位限制部123之外。 焊料流動區域122係形成於實際接合區域i2i的至少 -側’藉以允許焊，料101在溶融狀態時於此焊料流動區域 122内流動’其中焊料流動區域122可為任意形狀，以提供 :餘之熔融焊_ 1〇1的流動空間，以增強焊接強度。於本 實施例中’疋位限制部123例如係與焊塾之第二寬卢〖 鄰接並且延著垂直第二寬度t之方向延伸，以限制溶二 錫122的机動在第二寬度t的範圍之内進而可限制半導 1362094 體元件200在焊墊12〇 2〇〇 ^ ^ ^ 上的位移夏’因而避免半導體元件 200發生在焊墊m切動偏移的情形 題。值得洼音的a _ 年双疋伹侷差問 w疋’本實施例的定位限制部123可藉由焊 … 外圍形狀所定義，亦即藉由焊塾120的外圍 制溶融谭錫101的流動，並同時藉由焊錫流動區 域122來提供多餘之炼融焊錫ι〇ι的流動空間。The base is mounted and two electrode pins 24 are exposed to provide an electrical connection path. As shown in FIG. 2, the carrier substrate 1 of the present embodiment is, for example, a printed circuit board (PCB) or a flexible printed circuit board (Fpc) to provide electrical connection of the semiconductor component 2 (9). Circuit (not shown). The carrier substrate 10 includes at least a substrate body 110, a pad 120, and a solder resist layer 13A. The material of the substrate main body 11 is made of an electrically insulating material, for example, BT (Bismaleimide Triazine) thermosetting resin material, epoxy resin, Tao Jing or plexiglass fiber, wherein the substrate body 110 can be provided with a through hole (not Draw) to embed passive components. Furthermore, the substrate body 11 can also be a composite structure, wherein the composite structure can be composed of a 1362094 conductive material and an electrically insulating material, such as a printed circuit board having a metal core (M coffee Core PCB; McpCB), and this conductive The material is selected from the group consisting of metal materials, ceramic materials, semiconductor materials, and any of the above-mentioned materials. The solder pad 120 is formed on the surface of the substrate body 11 so that electrodes (not shown) or electrode pins 240 of the semiconductor device 2 can be solder bonded to the solder pads 120 of the carrier substrate 100, wherein when solder bonding The material 1G1 can be used as a bonding material, such as a stud tin (Pb-Sn) alloy, a tin-silver alloy, a tin-copper alloy or other lead-free solder. The pad 120 is patterned by a metal material such as copper, wherein the pad process may have a surface treatment such as: surface coating of 保rganic Solderability Preservatives or surface plating of nickel gold to avoid solder pads 120 occurs in the case of surface oxidation, the solder resist layer 13 is formed on one side surface of the substrate main body, and is formed outside the bonding pad 12〇, in order to avoid the use of the solder 101 used in the known bonding may be due to high temperature Any flow, resulting in a short circuit situation. The material of the solder resist layer 130 is, for example, green paint (s〇ldermask〇r Solder Resist), which can utilize screen printing, Curtain Coating, spray coating, and spray coating. Electrostatic spraying or roller coating (R 〇 er 〇 。) is formed on the substrate body 110. Since the solder resist layer 13 is formed in a region other than the pad 120, the solder 101 in a molten state can flow only in the region of the pad 120 when soldering is performed. It should be noted that in other embodiments, the semiconductor device 200 of the present embodiment may be directly bonded to the carrier substrate 1 before being packaged. In this case, the two electrodes of the semiconductor device 200 may be bonded to the carrier substrate 1 . a solder pad 120; or, an electrode of the semiconductor device 200 is directly bonded to the pad 1362094: and the other electrode of the semiconductor device 2° is connected by a wire bonding method. The welding pad according to the first embodiment of the present invention: the pad 120 of the t embodiment has a second bead m in the - direction including at least the second width t' and 122. Be careful with the people. The teeth are connected to the area 121 and the solder flow area. Ray: The surname s region 121 is used to directly carry the region on the semiconductor element 200 m, "the real member 200 is actually bonded to the pad/, and the intermediate intervening junction region 121 is parallel to the first width τ: width t The width is substantially close to the second width. For example, in the example (4), the weld is ten-sided, and the structure naturally has a width-reducing region b outside the actual joint region 121. And p reduces the first width τ of the pad to the second width t in the − direction. And at least = the actual bonding region 121 is located in the illuminating region formed by the second width t and is subjected to the second width t The restriction is such that the bonding of the electrode of the semiconductor element and the pad does not deviate from the second width t, that is, does not deviate from the "cold stop portion 123". The solder flow region 122 is formed on at least the side of the actual joint region i2i to allow welding, and the material 101 flows in the solder flow region 122 when in the molten state. The solder flow region 122 may be of any shape to provide: Weld the flow space of _ 1〇1 to enhance the weld strength. In the present embodiment, the "clamping restriction portion 123" is adjacent to the second width of the solder joint and extends in the direction perpendicular to the second width t to limit the maneuverability of the dissolving tin 122 in the range of the second width t. In turn, the displacement of the semiconductor component 200 on the pad 12〇2〇〇^^^ can be limited, thereby avoiding the problem that the semiconductor component 200 is displaced in the pad m. A _ year 疋伹 差 差 洼 洼 洼 疋 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本At the same time, the flow area of the excess smelting solder ι〇ι is provided by the solder flow area 122.
(t/τ:二貫施例中’第二寬度1相較於第—寬度T的比例 t T)例如係小於等於0.8,例如當焊整12〇之第一寬度丁為 〇.85mm時，第二寬度t可為〇 5mm。 再者，焊墊120之面積a(亦即實際接合區域i2i和谭 錫流動區域122之面積總和）相較於實際接合區域i2i之面 積a的比例（a / a)較佳係實質介於1」與2 $之間。例如當實 際接合區❺⑵之面帛&為〇.33_2時，焊塾m之面:a 可為 0.65mm2。 因此’當半導體元件200焊接接合於承載基板1〇〇上 時’承載基板10G之料！2G可提供多餘之溶融焊錫ι〇ι 的流動空間’以增強焊接強度’並可同時限制半導體元件 細在炼融浑们01上浮動偏移的情形，因而可精確地定位 半導體元件200於承載基板100上，以減少定位偏差的情 形0 請參照第4圖，其繪示依照本發明之第二實施例之焊 墊的俯視示意圖。以下僅就本實施例與第—實施例之相異 處進行說明，關於相似處在此不再贅述。相較於第一實施 例，第二實施例之焊墊i 2 0 a可例如為c形平面結構，並^ -方向上具有第一寬度T和第二寬度t’第—寬度τ係大於 11(t/τ: in the second embodiment, the ratio of the second width 1 to the first width T t is, for example, less than or equal to 0.8, for example, when the first width of the 12 焊 is 〇.85 mm, The second width t can be 〇5 mm. Furthermore, the ratio a (a / a) of the area a of the pad 120 (that is, the sum of the areas of the actual joint area i2i and the tan-tin flow area 122) to the area a of the actual joint area i2i is preferably substantially 1 Between 2 and 2. For example, when the face amp& of the actual joint zone 2(2) is 〇.33_2, the face of the weld 塾m: a can be 0.65 mm2. Therefore, when the semiconductor element 200 is solder bonded to the carrier substrate 1 ’, the material of the substrate 10G is carried! 2G can provide a redundant flow space of the molten solder ι〇ι to enhance the soldering strength and can simultaneously limit the floating displacement of the semiconductor component finely on the smelting we01, so that the semiconductor component 200 can be accurately positioned on the carrier substrate. 100. In order to reduce the positioning deviation, please refer to FIG. 4, which is a top plan view of the bonding pad according to the second embodiment of the present invention. In the following, only the differences between the embodiment and the first embodiment will be described, and the similarities will not be described herein. Compared with the first embodiment, the pad i 2 0 a of the second embodiment may be, for example, a c-shaped planar structure having a first width T and a second width t' in the direction - the width τ is greater than 11