200929470 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體元件之承載基板與其應 用，特別是有關於可提升半導體元件定位精度之承載基板 與其應用。 【先前技術】 現今的電子工業中，光電半導體元件已成為一般電子 產品必備之基本元件，以發光二極體（Ught_EmittingBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier substrate for a semiconductor device and an application thereof, and more particularly to a carrier substrate and an application thereof for improving the positioning accuracy of a semiconductor device. [Prior Art] In the current electronics industry, optoelectronic semiconductor components have become essential components for general electronic products, with LEDs (Ught_Emitting)
Diode; LED)為例，發光二極體具有工作電壓低，耗電量小， 發光效率尚’反應時間短，光色純，結構牢固，抗衝擊， 耐振動，性能穩定可靠，重量輕，體積小及成本低等特點。 隨著技術的進步，發光二極體可展現的亮度等級越來越 鬲，其應用領域也越來越廣泛，例如：大面積圖文顯示全 彩屏，狀態指示、標誌照明、信號顯示 '液晶顯示器的背 光源或車内照明。 習知的發光二極體封裝結構係以金屬導電支架（Lead Frame)配合塑料射出成形方式製作出封裝基座。導電支架 係用以電性連接發光二極體晶片之電極。封裝基座係以射 出成形方式形成，藉以使封裝材料包覆及固定住導電支 架。封裝基座内形成一凹口區域用以放置發光二極體晶 片。在發光二極體晶片置入封裝基座内後，接著，填入一 透明封裝材料（例如環氧樹脂）於封裝基座内，並結合光學透 鏡於封裝基座上，以提高發光效率。在發光二極體完成封 裝後，可利用表面黏著技術（Surface M〇lmt Techn〇1〇gy，· 5 200929470 r SMT)將發光一極體之正負極焊合於基板上形成電性通 • 路，以形成發光一極體模組’其中基板通常為印刷電路板 (Printed Circuit Board ; PCB)。 s青參知、第1A圖和第1B圖，第1 a圖係繪示依照習知 技術一種發光一極體焊合於基板的側視示意圖，第iB圖係 繪示依照習知技術之焊墊的俯視示意圖。一般當發光二極 體910焊合於基板920時，基板920設有焊墊921，而發光 二極體910的電極接腳911係藉由焊錫9〇1來焊接於焊墊 籲 921上，通常基板920的焊墊921係呈矩形，且其面積通常 需大於電極接腳911與焊墊921的實際接觸面積a，藉以預 留熔融焊錫901的流動空間。然而，當電極接腳911焊接 於焊墊921上時，由於焊錫9〇1係呈熔融狀態，因而發光 二極體910容易發生在焊墊921上浮動的情形，進而導致 發光一極體910在焊接後具有偏移、旋轉、前傾、後翹或 左右浮立等定位問題，嚴重地影響組裝精度。 ❹ 【發明内容] 因此，本發明之一方面係在於提供一種半導體元件的 承载基板及其應用，藉以在進行烊接時限制半導體元件的 移動空間’並避免半導體元件在焊墊上的浮動情形，因而 可減少定位偏差問題。 _根據本發明之實施例，此承載基板係用以承载半導體 兀件，其中承載基板至少包含有基板主體和輝墊，焊 S成於基板主體的—側表面上，其中焊墊在-方向上且有 第一寬度和第二官由域 _ . ^ ^ — 又’第一寬度係大於第二寬度，且谭墊 6 200929470 ^包含有—實際接合區域，用以直接承载半導體元件， '際接合區域在此方向上的寬度係實質接近於第二寬产。 ^根據本發明之實施例，此半導體㈣模組至=包 半導二ΓΓ元件和承載基板。承載基板係用以承載 焊執/、’其中承載基板至少包含有基板主體和焊塾， 糸形成於基板主體的一側表面上，其 上，有第-寬度和第二寬度，第—寬度係大於第二^ ❹Diode; LED) As an example, the LED has low operating voltage, low power consumption, low luminous efficiency, simple reaction time, pure light color, firm structure, impact resistance, vibration resistance, stable and reliable performance, light weight and volume. Small and low cost. With the advancement of technology, the brightness level of the LED can be more and more ambiguous, and its application fields are more and more extensive, for example: large-area graphic display full color screen, status indication, logo illumination, signal display 'liquid crystal display Backlight or interior lighting. The conventional LED package structure is formed by a metal conductive bracket (Lead Frame) and a plastic injection molding method. The conductive support is used to electrically connect the electrodes of the LED chip. The package base is formed by injection molding so that the package material covers and holds the conductive support. A recessed region is formed in the package base for placing the LED wafer. After the LED chip is placed in the package base, a transparent encapsulating material (such as epoxy) is then filled in the package base and combined with the optical lens on the package base to improve luminous efficiency. After the light-emitting diode is packaged, the surface and the adhesion technology (Surface M〇lmt Techn〇1〇gy,· 5 200929470 r SMT) can be used to solder the positive and negative electrodes of the light-emitting body to the substrate to form an electrical path. To form a light-emitting diode module, wherein the substrate is usually a printed circuit board (PCB). s Qingshen, 1A and 1B, the first diagram shows a side view of a light-emitting body welded to a substrate according to the prior art, and the iB is a solder according to the prior art. A schematic view of the mat. Generally, when the LED 910 is soldered to the substrate 920, the substrate 920 is provided with a pad 921, and the electrode pins 911 of the LED 910 are soldered to the pad 921 by solder 9〇1, usually The pad 921 of the substrate 920 has a rectangular shape, and its area generally needs to be larger than the actual contact area a of the electrode pin 911 and the pad 921, thereby preserving the flow space of the molten solder 901. However, when the electrode pin 911 is soldered to the pad 921, since the solder 9〇1 is in a molten state, the light emitting diode 910 is likely to float on the pad 921, thereby causing the light emitting body 910 to be After welding, there are positioning problems such as offset, rotation, forward tilt, back tilt or left and right floating, which seriously affect assembly accuracy. SUMMARY OF THE INVENTION Accordingly, it is an aspect of the present invention to provide a carrier substrate for a semiconductor device and an application thereof, thereby limiting a moving space of a semiconductor device during splicing and avoiding floating of the semiconductor device on the pad, thereby Can reduce the positioning deviation problem. According to an embodiment of the present invention, the carrier substrate is used to carry a semiconductor device, wherein the carrier substrate includes at least a substrate body and a glow pad, and the solder S is formed on a side surface of the substrate body, wherein the pad is in the − direction and There is a first width and a second official by the domain _ . ^ ^ - and 'the first width is greater than the second width, and the Tan pad 6 200929470 ^ contains the actual joint area for directly carrying the semiconductor component, the 'intersection area The width in this direction is substantially close to the second wide yield. According to an embodiment of the invention, the semiconductor (four) module to the package semi-conductive diode element and the carrier substrate. The carrier substrate is used to carry the soldering/, wherein the carrier substrate comprises at least the substrate body and the soldering pad, and the germanium is formed on one side surface of the substrate body, and has a first width and a second width, the first width Greater than the second ^ ❹
且焊墊至少包含有—實際接合區域，用以直接承載半導體 =件’實際接合區域在此方向上的寬度係實f接近於第二 見度。 又’根據本發明之實施例，上述半導體元件模組係一 發光二極體模組。 因此本發明之半導體元件的承載基板及其應用可在進 行谭接時提供多餘之熔融焊錫的流動空間以加強㈣㈣ 焊接強度’制時定位半導體元件於承載基㈣焊塾上， 因而可大幅地提升半導體元件的定位準確度。 【實施方式】 為讓本發明之上述和其他目的'特徵、優點與實施例 能更明顯易懂，本說明書將特舉出一系列實施例來加以說 月但值得注意的是，此些實施例只是用以說明本發明之 實施方式，而非用以限定本發明。 請參照第2圖，其繪示依照本發明第一實施例之半導 體元件設置於承載基板上時的剖面示意圖。本實施例之承 载基板100係用以承載至少一半導體元件2〇〇，例如可選自 200929470And the pad contains at least the actual joint area for directly carrying the semiconductor = piece 'the actual joint area in this direction is the width f close to the second view. Further, according to an embodiment of the present invention, the semiconductor element module is a light emitting diode module. Therefore, the carrier substrate of the semiconductor device of the present invention and the application thereof can provide excess molten solder flow space during the bonding to strengthen (4) (4) soldering strength, and position the semiconductor component on the carrier (four) soldering pad, thereby greatly improving Positioning accuracy of semiconductor components. [Embodiment] The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. It is intended to illustrate the embodiments of the invention and not to limit the invention. Referring to Figure 2, there is shown a cross-sectional view of a semiconductor component according to a first embodiment of the present invention when it is disposed on a carrier substrate. The carrier substrate 100 of the present embodiment is used to carry at least one semiconductor component 2, for example, may be selected from 200929470
由雙極性U體⑻τ)、錢半電㈣（M :電⑽)、高功率電晶體、異質接面電晶二 及面電子移動率電晶體（HEMT)所㈣之—族群、或 電-件’例如可選自於由發光二極體、雷射二極體、太陽 能電池、以及光檢測輯組成之_族群，藉以形成半導體 疋件模組（例如發光二極體模組）。其中此光電元件。在另— 些實施例中，半導體元件2〇〇亦可為積體電路晶片。By bipolar U body (8) τ), money semi-electric (four) (M: electricity (10)), high-power transistor, heterojunction electro-crystal two and surface electron mobility transistor (HEMT) (four) - group, or electric - For example, it may be selected from a group consisting of a light-emitting diode, a laser diode, a solar cell, and a photodetection to form a semiconductor component module (for example, a light-emitting diode module). Among them, this photoelectric element. In other embodiments, the semiconductor component 2 can also be an integrated circuit chip.
❹ 如第2圖所示，在本實施例中，半導體元件勘可預 先進行封裝，再結合（焊接）於承載基板丨⑻上，亦即半導體 儿件2G0可預絲成半導體元件封裝結構（例如發光二極體 封裳結構）’再結合於承載基板刚上。當半導體㈣2〇〇 形成半導體元件封裝結構時，半導體元件晶片2ig(例如發 光二極體晶片）可設置於承載器22〇上，承載器22〇例如為 導電支架（Lead Frame)，且承制22〇可藉由一體成型的方 式（例如射出成型或共燒成型）來結合一座體23〇，而形成封 裝基座’並外露出二個電極接腳24〇，以提供電性連接路徑。 如第2圖所不，本實施例之承載基板1〇〇例如為印刷 電路板（Printed circuit board ; pcB)或軟性印刷電路板 (Flexible Printed Circuhs ; Fpc)，以提供半導體元件· 可電性連接之電路（未繪示）。承載基板1〇〇至少包含有基板 主體110焊塾120及防焊層130。基板主體11〇的材質係 由電性絕緣材料所製成，例如為：BT(BiSmaleimide Tdazine) 熱固性樹脂材料、環氧樹脂、m有機玻璃纖維，其中 土板主體11 〇可设有貫孔（未繪示），用以埋設被動元件。再 者’基板主體110亦可為複合結構，其中此複合結構可由 8 200929470 導電材料與電性絕緣材料所組成’例如具有金屬核心的印 刷電路板（Metal C〇re PCB ; MCPCB)，且此導電材料係選自 於由金屬材料、陶曼材料、半導體材料及上述材料之任意 組合所組成之一族群。焊墊12〇係形成於基板主體ιι〇的 一表面上，藉以使半導體元件2〇〇的電極（未繪示）或電極接 腳240可焊接結合於承載基板1〇〇的焊墊12〇上其中當 焊接結合時可藉由焊料1G1來作為接著材料，例如為絡锡 (Pb-Sn)合金、錫銀合金、錫銅合金或其他無鉛焊料。焊墊 120係以金屬材料（例如銅）所圖案化形成，其中焊墊^加可 具有表面處理，例如：表面塗佈有機保焊劑（Organs Solderability preservatives)或表面電鍍鎳金以避免焊墊 120發生表面氧化情形。防焊層13〇係形成於基板主體ιι〇 的-側表面上，且形成於焊# 12G之外，用以避免在進行 焊接結合時所使用之焊肖1Q1可能因高溫而任意流動，導 致短路情形。防焊層130的材料例如為綠漆(s〇lder刪 Solder Resist) ’ 其可利用網印（Screen printing)、簾幕塗佈 (Curtain Coating)、喷霧塗佈（Spray c〇ating)、靜電噴塗 (Electrostatic Spraying)或滾輪塗佈（R〇ller c〇ating)等方式 來形成於基板主體110上。由於防焊I 13〇係形成於焊墊 120之外的區域，因此，當進行谭接時，炫融狀態的谭料 1 〇 1僅能在谭墊120的區域内流動。 值得注意的是，在另一些實施例中，本實施例的半導 體元件200亦可在封裝前直接結合於承載基板1〇〇上，此 時’半導體元件200的二電極可接合於承載基板1〇〇的焊 墊120’或者’半導體元件·的—電極係直接接合於谭塾 9 200929470 1 二’而半導體元件200的另-電極係藉由打線方式來連接 電路。 ❹ 請參照第3圖，其繪示依照本發明之第一實施例之焊 墊的俯視示意圖。本實施例的焊塾12〇在一方向上具有第 2度τ和第二寬度t，第—寬度了係大於第二寬度t，且 丄20至少包含有實際接合㈣ΐ2ι及焊料流動區域 實際接合區域121 _以直接承載半導體元件電 極或電極接腳24〇,亦即為半導體元件2⑽實際接合於焊塾 120上^域’其中實際接合區域121在平行料一寬度τ 和第二寬度t之方向上的寬度係實質接近於第二寬度卜較 佳係略小於第二寬度t。如第3圖所示，在本實施例中，焊 墊120可例如為L形平面結構，因而在實際接合區域⑵ 和焊料流動區域122之外自然地具有一寬度縮減區域卜亦 即在-方向上縮減焊墊的第一寬度T至第二寬度卜且至少 部份之實際接合區4 121係位於由第二寬度t所構成的焊 墊區域内，而受到第二寬度t的限制，使得半導體元件· 之電極與焊墊的接合不致偏出第H t之外，亦即不致 偏出定位限制部123之外。 焊料流動區域122係形成於實際接合區域121的至少 一側’藉以允許焊们G1纽融狀態時於此谭料流動區域 122内流動’其中焊料流動區域122可為任意形狀，以提供 多餘之熔融料1G1的流動空間，以增強焊接強度。於本 實施例中，定位限制部123例如係與焊墊12〇之第二声 鄰接並且延著垂直第二寬度t之方向延伸，以限制熔、:焊 錫122的流動在第二寬度t的範圍之内，進而可限制半導 200929470 體…〇在焊塾120上的位移量 2°°發生在谭上浮動偏移的情形， 題。值得注意的是，太寺疋位偏μ問 實 < 的疋位限制部123可藉由焊 種來二圍形狀所定義’亦即藉由焊墊120的外圍 ===熔融焊錫1G1的流動，朗時藉由焊錫流動區 域122^供多餘之_焊錫ΐ()ι的流動空間。 2實施例中，第二寬度t相較於第—寬度了的比例 ❹As shown in FIG. 2, in the present embodiment, the semiconductor component can be packaged in advance and then bonded (welded) to the carrier substrate (8), that is, the semiconductor device 2G0 can be pre-wired into a semiconductor device package structure (for example, The light-emitting diode package structure) is re-bonded to the carrier substrate. When the semiconductor (4) 2 turns into a semiconductor device package structure, the semiconductor device wafer 2ig (for example, a light-emitting diode wafer) may be disposed on the carrier 22, and the carrier 22 is, for example, a conductive frame, and the carrier 22 The crucible can be joined to the body by means of an integral molding method (for example, injection molding or co-firing molding) to form a package base 'and to expose two electrode pins 24 to provide an electrical connection path. As shown in FIG. 2, the carrier substrate 1 of the present embodiment is, for example, a printed circuit board (PCBB) or a flexible printed circuit board (Flexible Printed Circuhs; Fpc) to provide a semiconductor component and an electrical connection. Circuit (not shown). The carrier substrate 1 includes at least a substrate body 110 solder bump 120 and a solder resist layer 130. The material of the substrate main body 11 is made of an electrically insulating material, for example, BT (BiSmaleimide Tdazine) thermosetting resin material, epoxy resin, m plexiglass fiber, wherein the soil plate body 11 can be provided with a through hole (not Draw) to embed passive components. Furthermore, the substrate body 110 may also be a composite structure, wherein the composite structure may be composed of 8 200929470 conductive material and an electrically insulating material, such as a printed circuit board (Metal C〇re PCB; MCPCB) having a metal core, and this conductive The material is selected from the group consisting of metal materials, Tauman materials, semiconductor materials, and any combination of the foregoing. The solder pad 12 is formed on a surface of the substrate body ι, so that the electrode (not shown) or the electrode pin 240 of the semiconductor device 2 can be soldered to the pad 12 of the carrier substrate 1 When solder bonding, the solder 1G1 can be used as a bonding material, such as a tin-rich (Pb-Sn) alloy, a tin-silver alloy, a tin-copper alloy or other lead-free solder. The pad 120 is patterned by a metal material (for example, copper), wherein the pad may have a surface treatment such as: Organs Solderability preservatives or surface nickel plating to avoid the occurrence of the pad 120. Surface oxidation. The solder resist layer 13 is formed on the side surface of the substrate main body and is formed outside the solder # 12G to prevent the soldering 1Q1 used in the solder bonding from arbitrarily flowing due to high temperature, resulting in a short circuit. situation. The material of the solder resist layer 130 is, for example, a green paint (S〇lder Deleted Solder Resist), which can utilize screen printing, Curtain Coating, Spray coating, and static electricity. It is formed on the substrate main body 110 by means of electrostatic spraying or roller coating. Since the solder resist I 13 is formed in a region other than the pad 120, the Tan 1 〇 1 in the molten state can flow only in the region of the pad 120 when the tandem is performed. It should be noted that in other embodiments, the semiconductor device 200 of the present embodiment can also be directly bonded to the carrier substrate 1 before being packaged. In this case, the two electrodes of the semiconductor device 200 can be bonded to the carrier substrate 1 . The pad of the germanium 120' or the electrode of the 'semiconductor element is directly bonded to the tantalum 9 200929470 1 ' and the other electrode of the semiconductor element 200 is connected by a wire bonding method. ❹ Referring to Figure 3, there is shown a top plan view of a solder pad in accordance with a first embodiment of the present invention. The solder fillet 12 of the present embodiment has a second degree τ and a second width t in one direction, the first width is greater than the second width t, and the crucible 20 includes at least the actual joint (four) and the solder flow region actual joint region 121. _ directly carrying the semiconductor element electrode or electrode pin 24, that is, the semiconductor element 2 (10) is actually bonded to the pad 120, wherein the actual bonding region 121 is in the direction of the parallel width τ and the second width t The width is substantially close to the second width, preferably slightly less than the second width t. As shown in FIG. 3, in the present embodiment, the pad 120 may be, for example, an L-shaped planar structure, and thus naturally has a width reduction region outside the actual bonding region (2) and the solder flow region 122, that is, in the - direction. Up reducing the first width T to the second width of the bonding pad and at least a portion of the actual bonding region 4 121 is located in the pad region formed by the second width t, and is limited by the second width t, so that the semiconductor The bonding of the electrode of the element and the pad does not deviate from the Ht, that is, it does not deviate from the positioning restricting portion 123. The solder flow region 122 is formed on at least one side of the actual joint region 121 'to allow the weld to flow in the tan flow region 122 when the G1 is in a melted state', wherein the solder flow region 122 can be of any shape to provide excess melting The flow space of 1G1 is used to enhance the welding strength. In the present embodiment, the positioning restricting portion 123 is adjacent to the second sound of the bonding pad 12, for example, and extends in the direction perpendicular to the second width t to limit the melting, and the flow of the solder 122 is in the range of the second width t. Within this, it is possible to limit the case where the displacement of the semi-conducting 200929470 body 〇2 on the soldering iron 120 occurs at a floating offset on the tan. It is worth noting that the depression limit 123 of the Taisi 偏 position can be defined by the weld shape, that is, by the periphery of the pad 120 === the flow of the molten solder 1G1 The Langshi uses the solder flow area 122 to supply the excess _ solder ΐ () ι flow space. In the second embodiment, the ratio of the second width t to the first width ❹
〇.85mm時，第二寬度t可為〇.5mm。 再者’焊墊120之面積a(亦即實際接合區域ΐ2ι和焊 錫流動區域122之面積總和)相較於實際接合區域121之面 積a的比例（Α/a)較佳係實質介於！」與2 5之間。例如當實 際接合區域121之面積4〇 3W時，焊塾12〇之面積A 可為 0.65.mm2。 因此，當半導體元件200焊接接合於承載基板刚上 時，承載基板_之焊$12〇可提供多餘之溶融焊锡ι〇ι 的仇動工間’以增強焊接強度，並可同時限制半導體元件 200在㈣焊錫1G1上浮動偏移的情形，因而可精確地定位 半導體元件於承載基板⑽±，以減少定位偏差的情 請參照第4圖，其緣示依照本發明之第二實施例之焊 墊的俯視示意圖。以下僅就本實施例與第一實施例之相異 處進行說明’關於相似處在此不再贅述。相較於第一實施 二’第二實施例之焊墊12Ga可例如為〔形平面結構，並在 -方向上具有第一寬度T和第二寬度t，第—寬度τ係大於 11 200929470 第二寬度t，於本實施例中，定位限制部123a係形成於此 些焊錫流動區域122a之間，至少部份之實際接合區域ΐ2ι 係位於由第二寬度t所構成的焊墊區域之内，以定位半導 體元件200於焊塾120a上，因而減少定位偏差的情形。 請參照第5A和5B圖，其繪示依照本發明之第三實施 例之焊墊的俯視示意圖。以下僅就本實施例與第一實施例 之相異處進行說明，關於相似處在此不再贅述。相較於第 一實施例，第三實施例之焊墊12〇b設有一個或複數個焊料 流動區域122b’其設置於實際接合區域121b的至少一側， 以提供熔融焊錫101的流動空間，且焊墊12〇b具有第一寬 度T和第二寬度t’第一寬度T係大於第二寬度t。於本實 施例中，定位限制部123b例如係沿著第二寬度【之垂直方 向延伸，而形成於實際接合區域121b的兩側周圍，並可位 於此些焊料流動區域！22b之間，以定位半導體元件2〇〇於 焊墊120b上。 由上述本發明之實施例可知，本發明之半導體元件的 承載基板及其應用可提供多餘之熔融焊料的流動空間，並 可有效地定位半導體元件於承載基板的焊墊上，因而大幅 地提升定位精度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 12 200929470 為讓本發明之上述和其他目的、特徵、優點與實施例 月b更明顯易懂’所附圖式之詳細說明如下. 第1A圖係緣示依照習知技術一種發光二極體焊合於 基板的側視示意圖。 第1B圖係緣示依照習知技術之焊塾的俯視示意圖。 第2圖係緣示依照本發明第一實施例之半導體元件設 置於承載基板上時的剖面示意圖。 e 第3圖係繪示依照本發明之第一實施例之焊墊的俯視 示意圖。 第4圖係緣示依照本發明之第二實施例之焊墊的俯視 示意圖。 第5A和5B圖騎示依照本發明之第三實施例之焊塾 的俯視示意圖。 主要元件符號說明】 b :寬度縮減區域 t :第一寬度 100 :承載基板 120a、120b :焊墊 121b :實際接合區域 卩，、122b :焊錫流動區域 23a、123b :定位限制部 防焊層 :半導體元件 220 :承載器 T :第 120 121 122 123 130 110 一寬度 基板主體 240 :電極接腳 910 :發光二極 920 ·基板 901 :焊錫 :焊錫 21〇:半導體元件晶片 230 :座體 體 911 :電極接腳 921 =焊墊 \ι〇.85mm, the second width t may be 〇.5mm. Further, the area a of the pad 120 (i.e., the sum of the areas of the actual bonding area ΐ2ι and the solder flow area 122) is preferably substantially proportional to the ratio (Α/a) of the area a of the actual bonding area 121! Between 2 and 5. For example, when the area of the actual joint region 121 is 4 〇 3 W, the area A of the weir 12 可 can be 0.65 mm 2 . Therefore, when the semiconductor component 200 is solder bonded to the carrier substrate, the soldering of the carrier substrate _12 〇 can provide a redundant soldering solder ι 〇 仇 工 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 , , , In the case where the solder 1G1 is floatingly offset, the semiconductor element can be accurately positioned on the carrier substrate (10)± to reduce the positioning deviation. Referring to FIG. 4, the edge of the solder pad according to the second embodiment of the present invention is seen. schematic diagram. In the following, only the differences between the embodiment and the first embodiment will be described. The description of the similarities will not be repeated here. The pad 12Ga of the second embodiment can be, for example, a [planar planar structure and has a first width T and a second width t in the − direction, and the first width τ is greater than 11 200929470 second. Width t, in this embodiment, the positioning limiting portion 123a is formed between the solder flow regions 122a, at least a portion of the actual bonding region ΐ2ι is located within the pad region formed by the second width t, The semiconductor element 200 is positioned on the pad 120a, thereby reducing the positional deviation. Referring to Figures 5A and 5B, there is shown a top plan view of a solder pad in accordance with a third embodiment of the present invention. In the following, only the differences between the embodiment and the first embodiment will be described, and the details are not described herein again. Compared with the first embodiment, the pad 12〇b of the third embodiment is provided with one or a plurality of solder flow regions 122b' disposed on at least one side of the actual bonding region 121b to provide a flow space for the molten solder 101, And the pad 12〇b has a first width T and a second width t′, and the first width T is greater than the second width t. In the present embodiment, the positioning restricting portion 123b extends, for example, in the vertical direction of the second width, and is formed around both sides of the actual bonding region 121b, and can be located in the solder flow regions! Between 22b, the semiconductor element 2 is positioned on the pad 120b. It can be seen from the embodiments of the present invention that the carrier substrate of the semiconductor device of the present invention and the application thereof can provide a redundant flow space of the molten solder, and can effectively position the semiconductor component on the pad of the carrier substrate, thereby greatly improving the positioning accuracy. . While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The above-mentioned and other objects, features, advantages and embodiments of the present invention are more clearly understood. The detailed description of the drawings is as follows. FIG. 1A is based on the prior art. A schematic side view of a light emitting diode soldered to a substrate. Fig. 1B is a schematic plan view showing a soldering iron according to a conventional technique. Fig. 2 is a schematic cross-sectional view showing a state in which a semiconductor element according to a first embodiment of the present invention is placed on a carrier substrate. e Fig. 3 is a top plan view showing a pad according to a first embodiment of the present invention. Fig. 4 is a schematic plan view showing a solder pad according to a second embodiment of the present invention. 5A and 5B are schematic views showing a plan view of a welding bead according to a third embodiment of the present invention. Main component symbol description] b: width reduction region t: first width 100: carrier substrate 120a, 120b: pad 121b: actual bonding region 卩, 122b: solder flow region 23a, 123b: positioning restriction portion solder mask: semiconductor Element 220: Carrier T: 120 121 122 123 130 110 110 Width substrate body 240: Electrode pin 910: Light-emitting diode 920 • Substrate 901: Solder: Solder 21 〇: Semiconductor element wafer 230: Seat body 911: Electrode Pin 921 = pad \