0610104ITW 21556twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種主動元件陣列基板(actWe device army substrate)，且特別是有關於一種可修補其周邊線路 (peripheral circuit)之主動元件陣列基板及其修補方法。 【先前技術】 液晶顯示器（liquid crystal display，LCD)由於具備了 輕、.薄、省電、無輻射以及低電磁干擾的優點，而大量應 用在手機(mobile phone)、筆記型電腦(notebo〇lc pers〇nal computer)、個人數位助理(personaldigital assistant，PDA)、 數位相機(digital camera)、數位攝影機(digital video camera) 等各式電子產品。由於業界積極地投入液晶顯示器之研 發’如此’帶動液晶顯不益的品質不斷提升。然而，在液 晶顯示面板製造過程中，信號配線(signal line)如掃描配線 (scan line)或是資料配線(data line)偶爾會有缺陷(defect)產 生。 圖1為習知一種薄膜電晶體陣列基板(thin film transistor array substrate, TFT array substrate)與其驅動電路 (driving circuit)之連接關係示意圖。請參照圖1，用以驅動 習知薄膜電晶體陣列基板110的驅動電路120包括多個源 極驅動器（source driver) 122、多個閘極驅動器(gate driver) 128、一第一印刷電路板(printed circuit board) 124 以及一第 二印刷電路板126。源極驅動器122電性連接於第一印刷 電路板124與薄膜電晶體陣列基板110之間，閘極驅動器 ^60706 0610104ITW 21556twf.doc/n 128電性連接於第二印刷電路板i26與薄膜電晶體陣列基 板no之間’而第一印刷電路板124與第二印刷電路板126 電性連接。薄膜電晶體_基板丨丨〇具有—顯示區(此㈣ region) A及一位於顯示區外圍之周邊線路區(peripherai circuit region) B，且薄膜電晶體陣列基板u〇包括多個資 料配線112、多個掃描配線114以及多個畫素結構116。畫 素結構116配置於顯示區a内，且各畫素結構116中包括 一薄膜電晶體116a以及與其電性連接之一晝素電極 116b。資料配線112與掃描配線114橫跨顯示區a與周邊 線路區B，且分別電性連接於源極驅動器122與閘極驅動 益128。而薄膜電晶體U6是與資料配線112以及掃描配 線114電性連接，以藉由資料配線112以及掃描配線ιΐ4 進行驅動。 當資料配線112產生缺陷D，而形成不互相連結的資 料配線上段112a與資料配線下段112b時，資料配線上段 112a仍可正常傳送由源極驅動器ι22所送出的信號，但資 料配線下段112b因缺陷d的關係而無法傳送由源極驅動 器122所傳送的信號。如此一來，會導致採用薄膜電晶體 陣列基板110之液晶顯示面板在缺陷D以下的區域無法正 常顯不’而嚴重影響液晶顯示面板之顯示品質。 圖2為修補配線組及圖1之薄膜電晶體陣列基板與其 驅動電路的示意圖。請參照圖2,為了改善薄膜電晶體陣 列基板110在資料配線112產生缺陷D時所造成的問題， 可在薄膜電晶體陣列基板11()及驅動電路12〇上配置一修 7 1360706 0610104ITW 21556twf.doc/n 補配線組(repair line set) 210。修補配線组210包括多個第 一修補配線212a、多條擬配線(dummy line)212b以及一第 二修補配線212c。第一修補配線212a配置於薄膜電晶體 陣列基板110上靠近源極驅動器122的周邊線路區B内， 並浮跨於數條資料配線112上。擬配線212b配置於源極驅 動器122上。第二修補配線212c橫跨第一印刷電路板 124、第二印刷電路板126、閘極驅動器128 q及薄膜電晶 體陣列基板110上遠離源極驅動器122的一叫之周邊線路 區B，並浮跨於資料配線112的末端上。第一修補配線 212a、擬配線212b以及第二修補配線212c彼此電性連接。 當資料配線112產生缺陷D，而形成不互相連結的資 料配線上段112a與資料配線下段112b時，可利用雷射熔 接方法將第一修補配線212a與資料配線上段n2a的交會 處220a熔接，並將第二修補配線212c與資料配線下段 112b的乂會處220b溶接。如此一來，源極驅動器122所 送出的信號便可經由資料配線上段112a、第一修補配線 212a、擬配線212b、第二修補配線212c而傳遞至資料配 線下段112b。這樣便可以修補薄膜電晶體陣列基板n〇於 製程中所產生的資料配線112之缺陷d。 上述修補方式僅能針對薄膜電晶體陣列基板丨1〇之顯 示區A内的資料配線112進行修補。請繼續參考圖2，當 資料配線112,在周邊線路區B處發生缺陷D，時，顯示區: 中所有與資料配線112’電性連接之晝素皆無法作動’而影 響到整個面板之正常顯示。然而，上述修補方式並無法針 1360706 0610104ITW 21556twf.d〇c/n 對周邊線路區B處之缺陷d，進行修補。 【發明内容】 本發明之目的是提供一種主動元件陣列基板，以改善 因其周邊線路區的信號配線斷裂所造成的良率下降。 本發明之另一目的是提供一種主動元件陣列基板之 周邊線路的修補方法，以提升主動元件陣列基板的良率。 為達上述或是其他目的，本發明提出一種主動元件陣 歹J基板，其包括一基板(substmte)、一晝素陣列（pkd aiTay)、夕條化號配線、一擬配線、一驅動晶片（driver chip)、一第一修補配線以及一第二修補配線。基板具有一 顯示區以及位於顯示區外圍之一周邊線路區。晝素陣列配 置於基板之顯示區内。信號配線配置於基板上，並由顯示 區延伸至周邊線路區’且與晝素_電性連接。驅動晶片 配置於基板之周邊線路區的這些信號配線上，且與這些信 號配線電性連接。驅動晶片具有至少一擬接腳(d^v pm)，並具有一鄰近於顯示區之一第一侧邊以及與其相對 之一第二側邊，其中這些信號配線是由驅動晶片之第一側 邊延伸並凸出於第二侧邊。擬配線配置於基板之周邊線路 區内且對應於擬接腳而設置。第一修補配線位於驅動晶 片之第一側邊與顯示區之間，其中第一修補配線橫跨這些 k號配線及擬配線，並與這些信號配線及擬配線電性絕 緣。第二修補配線配置於基板之周邊線路區内，並鄰近於 驅動晶片之第二側邊’其巾第二修獅線橫跨這些信號配 線及擬配線，並與這些信號配線及擬配線電性絕緣。 9 1360706 0610104ITW 21556twf.do«7n 在本發明之一實施例中，上述這些信號配線包括資料 配線。 在本發明之一實施例中，上述這些信號配線包括掃描 配線。 為達上述或是其他目的，本發明更提出一種主動元件 陣列基板之周邊線路的修補方法，其包括下列步驟。首先， 提供上述之主動元件陣列基板。主動元件陣列基板位於周 邊線路區之其中一信號配線具有一缺陷，此缺陷位於第一 修補配線與驅動；之第—側邊之間。具有賴之信號配 線與第一修補配線與第二修補配線交會處分別為一第一熔 接，(melted COnnected point)以及一第二熔接點，而擬配線 與第一修補配線與第二修補配線交會處分別為一第三熔接 點以及一第四炼接點。 接著，對第一熔接點、第二熔接點、第三熔接點以及 第四熔接點進行熔接，使具有缺陷之信號配線與第一修補 配線以及第二修補配線電性連接，並使擬配線與第一修補 配線以及第二修補配線電性連接。 在本發明之一實施例中，上述對第一熔接點、第二熔 接點、第三熔接點以及第四熔接點進行熔接的方法為以雷 射光束照射第一熔接點 '第二熔接點、第三熔接點以及第 四熔接點。 在本發明之一實施例中，上述之主動元件陣列基板位 於周邊線路區之另一信號配線具有另一缺陷，此另一缺陷 位於第一修補配線與驅動晶片之第一側邊之間。具有另一 1360706 0610104ITW 21556twf.doc/n •缺陷之，號配線與第-修補配線與第二修補配線交會處分 -別為二第五炫接點以及一第六炫接點，而另一擬配線與第 修補配線與第二修補配較會處分別為_第七熔接點以 及一第八炫接點。此情況下之主動元件陣列基板之周邊線 路的修補方法更包括下列步驟。 一、 對第五熔接點、第六熔接點、第七熔接點以及第 讀接點進㈣接，使具有另—賴之信號配線與第一修 • _己線以及第二修補配線電性連接，並使另-擬配線與第 一修補配線以及第二修補配線電性連接。 二、 將第一修補配線介於具有缺陷之信號配線與具有 另一缺陷之信號配線之間的部分切斷，並將第二修補配線 介於具有缺陷之信號配線與具有另一缺陷之信號配線之間 的部分切斷，以使具有缺陷之信號配線與具有另一缺陷之 k號配線彼此電性絕緣。 上述熔接第一至第四熔接點的步驟、上述步驟一以及 步驟一的先後次序可任意對調。 在本發明之一實施例中，上述對第五熔接點、第六熔 接點、第七熔接點以及第八熔接點進行熔接的方法為以雷 射光束照射第五熔接點、第六熔接點、第七熔接點以及^ 八熔接點。 本發明因採用位於周邊線路區的第一修補配線盘第 二修補配線搭配擬配線的結構，因此可用以修補位於周邊 線路區的信號配線之缺陷。此外，此結構所佔的線路佈局 面積較小，故擬配線、第一修補配線以及第二修補配線的 1360706 0610104ITW 21556twf.doc/n 數目較不會受到限制。因此，相較於習知技術，本發明能 修補的信號配線數可以較多。再者，本發明能修補的信號 配線包括資料配線和掃描配線。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖3為根據本發明之一實施例之一種主動元件陣列基 板的上視示意圖。請參照圖3，本實施例之主動元件陣列 基板300適於應用於液晶顯示面板、有機發光二極體顯示 面板(organic light emitting diode display panel)或其他顯示 面板中。主動元件陣列基板300包括一基板31〇、一晝素 陣列320、多條信號配線330、多條擬配線340、至少一驅 動晶片350、至少一第一修補配線36〇以及一第二修補配 線370。以下將搭配圖式說明薄膜電晶體陣列基板上之各 元件以及各元件之間的連接關係。 基板310具有一顯示區a以及位於顯示區a外圍之 一周邊線路區B。晝素陣列320配置於基板310之顯示區 A内’且包含多個呈矩陣型式排列之晝素結構322。各畫 素結構322中分別包括一薄膜電晶體322&以及與其電性連 接之一晝素電極322b。信號配線330包含有多條配置於基 板310上之資料配線332與掃描配線334，這些信號配線 330是由顯示區a延伸至周邊線路區B，並分別與畫素陣 列320中之薄膜電晶體322a電性連接。驅動晶片35〇配置 12 1360706 0610104ITW 21556twf.d〇c/, 於基板310之周邊線路區B，且與這些信號配線33〇電性 連接。舉例來說，驅動晶片350可以其信號接腳356與信 號配線330電性連接。驅動晶片35〇具有至少一擬接腳 358，並具有一鄰近於顯示區A之一第一側邊352以及與 其相對之一第二側邊354，其中這些信號配線33〇是由驅 動晶片350之第一侧邊352延伸並凸出於驅動晶片35〇之 第二側邊354。值得注意的是’本發明並不限定主動元件 陣列基板300之驅動晶片35〇的數量為如圖3所示之五 個，在本發明的其他實施例中，驅動晶片35〇的數量可視 實際需要而為一個以上的任意數量。 擬配線340包括第一擬配線34〇a與第二擬配線 340b’其配置於基板31〇之周邊線路區b内，且擬配線340 是對應於擬接腳358而設置。此外，擬配線340可與對應 的擬接腳358電性連接。在本實施例中，擬接腳358可分 別配置於靠近驅動晶片350之相對兩側的位置，而第一擬 配線340a與第二擬配線340b分別對應地配置於與同一驅 動晶片350電性連接的一組信號配線33〇的兩側，並用以 修補此組信號配線330。以下將與同一驅動晶片350電性 連接的多條信號配線330統稱為同一組信號配線330。 第一修補配線360位於驅動晶片350之第一側邊352 與顯示區A之間，且第一修補配線360橫跨同一組信號配 線330、第一擬配線340a以及第二擬配線340b，並與信號 配線330、第一擬配線340a以及第二擬配線340b電性絕 緣。第二修補配線370配置於基板310之周邊線路區b内， 13 1360706 0610104ITW 21556twf.doc/n 並鄰近於驅動晶片350之第二側邊354。第二修補配線370 橫跨同一組信號配線330、第一擬配線340a及第二擬配線 340b，並與信號配線330、第一擬配線340a及第二擬配線 340b電性絕緣。 然而’本發明並不限定用以修補同一組信號配線330 的擬配線340數為二條’在本發明之其他實施例中，用以 修補同一組信號配線330的擬配線340數亦可為一條或三 條以上。當用以修補同一組信號配線330的擬配線340數 為一條或三條以上時’第一修補配線360橫跨擬配線340 與此組信號配線330，且第二修補配線370亦橫跨擬配線 340與此組信號配線330。此外，在本發明的其他實施例 中，第一修補配線360與第二修補配線370亦可橫跨多組 k號配線330及用以修補多組信號配線33〇的擬配線34〇。 本發明亦不限定擬配線340是位於同一組信號配線 330的兩侧或一側，在本發明之其他實施例中，擬配線34〇 亦可配置於相鄰的兩條信號配線33〇之間。 在本實施例中，擬配線340是位於驅動晶片350的下 方，且凸出於驅動晶片35〇之第一側邊352與第二侧邊 然而在本發明之其他實施例中擬配線％^亦可位於 驅動晶片350旁，而不被驅動晶片35〇所覆蓋。 圖4為根據本發明一實施例之一種主動元件陣列基板 =周邊線路的修補方法之示意圖。主動元件陣列基板在製 程中，其彳遷配線難免會產生缺陷。舉例來說，請參 “、、圖4，如圖3所繪示之主動元件陣列基板300在製作過 1360706 0610104ITW 21556twf.doc/n 程中，位於周邊線路區B之其中一資料配線332a處產生 了 一缺陷D ,此缺陷D位於第一修補配線360與驅動晶片 350之第一側邊352之間。缺陷〇例如為斷裂缺陷，或未 元王斷裂但使彳§號配線330的電阻值增加的缺陷。具有資 料配線332a與第一修補配線360與第二修補配線370交會 處分別定義為一第一溶接點382以及一第二溶接點384， 而第一擬配線340a與第一修補配線360與第二修補配線 370交會處分別定義為一第三熔接點386以及一第四熔接 點388。本實施例對主動元件陣列基板3〇〇之周邊線路的 修補方法包括下列步驟。 首先’對第一熔接點382、第二熔接點384、第三炫 接點386以及第四熔接點388進行熔接，進行熔接的方法 例如是以雷射光束照射欲熔接處。如此一來，具有缺陷D 之資料配線332a與第一修補配線360以及第二修補配線 370便可電性連接’而第一擬配線340a與第一修補配線360 以及第二修補配線370亦可電性連接。這樣的話，驅動晶 片350所發出的訊號便可經由路徑e而傳遞至顯示區a 内’以達到修補缺陷D的效果。 在本實施例中，修補缺陷D的方法為將第一熔接點 382、第二熔接點384、第三熔接點386及第四熔接點388 炫接’然而在本發明的其他實施例中，修補缺陷D的方法 亦可以是將具有缺陷D之信號配線330與第一修補配線 360與第二修補配線370的交會處熔接，並將第二擬配線 340b與第一修補配線36〇與第二修補配線37〇的交會處熔 15 1360706 0610104ITW 21556twf.doc/n ^。這樣-來’驅動晶片35()所發出的訊镜便可經由通過 第一擬配線340b的另一路徑傳遞至顯示區A内^ 值得注意的是’本發明之主動元件陣列基板之周邊線 路的修補方法並不限定_ D是位關4之位置才评 補。在本發明的其他實施例中，當缺陷是位於周邊線路區 A :的任何資料配線332上，或位於周邊線路區a中的任 何掃描配線334上時，亦可以與本實施例相同原理的修補 方法來修補缺陷D，在此不再重述。 圖5為根據本發明另一實施例之一種主動元件陣列基 板之周邊線路的修補方法之示意圖。請參照圖5，如圖1 之主動元件陣列基板300在製造過程中除了如同圖4所繪 示在周邊線路區B的資料配線332a上產生一缺陷D ^ 外’更在與資料配線332a同一組資料配線332中的另一資 料配線332b上產生另一缺陷D，。。缺陷D，位於第一修補 配線360與驅動晶片350之第一側邊352之間。具有缺陷 D’之資料配線332b與第一修補配線36〇與第二修補配線 37〇交會處分別定義為一第五熔接點382，以及一第六熔接 點384，而第一擬配線340b與第一修補配線360與第二 修補配線370交會處分別定義為一第七熔接點386，以及一 苐八炫接點388’。本實施例對主動元件陣列基板之周 邊線路的修補方法包括下列步驟。 ° 一、對第一熔接點382、第二熔接點384、第三熔接 點386、第四熔接點388、第五熔接點382，、第六熔接點 384’、第七熔接點386，以及第八熔接點388，進行熔接進 1360706 0610104ITW 21556twf.doc/n 行熔接的方法例如是以雷射光束照射欲熔接處。如此一 來’具有缺陷D’之資料配線332b與第一修補配線360以 及第二修補配線370便可電性連接，而第二擬配線340b 與第一修補配線360以及第二修補配線370亦可電性連 接。這樣的話，驅動晶片350所發出的訊號便可經由路徑 G而傳遞至顯示區A内’以達到修補缺陷D’的效果。 二、將第一修補配線）60介於具有缺陷d之資料配線 332a與具有缺陷D’之資料配線332b之間的部分切斷(其切 斷處Η可位於如圖5所示的位置），並將第二修補配線37〇 介於具有缺陷D之資料配線332a與具有缺陷D，之資料配 線332b之間的部分切斷(其切斷處I可位於如圖5所示的 位置），以使具有缺陷D之資料配線332a與具有缺陷D， 之S料配線332b彼此電性絕緣。如此一來，具有缺陷d 之資料配線332a與具有缺陷D，之資料配線332b便可分別 傳送彼此獨立的信號至顯示區A内。此外，將第一修補配 線360及第二修補配線370切斷的方法例如是用雷射光束 照射欲切斷處，而將欲切斷處熔斷。 上述步驟一及步驟二的順序可對調，舉例來說，上述 兩個步驟的進行順序可依次為步驟一及步驟二，或者依次 為步驟二及步驟一。 以與本實施例相同原理的修補方法可修補每組信號 配線中有兩條以下的信號配線具有缺陷的主動元件陣列基 板。換句話說，若主動元件陣列基板具有N個驅動晶片（即 具有N組信號配線）’則以與本實施例相同原理之修補方 17 1360706 0610104ITW 21556twf.doc/n[Technical Field] The present invention relates to an actWe device army substrate, and in particular to a repairable peripheral circuit thereof. Active device array substrate and repair method thereof. [Prior Art] Liquid crystal display (LCD) has many advantages in light, thin, power saving, no radiation and low electromagnetic interference, and is widely used in mobile phones and notebook computers (notebo〇lc). Pers〇nal computer), personal digital assistant (PDA), digital camera, digital video camera and other electronic products. As the industry actively invests in the research and development of liquid crystal displays, the quality of LCDs has been increasing. However, in the manufacturing process of a liquid crystal display panel, a signal line such as a scan line or a data line occasionally has a defect. FIG. 1 is a schematic diagram showing the connection relationship between a thin film transistor array substrate (TFT array substrate) and a driving circuit thereof. Referring to FIG. 1, a driving circuit 120 for driving a conventional thin film transistor array substrate 110 includes a plurality of source drivers 122, a plurality of gate drivers 128, and a first printed circuit board ( Printed circuit board 124 and a second printed circuit board 126. The source driver 122 is electrically connected between the first printed circuit board 124 and the thin film transistor array substrate 110, and the gate driver ^60706 0610104ITW 21556twf.doc/n 128 is electrically connected to the second printed circuit board i26 and the thin film transistor. The first printed circuit board 124 is electrically connected to the second printed circuit board 126 between the array substrates no. The thin film transistor _ substrate 丨丨〇 has a display area (this (four) region) A and a peripheral circuit region B located at the periphery of the display area, and the thin film transistor array substrate 〇 includes a plurality of data lines 112, A plurality of scan lines 114 and a plurality of pixel structures 116. The pixel structure 116 is disposed in the display area a, and each of the pixel structures 116 includes a thin film transistor 116a and a halogen electrode 116b electrically connected thereto. The data wiring 112 and the scanning wiring 114 straddle the display area a and the peripheral line area B, and are electrically connected to the source driver 122 and the gate driving benefit 128, respectively. The thin film transistor U6 is electrically connected to the data wiring 112 and the scanning wiring 114 to be driven by the data wiring 112 and the scanning wiring ι4. When the data wiring 112 generates the defect D and forms the data wiring upper segment 112a and the data wiring lower segment 112b which are not connected to each other, the data wiring upper segment 112a can normally transmit the signal sent by the source driver ι22, but the data wiring lower segment 112b is defective. The relationship of d cannot transfer the signal transmitted by the source driver 122. As a result, the liquid crystal display panel using the thin film transistor array substrate 110 cannot be normally displayed in the region below the defect D, which seriously affects the display quality of the liquid crystal display panel. Fig. 2 is a schematic view showing the repair wiring group and the thin film transistor array substrate of Fig. 1 and its driving circuit. Referring to FIG. 2, in order to improve the problem caused when the thin film transistor array substrate 110 generates the defect D in the data wiring 112, a thin film transistor array substrate 11 () and the driving circuit 12A can be arranged on a 1 1360706 0610104ITW 21556twf. Doc/n repair line set 210. The repair wiring group 210 includes a plurality of first repair wirings 212a, a plurality of dummy lines 212b, and a second repair wiring 212c. The first repair wiring 212a is disposed on the thin film transistor array substrate 110 in the peripheral line region B adjacent to the source driver 122, and floats across the plurality of data wirings 112. The dummy wiring 212b is disposed on the source driver 122. The second repairing line 212c spans the first printed circuit board 124, the second printed circuit board 126, the gate driver 128q, and the peripheral circuit area B of the thin film transistor array substrate 110 away from the source driver 122, and floats Across the end of the data wiring 112. The first repair wiring 212a, the dummy wiring 212b, and the second repair wiring 212c are electrically connected to each other. When the data wiring 112 generates the defect D and forms the data wiring upper segment 112a and the data wiring lower segment 112b which are not connected to each other, the first repaired wiring 212a and the intersection portion 220a of the data wiring upper segment n2a may be welded by the laser welding method, and The second repair wiring 212c is in contact with the buffer portion 220b of the lower portion 112b of the data wiring. In this manner, the signal sent from the source driver 122 can be transmitted to the data distribution lower segment 112b via the data wiring upper segment 112a, the first repair wiring 212a, the dummy wiring 212b, and the second repair wiring 212c. Thus, the defect d of the data wiring 112 generated in the thin film transistor array substrate can be repaired. The above repair method can only repair the data wiring 112 in the display area A of the thin film transistor array substrate. Please continue to refer to FIG. 2. When the defect D occurs in the peripheral wiring area B of the data wiring 112, all the elements in the display area: which are electrically connected to the data wiring 112' cannot be activated, and affect the normality of the entire panel. display. However, the above repair method cannot repair the defect d at the peripheral line region B by pin 1360706 0610104ITW 21556twf.d〇c/n. SUMMARY OF THE INVENTION An object of the present invention is to provide an active device array substrate to improve yield degradation caused by breakage of signal wiring in its peripheral line region. Another object of the present invention is to provide a method of repairing a peripheral line of an active device array substrate to improve the yield of the active device array substrate. In order to achieve the above or other objects, the present invention provides an active device array J substrate comprising a substrate, a pixel array (pkd aiTay), a stencil wiring, a dummy wiring, and a driving wafer ( Driver chip), a first repair wiring, and a second repair wiring. The substrate has a display area and a peripheral line area located at a periphery of the display area. The halogen array is placed in the display area of the substrate. The signal wiring is disposed on the substrate and extends from the display region to the peripheral wiring region' and is electrically connected to the halogen. The driving wafers are disposed on the signal wirings in the peripheral wiring region of the substrate, and are electrically connected to the signal wirings. The driving chip has at least one dummy pin (d^v pm) and has a first side adjacent to one of the display areas and a second side opposite thereto, wherein the signal wiring is driven by the first side of the wafer The sides extend and protrude from the second side. The wiring is arranged in the peripheral circuit area of the substrate and is provided corresponding to the intended pin. The first repair wiring is located between the first side of the driving wafer and the display area, wherein the first repair wiring crosses the k-type wiring and the dummy wiring, and is electrically insulated from the signal wiring and the wiring. The second repair wiring is disposed in the peripheral circuit region of the substrate, and adjacent to the second side of the driving chip, the second lion line of the towel spans the signal wiring and the intended wiring, and the signal wiring and the wiring electrical property insulation. 9 1360706 0610104ITW 21556twf.do «7n In an embodiment of the invention, the signal wirings described above comprise data wiring. In an embodiment of the invention, the signal wirings described above comprise scan wiring. To achieve the above or other objects, the present invention further provides a method for repairing a peripheral line of an active device array substrate, which comprises the following steps. First, the above-described active device array substrate is provided. The active device array substrate is located in one of the peripheral wiring regions and has a defect between the first repair wiring and the first side of the drive; The signal wiring and the first repair wiring and the second repair wiring intersection are respectively a first welded, a (melted COnnected point) and a second welded joint, and the intended wiring meets the first repaired wiring and the second repaired wiring. The locations are a third weld joint and a fourth weld joint. Then, the first fusion splice, the second splice, the third splice, and the fourth splice are welded, and the defective signal wiring is electrically connected to the first repair wiring and the second repair wiring, and the pseudo wiring is The first repair wiring and the second repair wiring are electrically connected. In an embodiment of the present invention, the method of welding the first fusion splice point, the second fusion splice point, the third fusion splice point, and the fourth fusion splice point is to irradiate the first fusion splice point 'the second fusion splice point with the laser beam, The third fusion joint and the fourth fusion joint. In an embodiment of the invention, the other signal wiring of the active device array substrate located in the peripheral line region has another defect, and the other defect is located between the first repair wiring and the first side of the driving wafer. Have another 1360706 0610104ITW 21556twf.doc/n • Defective, number wiring and the first repair wiring and the second repair wiring intersection - not the second fifth bright point and one sixth bright joint, and another intended wiring The meeting place with the repaired wiring and the second repairing is respectively a seventh fusion joint and an eighth flexible joint. The repair method of the peripheral line of the active device array substrate in this case further includes the following steps. 1. Connecting the fifth welding contact, the sixth welding contact point, the seventh welding contact point and the reading contact point (4) to electrically connect the signal wiring with the other repair and the first repair line and the second repair wiring. And electrically connecting the other wiring to the first repair wiring and the second repair wiring. 2. Cutting the first repair wiring between the defective signal wiring and the signal wiring having another defect, and cutting the second repair wiring between the defective signal wiring and the signal wiring having another defect The partial cut between them is such that the defective signal wiring and the k-number wiring having another defect are electrically insulated from each other. The steps of fusing the first to fourth splice points, the steps of the above steps 1 and 1 may be arbitrarily reversed. In an embodiment of the present invention, the method of welding the fifth welding point, the sixth welding point, the seventh welding point, and the eighth welding point is to irradiate the fifth welding point, the sixth welding point, and the laser beam with the laser beam. The seventh weld joint and the ^ eight weld joint. The present invention can be used to repair the defect of the signal wiring located in the peripheral line area by adopting the structure of the second repair wiring of the first repair wiring board located in the peripheral wiring area and the wiring. In addition, the structure occupies a small layout area, so the number of 1360706 0610104ITW 21556twf.doc/n of the proposed wiring, the first repair wiring, and the second repair wiring is not limited. Therefore, the number of signal wirings that can be repaired by the present invention can be increased as compared with the prior art. Furthermore, the signal wiring that can be repaired by the present invention includes data wiring and scanning wiring. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] FIG. 3 is a top plan view of an active device array substrate according to an embodiment of the present invention. Referring to FIG. 3, the active device array substrate 300 of the present embodiment is suitably applied to a liquid crystal display panel, an organic light emitting diode display panel, or other display panel. The active device array substrate 300 includes a substrate 31 , a pixel array 320 , a plurality of signal wires 330 , a plurality of dummy wires 340 , at least one driving wafer 350 , at least one first repairing wire 36 , and a second repairing wire 370 . . Hereinafter, the components on the thin film transistor array substrate and the connection relationship between the respective elements will be described with reference to the drawings. The substrate 310 has a display area a and a peripheral line area B located on the periphery of the display area a. The halogen array 320 is disposed in the display area A of the substrate 310 and includes a plurality of pixel structures 322 arranged in a matrix pattern. Each of the pixel structures 322 includes a thin film transistor 322 & and a battery element 322b electrically connected thereto. The signal wiring 330 includes a plurality of data wirings 332 and scanning wirings 334 disposed on the substrate 310. The signal wirings 330 extend from the display area a to the peripheral wiring area B and respectively to the thin film transistors 322a in the pixel array 320. Electrical connection. The driving chip 35 is configured to be electrically connected to the signal lines 33 of the substrate 310 in the peripheral line region B of the substrate 310. For example, the driver chip 350 can be electrically connected to the signal wiring 330 by its signal pin 356. The driving chip 35 has at least one dummy pin 358 and has a first side 352 adjacent to one of the display areas A and a second side 354 opposite thereto, wherein the signal wirings 33 are driven by the driving chip 350 The first side 352 extends and protrudes from the second side 354 of the drive wafer 35A. It should be noted that the present invention does not limit the number of driving chips 35A of the active device array substrate 300 to five as shown in FIG. 3. In other embodiments of the present invention, the number of driving chips 35A may be practically needed. And for any number of more than one. The dummy wiring 340 includes a first dummy wiring 34A and a second wiring 340b' disposed in the peripheral wiring region b of the substrate 31, and the dummy wiring 340 is disposed corresponding to the dummy pin 358. In addition, the dummy wiring 340 can be electrically connected to the corresponding dummy pin 358. In this embodiment, the dummy pins 358 are respectively disposed at positions close to opposite sides of the driving die 350, and the first dummy wires 340a and the second dummy wires 340b are respectively disposed to be electrically connected to the same driving die 350. A set of signal wirings 33 〇 are on both sides and are used to repair the set of signal wirings 330. Hereinafter, a plurality of signal wirings 330 electrically connected to the same driving wafer 350 are collectively referred to as the same group of signal wirings 330. The first repairing wiring 360 is located between the first side 352 of the driving wafer 350 and the display area A, and the first repairing wiring 360 spans the same set of signal wiring 330, the first dummy wiring 340a, and the second dummy wiring 340b, and The signal wiring 330, the first dummy wiring 340a, and the second dummy wiring 340b are electrically insulated. The second repair wiring 370 is disposed in the peripheral line region b of the substrate 310, 13 1360706 0610104ITW 21556twf.doc/n and adjacent to the second side 354 of the driving wafer 350. The second repair wiring 370 straddles the same group of signal wirings 330, the first dummy wiring 340a, and the second dummy wiring 340b, and is electrically insulated from the signal wiring 330, the first dummy wiring 340a, and the second dummy wiring 340b. However, the present invention does not limit the number of pseudo-wirings 340 for repairing the same set of signal wirings 330 to two. In other embodiments of the present invention, the number of pseudo-wirings 340 for repairing the same set of signal wirings 330 may be one or More than three. When the number of pseudo-wirings 340 for repairing the same set of signal wirings 330 is one or three or more, 'the first repair wiring 360 straddles the dummy wiring 340 and the set of signal wirings 330, and the second repair wiring 370 also spans the dummy wiring 340. And this group of signal wirings 330. Furthermore, in other embodiments of the present invention, the first repair wiring 360 and the second repair wiring 370 may also span the plurality of sets of k-number wirings 330 and the dummy wirings 34A for repairing the plurality of sets of signal wirings 33A. The present invention also does not limit the quasi-wiring 340 on either side or side of the same set of signal wirings 330. In other embodiments of the present invention, the pseudo-wiring 34〇 may also be disposed between two adjacent signal wirings 33〇. . In the present embodiment, the dummy wiring 340 is located below the driving wafer 350 and protrudes from the first side 352 and the second side of the driving wafer 35. However, in other embodiments of the present invention, the wiring is also It can be located next to the drive wafer 350 without being covered by the drive wafer 35A. 4 is a schematic diagram of a method for repairing an active device array substrate=peripheral line according to an embodiment of the invention. In the process of the active device array substrate, the relocation wiring is inevitably defective. For example, please refer to ",, FIG. 4, the active device array substrate 300 as shown in FIG. 3 is produced in one of the data lines 332a of the peripheral line area B in the process of making 1360706 0610104ITW 21556twf.doc/n. A defect D is located between the first repairing line 360 and the first side 352 of the driving wafer 350. The defect 〇 is, for example, a fracture defect, or the rupture of the element, but the resistance value of the 彳 配线 wire 330 is increased. The intersection of the data wiring 332a and the first repair wiring 360 and the second repair wiring 370 is defined as a first melting point 382 and a second melting point 384, respectively, and the first dummy wiring 340a and the first repair wiring 360 The intersection with the second repair wiring 370 is defined as a third fusion joint 386 and a fourth fusion joint 388. The repair method for the peripheral circuit of the active device array substrate 3 includes the following steps. A fusion joint 382, a second fusion joint 384, a third joint 386, and a fourth fusion joint 388 are welded, and the method of welding is performed, for example, by irradiating a laser beam with a laser beam. Thus, The data wiring 332a of the trap D can be electrically connected to the first repair wiring 360 and the second repair wiring 370, and the first dummy wiring 340a and the first repair wiring 360 and the second repair wiring 370 can be electrically connected. The signal sent by the driving chip 350 can be transmitted to the display area a via the path e to achieve the effect of repairing the defect D. In the embodiment, the method of repairing the defect D is to use the first fusion point 382, the second method. The welding point 384, the third welding point 386, and the fourth welding point 388 are dashed. However, in other embodiments of the present invention, the method of repairing the defect D may also be the signal wiring 330 having the defect D and the first repairing wiring 360. The intersection with the second repair wiring 370 is welded, and the intersection of the second dummy wiring 340b and the first repair wiring 36〇 and the second repair wiring 37〇 is melted 15 1360706 0610104ITW 21556twf.doc/n ^. The mirror emitted by the driving chip 35() can be transferred to the display area A via another path through the first dummy line 340b. It is noted that the repair method of the peripheral line of the active device array substrate of the present invention is not The definition _D is the position of the level 4. In other embodiments of the invention, when the defect is on any of the data lines 332 of the peripheral line area A: or any of the scan lines 334 located in the peripheral line area a In the above, the defect D can be repaired by the repair method of the same principle as the embodiment, and will not be repeated here. FIG. 5 is a schematic diagram of a repair method of the peripheral circuit of the active device array substrate according to another embodiment of the present invention. Referring to FIG. 5, the active device array substrate 300 of FIG. 1 is identical to the data wiring 332a except that a defect D^ is generated on the data wiring 332a of the peripheral line region B as shown in FIG. Another defect D is generated on the other data wiring 332b in the group data wiring 332. . The defect D is located between the first repair wiring 360 and the first side 352 of the drive wafer 350. The data wiring 332b having the defect D' and the first repair wiring 36A and the second repair wiring 37 are respectively defined as a fifth fusion joint 382 and a sixth fusion joint 384, and the first pseudo wiring 340b and the first The intersection of a repaired wiring 360 and the second repaired wiring 370 is defined as a seventh fusion splice point 386, and a tandem joint 388'. The method for repairing the peripheral line of the active device array substrate in this embodiment includes the following steps. °, for the first fusion joint 382, the second fusion joint 384, the third fusion joint 386, the fourth weld joint 388, the fifth weld joint 382, the sixth weld joint 384', the seventh weld joint 386, and The eight-fusion joint 388 is fused to the 1360706 0610104ITW 21556 twf.doc/n line for the method of welding, for example, by laser beam irradiation. In this way, the data wiring 332b having the defect D can be electrically connected to the first repair wiring 360 and the second repair wiring 370, and the second dummy wiring 340b and the first repair wiring 360 and the second repair wiring 370 can also be used. Electrical connection. In this case, the signal from the driving chip 350 can be transmitted to the display area A via the path G to achieve the effect of repairing the defect D'. 2. The first repair wiring 60 is cut between a portion of the data wiring 332a having the defect d and the data wiring 332b having the defect D' (the cut portion thereof may be located at a position as shown in FIG. 5). And the second repair wiring 37 is cut between the data wiring 332a having the defect D and the data wiring 332b having the defect D, and the cut portion I can be located at the position shown in FIG. 5 to The data wiring 332a having the defect D and the S material wiring 332b having the defect D are electrically insulated from each other. As a result, the data wiring 332a having the defect d and the data wiring 332b having the defect D can respectively transmit signals independent of each other into the display area A. Further, the method of cutting the first repairing line 360 and the second repairing wiring 370 is, for example, irradiating a portion to be cut with a laser beam, and blowing the portion to be cut. The sequence of the foregoing steps 1 and 2 may be reversed. For example, the sequence of the above two steps may be step 1 and step 2, or step 2 and step 1 in sequence. In the repair method of the same principle as the present embodiment, it is possible to repair the active element array substrate having two or less signal wirings in each set of wiring. In other words, if the active device array substrate has N drive wafers (i.e., has N sets of signal wirings), then the repair method of the same principle as the present embodiment is used. 17 1360706 0610104ITW 21556twf.doc/n
法最多能修補2N條信號配線。此外，若n個驅動晶片各 自具有Μ個擬接腳’則每一驅動晶片可以有Μ條^配線 與其對應’如此最多可修補Μ*Ν條信號配線，其中厘與 Ν為正整數。再者，由於擬配線、第一修補配線及第二修 補配線佔據很少的線路佈局面積，故可配置擬配線、第一 修補配線及第一修補配線的數目不易受到總線路佈局面積 的限制，因此本發明之主動元件陣0基板之周邊線路的修 補方法能修補的信號配線數可以很乡。如此一來，便能有 效地提高主動元件陣列基板的良率。 、值得注意的是，本發明之主動元件之周邊線路的修補 方法並不限足僅此用以修補主動元件陣列基板，其亦 可用^修财有本剌之龍的其他絲元件陣列基板。 、綜上所述，由於本發明採用位於周邊線路區的第一修 補配線與第二修獅祕配擬配線的結構，因此可用以修 =於周邊線路區的信號配線之缺陷。此外，此結構所佔 欲、、土路佈局面積很小，故擬配線、第—修補配線以及第二 的數目不易受舰制。因此，本發明能修涵信 =良率。可魏多’因而能有效地提升主動元件陣列基板 措再者，本發明能修補的信號配線包括資料配線和 料二1己線4而不像習知技術所能修補的信號配線僅限於資 接弁^处是本發明之絲元件_基板的良率能有效 配線、原因。另外，本發明之主動元件陣列基板的擬 像習4 MV修補配線及第二修補配線的設計較為簡單，不 Μ㈣示面㈣修補配線所提供的迴路必須繞過 18 1360706 0610104ITW 21556twf.doc/n 印刷電路板那麼複雜。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為習知一種薄膜電晶體陣列基板與其驅動電路之 連接關係示意圖。 圖2為修補配線組及圖1之薄膜電晶體陣列某盘 驅動電路的示意圖。 圖3為根據本發明之一實施例之一種主動元件陣列基 板的上視示意圖。 土 圖4為根據本發明一實施例之一種主動元件陣列基板 之周邊線路的修補方法之示意圖。 土 圖5為根據本發明另一實施例之一種主動元件陣列基 板之周邊線路的修補方法之示意圖。 土 【主要元件符號說明】 110:薄膜電晶體陣列基板 112、112’··資料配線 112a ‘貧料配線上段 112b ·資料配線下段 114 :掃描配線 U6 :薄膜電晶體 120 :驅動電路 1360706 0610104ITW 21556twf.doc/n 122 :源極驅動器 124 :第一印刷電路板 126 :第二印刷電路板 128 :閘極驅動器 210 :修補配線組 212a :第一修補配線 212b :擬配線 212c :第二修補配線 220a、220b :交會處 300、300a、300b :主動元件陣列基板 310 :基板 320 :晝素陣列 322 :晝素結構 322a :薄膜電晶體 322b :晝素電極 330 :信號配線 332、332a、332b :資料配線 334 :掃描配線 340 :擬配線 340a :第一擬配線 340b :第二擬配線 350 .驅動晶片 352 :第一側邊 354 :第二側邊 20 1360706 0610104ITW 21556twf.doc/n 356 :信號接腳 . 358 :擬接腳 360 :第一修補配線 370 :第二修補配線 382 :第一熔接點 382’ ：第五熔接點 384 :第二熔接點 384’ ：第六熔接點 * . 386 :第三熔接點 386’ ：第七熔接點 388 :第四熔接點 388’ ：第八熔接點 A ·顯不區 B:周邊線路區 D、 D’ ：缺陷 E、 G:路徑 φ Η、I :切斷處 21The method can repair up to 2N signal wiring. In addition, if each of the n driving chips has a dummy pin, then each of the driving chips may have a wire and a wire corresponding thereto. Thus, a maximum of Μ*Ν signal wiring can be repaired, wherein PCT and Ν are positive integers. Furthermore, since the dummy wiring, the first repair wiring, and the second repair wiring occupy a small layout area, the number of the configurable wiring, the first repair wiring, and the first repair wiring is not easily limited by the total line layout area. Therefore, the number of signal wirings that can be repaired by the repair method of the peripheral circuit of the active device array substrate of the present invention can be very good. In this way, the yield of the active device array substrate can be effectively improved. It should be noted that the repairing method of the peripheral circuit of the active component of the present invention is not limited to repairing the active device array substrate, and it is also possible to use other wire component array substrates of the Dragon. In summary, since the present invention adopts the structure of the first repair wiring and the second lion-finishing wiring in the peripheral line area, it can be used to repair the defect of the signal wiring in the peripheral line area. In addition, the structure and the layout of the dirt road are small, so the number of wiring, the first repair wiring, and the second number are not easily affected by the ship system. Therefore, the present invention is capable of repairing the letter = yield. Weiduo's can effectively improve the active device array substrate. The signal wiring that can be repaired by the present invention includes the data wiring and the material wiring. The signal wiring that can be repaired by the prior art is limited to the connection.弁^ is the wire component of the present invention. The yield of the substrate can be effectively wired and the reason. In addition, the design of the MV repair wiring and the second repair wiring of the active device array substrate of the present invention is relatively simple, and the circuit provided by the (four) display surface (four) repair wiring must bypass the printing of 18 1360706 0610104ITW 21556twf.doc/n The board is so complicated. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the connection relationship between a thin film transistor array substrate and a driving circuit thereof. Fig. 2 is a schematic view showing a repair wiring group and a disk drive circuit of the thin film transistor array of Fig. 1. 3 is a top plan view of an active device array substrate in accordance with an embodiment of the present invention. FIG. 4 is a schematic diagram of a repair method of a peripheral line of an active device array substrate according to an embodiment of the invention. Figure 5 is a schematic illustration of a method of repairing a peripheral line of an active device array substrate in accordance with another embodiment of the present invention. Soil [Main component symbol description] 110: Thin film transistor array substrate 112, 112'··Data wiring 112a 'Poor material wiring upper section 112b · Data wiring lower section 114: Scanning wiring U6: Thin film transistor 120: Driving circuit 1360706 0610104ITW 21556twf. Doc/n 122: source driver 124: first printed circuit board 126: second printed circuit board 128: gate driver 210: repair wiring group 212a: first repair wiring 212b: dummy wiring 212c: second repair wiring 220a, 220b: intersection 300, 300a, 300b: active device array substrate 310: substrate 320: halogen array 322: halogen structure 322a: thin film transistor 322b: halogen electrode 330: signal wiring 332, 332a, 332b: data wiring 334 : scan wiring 340 : pseudo wiring 340a : first dummy wiring 340b : second dummy wiring 350 . driving wafer 352 : first side 354 : second side 20 1360706 0610104ITW 21556twf.doc / n 356 : signal pin. 358 : Proposed pin 360 : First repair wiring 370 : Second repair wiring 382 : First fusion joint 382 ′: Fifth fusion joint 384 : Second fusion joint 384 ′ : Sixth fusion joint * . 386 : Third fusion joint 38 6': seventh weld joint 388: fourth weld joint 388': eighth weld joint A · display area B: peripheral line area D, D': defect E, G: path φ Η, I: cut point 21