1360103 _ 100年11月23日修正替換頁 、 九、發明說明： --~-——_____ _ 【發明所屬之技術領域】 本發明涉及一種移位暫存器，尤其是指一種利用一放電電路來降低偏 ·- 壓效應（Stress)與增加輸出級（OutputStage)穩態時間之移位暫存器。 【先前技術】 功能先進的顯示器漸成為現今消費電子產品的重要特色，其中液晶顯 不器已經逐漸成為各種電子設備如行動電話、個人數位助理(PDA)、數位相 Φ 機、電腦螢幕或筆記型電腦螢幕所廣泛應用具有高解析度彩色螢幕的顯示 器。 • 移位暫存器（shift register)為液晶顯示面板之驅動電路中之一重要結 構，其用以驅動液晶顯示面板中各級顯示電路，因此移位暫存器之電路設 計對液晶顯示面板之效能具有決定性之影響。 請參閱第1圖’第1圖係先前技術之液晶顯示器中單級移位暫存器10 _ 之電路結構圖。該移位暫存器（shift register) 10主要包含一 CK時脈訊號 拉低模組（CK pull-down module) 12、一 XCK時脈訊號拉低模組（XCK pull-down module) 14 與一主要拉低模組（key pull-down module) 16。CK 時脈訊號與XCK時脈訊號之相位差為180度。CK時脈訊號拉低模組12由 - 五個電晶體T109、T110、T111、T112、T113組成，當CK時脈訊號為高電 位時（即XCK時脈訊號為低電位時），電晶體Τ112與Ή10被打開，使節 點Q (即閘極線，gate line)與電晶體Τ102之閘極之電位經由電晶體Τ110 拉低至VSS電位。XCK時脈訊號拉低模組14由六個電晶體T103、T104、 6 1360103 100年11月23日修正替換頁 T105、T106、T107、T108 組成，當 XCK 時脈訊號為- . 脈訊號為低電位時）’電晶體T104與T106被打開，使節點q與電晶體丁1〇2 之閘極之電位經由電晶體T106拉低至VSS電位。主要拉低模組16由兩個 電晶體T116、T117組成’用以在電晶體T101輸出一輪出訊號到節點Q後， 迅速將節點Q與電晶體Τ102之閘極之電位經由電晶體τι 17拉低至vSS電 位。移位暫存器10另包含一電晶體Τ121，用以控制輸出下一級的驅動節點 N+1 ST。 籲 在先前技術之移位暫存器10中’輸出節點N ST負責將驅動訊號輸出 到面板内之相應畫素’驅動節點N+1 ST則負責將驅動訊號輸出到下一級移 - 位暫存器。然而’由於先前技術之移位暫存器10之電路結構，CK時脈訊 齡:低模組12或XCK時脈訊號拉健組14可能會隨著工作時間的增加， 導致其中之電晶體因為偏壓效應（Stress)而失效，使整個移位暫存器產生 電路誤動作，進而導致所對應之面板内晝素無法正常運作。 籲 目此’有必要提出一種移位暫存器，其可在CK時脈訊號拉低模組或 xck時脈訊號拉低模組發生故障時，仍能有效地降低輸出級之偏壓效應， 使輸出級之輸出峨迅速到達觀，以増加輸出級穩態時間。 【發明内容】 g)jtb 触#提供—翻用—放電電路來降低偏壓效 應與增加輸出級穩態時間之移位暫存器。 依據本發明之上述目的’本發明提供—種單級移位暫存器，其包含一 1360103 100年11月23日修正替換頁 包含一第一時脈訊號拉低模組、一第二時脈訊號拉低^且、一第一主姜哀一一_ 低模組、-第二主要拉低模組與一放電電路。當該第一時脈訊號拉健組 或第二時脈訊號拉健組發生電路異常而使移位暫存器電路無法正常放電 時’該放電電路可持續對歸位暫抑f路進行放電，崎低移位暫存器 電路之偏壓效應4外，該放電電路之放電速度係'遠小於移位暫存器電路 被充電至高電位時之充電速度’故不會影響移位暫存器電路在進行充電時 之正常運作。 該放電電路可為一等效二極體電路，該等效二極體電路可利用閘極與 没極電性連接之-電晶體來實現，其中該電晶體之閘極通道之長度可遠小 於寬度，以使該放電電路之放電速度遠小於移位暫存器電路被充電至高電 位時之充電速度。 該放電電路可·電阻或電容來卿該放電輪之放電速度。 本發明之移位暫存器可在第一時脈訊號拉低模組或第二時脈訊號拉低 模組發生轉時，健·娜㈣存胃電路進行魏，可纽地降低輸 出級之偏壓效應，進而使輸{狀輸ώ城迅朗義態，錄出級之穩 態時間增加。 【實施方式】 明參閱第2圖，第2圊為-液晶顯示器2〇〇之功能方塊圖。液晶顯示 器200包含-液晶顯示面板212、一間極驅動器(g細加㈣叫以及一源 極驅動器(S_eDriVer)216。液晶顯示面板212包含複數個像素，而每一個 像素包s二個分別代表紅綠藍邮3)三原色的像素單元22〇構成。閉極驅動 8 1360103 100年11月23日修正替換頁1360103 _November 23, 100 revised replacement page, nine, invention description: --~--_____ _ Technical Field of the Invention The present invention relates to a shift register, in particular to a discharge circuit To reduce the bias and pressure effect (Stress) and increase the output stage (OutputStage) steady state time shift register. [Prior Art] Advanced display has become an important feature of today's consumer electronics products, and LCD display devices have gradually become various electronic devices such as mobile phones, personal digital assistants (PDAs), digital phase Φ machines, computer screens or notebooks. A display with a high-resolution color screen is widely used on computer screens. • Shift register is one of the important structures in the driving circuit of the liquid crystal display panel, which is used to drive the display circuits of various stages in the liquid crystal display panel. Therefore, the circuit design of the shift register is applied to the liquid crystal display panel. Performance has a decisive impact. Please refer to FIG. 1 'FIG. 1 is a circuit diagram of a single-stage shift register 10 _ in a prior art liquid crystal display. The shift register 10 mainly includes a CK pull-down module 12 and an XCK pull-down module 14 and a The main key pull-down module 16 is used. The phase difference between the CK clock signal and the XCK clock signal is 180 degrees. The CK clock signal pull-down module 12 is composed of - five transistors T109, T110, T111, T112, T113. When the CK clock signal is high (ie, the XCK clock signal is low), the transistor Τ 112 The Ή10 is turned on, and the potential of the gate of the node Q (ie, the gate line) and the transistor Τ102 is pulled down to the VSS potential via the transistor Τ110. The XCK clock signal pull-down module 14 is composed of six transistors T103, T104, 6 1360103, November 23, 2014, correction replacement pages T105, T106, T107, T108, when the XCK clock signal is -. The pulse signal is low. At the time of the potential, the transistors T104 and T106 are turned on, and the potential of the gate of the node q and the transistor D1 is pulled down to the VSS potential via the transistor T106. The main pull-down module 16 is composed of two transistors T116 and T117. After outputting a round of signals to the node Q in the transistor T101, the potential of the gate of the node Q and the transistor Τ102 is quickly pulled through the transistor τι 17 As low as vSS potential. The shift register 10 further includes an transistor Τ121 for controlling the output of the drive node N+1 ST of the next stage. In the prior art shift register 10, the output node N ST is responsible for outputting the driving signal to the corresponding pixel in the panel. The driving node N+1 ST is responsible for outputting the driving signal to the next level of shift-bit temporary storage. Device. However, due to the circuit structure of the prior art shift register 10, the CK clock age: the low module 12 or the XCK clock signal pull group 14 may increase with the working time, causing the transistor to be The bias effect (Stress) fails, causing the entire shift register to cause a circuit malfunction, which in turn causes the corresponding panel internals to fail to operate normally. It is necessary to propose a shift register that can effectively reduce the bias effect of the output stage when the CK clock signal pull-down module or the xck clock signal pull-down module fails. The output of the output stage is quickly reached to the output stage to increase the steady state time of the output stage. SUMMARY OF THE INVENTION g) jtb touch #provide-reverse-discharge circuit to reduce the bias effect and increase the output stage steady state time shift register. According to the above object of the present invention, the present invention provides a single-stage shift register, which includes a 1360103, a modified replacement page on November 23, 100, including a first clock signal pull-down module, and a second clock. The signal pulls down ^, and a first main ginger _ _ low module, - the second main pull low module and a discharge circuit. When the first clock signal pull group or the second clock signal pull group generates a circuit abnormality and the shift register circuit cannot be normally discharged, the discharge circuit can continue to discharge the home return f path. In addition to the bias effect 4 of the low shift register circuit, the discharge speed of the discharge circuit is 'far less than the charging speed when the shift register circuit is charged to a high potential', so the shift register circuit is not affected. It works normally when charging. The discharge circuit can be an equivalent diode circuit, and the equivalent diode circuit can be realized by using a gate and a galvanically connected transistor, wherein the length of the gate channel of the transistor can be much smaller than The width is such that the discharge speed of the discharge circuit is much less than the charge speed at which the shift register circuit is charged to a high potential. The discharge circuit can use a resistor or a capacitor to clarify the discharge speed of the discharge wheel. The shift register of the present invention can perform the rotation of the first clock signal pull-down module or the second clock signal pull-down module, and Jian Na (four) saves the stomach circuit to perform Wei, and can reduce the output level The biasing effect, in turn, causes the transmission to change, and the steady-state time of the recording stage increases. [Embodiment] Referring to Fig. 2, the second block is a functional block diagram of the liquid crystal display 2A. The liquid crystal display 200 includes a liquid crystal display panel 212, a pole driver (g) and a source driver (S_eDriVer) 216. The liquid crystal display panel 212 includes a plurality of pixels, and each of the pixel packs s represents a red color. Green and blue mail 3) The pixel unit 22 of the three primary colors is configured. Closed-circuit drive 8 1360103 November 23, 100 revised replacement page
器214輸出掃描訊號使得每一列的電晶體222依序^啟，同時源極驅動裏一'一' 216則輸出對應的資料訊號至一整列的像素單元220使其充電到各自所需的 電壓’以顯示不同的灰階。當同一列充電完畢後，閘極驅動器214便將該 列的掃描訊號關閉，然後閘極驅動器214再輸出掃描訊號將下一列的電晶 體222打開’再由源極驅動器216對下一列的像素單元220進行充電。如 此依序下去’直到液晶顯示面板212的所有像素單元220都充電完成，再 重頭從第一列開始充電。在目前的液晶顯示面板設計中，閘極驅動器214 之控制電路等效上係為移位暫存器(Shift Register)，其目的即每隔一固定間 隔輸出掃描訊號至液晶顯示面板212。 請參閱第3圖，第3圖係本發明之一單級移位暫存器3〇之電路結構圖。 移位暫存器30係應用於一液晶顯示器中以實現上述之閘極驅動器之控制電 路。移位暫存器30包含一第一時脈訊號拉低模組32、一第二時脈訊號拉低 模組34、一第一主要拉低模組36、一第二主要拉低模組38與一放電電路 D300。該第一時脈訊號與第二時脈訊號之相位差為18〇度，該第一時脈訊 號可為一 CK時脈訊號，該第二時脈訊號可為一 xck時脈訊號。 第' —時脈訊號拉低模組32由五饱電晶體Τ309、Τ310、Τ312、Τ313、 Τ332組成’當第-時脈訊號為高電位時(即第二時脈訊號為低電位時)，電 曰曰體Τ312與Τ310被打開，使節點Q (即閘極線，gate丨丨此）與電晶體Τ3〇2、 Τ331之閘極之電位經由電晶體Τ310拉低至辦電位。第二時脈訊號拉低 模組34包含-電晶體T303，當第二時脈訊號為高電位時（即第一時脈訊號 為低電位時電晶體T303被打開，使節點piXELN之電位經由電晶體T3〇3 9 100年11月23日修正替換頁 拉低至VSS電位。第一主要拉低模組36由兩個電晶άτ315、五16組成， 用以在第Ν+1級驅動訊號STN+1輸入到電晶體Τ315、Τ316之閘極時，使 電晶體Τ315、Τ316打開，而將節點PIXELN之電位經由電晶體Τ315拉低 至VSS電位，並將電晶體Τ302、Τ331之閘極電位（節點Q)經由電晶體 Τ316拉低至VSS電位。第二主要拉低模組38由兩個電晶體Τ333、Τ334 組成，用以在第Ν+2級驅動訊號STN+2輸入到電晶體Τ333、Τ334之閘極 時’使電晶體Τ333、Τ334打開，而將電晶體Τ302、Τ331之閘極電位（節 點Q)經由電晶體Τ333拉低至VSS電位，並將節點STN之電位經由電晶 體Τ334拉低至VSS電位。 放電電路D300可視為一等效二極體電路’其藉由等效二極體電路將節 點Q以順向偏壓之形式連接到VSS電位。換句話說，放電電路D300利用 一等效二極體電路對節點Q進行放電，使節點Q之電位（即電晶體Τ302、 Τ331之閘極電位）不會因電荷累積而產生偏壓效應。特別是當第一時脈訊 號拉低模組32或第二時脈訊號拉低模組34發生電路異常而使節點Q之電 位無法正常放電時，放電電路D3〇〇可確保電晶體Τ3〇2、Τ331不會被打開 而維持移位暫存器電路之正常運作。請參閱第4圖，第4圖係移位暫存器 30之各f卩點之訊號時序圖。其中節點q之電位在時間之後即呈低電位， 放電電路D300可在時間T3後持續釋放節點Q之電荷，使節點q可保持低 電位。 請參閱第5圖，第5圖係放電電路D300之電路示意圖。放電電路D300 可將一電晶體T52〇之閘極（Gate)與汲極（Drain)電性導通，即可在節點 1360103 ~ ------ 100年11月23日修正替換頁 Q與電位vss之間形成-呈順向偏壓之二極體電路。[然而，當正;-. - 訊號（如第N-1級驅動訊號STN-1)輸入到電晶體T502'T531之閘極時， 節點Q必須保持在高電位，使移位暫存器可正常運作。因此，電晶體丁52〇 在導通時之放電速度須遠小於節點q被充電至高電位時之充電速度，使節 點Q在正常充電時可忽略電晶體Τ52〇之放電速度。故電晶體τ52〇其閉極 通道之長度須遠大於寬度。在本發明之實施例中，寬長比（鬚In她） 設置為約6/240，亦即寬長比約為·。如此—來，節點⑽正常充電時即 • $會受龍晶體T52G之放電速度影響，而可維持雜暫存器電路之正常運 作；當節點Q須維持在低電位時，則可藉由電晶體T52〇持續進行放電，以 . 降麟點Q之讎聽並增加雜雜ϋ輸恤之穩態時間。 請參閱帛6"與_ ’為放電電路D300之其他實施例之電路示意圖。 在第6a圖中，電晶體Τ602之汲極與源極（s〇urce)之間電性連接一電容 C62 ’電容C62可用以降低整體放電電路之放電速率，以調節放電電路之放 電速率。在第6b圖卜電晶體刪之沒極與節點Q (或節點N、Q+N) 之間電性連接-電阻R6〇 ’並在節點Q與電位vss之間電性連接一電容 C64，電阻R60與電容⑽同樣可用以降低整體放電電路之放電速率，以 調節放電電路之放電速率。 她於先前技術，本發明之移位暫存器可在第一時脈訊號拉健組或 第二時脈訊號拉低模組發生故障時，仍能持續對節點Q進行放電，可有效 地降低輸出級之偏驗應，進而使輸出級之輸出城财職穩態，使輸 出級之穩態時間增加。 11 1360103 100年11月23日修正替換頁 以上所述繼她權魏料，物 依本發明之精神所作之等效修飾或，輪蓋於伽之㈣專郷圍内。 【圖式簡單說明】 第1圖為先前技術之單級移位暫存器之電路結構圖。 第2圖為一液晶顯示器之功能方塊圖。 第3圖為本發明之單級移位暫存结構圖。 第4圖為第3圖中該移位暫存器各節點之訊號時序圖。 第5圖係一放電電路之電路示意圖。 第6&與6b圖為該放電電路之其他實施例之電路示意圖。 【主要元件符號說明】 200 液晶顯示器 212 液晶顯示面板 214 閘極驅動器 216 源極驅動器 220 像素單元 222 電晶體 30 移位暫存器 32 第一時脈訊號拉低模組 34 第二時脈訊號拉低模組 36 第一主要拉低模組 38 第二主要拉低模組 C62、C64 電容 R60 電阻 D300 放電電路 T301-T334 電晶體 T501-T631 電晶體 T602、T604 電晶體 CK 第一時脈訊號 XCK 第二時脈訊號 Q、N 節點 12The 214 outputs a scan signal such that the transistors 222 of each column are sequentially turned on, and a 'one' 216 of the source driver outputs a corresponding data signal to an entire column of pixel units 220 to charge them to respective required voltages. To show different gray levels. After the same column is charged, the gate driver 214 turns off the scan signal of the column, and then the gate driver 214 outputs the scan signal to turn on the transistor 222 of the next column. Then the source driver 216 pairs the pixel unit of the next column. 220 is charged. Thus, the sequence is continued until all the pixel units 220 of the liquid crystal display panel 212 are charged, and then the charging is started from the first column. In the current liquid crystal display panel design, the control circuit of the gate driver 214 is equivalently a shift register, and the purpose is to output a scan signal to the liquid crystal display panel 212 every fixed interval. Please refer to FIG. 3, which is a circuit diagram of a single-stage shift register of the present invention. The shift register 30 is applied to a liquid crystal display to implement the control circuit of the above-described gate driver. The shift register 30 includes a first clock signal pull-down module 32, a second clock signal pull-down module 34, a first main pull-down module 36, and a second main pull-down module 38. With a discharge circuit D300. The phase difference between the first clock signal and the second clock signal is 18 degrees. The first clock signal can be a CK clock signal, and the second clock signal can be an xck clock signal. The '-clock signal pull-down module 32 is composed of five-saturated crystals Τ 309, Τ 310, Τ 312, Τ 313, Τ 332 ′ when the first-clock signal is high (ie, when the second clock signal is low), The electric rafts 312 and Τ 310 are turned on, so that the potential of the gates of the node Q (ie, the gate line, gate) and the transistors 〇3〇2, Τ331 is pulled down to the potential through the transistor Τ310. The second clock signal pull-down module 34 includes a transistor T303. When the second clock signal is high (ie, the first clock signal is low, the transistor T303 is turned on, so that the potential of the node piXELN is electrically Crystal T3〇3 9 November 23, 100, the replacement page is pulled down to the VSS potential. The first main pull-down module 36 is composed of two electro-crystals 315τ315, five 16 for driving the signal ST +1 at the +1st stage. When +1 is input to the gates of the transistors Τ315 and Τ316, the transistors Τ315 and Τ316 are turned on, and the potential of the node PIXELN is pulled down to the VSS potential via the transistor 315, and the gate potentials of the transistors Τ302 and Τ331 are turned ( The node Q) is pulled down to the VSS potential via the transistor Τ 316. The second main pull-down module 38 is composed of two transistors Τ333 and Τ334 for inputting to the transistor Τ333 at the Ν+2 stage driving signal STN+2, When the gate of Τ 334 is turned on, the transistor Τ 333 and Τ 334 are turned on, and the gate potential (node Q) of the transistors Τ 302 and Τ 331 is pulled down to the VSS potential via the transistor Τ 333, and the potential of the node STN is pulled through the transistor Τ 334. As low as VSS. Discharge circuit D300 can be regarded as an equivalent diode 'It connects the node Q to the VSS potential in the form of a forward bias by an equivalent diode circuit. In other words, the discharge circuit D300 discharges the node Q by an equivalent diode circuit, so that the node Q The potential (ie, the gate potential of the transistors Τ302, Τ331) does not cause a bias effect due to charge accumulation, especially when the first clock signal pull-down module 32 or the second clock signal pull-down module 34 generates a circuit. When the abnormality causes the potential of the node Q to fail to be discharged normally, the discharge circuit D3 ensures that the transistor 〇3〇2, Τ331 will not be opened to maintain the normal operation of the shift register circuit. Please refer to Fig. 4, page 4. The signal timing diagram of each f卩 point of the shift register 30. The potential of the node q is low after time, and the discharge circuit D300 can continuously release the charge of the node Q after the time T3, so that the node q can Keep the low potential. Please refer to Figure 5, Figure 5 is the circuit diagram of the discharge circuit D300. The discharge circuit D300 can electrically connect the gate of a transistor T52 to the drain (Drain). Node 1360103 ~ ------ November 23, 100 revised Forming a positive-biased diode circuit between the page change Q and the potential vss. [However, when a positive; -. - signal (such as the N-1th drive signal STN-1) is input to the transistor T502'T531 At the gate, the node Q must be kept at a high potential, so that the shift register can operate normally. Therefore, the discharge speed of the transistor 〇52〇 when turned on must be much smaller than the charging speed when the node q is charged to a high potential. The node Q can ignore the discharge speed of the transistor 〇52〇 during normal charging. Therefore, the length of the closed channel of the transistor τ52 must be much larger than the width. In an embodiment of the invention, the aspect ratio (must be in her) is set to about 6/240, i.e., the aspect ratio is about . In this way, when the node (10) is normally charged, it will be affected by the discharge speed of the dragon crystal T52G, and the normal operation of the memory circuit can be maintained; when the node Q is to be maintained at a low potential, the transistor can be used. T52〇 continues to discharge, to listen to and reduce the steady-state time of the miscellaneous miscellaneous. Please refer to 帛6" and _' as a circuit diagram of other embodiments of the discharge circuit D300. In Fig. 6a, a capacitor C62' is electrically connected between the drain and the source of the transistor 602. The capacitor C62 can be used to lower the discharge rate of the overall discharge circuit to adjust the discharge rate of the discharge circuit. In the 6bth diagram, the transistor is electrically connected to the node Q (or the node N, Q+N) and the resistor R6〇' is electrically connected to the capacitor C64 between the node Q and the potential vss. R60 can also be used with capacitor (10) to reduce the discharge rate of the overall discharge circuit to regulate the discharge rate of the discharge circuit. In the prior art, the shift register of the present invention can continue to discharge the node Q when the first clock signal pull group or the second clock signal pull module fails, which can effectively reduce The bias of the output stage should be such that the output stage of the output stage is stable and the steady state time of the output stage is increased. 11 1360103 Revised replacement page on November 23, 100. The above-mentioned equivalent modification of the material in accordance with the spirit of the present invention, or the wheel cover in the gamma (4) special area. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a prior art single-stage shift register. Figure 2 is a functional block diagram of a liquid crystal display. Figure 3 is a diagram showing the single-stage shift temporary storage structure of the present invention. Figure 4 is a timing diagram of the signals of each node of the shift register in Figure 3. Figure 5 is a circuit diagram of a discharge circuit. 6 & 6b are schematic circuit diagrams of other embodiments of the discharge circuit. [Main component symbol description] 200 LCD display 212 Liquid crystal display panel 214 Gate driver 216 Source driver 220 Pixel unit 222 Transistor 30 Shift register 32 First clock signal pull-down module 34 Second clock signal pull Low module 36 First main pull-down module 38 Second main pull-down module C62, C64 Capacitor R60 Resistance D300 Discharge circuit T301-T334 Transistor T501-T631 Transistor T602, T604 Transistor CK First clock signal XCK Second clock signal Q, N node 12