TWI357997B - Outer lead structure, active device array substrat - Google Patents

Description

1357997 AU0702008 25435twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to an external lead structure, an active device array substrate and an optoelectronic device having the same external pin junction, and a method of manufacturing the same, In particular, 2 relates to an external lead structure having a three-dimensional arrangement design, an active device array substrate having a monthly outer lead structure, an optoelectronic device, and a bean manufacturing method. ^

[Prior Art] At present, liquid crystal displays are widely used in mobile phones, televisions, notebooks, brains and other electronic products, and in response to market demand, in addition to liquid crystal display, the size of the screen surface is constantly increasing, the screen analysis The degree is also constantly increasing, so the output signal of the internal chip of the liquid crystal display or the number of wafers used must also increase. Du Chuanjing shows that the wafer can be connected to the liquid crystal display by several configurations, such as bonding the wafer to the glass.

On the glass substrate (Chip 〇n Glass, CqG), or on the crystal two soft (ChiP〇nFiim, c〇F). And taking the board At present, in terms of the arrangement in which the wafer is bonded to the glass substrate, a plurality of outer leads connected to the wafer and the liquid crystal display are disposed on the glass substrate. In order to respond to the increase in the output signal of the wafer, the number of outer bows is also increased. However, in order to further improve the contact of the contact point, the conventional technique is to reduce the distance between the outer leads on the glass substrate or to reduce the size of the contact of the outer pin. However, when the spacing between the outer pins on the glass substrate is as small as 1357997 AU0702008 25435twf.doc/p degrees, the machine will be affected by the limit of the capacity of the machine. In addition, in order to match: the size of the bump on the wafer is reduced. When the process on the wafer is used, the shear strength of the bumps is lowered, so that the bumps are easily detached to make the guilty low, thereby increasing the manufacturing cost. SUMMARY OF THE INVENTION The present invention relates to an external pin structure and a method of manufacturing the same, which may be added

= Outer pin density and does not require the size between the contacts on the substrate: shrink or 疋% small contacts. The invention further relates to an active device array substrate and an i manufacturing method for increasing the turn-off signal of a wafer disposed on an active device array substrate. The present invention also relates to an optoelectronic device and a method of fabricating the same that can improve the resolution of a display panel in an optoelectronic device. To specifically describe the contents of the present invention, an external pin structure is proposed and the outer pin structure is disposed on a substrate. The outer pin structure includes a plurality of first outer leads, a plurality of second outer leads, and a patterned dielectric layer. The first outer pin is disposed on the substrate, and the first outer pin includes a plurality of substantially parallel first wires and a plurality of first contacts at the ends of the first wires. The second outer lead is disposed on the substrate, and the second outer lead includes a plurality of second wires and a plurality of second contacts at the ends of the second wires, and each of the second contacts and one of the first wires Overlap. The patterned dielectric layer is between the first outer lead and the second outer lead, and the patterned dielectric layer exposes the first connection

Efc 〇 To specifically describe the contents of the present invention, an optoelectronic device is proposed herein, 1357997 AU0702008 25435 twf.doc/p and the optoelectronic device comprises at least one of the above-described external pin structures. To specifically describe the content of the present invention, an active device array substrate is provided. The active device array substrate includes a substrate, a plurality of pixel units, a plurality of first outer leads, a plurality of second outer leads, and a patterning Dielectric layer. The substrate has a display area and a peripheral line area outside the display area, and the pixel unit is disposed in the display area. The first outer pin is disposed in the peripheral line region and electrically connected to the pixel unit, and the first outer pin includes a plurality of first wires and a plurality of first contacts at the ends of the first wires. The second outer pin is disposed in the peripheral circuit region and electrically connected to the pixel unit, and the second outer pin includes a plurality of second wires and a plurality of second contacts at the end of the second wire, and each second The contact partially overlaps one of the first wires. The patterned dielectric layer is disposed between the first outer lead and the second outer lead, and the patterned dielectric layer exposes the first contact. In one embodiment of the invention, the first contacts are aligned along a first direction and the second contacts are aligned along a second direction, and the first direction is substantially parallel to the second direction. In an embodiment of the invention, the second wire overlaps the first wire portion. In an embodiment of the present invention, each of the second wires includes a first segment, a second segment, and a third segment, the first segment overlapping the first wire and connecting the first contact and the second segment being connected to the first segment Between a segment and a third segment, the third segment and the first wire are staggered in parallel with each other. In one embodiment of the invention, the third segment and the first outer lead are fabricated from the same film layer. 1357997 AU0702008 25435twf.doc/p In one embodiment of the invention, at least one of each of the first contacts and each of the second contacts is substantially staggered. In order to specifically describe the contents of the present invention, a method for fabricating an external lead structure is proposed herein, which includes forming a plurality of first-outer pins on a substrate, and the first-outer hearing includes a plurality of substantially parallel n(four) And a plurality of first contacts located at the end of the first wire. A patterned dielectric layer is formed on the substrate and the patterned dielectric layer covers a portion of the first conductor and exposes the first contact. Forming a plurality of second outer leads on the patterned dielectric layer, and the second outer leads include a plurality of second wires and a plurality of second contacts at the ends of the second wires, and the first contacts and the first The wires partially overlap. In order to specifically describe the contents of the present invention, a manufacturing method of an active element array substrate is proposed herein, and a method of manufacturing a wire element array substrate includes the above-described method of manufacturing a pin structure. In order to specifically describe the contents of the present invention, a method of manufacturing a photovoltaic device is proposed herein, and a method of manufacturing the photovoltaic device includes a manufacturing method other than the above. The external pin structure of the present invention allows the first outer pin and the second outer pin to be arranged in a two-dimensional space to improve the prior art by arranging only the two-dimensional plane to make the outer pin The problem that the distribution density of the contacts cannot be improved. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the embodiments of the invention <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; 1 is a schematic view of an outer lead structure according to an embodiment of the present invention, and FIG. 2A is a cross-sectional view of a line along the line of FIG. 1, and FIG. 2B is a cross-sectional view taken along line Π-Π' of FIG. Referring to FIG. 1 , FIG. 2A and FIG. 2B simultaneously, the pin structure 1 本 of the present invention is disposed on a substrate 200 . The substrate 200 may be a transparent substrate (eg, a glass substrate, a quartz substrate, or other substrate), or a flexible substrate (eg, a plastic substrate, a thinned glass substrate, a polyester substrate, a polyketone substrate, a polyether substrate, a polyester substrate, a polyolefin substrate, a polyblock substrate, a polyoxyalkylene substrate, a polycycloolefin substrate, a polycycloalkyl substrate, a polyfluorene substrate, a polyphenol substrate, a polyaldehyde substrate, or Other polymer-based substrates, or combinations thereof, opaque substrates (eg, ruthenium, ceramic, or other substrates), printed circuit boards, flexible printed circuit boards, printed wiring boards, and flexible printed circuits Board, or other suitable board or substrate. The outer lead structure 1A includes a plurality of first outer leads U, a plurality of second outer leads 120, and a patterned dielectric layer 13A. The first outer lead 110 is disposed on the substrate 200, and the first outer lead 110 includes a plurality of substantially parallel first conductive lines 112 and a plurality of first contacts 114 at the ends of the first conductive lines 112, wherein the first The wire 112 is connected to the first contact 114. The second outer lead 120 is also disposed on the substrate 2A. The second outer lead 120 includes a second wire 122 and a second contact 124 ′ at the end of the second wire 122. The second wire 122 is connected to the second contact 124, and each of the second contacts 124 is associated with one of the second contacts 124. The first wires 112 partially overlap. Further, in the present embodiment, the second wire 122 and the first wire 112 may partially overlap. The first outer lead 110 and the second outer lead 120 are at least one of 1357997 AU0702008 25435twf.doc/p, which is a single layer structure or a multi-layer structure. The material is gold, silver, copper, iron, tin, wrong, and transparent material ( Such as: a metal such as zinc, the above alloy, the above-mentioned compound, germanium, titanium, button, aluminum, or a combination thereof, and a transparent material (such as: the above metal nitride, zinc oxide, scale oxide, Record (4), indium zinc oxide, tin zinc oxide, oxidation, zinc oxide, or other materials = combination, or a combination thereof. Or the upper group of the other 'patterned dielectric layer 13 — - between the outer pins 120', that is, the first outer pin (1) pin 00 and the second substantially electrically insulated. Wherein, the _b dielectric layer multi-layer structure, the material thereof comprises an inorganic material (such as H, , or oxidized stone, oxidized, nitrided, oxidized, tm, nitrogen, or the combination thereof), organic material (eg: containing ': di- or compound, polyalcohol, poly-, poly-anthracene, stupid butadiene, poly-phosphorus, polyene, photoresist, polycycloolefin, polycyclic "Class, ::2:Page:: aldehyde, poly-, polyaldehyde, or other polymer, or a combination of the above), or a combination of the above. Patterning the dielectric layer (10) openings 132 to expose The first contact 114. When the autumn eve 130 can also cover only the first portion of the first wire m and the layer = 4 ΐΓ part of the first wire m, and expose the two injured 苐-wire 112 and * And the subsequent conductive layer structure is produced. The first outer pin 11A including the first wire 112 and the second outer pin 12 including the wire 122 are still substantially electrically insulated - transmission signal transmission On the original outer pin, 'b let 1357997 AU0702008 25435^^00/, • However, the outer pin structure 100 of the present invention is not limited thereto, that is, The pin structure 100 can be a conductor structure of two or more layers. For example, the outer pin structure 100 further has a third outer pin (not shown), a fourth outer pin (not shown), and is incorrectly patterned by the second pattern. A dielectric layer (not shown), a third patterned dielectric layer (not shown) is used to separate and insulate. As described above, the external pin structure 100 of the present invention has a first external pin U〇 and a The second outer lead 120 is separated from the first outer lead 110 and the second outer lead 120 by the patterned dielectric layer 13 , so that the first outer lead 110 is substantially electrically insulated from the first outer lead 120 . Therefore, the present invention allows the outer pins 110, 120 to be arranged in a three-dimensional space to improve the density of the outer pins n〇, 12〇 by arranging the outer pins 11〇, 12〇 only on a two-dimensional plane. The problem that cannot be improved. Therefore, the present invention can effectively increase the outer pins 11 〇, 12 基板 on the substrate 200 without reducing the pitch between the contacts 114, 124 or the size of the contacts 114, 124. In other words, the phase of the substrate 200 is effectively improved because the present invention can effectively increase the twist of the outer leads n〇, 12〇. In terms of area, the present invention can configure more external pins 110, 12〇 than the prior art, and the arrangement of more external pins 110, 120 on the substrate 2〇〇 can help to increase the external pins u〇, 12总量 The total amount of transmission signals. Therefore, when the external pin structure 1 〇〇 is applied to the display device, it will help to improve the resolution of the screen. Of course, the present invention may also be the external pin 110 disposed on the substrate 200. The number of 12 turns is the same as the number of outer pins of the prior art 'But the outer pins u〇, 12〇 of the present invention have a smaller area than the outer pins of the prior art. Therefore, the same transfer is performed. In the case of the total amount of signals, the external pins u〇 and 12〇 of the present invention contribute to the reduction of the substrate.

11 1357997 AU0702008 25435twf.doc/p 200 area. Alternatively, the outer leads 110, 120 of the present invention may increase the freedom of configuration of other components (not shown) on the substrate 200. Then, referring to Fig. 1, Fig. 2A and Fig. 2B, the manufacturing method of the outer lead structure 100 of this embodiment is as follows. A plurality of first outer leads 11 形成 are formed on the substrate 2 , and the first outer lead 丨 1 〇 includes a first lead 112 that is substantially parallel and a first contact 114 at the end of the first lead 112 . . Then, a patterned dielectric layer 130 is formed on the substrate 200, and the patterned dielectric layer 130 covers the first conductive line 112 and exposes the first contact 114 as an example, but is not limited thereto. Thereafter, a plurality of second outer leads 120 are formed on the patterned dielectric layer 13A, and the second outer leads 120 include a second wire 122 and a second contact 124 at the end of the second wire 122, and The two contacts 124 partially overlap the first wire 112. The manufacturing method of the lead structure 100 other than the present embodiment can be applied to the manufacturing method of the active element array substrate or to the manufacturing method of the photovoltaic device. When the manufacturing method of the lead structure 1 之外 is applied to the manufacturing method of the active device I1 in the train substrate, the first outer lead 11 〇 and the second outer lead 120 may be combined with the active device array substrate. The conductor lines are simultaneously formed 'and the patterned dielectric layer 130 can be combined with a dielectric layer in the active device array substrate (eg, an insulating film layer, an inner dielectric layer, a protective layer, and a flat layer, a dye layer, or other film) The layers, or the above-described layers, are simultaneously formed. In other words, the fabrication of the lead structure 100 other than the present embodiment can be compatible with the active device array process. Furthermore, the manufacturing method of the lead structure 100 other than the present embodiment is taken as an example in the form of deposition, exposure, and residual, but is not limited thereto. It may also be an inkjet method, a screen printing method, a deposition method, and a laser stripping method. 12 1357997 AU0702008 25435twf.doc/p A (laser ablation) mode, or other means, or a combination of the above. In this embodiment, the second wire 122 includes a first segment 122a, a first leg 122b, and a third segment 122c. The first segment 122a overlaps the portion of the first wire 112 and is directly connected to the second contact 124. The second segment 122b is connected between the second segment 122a and the third segment i22c. The third segment 122c and the first wire 112 are arranged in parallel with each other, and the third segment 122c and the second segment 12邡 are partially enlarged and are electrically connected by the contact window 134. The third segment i22c and the first outer lead 110 may be made of the same film layer. In other embodiments, the third segment 122c and the first outer lead 11A may also be fabricated from different layers. In other words, the outer pin structure has a first outer pin and a second outer pin made of different film layers, but not limited thereto, and can also be made of the same film layer. In this embodiment, the first contacts 114 may be arranged along a direction a and the second contacts 124 may be aligned along a second direction b, and the first direction A and the second direction B are substantially parallel. That is to say, the arrangement of the first contact 114 and the second contact 124 is synchronously changed. Other various arrangements of the first contact 114 and the second contact 124 will be described below with reference to Figs. Of course, the following description is merely an example of implementation, and the invention is not limited thereto. In addition, referring to FIG. 3, each of the first contacts 314 and each of the second contacts 324 of the external pin structure 3A of the present invention are substantially arranged with high and low interlaces. Further, the arrangement of the first contact 314 and the second contact 324 is synchronously changed. It can be known from the prior art that the high and low staggered contact arrangement helps to increase the distribution density of the contacts, and the present invention has a different position than the first one of the first joints 314 of the same layer. A layer of 13 13357997 AU0702008 25435twf.doc / p, the target ' can be - one, two, three, four, five, six or more and so on. An embodiment in which the outer lead structure 3〇〇 of the present invention is applied to the active element array substrate will be further explained below. Of course, the following is an example of implementation of the county, and the present invention is not limited thereto. Figure 7 is a diagram showing an active device array substrate according to an embodiment of the present invention. Referring to FIG. 7, the active device array substrate 7 of the present invention includes a substrate 710, a plurality of pixel units 720, a plurality of first outer leads 31A, a plurality of second outer leads 320, and a patterned dielectric layer. 13〇. The substrate 71 has a display area 712 and a peripheral line area 714' outside the display area 712, and the pixel unit 72 is located in the display area 712. The first outer lead 31 is disposed in the peripheral line region 714, and the first outer pin 31 is electrically connected to the pixel unit 720. The second outer lead 32 is disposed in the peripheral line region 7M, and the first outer lead 320 is electrically connected to the pixel unit 720. In addition, the patterned dielectric layer 130 is disposed between the first outer lead 310 and the second outer lead 320, and the patterned dielectric layer 13 〇 exposes the first contact 314. The manner in which the patterned dielectric layer 130 exposes the first contact 314 may be that the patterned dielectric layer 130 has a plurality of openings 132 corresponding to the first contacts 314 or a first portion of the patterned dielectric layer 130 covering portions. The wire 312 exposes the first contact 314 and another portion of the first wire 312. However, the embodiment of the present invention is such that the staggered arrangement of the first outer lead 310 and the second outer lead 320 in one peripheral line region 714 is taken as an example, but is not limited thereto, and the first outer lead 310 and the first The arrangement of the two outer pins 320 may also be selected from at least one of the above embodiments. Moreover, the first outer guide 31〇15 1357997 AU0702008 25435twf.doc/p and the second outer lead 32〇 are disposed in several peripheral line areas 714, as can be seen from the 5th and 5th requirements and the number of peripheral line areas 714 (such as: ^, 2, 3, 4, etc.). Furthermore, the present invention sets the outer lead structure 3A on the active device array substrate 700 as an example, but is not limited thereto. For example, the present invention may also select at least one of the arrangement of the pin structures other than the above embodiments to be disposed on a region where the driving circuit (eg, qc: wafer) is connected to the external component, and the flexible printed circuit board. Any combination of areas where the printed circuit board is connected to the external component, or other area connected to the external component, or any of the above-mentioned areas on the area where the external component is connected. The external component may be a wire, a contact pad, a circuit having a function of transmitting a number, or other components, or any combination thereof. FIG. 8 is a schematic diagram of an optoelectronic device according to an embodiment of the invention. Referring to FIG. 8, in the present embodiment, the external pin structure of the present invention can be applied to the optoelectronic device 800, and the optoelectronic device 800 includes a display panel 81A and at least one electronic component 820. At least one of the display panel 81A and the electronic component 82 is configured with a pin structure for transmitting signals, wherein the external pin structure may be any one or more of the external pin structures described in the above embodiments. When the display panel 810 is a liquid crystal display panel, the display panel 81 can be a transparent display panel, a semi-transmissive display panel, and a reflective display panel color/light panel on the active layer (c〇)〇ron array) Display panel, active layer on color enamel sheet (array 〇nc〇l〇r out) display panel, vertical alignment type (VA) display panel, horizontal switching type (ips) display panel, multi-domain vertical alignment type ( MVA) display panel, twisted nematic (TN) display panel, super twisted nematic (STN) display panel, Fig. 16 1357997 AU0702008 25435twf.doc/p vertical alignment type (PVA) display panel, super pattern vertical alignment type (S-PVA) display panel, advanced large viewing angle (ASV) display panel, edge electric field switching type (FFS) display panel, continuous flame-like arrangement (CPA) display panel, axisymmetric array microcell (ASM) display panel , optically compensated curved alignment (OCB) display panel, super horizontal switching (S-IPS) display panel, advanced super horizontal switching type (AS-IPS) display panel, extreme edge electric field switching type (UFFS) display panel, high score A sub-stabilized alignment type display panel, a dual-view display panel, a triple-view display panel, a three-dimensional display panel or other type of panel, or a combination thereof. In addition, the display panel may also be an organic electroluminescent display panel (such as a Rao organic electroluminescence display panel, a phosphorescent organic electroluminescence display panel, or a combination thereof), and the phosphorescent and fluorescent molecules may be small molecules. , macromolecules, or a combination of the above. Furthermore, the display panel may also be an inorganic electroluminescent display panel, or the display panel may be a hybrid display panel. For example, the liquid crystal display panel has both a liquid crystal component and an electroluminescence component, or is electrically excited. The light display panel has both an organic electroluminescence component and an inorganic electroluminescence component. Furthermore, electronic component 820 can be a control component, an operational component, a processing component, an input component, a memory component, a drive component, a light-emitting component, a protection component, a sensing component, a detection component, or other functional component, or a combination of the foregoing. Types of optoelectronic devices 800 include portable products (such as cell phones, cameras, cameras, notebooks, game consoles, watches, music players, e-mail transceivers, map navigators, digital photos, or the like) 17 1357997 AU0702008 25435twf .doc/p production, audio and video products (such as audio and video projectors or similar products), screens, TV &amp;, / internal / outdoor billboards or panels in the projector.

In summary, the external pin structure of the present invention has a first outer pin and a second outer pin 'and is separated by a patterned dielectric layer - the outer pin and the second outer pin are made - The outer pin is substantially electrically insulated from the second outer pin. Therefore, the present invention can design the three-dimensional space of the external pins to improve the conventional/arranged outer pins on a one-dimensional plane so that the density of the outer pins cannot be increased. Therefore, the present invention can effectively increase the density of the outer pins on the substrate without reducing the pitch between the contacts on the substrate or the size of the contacts. Although the external pin structure is applied to the display device, the resolution of the camp can be improved. Further, in the process of the active device array substrate, the external structure of the present invention can be collectively produced. Therefore, the fabrication of the pin structure other than the present invention does not increase the manufacturing cost and the method is simple, but is not limited thereto. For example, the present; can also be produced without the process of the active device array substrate. X Although the present invention has been disclosed above by way of example, it is not intended to be used by those of ordinary skill in the field of YANG-23, and can be modified and retouched without departing from the spirit of February. The scope of the patent application is subject to the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of an external pin structure on a board in accordance with one embodiment of the present invention. Figure 2A is a cross-sectional view of the Ι-Γ line segment of Figure 1. Figure 2B is a cross-sectional view taken along line η-Π of Figure 1. FIG. 3 is a schematic diagram showing another external pin structure disposed on a substrate of 18 1357997 AU0702008 25435 twf.doc/p according to an embodiment of the invention. FIG. 4 is a schematic diagram showing another external pin structure disposed on a substrate according to an embodiment of the invention. FIG. 5 is a schematic diagram showing still another external pin structure disposed on a substrate according to an embodiment of the invention. FIG. 6 is a schematic diagram showing another external pin structure disposed on a substrate according to an embodiment of the invention.

Figure 7 is a schematic illustration of an active device array substrate in accordance with one embodiment of the present invention. FIG. 8 is a schematic diagram of an optoelectronic device according to an embodiment of the invention. [Main component symbol description] 100, 300, 400: outer pin structure 110, 310: first outer pin 112, 312: first wire 114, 314, 412, 612: first contact 120, 320: second Outer pin

122, 322: second wire 122a: first segment 122b: second segment 122c: third segment 124, 324, 422, 512: second contact 130 patterned dielectric layer 132 opening 134 contact window 19 1357997 AU0702008 25435twf. Doc/p 200, 710: substrate 700: active device array substrate 712: display area 714: peripheral line area 720: pixel unit 800: photovoltaic device 810: display panel 820: electronic component A: first direction B: second direction

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Claims (1)

100-11-29 Revised this day, the scope of the patent application: On the package: - an external pin structure, arranged on a substrate, the outer pin junction includes a plurality of feet, disposed on the substrate, the The first wires of the plurality of second terminals 2 at the first outer lead end and the second outer pins ' at the end of the first wires are disposed on the substrate, and the L wires are located at the second wires a plurality of second θ ^ k-th contacts of the end and one of the first wire portions are re-entered, and each of the first wires is electrically insulated from each of the second contacts; and The electrical layer is located on the first outer leads and exposes: two, - contacts, the second outer leads are formed on the _ dielectric layer, and the first and outer leads are Each of the second outer leads is electrically insulated. 2. The pin structure as described in item 1 of the patent scope of the invention, wherein the first contact is arranged along the -first direction, and the second contacts are along the second direction, and The first direction is substantially parallel to the second direction. 3. The pin structure is as described in item 1 of the patent scope, wherein a wire is partially overlapped with the first wires. 4. The pin structure as described in claim 1, wherein each of the second wires comprises a - segment, a second segment, and a third segment, the first segments and the first wires And overlapping the second contacts, the second segments are connected between the first segments and the third segments, and the third segments and the first wires are staggered in parallel with each other. 5. The pin structure as described in claim 4, wherein 21 1357997 100-11-29 the second segment and the first-outer pins are made of the same film layer. - 6. The pin structure as described in the scope of claim 2, wherein each of the first contacts and between each of the second contacts is substantially staggered.夕^ 7. An active device array substrate comprising: a substrate-substrate having a display area and a plurality of pixel units located on a peripheral line outside the display area, disposed in the display area; a plurality of first-outer (10) Configuring a peripheral unit in the peripheral circuit region electrically connected, the first-outer pins comprising a plurality of first-conductors and a plurality of first-contacts at the ends of the first wires; The foot 'is disposed in the peripheral circuit region and is connected to the plurality of second contacts, and the second outer leads comprise a plurality of second contacts, and the plurality of second contacts are disposed at a plurality of second contacts at the ends of the second wires And each of the first, a point and the - the first wire partially overlap, and each of the second = the second contact is electrically insulated; and, the friend and the respective - patterned dielectric layer are formed in the The first outer pin is connected to the first outer pin, and the second outer pin is formed on the patterned dielectric to be exposed and the first outer pin and each of the second outer pin are electrically connected. insulation. , above, 8.% of the active element board mentioned in item 7 of the patent application scope, wherein the first _ y y 歹丨 歹丨 j is a poor contact point along the thousand squares - the first direction, and the first The first direction is aligned, and the first direction is parallel to the second one. ^ 13⁄4 9. If you are applying for the active component of the system, the J-based 22 1357997 100-11-29 board, wherein the second wires partially overlap the first wires. 10. The active device array substrate of claim 7, wherein each of the second wires comprises a first segment, a second segment, and a third segment, the first segments and the first wires And overlapping the second contacts, the second segments are connected between the first segments and the third segments, and the third segments and the first wires are staggered in parallel with each other. 11. The active device array substrate of claim 1, wherein the third segments and the first outer leads are made of the same film layer. 12. The active device array substrate as described in claim 7 wherein at least one of each of the first contacts and each of the second contacts is substantially staggered. 13. The method of fabricating an external pin structure, comprising: forming a plurality of first outer leads on a substrate, the first outer leads comprising a plurality of substantially parallel first wires and located at the first a plurality of first contacts at the end of the wire; forming a patterned dielectric layer on the substrate, covering a portion of the first wires and exposing the first contacts; and forming on the patterned dielectric layer a plurality of second outer leads, the second outer leads include a plurality of second wires and a plurality of second contacts at the ends of the second wires, and the second contacts and the first wires Partially overlapping, and each of the first wires is electrically insulated from each of the second contacts. A method of manufacturing an active device array substrate, comprising the method of manufacturing a pin structure as described in claim 13 of the patent application. 15. An optoelectronic device comprising at least one pin structure as described in the scope of the patent application No. i 23 1357997 100-11-29. A method of manufacturing an optoelectronic device, comprising the method of manufacturing a pin structure as described in claim 13 of the patent application. twenty four