CN104064567A - Array substrate, display device and manufacture method of the array substrate - Google Patents
Array substrate, display device and manufacture method of the array substrate Download PDFInfo
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- CN104064567A CN104064567A CN201410308893.6A CN201410308893A CN104064567A CN 104064567 A CN104064567 A CN 104064567A CN 201410308893 A CN201410308893 A CN 201410308893A CN 104064567 A CN104064567 A CN 104064567A
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Abstract
The invention discloses an array substrate, a display device and a manufacture method of the array substrate. The array substrate comprises an IC crimping region including an IC region and a terminal region arranged on one side of the IC region and near an edge of the array substrate. The terminal region is provided with a plurality of transmission terminals. The IC region comprises a conductor layer, a first insulating layer, a separating layer and a second insulating layer stacked one by one. Each transmission terminal comprises a first conductive layer which is arranged on the second insulating layer and extends from the terminal region to the IC region. The separating layer is arranged in the IC region and at least overlaps with the first conductive layers extending to the IC region. When a small-size IC chip is adopted, contact failure between the IC chip and the terminals of the array substrate can be prevented. Meanwhile, short circuit risks between the first conductive layers and the conductor layer can be avoided.
Description
Technical field
The present invention relates to flat panel display, particularly the manufacture method of a kind of array base palte, display unit and array base palte.
Background technology
The advantages such as frivolous, low in energy consumption and low radiation that panel display apparatus has, are widely used in various fields.Along with scientific and technological fast development, people are more and more higher for the quality requirements of panel display apparatus, and wide visual angle, ultrathin, narrow frame become the key factor of selecting panel display apparatus gradually.
COG encapsulates (chip on glass), be about to drive chip to be directly bundled in a kind of encapsulation technology on glass, this mode can reduce the volume of whole panel display apparatus greatly, and reduced cabling and the number of plies on printed circuit board (PCB), the size and sophistication of having cut down circuit board, integral body has reduced cost.
Fig. 1 is the structure chart of array base palte frame region COG encapsulation in prior art, as shown in Figure 1, array base palte frame region comprises for binding IC (Integrated Circuit, integrated circuit) region of chip, in this region, comprise IC chip rest area 2, be arranged on the input subarea 1 of IC chip rest area one side, input subarea 3 is provided with a plurality of input terminals 31, be arranged on the output subarea 3 of IC chip rest area opposite side, output subarea 1 is provided with a plurality of lead-out terminals 11.When binding IC chip (not shown), IC chip input pin and input terminal 31 corresponding electrical connection one by one, IC chip output pin and lead-out terminal 11 corresponding electrical connection one by one, to realize the transmission of signal.
Conventionally, to the criterion of IC chip selection, be: the distance D between IC chip input pin and output pin be more than or equal to distance D between array base palte input subarea and output subarea '.In order to realize narrow frame and to reduce costs, the development trend of IC chip is that size is more and more less.But, under the constant prerequisite of array base palte project organization, if IC chip is too small, when IC chip bonding, first make the output pin of IC chip match with lead-out terminal, at this moment, the input pin of IC chip can enter into the cabling district of IC chip rest area, and the input terminal contact area on IC chip terminal pin and array base palte will diminish, and causes the loose contact of IC chip and array base palte terminal, meanwhile, the risk of the inner cabling short circuit of IC also can increase.
Summary of the invention
In view of this, the invention provides a kind of array base palte, comprise IC crimping district, described IC crimping district comprises IC district, and the terminal region that is arranged on IC district one side and close described array base palte edge, described terminal region is provided with a plurality of transmission terminals, described IC district comprises the conductor layer being cascading, the first insulating barrier, separator and the second insulating barrier, described transmission terminal comprises the first conductive layer that is arranged on described the second insulating barrier and extends to described IC district from described terminal region, wherein, described separator is arranged on described IC district and at least overlaps mutually with described the first conductive layer that extends to described IC district.
The present invention also provides a kind of display unit, comprises above-mentioned array base palte, and subtend substrate is oppositely arranged with described array base palte.
The present invention also provides a kind of manufacture method of manufacturing above-mentioned array base palte, comprising: substrate is provided, and described substrate comprises IC crimping district, and described IC crimping district comprises IC district, and the terminal region that is arranged on IC district one side and close described array base palte edge; In described substrate IC district, form conductor layer; On described conductor layer, cover the first insulating barrier; On described first insulating barrier in described IC district, form separator; On described separator and described the first insulating barrier, cover the second insulating barrier; On described the second insulating barrier, form the first conductive layer of transmission terminal, described the first conductive layer extends to described IC district from described terminal region; Wherein, described separator is arranged on described IC district and at least overlaps mutually with described the first conductive layer that extends to described IC district.
Due to the first conductive layer of transmission terminal is extended to IC district from terminal region, when the IC chip of selecting hour, the output pin of IC chip one side is matched with lead-out terminal, the input pin of IC chip opposite side also can guarantee enough overlapping areas with the first conductive layer that extends to IC district, and then reduces the loose contact of IC chip and array base palte terminal.Meanwhile, owing between first conductive layer in IC district and conductor layer, separator being set, increase thickness between the two, when the crimping of IC chip, avoided the short-circuit risks between the first conductive layer and conductor layer.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation in prior art array base palte IC crimping district;
Fig. 2 is the structural representation in a kind of array base palte IC crimping district of providing of the embodiment of the present invention;
Fig. 3 is that Fig. 2 is along the sectional structure chart in a kind of IC crimping district in A-A ' cross section;
Fig. 4 is the binding schematic diagram in a kind of array base palte IC crimping district of providing of the embodiment of the present invention;
Fig. 5 is the structural representation in the another kind of array base palte IC crimping district that provides of the embodiment of the present invention;
Fig. 6 is that array base palte IC crimping district in Fig. 5 embodiment of the present invention is at the partial enlarged drawing of position a;
Fig. 7 is that Fig. 6 is along the sectional structure chart in a kind of IC crimping district in B-B ' cross section;
Fig. 8 is that Fig. 6 is along the sectional structure chart in the another kind of IC crimping district in B-B ' cross section;
Fig. 9 is that Fig. 6 is along the sectional structure chart in the another kind of IC crimping district in B-B ' cross section;
Figure 10 a～10f is the manufacturing flow chart of a kind of array base palte of providing of the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Array base palte generally includes viewing area and rim area, viewing area comprises a plurality of pixel cells that matrix is arranged that are, each pixel cell is provided with thin film transistor switch, by the control of liquid crystal molecule in pixel cell is realized to picture disply, rim area is centered around viewing area surrounding for peripheral circuit is set, so that pixel cell display frame signal to be provided.
Fig. 2 is the structural representation in a kind of array base palte IC crimping district of providing of the embodiment of the present invention.Fig. 3 is that Fig. 2 is along the sectional structure chart in a kind of IC crimping district in A-A ' cross section.As shown in Figure 2, in the rim area of array base palte, comprise that IC crimping district is arranged on the fringe region of array base palte for the IC crimping district of COG encapsulation, conventionally, be arranged on array base palte and compare the outstanding stepped area of subtend substrate.IC crimping district comprises IC district 2, and the terminal region 1 that is arranged on IC district 2 one sides and close array base palte edge, terminal region 1 is provided with a plurality of transmission terminals 12, in the present embodiment, this terminal region 1 is input subarea, transmission terminal 12 is input terminal, that is to say, terminal region 1 is parallel with the edge of array base palte, and transmission terminal 12 is arranged successively along this edge, transmission terminal is corresponding and be electrically connected to one by one near the one end in IC district 2 and IC chip input pin, and transmission terminal extends to array base palte edge away from the one end in IC district 2 and is electrically connected to flexible PCB.The corresponding IC chip position in IC district 2, IC district 2 is provided with many wires, for signal transmission,
Shown in Fig. 3, transmission terminal 12 in terminal region 1 comprises the first metal layer 15 being arranged on substrate 10, IC district 2 comprises the conductor layer 21 being arranged on substrate 10, between the first metal layer 15 and conductor layer 21, insulation disconnects, conductor layer 21 is configured for many wires of signal transmission, can adopt with layer and manufacture with the first metal layer 15; The first insulating barrier 16 covers on the first metal layer 15 and conductor layer 12; In terminal region, the first insulating barrier 16 of 1 is provided with a plurality of via holes 14, expose portion the first metal layer 15; On the first insulating barrier 16, be provided with the first conductive layer 13, the first conductive layers 13 and be electrically connected to the first metal layer 15 by via hole 14, and 1 extend to IC district 2 from terminal region.
When thin film transistor switch structure is the grid layer that stacks gradually, gate insulator, semiconductor layer, source-drain electrode metal level, passivation layer and pixel electrode layer, the first conductive layer 13 can adopt with pixel electrode layer and make with layer, the first insulating barrier can adopt with gate insulator and make with layer, adopt identical material, in same processing step, make, to simplify manufacture craft simultaneously.
IC district 2 opposite side relative with terminal region 1 also includes output subarea 3, output subarea 3 comprises a plurality of lead-out terminals 31, lead-out terminal 31 is near the one end in IC district 2 and the corresponding electrical connection one by one of the output pin of IC chip, lead-out terminal 31 is electrically connected to away from the one end in IC district 2 and the holding wire of viewing area, carries display frame signal.
Due to the first conductive layer 13 of transmission terminal 12 1 is extended to IC district 2 from terminal region, when the IC chip of selecting hour, the output pin of IC chip one side and the transmission terminal 14 of terminal region 1 are matched, the first conductive layer 13 that the input pin of IC chip opposite side also can extend to IC district 2 with transmission terminal 14 guarantees enough overlapping areas, and then reduces the loose contact of IC chip and array base palte terminal.
Research shows by experiment, adopts the IC crimping plot structure of the array base palte in Fig. 2 embodiment, when carrying out IC chip bonding, as described in Figure 5, has the risk of conductor layer 21 short circuits in IC chip pin 5 YuIC districts 2.This is due to when the IC chip bonding, adopt ACF (Anisotropic ConductiveF-Im, anisotropy conductiving glue) as the electrical connection tack coat between IC chip input pin and transmission terminal, for guaranteeing bonding strength and the electricity connectivity between IC chip and array base palte, need under the condition of larger pressure and higher temperature, bind.And ACF6 comprises many conducting particless 61, under the crimp strength of larger pressure, conducting particles 61 can be through the first conductive layer 13 and the first insulating barrier 16, the conductor layer 21 in YuIC district 2 is electrically connected to, so just caused IC chip input pin 5 to be electrically connected to conductor layer 21 by conducting particles 61, be the inner lead short circuit of IC chip and array base palte, cause and show extremely.
Therefore, the present invention has proposed again a kind of new array base palte, both can design under constant prerequisite in array base palte overall routing, distance D between applicable IC chip input pin and output pin be less than distance D between array base palte input subarea and output subarea ' situation, can also avoid the first conductive layer 13 when transmission terminal 12 1 to extend to IC district 2 from terminal region, while being electrically connected to IC chip input pin, the problem of the inner lead short circuit of IC chip and array base palte.
Fig. 5 is the structural representation in the another kind of array base palte IC crimping district that provides of the embodiment of the present invention, and Fig. 6 is that array base palte IC crimping district in Fig. 5 embodiment of the present invention is at the partial enlarged drawing of position a.As shown in Figure 5, in the rim area of array base palte, comprise that IC crimping district is arranged on the fringe region of array base palte for the IC crimping district of COG encapsulation, conventionally, be arranged on array base palte and compare the outstanding stepped area of subtend substrate.IC crimping district comprises IC district 2, and the terminal region 1 that is arranged on IC district 2 one sides and close array base palte edge, terminal region 1 is provided with a plurality of transmission terminals 12, in the present embodiment, this terminal region 1 is input subarea, transmission terminal 12 is input terminal, that is to say, terminal region 1 is parallel with the edge of array base palte, and transmission terminal 12 is arranged successively along this edge, transmission terminal is corresponding and be electrically connected to one by one near the one end in IC district 2 and IC chip input pin, and transmission terminal extends to array base palte edge away from the one end in IC district 2 and is electrically connected to flexible PCB.The corresponding IC chip position in IC district 2, IC district 2 is provided with many wires, for signal, transmits.IC district 2 opposite side relative with terminal region 1 also includes output subarea 3, output subarea 3 comprises a plurality of lead-out terminals 31, lead-out terminal 31 is near the one end in IC district 2 and the corresponding electrical connection one by one of the output pin of IC chip, lead-out terminal 31 is electrically connected to away from the one end in IC district 2 and the holding wire of viewing area, carries display frame signal.
Fig. 7 is that Fig. 6 is along the sectional structure chart in a kind of IC crimping district in B-B ' cross section.Shown in Fig. 6 and Fig. 7, transmission terminal 12 in terminal region 1 comprises the first metal layer 15 being arranged on substrate 10, IC district 2 comprises the conductor layer 21 being arranged on substrate 10, between the first metal layer 15 and conductor layer 21, insulation disconnects, conductor layer 21 is configured for many wires of signal transmission, can adopt with layer and manufacture with the first metal layer 15; The first insulating barrier 16 covers on the first metal layer 15 and conductor layer 12; On first insulating barrier 16 in IC district 2, be provided with separator 22; On separator 22 and the first insulating barrier 16, cover the second insulating barrier 17; On the first insulating barrier 16 of terminal region 1 and the second insulating barrier, be provided with a plurality of via holes 14, expose portion the first metal layer 15; On the second insulating barrier 17, be provided with the first conductive layer 13, the first conductive layer 13 is electrically connected to the first metal layer 15 by via hole 14, and 1 extends to IC district 2 from terminal region, wherein, the separator 22 that is arranged on IC district 2 at least overlaps mutually with the first conductive layer 13 that extends to IC district 2, that is to say, the first conductive layer 13 that extends to IC district 2 the projected area perpendicular to substrate 2 completely and separator 22 overlap mutually.
The first conductive layer 13 comprises a plurality of conducting terminals, and transmission terminal 11 is strip structure, therefore, transmission terminal 11 be also strip structure.Separator comprises a plurality of isolating bars, isolating bar is also strip structure, for guarantee to extend to first conductive layer 13 in IC district 2 can be completely and separator 22 overlap mutually, isolating bar is more than or equal to 5 μ m at the Edge Distance d of the projection perpendicular to substrate 10 and the first metal layer 15, and the width of each isolating bar is more than or equal to the width of conducting terminal.Between adjacent isolating bar, there is default spacing distance, guarantee mutually insulated between adjacent isolating bar.
In the present embodiment, separator is single layer structure, when thin film transistor switch structure is the grid layer that stacks gradually, gate insulator, semiconductor layer, source-drain electrode metal level, passivation layer and pixel electrode layer, the first conductive layer 13 can adopt with pixel electrode layer and make with layer, the first insulating barrier 16 can adopt with gate insulator and make with layer, the second insulating barrier 17 can adopt with passivation layer and make with layer, adopt identical material, in same processing step, make, to simplify manufacture craft simultaneously.
Due to the first conductive layer 13 of transmission terminal 12 1 is extended to IC district 2 from terminal region, when the IC chip of selecting hour, the output pin of IC chip one side and the transmission terminal 14 of terminal region 1 are matched, the first conductive layer 13 that the input pin of IC chip opposite side also can extend to IC district 2 with transmission terminal 14 guarantees enough overlapping areas, and then reduces the loose contact of IC chip and array base palte terminal.Meanwhile, owing between first conductive layer 13 in IC district 2 and conductor layer 21, separator 22 being set, increase thickness between the two, when the crimping of IC chip, avoided the short-circuit risks between the first conductive layer 13 and conductor layer 21.
Fig. 8 is that Fig. 6 is along the sectional structure chart in the another kind of IC crimping district in B-B ' cross section.As shown in Figure 8, in the present embodiment and Fig. 7 embodiment, the difference of IC crimping plot structure is, separator 22 is double-decker, when thin film transistor switch structure is the grid layer that stacks gradually, gate insulator, semiconductor layer, source-drain electrode metal level, passivation layer and pixel electrode layer, separator 22 comprises the semiconductor layer 221 on the first insulating barrier 16 that is arranged on IC district 2, and is layered in the source-drain electrode metal level 222 on semiconductor layer 221.The first conductive layer 13 can adopt with pixel electrode layer and make with layer, the first insulating barrier 16 can adopt with gate insulator and make with layer, and the second insulating barrier 17 can adopt with passivation layer and make with layer, adopts identical material, in same processing step, make, to simplify manufacture craft simultaneously.
The present embodiment is owing to having adopted double-deck separator, in physical structure, further increased the thickness between the first conductive layer 13 and conductor layer 21, when the crimping of IC chip, short-circuit risks between the first conductive layer 13 and conductor layer 21 can further reduce, and also can not increase extra processing step simultaneously.
Fig. 9 is that Fig. 6 is along the sectional structure chart in the another kind of IC crimping district in B-B ' cross section.As shown in Figure 9, in the present embodiment and Fig. 7 embodiment, the difference of IC crimping plot structure is, separator 22 is four-layer structure, when thin film transistor switch comprises the grid layer setting gradually, gate insulator, semiconductor layer, source-drain electrode metal level, passivation layer, the first transparent electrode layer, when interlayer insulating film and the second transparent electrode layer, separator 22 comprises the semiconductor layer 221 on the first insulating barrier 16 that is arranged on IC district 2, be layered in the source-drain electrode metal level 222 on semiconductor layer 221, be layered in the passivation layer 223 on source-drain electrode metal level 222, and be layered in the first transparent electrode layer 223 on passivation layer 223.The first conductive layer 13 can adopt with the second transparent electrode layer and make with layer, and the second insulating barrier 17 can adopt with interlayer insulating film and make with layer.
Under different manufacture crafts, the first transparent electrode layer can be pixel electrode, and the second transparent electrode layer can be public electrode; Or the first transparent electrode layer can be public electrode, the second transparent electrode layer can be pixel electrode.
The present embodiment is owing to having adopted four layers of separator, compare IC crimping plot structure in Fig. 8 embodiment, in physical structure, there is the further thickness having increased between the first conductive layer 13 and conductor layer 21, when the crimping of IC chip, short-circuit risks between the first conductive layer 13 and conductor layer 21 can further reduce, and also can not increase extra processing step simultaneously.
A display unit, comprises the array base palte in above-described embodiment, and the subtend substrate with array base palte is oppositely arranged is provided with liquid crystal layer between array base palte and subtend substrate.The structure in array base palte IC crimping district is consistent with structure in the various embodiments described above, does not repeat them here.
Figure 10 a～10f is the manufacturing flow chart of a kind of array base palte of providing of the embodiment of the present invention.In the present embodiment, the thin film transistor switch structure of array base palte viewing area is grid layer, gate insulator, semiconductor layer, source-drain electrode metal level, passivation layer and the pixel electrode layer stacking gradually.
As shown in Figure 10 a, a substrate 10 is provided, substrate 10 comprises IC crimping district, described IC crimping district comprises IC district, and the terminal region that is arranged on IC district one side and close described array base palte edge; Terminal region 1 at substrate 10 forms the first metal layer 15, and meanwhile, IC district 2 forms conductor layer 21.The first metal layer 15 is made with layer with conductor layer, and mutually insulated interval between the two.The first metal layer 15 and conductor layer 21 are grid layer, can adopt Mo-Al-Mo (molybdenum-aluminium-molybdenum) composite material.
As shown in Figure 10 b, on the first metal layer 15 and conductor layer 21, cover the first insulating barrier 16.The first insulating barrier 16 is gate insulator, can adopt silica or silicon nitride material.
As shown in Figure 10 c, on first insulating barrier 16 in IC district 2, form separator 22.In the present embodiment, separator 22 is single layer structure, and the step that forms separator 22 specifically comprises: on the first insulating barrier 16, form semiconductor layer, etching, development, exposure semiconductor layer form separator 22; Or on the first insulating barrier 16, form source-drain electrode metal level, etching, development, exposure source drain metal layer form separator 22.The corresponding transmission terminal of separator 22, comprises a plurality of isolating bar (not shown)s, and because transmission terminal is strip structure, isolating bar is also strip structure.
The generation type of above-mentioned separator is only a kind of of the present embodiment, separator can also be double-decker, the step that forms separator comprises: on the first insulating barrier, form semiconductor layer, etching, development, exposure semiconductor layer form the first separator, on described the first separator, form source-drain electrode metal level, etching, development, exposure source drain metal layer form the second separator.Stacked the first separator and the second separator form separator 22 jointly.
As shown in Figure 10 d, on separator 22 and the first insulating barrier 16, cover the second insulating barrier 17.The second insulating barrier 17 is passivation layer, can adopt silica or silicon nitride material.
As shown in Figure 10 e, in terminal region, 1 etching the first insulating barrier 16 and the second insulating barrier 17 form at least one via hole 14, expose portion the first metal layer 15.
As shown in Figure 10 f, the first conductive layer 13, the first conductive layers 13 that form transmission terminal on the second insulating barrier 17 1 extend to IC district 2 from terminal region; Wherein, separator 22 is arranged on IC district 2 and at least overlaps mutually with the first conductive layer 13 that extends to IC district 2.The first conductive layer 13 comprises a plurality of conducting terminal (not shown)s, and conducting terminal is also strip structure.For guarantee to extend to first conductive layer 13 in IC district 2 can be completely and separator 22 overlap mutually, separator 22 is more than or equal to 5 μ m at the Edge Distance d of the projection perpendicular to substrate 10 and the first metal layer 15, and the width of each isolating bar is more than or equal to the width of conducting terminal.The first conductive layer is pixel electrode layer, can adopt tin indium oxide (ITO) material.Between adjacent isolating bar, there is default spacing distance, guarantee mutually insulated between adjacent isolating bar.
In the embodiment of another kind of array base palte, thin film transistor switch comprises grid layer, gate insulator, semiconductor layer, source-drain electrode metal level, passivation layer, the first transparent electrode layer, interlayer insulating film and the second transparent electrode layer setting gradually.The manufacture method difference of a kind of array base palte providing with Figure 10 a-10f embodiment is, separator is four-layer structure, the step that forms separator comprises: on the first insulating barrier, form semiconductor layer, etching, development, exposure semiconductor layer form the first separator; On the first separator, form source-drain electrode metal level, etching, development, exposure source drain metal layer form the second separator; On the second separator, form passivation layer, etching, development, exposure passivation layer form the 3rd separator; On the 3rd separator, form the first transparent electrode layer, etching, development, exposure the first transparent electrode layer form the 4th separator.The first separator, the second separator, the 3rd separator and the 4th separator form separator jointly.
On separator and the first insulating barrier, cover the second insulating barrier, on the first transparent electrode layer of the Ji separator the superiors and the first insulating barrier, form the second insulating barrier.The second insulating barrier is interlayer insulating film, can adopt silica or silicon nitride material.
At terminal region etching the first insulating barrier and the second insulating barrier, form at least one via hole 14, expose portion the first metal layer.
On the second insulating barrier, form the first conductive layer of transmission terminal, the first conductive layer extends to IC district from terminal region; Wherein, separator is arranged on IC district and at least overlaps mutually with the first conductive layer that extends to IC district.The first conductive layer comprises a plurality of conducting terminal (not shown)s, and conducting terminal is also strip structure.For guarantee to extend to first conductive layer in IC district can be completely and separator overlap mutually, separator is more than or equal to 5 μ m at the Edge Distance d of the projection perpendicular to substrate and the first metal layer, and the width of each isolating bar is more than or equal to the width of conducting terminal.The first conductive layer is the second transparent electrode layer, can adopt tin indium oxide (ITO) material.
Under different manufacture crafts, the first transparent electrode layer can be pixel electrode, and the second transparent electrode layer can be public electrode; Or the first transparent electrode layer can be public electrode, the second transparent electrode layer can be pixel electrode.
The manufacture method of the first metal layer, conductor layer and first insulating barrier of the manufacture method of a kind of array base palte that the step of formation the first metal layer, conductor layer and the first insulating barrier provides with Figure 10 a-Figure 10 b embodiment is identical, does not repeat them here.
Due to the first conductive layer 13 of transmission terminal 12 1 is extended to IC district 2 from terminal region, when the IC chip of selecting hour, the output pin of IC chip one side and the transmission terminal 14 of terminal region 1 are matched, the first conductive layer 13 that the input pin of IC chip opposite side also can extend to IC district 2 with transmission terminal 14 guarantees enough overlapping areas, and then reduces the loose contact of IC chip and array base palte terminal.Meanwhile, owing between first conductive layer 13 in IC district 2 and conductor layer 21, separator 22 being set, increase thickness between the two, when the crimping of IC chip, avoided the short-circuit risks between the first conductive layer 13 and conductor layer 21.
The manufacture method of a kind of array base palte, display unit and the array base palte above embodiment of the present invention being provided is described in detail, applied specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention meanwhile.
Claims (18)
1. an array base palte, comprise IC crimping district, described IC crimping district comprises IC district, and the terminal region that is arranged on IC district one side and close described array base palte edge, described terminal region is provided with a plurality of transmission terminals, described IC district comprises the conductor layer being cascading, the first insulating barrier, separator and the second insulating barrier, described transmission terminal comprises the first conductive layer that is arranged on described the second insulating barrier and extends to described IC district from described terminal region, wherein, described separator is arranged on described IC district and at least overlaps mutually with described the first conductive layer that extends to described IC district.
2. array base palte as claimed in claim 1, it is characterized in that, described array base palte comprises a plurality of thin film transistor switch, and described thin film transistor switch comprises grid layer, gate insulator, semiconductor layer, source-drain electrode metal level, passivation layer and the pixel electrode layer setting gradually.
3. array base palte as claimed in claim 2, is characterized in that, described separator is single layer structure, with described semiconductor layer or the same layer of source-drain electrode metal level; Described the first conductive layer and described pixel electrode layer are with layer, and described the second insulating barrier and described passivation layer are with layer.
4. array base palte as claimed in claim 2, is characterized in that, described separator is double-decker, comprises the first separator and the second separator, and described the first separator and described semiconductor layer are with layer, and described the second separator and source-drain electrode metal level are with layer; Described the first conductive layer and described pixel electrode layer are with layer, and described the second insulating barrier and described passivation layer are with layer.
5. array base palte as claimed in claim 1, it is characterized in that, described array base palte comprises a plurality of thin film transistor switch, and described thin film transistor switch comprises grid layer, gate insulator, semiconductor layer, source-drain electrode metal level, passivation layer, the first transparent electrode layer, interlayer insulating film and the second transparent electrode layer setting gradually.
6. array base palte as claimed in claim 5, it is characterized in that, described separator is four-layer structure, comprise the first separator, the second separator, the 3rd separator and the 4th separator, the first separator and semiconductor layer are with layer, the second separator and source-drain electrode metal level are with layer, and the 3rd separator and passivation layer are with layer, and the 4th separator and the first transparent electrode layer are with layer; Described the first conductive layer and described the second transparent electrode layer are with layer, and described the second insulating barrier and described interlayer insulating film are with layer.
7. the array base palte as described in claim 2 or 5, is characterized in that, described conductor layer and described grid layer are with layer, and described the first insulating barrier and described gate insulator are with layer.
8. array base palte as claimed in claim 1, it is characterized in that, described separator comprises a plurality of isolating bars, described the first conductive layer comprises a plurality of conducting terminals, described conducting terminal and described isolating bar are strip structure, and described in each, the width of isolating bar is more than or equal to the width of described conducting terminal.
9. array base palte as claimed in claim 1, it is characterized in that, described transmission terminal is also included in the first metal layer, the first insulating barrier and the second insulating barrier stacking gradually below the first conductive layer of described terminal region, described the first insulating barrier and the second insulating barrier are provided with via hole, and described the first conductive layer is electrically connected to described the first metal layer by described via hole.
10. a display unit, comprises as the array base palte of any one in claim 1-9; Subtend substrate, is oppositely arranged with described array base palte.
11. 1 kinds of manufactures, as the manufacture method of any one array base palte in claim 1-9, comprising:
Substrate is provided, and described substrate comprises IC crimping district, and described IC crimping district comprises IC district, and the terminal region that is arranged on IC district one side and close described array base palte edge;
In described substrate IC district, form conductor layer;
On described conductor layer, cover the first insulating barrier;
On described first insulating barrier in described IC district, form separator;
On described separator and described the first insulating barrier, cover the second insulating barrier;
On described the second insulating barrier, form the first conductive layer of transmission terminal, described the first conductive layer extends to described IC district from described terminal region;
Wherein, described separator is arranged on described IC district and at least overlaps mutually with described the first conductive layer that extends to described IC district.
The manufacture method of 12. array base paltes as claimed in claim 11, it is characterized in that, described separator is single layer structure, and the step that forms described separator comprises: on described the first insulating barrier, form semiconductor layer, semiconductor layer forms described separator described in patterning; Or forming source-drain electrode metal level on described the first insulating barrier, source-drain electrode metal level forms described separator described in patterning.
The manufacture method of 13. array base paltes as claimed in claim 11, it is characterized in that, described separator is double-decker, and the step that forms described separator comprises: on described the first insulating barrier, form semiconductor layer, semiconductor layer forms the first separator described in patterning; On described semiconductor layer, form source-drain electrode metal level, source-drain electrode metal level forms the second separator described in patterning.
The manufacture method of 14. array base paltes as described in claim 12 or 13, it is characterized in that, described array base palte comprises a plurality of thin film transistor switch, described thin film transistor switch comprises grid layer, gate insulator, semiconductor layer, source-drain electrode metal level, passivation layer and the pixel electrode layer setting gradually, described conductor layer and described grid layer are with layer, described the first insulating barrier and described gate insulator are with layer, described the second insulating barrier and described passivation layer are with layer, and described the first conductive layer and described pixel electrode layer are with layer.
The manufacture method of 15. array base paltes as claimed in claim 11, it is characterized in that, described separator is four-layer structure, and the step that forms described separator comprises: on described the first insulating barrier, form semiconductor layer, semiconductor layer forms the first separator described in patterning; On described semiconductor layer, form source-drain electrode metal level, source-drain electrode metal level forms the second separator described in patterning; On described source-drain electrode metal level, form passivation layer, passivation layer forms the 3rd separator described in patterning; On described passivation layer, form the first transparent electrode layer, the first transparent electrode layer forms the 4th separator described in patterning.
The manufacture method of 16. array base paltes as claimed in claim 15, it is characterized in that, after described formation the first transparent electrode layer step, also comprise: on described the first transparent electrode layer, form interlayer insulating film, on described interlayer insulating film, form the second transparent electrode layer.
The manufacture method of 17. array base paltes as claimed in claim 16, it is characterized in that, described array base palte comprises a plurality of thin film transistor switch, described thin film transistor switch comprises the grid layer setting gradually, gate insulator, semiconductor layer, source-drain electrode metal level, passivation layer, the first transparent electrode layer, interlayer insulating film and the second transparent electrode layer, described conductor layer and described grid layer are with layer, described the first insulating barrier and described gate insulator are with layer, described the second insulating barrier and described interlayer insulating film are with layer, described the first conductive layer and described the second transparent electrode layer are with layer.
The manufacture method of 18. array base paltes as claimed in claim 11, is characterized in that, in the time of described formation conductor layer step, also comprises: in described terminal region, form the first metal layer;
After described covering the second insulating barrier step, also comprise: described the first insulating barrier in described terminal region
Form via hole with described the second insulating barrier, the first metal layer described in expose portion, described the first conduction
Layer is electrically connected to described the first metal layer by described via hole.
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