1356997 loo年11月16日核正. 六、發明說明： 【發明所屬之技術領域】 [0001]本發明係關於訊號傳輸系統，尤指一種主機板北橋晶片 與記憶體插槽間之訊號傳輸系統。 【先前技術】 [_ f腦主機板所支援之記題_和容量_記憶體插槽 來決定，目則主要應用於主機板上之記憶體插槽有：單 内聯記憶體模組（Single Inline M_Fy MQdule， sIMM)和雙列直插記憶體模組（Dual InHne Mem()i_y Module，DIMM)兩種 〇1356997 loo year November 16th nuclear. VI. Description of the invention: [Technical Field of the Invention] [0001] The present invention relates to a signal transmission system, and more particularly to a signal transmission system between a motherboard Northbridge chip and a memory slot. . [Prior Art] [_ f brain motherboard support of the problem _ and capacity _ memory slot to determine, the purpose is mainly applied to the memory slot on the motherboard: single inline memory module (Single Inline M_Fy MQdule, sIMM) and dual in-line memory modules (Dual InHne Mem() i_y Module, DIMM)
[_記憶體條透過金手指與主機板連接，記憶體條正反兩面 都帶有金手指，金手指可以在兩面提供不同之訊號，也 可以提供相同之訊號。_係一種兩側金手指都提供相 同訊號之記憶體結構，它多用於早期之快頁模式 Page Mode ’ FPM)動態隨機存取記憶體最初一次只能 傳輸8bit資料，後來逐漸發展出l6Mt、32bi^siMM 模組《在記憶體發展進入同步動態隨機存取記憶體（ Synchronous Dynamic Random Access Memory « SDRAM)時代後，SIMM逐漸被DIMM技術取代。 [0004]為了滿足筆記本電腦對記憶體尺寸之要求，小变雙列直 插記憶體模組（Small Outline Dual inline Memory Module，S0-DIMM)也已經被開發出來，其尺 寸比標準之DIMM要小很多，約為普通DIMM體積之65%， 但是存儲能力相同。 096103144 由於S0-DIMM係一種改良型DIMM模組 表單編號A0101 第4頁/共15頁 比一般之DIMM模 1003422227-0 [0005] 1356997 , 100年.11月16日核正替换頁 組體積小，隨著桌上型電腦逐漸趨向小型化，人們想要 將SO-DIMM安裝於桌上型電腦主機板上，以節約主機板空 間，惟，習知之桌上型電腦主機板由於採用DIMM模組， 其佈線與S0-DIMM不能相容，必須針對S0-DIMM設計新的 訊號傳輸系統，才能使S0-DIMM安裝於桌上型電腦主機板 上0 【發明内容】 [0006] 鑒於以上内容，有必要提供一種訊號傳輸系統，使S0-DIMM可安裝於桌上型電腦主機板上，並與北橋晶片進行 資訊傳輸。 [0007] 一種訊號傳輸系統，其包括一北橋晶片、一小型雙列直 插記憶體模組插槽及連接於該北橋晶片與小型雙列直插 記憶體模組插槽之間之複數訊號傳輸線，該複數訊號傳 輸線包括一差分對時鐘訊號線、一控制訊號線、一指令 訊號線、一資料訊號線及一差分對資料過濾訊號線，該 差分對時鐘訊號線、控制訊號線、指令訊號線、資料訊 號線及差分對資料過濾訊號線中每條訊號線均包括一回 避段、一截止段、一軌跡段及一插入段，該控制訊號線 及指令訊號線還分別包括一終端段，該小型雙列直插記 憶體模組插槽透過該控制訊號線及指令訊號線之終端段 各連接一終端電阻，該差分對時鐘訊號線之回避段、截 止段及插入段之佈線長度上限分別為50mils、700mils 及250mils，該差分對時鐘訊號線之轨跡段之佈線寬度在 微波傳輸帶時為6. 5mils，在帶狀線時為6mils，且該差 分對時鐘訊號線之全阻抗為420hm ;該控制訊號線之回避 096103144 表單編號A0101 第5頁/共15頁 1003422227-0 1356997 100年11月16日核正替接百 段、截止段、插入段及終端段之佈線長度上限分別為 lOOmils、700mils ' 250rails及250mils，該控制訊號 線之軌跡段之佈線寬度在微波傳輸帶時為7. 5mi Is，在帶 狀線時為7mils，且該控制訊號線之全阻抗為370hm ;該 指令訊號線之回避段、截止段、插入段及終端段之佈線 長度上限分別為lOOmils、700rails、500mils及 250mils，該指令訊號線之軌跡段之佈線寬度在微波傳輸 帶時為9.5mils，在帶狀線時為9rails，且該指令訊號線 之全阻抗為320hm ;該資料訊號線之回避段、截止段及插 入段之佈線長度上限分別為250mils、700mils及 500mils，該資料訊號線之轨跡段之佈線寬度在微波傳輸 帶時為6.5mils，在帶狀線時為6mils，且該資料訊號線 之全阻抗為400hm ;該差分對資料過濾訊號線之回避段、 截止段及插入段之佈線長度上限分別為250mils、 700mils及500mils，該差分對資料過濾訊號線之執跡段 之佈線寬度在微波傳輸帶時為6. 5mi Is，在帶狀線時為 6mi Is且該差分對資料過濾訊號線之全阻抗為400hm。 [0008] 上述訊號傳輸系統將S0-DIMM與桌上型電腦主機板之北橋 晶片連接，完成資訊傳輸，使用於筆記本電腦主機板之 S0-DIMM可運用於桌上型電腦主機板上，節約了桌上型電 腦主機板空間。 【實施方式】 [0009] 參考圖1，一種訊號傳輸系統10，其包括一北橋晶片12、 一小型雙列直插記憶體模組插槽14及連接於該北橋晶片 12與小型雙·列直插記憶體模組插槽14之間之複數訊號傳 096103144 表單编號A0101 第6頁/共15頁 1003422227-0 1356997 • ， 100年.11月16日接正替換頁 輸線16，該訊號傳輸線包括一差分對時鐘訊號線、一控 制訊號線、一指令訊號線、一資料訊號線及一差分對資 料過濾訊號線，該差分對時鐘訊號線、控制訊號線、指 令訊號線、資料訊號線及差分對資料過濾訊號線中每條 訊號線均包括一回避段ESCAPE、一截止段BREAKOUT、一 軌跡段ROUTING及一插入段BREAKIN。 [0010] 參考圖2，該控制訊號線還包括一終端段TERMINAL 166 ’該小型雙列直插記憶體模組插槽14透過該终端段TER- MINAL 166及一终端電阻Rt與一终端電壓Vtt連接，該指 令訊號線與該控制訊號線結構相同。 [0011] 在本較佳實施方式中，該差分對時鐘訊號線之佈線參數 如下：該差分對時鐘訊號線之全阻抗為420hm，差分阻抗 為700hm，該回避段ESCAPE、截止段BREAKOUT及插入段 BREAKIN之佈線長度上限分別為50mils、700mils及 250mils ;該回避段ESCAPE及截止段BREAKOUT之佈線寬 度為4. 5mils，該轨跡段ROUTING之佈線寬度在微波傳輸 帶時為6.5mils ’在帶狀線時為6mils，該插入段 BREAKIN之佈線寬度為6. 5mils ;該回避段ESCAPE及截 止段BREAKOUT之佈線間距最小為5mils，該軌跡段 ROUTING及插入段BREAK IN之佈線間距最小為20mi Is， 其中該差分對時鐘訊號線之兩條差分訊號傳輸線間距最 小為5 m i 1 s。 [0012] 該控制訊號線之佈線參數如下：該控制訊號線之全阻抗 為370hm，該回避段ESCAPE 160、截止段BREAKOUT 161、插入段BREAKIN 163及終端段TERMINAL 166之佈 096103144 表單編號A0101 第7頁/共15頁 1003422227-0 1356997 100年11月16日梭正替換頁 線長度上限分別為lOOmi Is、7〇〇mi is、250rai Is及 250rails ;該回避段ESCAPE 160及截止段BREAKOUT 161之佈線寬度為4mils，該軌跡段ROUTING 162之佈線 寬度在微波傳輸帶時為7.5mils，在帶狀線時為7mils， 該插入段BREAKIN 163及終端段TERMINAL 166之佈線寬 度為7.5mils ;該控制訊號線之回避段£)5(：斤£ 160及截 止段BREAKOUT 161之佈線間距最小為5mils，該控制訊 號線之軌跡段ROUTING 162、插入段BREAKIN 163及終 端段TERM INAL 166之佈線間距最小為9. 5mi Is。 [0013] 該指令訊號線之佈線參數如下：該指令訊號線之全阻抗 為320hm，該回避段ESCAPE、截止段BREAKOUT、插入段 BREAKIN及終端段TERMINAL之佈線長度上限分別為 lOOmils、700mils、500mils及250rails ;該回避段 ESCAPE及截止段BREAKOUT之佈線寬度為4mils，該軌跡 段ROUTING之佈線寬度在微波傳輸帶時為9. 5mils，在帶 狀線時為9mils，該插入段BREAKIN及終端段TERMINAL 之佈線寬度為分別為9. 5mi Is及7. 5mi Is ;該指令訊號線 之回避段ESCAPE之佈線間距最小為5mils，該指令訊號 線之截止段BREAKOUT之佈線間距最小為4. 5mi Is ,該指 令訊號線之軌跡段ROUTING、插入段BREAKIN及終端段 TERM INAL之佈線間距最小為5. 5mi Is。 [0014] 該資料訊號線之佈線參數如下：該資料訊號線之全阻抗 為400hm，該回避段ESCAPE、截止段BREAKOUT及插入段 BREAKIN之佈線長度上限分別為250mils、700mils及 500rails ;該回避段ESCAPE及截止段BREAKOUT之佈線寬 096103144 表單编號A0101 第8頁/共15頁 1003422227-0 1356997 « 、 100年.11月16日修正替換頁 度為4rails，該轨跡段ROUTING之佈線寬度在微波傳輸帶 時為6.5111丨13，在帶狀線時為611^15，該插入段81^八1(以 之佈線寬度為6. 5mi Is ;該資料訊號線之回避段ESCAPE 及截止段BREAKOUT之佈線間距最小為4. 5mi Is，該資料 訊號線之軌跡段ROUTING及插入段BREAK IN之佈線間距最 小為 17. 5 m i 1 s。 [0015] 該差分對資料過濾訊號線之佈線參數如下：該差分對資 料過濾訊號線之全阻抗為400hm，差分阻抗為700hm，該 回避段ESCAPE、截止段BREAKOUT及插入段BREAKIN之佈 線長度上限分別為250mils、700rails及500mils ;該回 避段ESCAPE及截止段BREAKOUT之佈線寬度為4mils，該 軌跡段ROUTING之佈線寬度在微波傳輸帶時為6. 5mils， 在帶狀線時為6rails，該插入段BREAKIN之佈線寬度為 6. 5mils ;該回避段ESCAPE及截止段BREAKOUT之佈線間 距最小為5mils，該軌跡段ROUTING及插入段BREAKIN之 佈線間距最小為1 8. 5ra i 1 s，其中該差分對資料過濾訊號 線之差分訊號傳輸線間距最小為5mi Is。 [0016] 综上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 熟悉本案技藝之人士 ’在爰依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 [0017] 【圖式簡單說明】 圖1係本發明訊號傳輸系統較佳實施方式之框圖。 [0018] 圖2係本發明訊號傳輸系統較佳實施方式中控制訊號線之 096103144 框圖。 表單編號A0101 第9頁/共15頁 1003422227-0 1356997 100年.11月16日按正替换百 【主要元件符號說明】 [0019] 訊號傳輸系統：10 [0020] 北橋晶片：12 [0021] 小型雙列直插記憶體模組插槽：14 [0022] 訊號傳輸線：1 6 [0023] 回避段：160 [0024] 截止段：161 [0025] 軌跡段：162 [0026] 插入段：163 [0027] 終端段：166 1003422227-0 096103144 表單编號A0101 第10頁/共15頁[_The memory strip is connected to the motherboard through the gold finger. The memory strip has gold fingers on both sides. The gold finger can provide different signals on both sides, and can provide the same signal. _ is a kind of memory structure that provides the same signal on both sides of the golden finger. It is mostly used in the early fast page mode. Page Mode 'FPM) The dynamic random access memory can only transmit 8bit data at a time, and then gradually develops l6Mt, 32bi. ^siMM Module "Since the era of memory development into Synchronous Dynamic Random Access Memory « SDRAM, SIMM has gradually been replaced by DIMM technology. [0004] In order to meet the memory size requirements of notebook computers, the Small Outline Dual inline Memory Module (S0-DIMM) has also been developed, and its size is smaller than standard DIMMs. Many, about 65% of the size of a normal DIMM, but the same storage capacity. 096103144 Because S0-DIMM is a modified DIMM module form number A0101 page 4 / 15 pages than the general DIMM module 1003422227-0 [0005] 1356997, 100 years. November 16 nuclear replacement page group is small, As desktop computers become smaller and smaller, people want to install SO-DIMMs on desktop computer motherboards to save space on the motherboard. However, the conventional desktop motherboards use DIMM modules. The wiring is incompatible with the S0-DIMM. A new signal transmission system must be designed for the S0-DIMM to enable the S0-DIMM to be mounted on the desktop computer board. [Inventive content] [0006] In view of the above, it is necessary A signal transmission system is provided to enable the S0-DIMM to be mounted on a desktop motherboard and transmit information to the Northbridge chip. [0007] A signal transmission system includes a north bridge chip, a small dual in-line memory module slot, and a plurality of signal transmission lines connected between the north bridge chip and the small dual in-line memory module slot The complex signal transmission line includes a differential pair clock signal line, a control signal line, an instruction signal line, a data signal line, and a differential pair data filtering signal line. The differential pair clock signal line, the control signal line, and the command signal line Each of the signal lines of the data signal line and the differential pair data filtering signal line includes a avoidance section, a cutoff section, a track segment and an insertion section, and the control signal line and the command signal line further comprise a terminal segment, respectively. The small dual in-line memory module slot is connected to a terminal resistor through the control signal line and the terminal line of the command signal line, and the upper limit of the wiring length of the avoidance section, the cutoff section and the insertion section of the differential pair clock signal line are respectively 50mils, 700mils, and 250mils, the wiring width of the track segment of the differential pair clock signal line is 6. 5mils in the microstrip and 6mil in the stripline. s, and the total impedance of the differential pair clock signal line is 420hm; the control signal line avoids 096103144 Form No. A0101 Page 5 / Total 15 Page 1003422227-0 1356997 On November 16, 100, the nuclear replacement is one hundred paragraphs, the deadline The upper limit of the wiring length of the segment, the insertion segment and the terminal segment are respectively 100 mils, 700 mils '250 miles and 250 mils, and the wiring width of the track segment of the control signal line is 7. 5 mi Is in the microstrip, 7 mils in the strip line, The total impedance of the control signal line is 370 hm; the upper limit of the wiring length of the avoidance section, the cut-off section, the insertion section and the terminal section of the command signal line are lOOmils, 700 rails, 500 mils and 250 mils respectively, and the wiring of the command signal line segment is The width is 9.5 mils for the microstrip and 9 rails for the stripline, and the full impedance of the command signal line is 320 hm; the upper limit of the wiring length of the avoidance section, the cutoff section and the insertion section of the data signal line is 250 mils, respectively. 700mils and 500mils, the wiring width of the track segment of the data signal line is 6.5mils on the microstrip, 6mils on the stripline, and the full impedance of the data signal is 400h. m; the upper limit of the wiring length of the avoidance section, the cutoff section and the insertion section of the differential pair data filtering signal line are 250 mils, 700 mils and 500 mils respectively, and the wiring width of the differential section of the data filtering signal line is in the microstrip 6. 5mi Is, 6mi Is in the stripline and the full impedance of the differential pair data filtering signal line is 400hm. [0008] The above signal transmission system connects the S0-DIMM to the north bridge chip of the desktop computer motherboard to complete the information transmission, and the S0-DIMM used in the notebook computer motherboard can be applied to the desktop computer motherboard, thereby saving Desktop computer motherboard space. Embodiments [0009] Referring to FIG. 1, a signal transmission system 10 includes a north bridge chip 12, a small dual in-line memory module slot 14, and a north double chip 12 connected to a small double column. The complex signal between the memory module slot 14 is transmitted 096103144 Form No. A0101 Page 6 / Total 15 pages 1003422227-0 1356997 • , 100 years. November 16th Replacement page transmission line 16, the signal transmission line The invention comprises a differential pair clock signal line, a control signal line, a command signal line, a data signal line and a differential pair data filtering signal line, the differential pair clock signal line, the control signal line, the command signal line, the data signal line and Each signal line in the differential pair data filtering signal line includes a avoidance segment ESCAPE, a cutoff segment BREAKOUT, a track segment ROUTING, and an insertion segment BREAKIN. [0010] Referring to FIG. 2, the control signal line further includes a terminal segment TERMINAL 166'. The small dual in-line memory module slot 14 passes through the terminal segment TER-MINAL 166 and a terminating resistor Rt and a terminal voltage Vtt. Connected, the command signal line has the same structure as the control signal line. [0011] In the preferred embodiment, the wiring parameters of the differential pair clock signal line are as follows: the differential impedance of the differential pair clock signal line is 420 hm, the differential impedance is 700 hm, the avoidance section ESCAPE, the cutoff section BREAKOUT, and the insertion section The maximum length of the wiring of BREAKIN is 50 mils, 700 mils and 250 mils respectively; the wiring width of the avoidance section ESCAPE and the cut-off section BREAKOUT is 4.5 mils, and the wiring width of the trajectory section ROUTING is 6.5 mils on the microstrip belt. The wiring width of the insertion section BREAKIN is 6. 5 mils; the wiring spacing of the avoidance section ESCAPE and the cut-off section BREAKOUT is at least 5 mils, and the wiring pitch of the trajectory section ROUTING and the insertion section BREAK IN is at least 20 mi Is, where The difference between the two differential signal transmission lines of the differential pair clock signal line is 5 mi 1 s. [0012] The wiring parameters of the control signal line are as follows: the total impedance of the control signal line is 370 hm, the avoidance section ESCAPE 160, the cut-off section BREAKOUT 161, the insertion section BREAKIN 163, and the terminal section TERMINAL 166 cloth 096103144 Form No. A0101 No. 7 Page / Total 15 pages 1003422227-0 1356997 On November 16, 100, the upper limit of the length of the page replacement line is lOOmi Is, 7〇〇mi is, 250rai Is and 250rails respectively; the routing of the avoidance segment ESCAPE 160 and the cut-off segment BREAKOUT 161 The width is 4 mils, the wiring width of the track segment ROUTING 162 is 7.5 mils on the microstrip, 7 mils on the strip line, and the wiring width of the insertion segment BREAKIN 163 and the terminal segment TERMINAL 166 is 7.5 mils; the control signal line The avoidance section £)5 (: 斤 £ 160 and the cut-off section BREAKOUT 161 has a minimum wiring pitch of 5 mils, and the control signal line trajectory section ROUTING 162, the insertion section BREAKIN 163, and the terminal section TERM INAL 166 have a minimum wiring pitch of 9. 5mi Is. [0013] The wiring parameters of the command signal line are as follows: the full impedance of the command signal line is 320 hm, the avoidance section ESCAPE, the cutoff section BREAKOUT, the insertion section BREAKIN and the terminal 5 mils, in the strip line, the wiring width of the traversing section is 9.5 mils, and the wiring width of the traversing section is 9.5 mils. When the time is 9 mils, the wiring width of the BREAKIN and the terminal segment TERMINAL is 9. 5mi Is and 7. 5mi Is; the routing distance of the ESCAPE of the avoidance segment of the command signal line is at least 5 mils, and the cutoff line of the command signal line is The minimum spacing of the wiring of the BREAKOUT is 4. 5mi Is , the wiring interval of the command signal line ROUTING, the insertion section BREAKIN and the terminal section TERM INAL is at least 5. 5mi Is. [0014] The wiring parameters of the data signal line are as follows: The full impedance of the data signal line is 400hm, and the upper limit of the cabling length of the ESCAPE, the cutoff section BREAKOUT and the insert section BREAKIN are 250mils, 700mils and 500rails respectively; the cabling width of the ESCAPE and the cutoff section BREAKOUT is 096103144. Form No. A0101 Page 8 of 15 1003422227-0 1356997 « , 100 years. November 16th revised replacement page degree is 4rails, the track segment ROUTING cloth The width is 6.5111丨13 for the microstrip, 611^15 for the stripline, and 81^8 for the insertion segment (the wiring width is 6. 5mi Is; the avoidance segment ESCAPE and the cutoff segment of the data signal line) The wiring spacing of the BREAKOUT is at least 4. 5mi Is, the track section of the data signal line ROUTING and the insertion section BREAK The minimum wiring pitch of the IN is 17. 5 mi 1 s. [0015] The wiring parameters of the differential pair data filtering signal line are as follows: the total impedance of the differential pair data filtering signal line is 400 hm, the differential impedance is 700 hm, and the upper limit of the wiring length of the avoidance section ESCAPE, the cutoff section BREAKOUT, and the insertion section BREAKIN are respectively 250 mils, 700 rails, and 500 mils; the width of the ESCAPE and the cut-off section BREAKOUT is 4 mils, and the width of the trajectory ROUTING is 6. 5 mils in the microstrip, 6 s in the strip line, the BREAKIN The wiring width is 6. 5 mils; the routing distance of the avoidance section ESCAPE and the cut-off section BREAKOUT is at least 5 mils, and the wiring pitch of the trajectory section ROUTING and the insertion section BREAKIN is at least 18.5ra i 1 s, wherein the differential pair data filtering The differential signal transmission line spacing of the signal line is at least 5mi Is. [0016] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a preferred embodiment of a signal transmission system of the present invention. 2 is a block diagram of a control signal line 096103144 in a preferred embodiment of the signal transmission system of the present invention. Form No. A0101 Page 9/15 pages 1003422227-0 1356997 100 years. November 16th replacement by positive [Main component symbol description] [0019] Signal transmission system: 10 [0020] Northbridge wafer: 12 [0021] Small Dual in-line memory module slot: 14 [0022] Signal transmission line: 1 6 [0023] Avoidance segment: 160 [0024] Cut-off segment: 161 [0025] Track segment: 162 [0026] Insert segment: 163 [0027 Terminal segment: 166 1003422227-0 096103144 Form number A0101 Page 10 of 15