TWI356455B - Semiconductor device and method of making the same - Google Patents

Description

Bamboo year r month,?日修(更)正I函99-5-17 IX. Description of the Invention: -—Technical Field of the Invention The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device including Metal wiring layer (metal ^ dielectric (IV), an inter-metal dielectric layer containing oxygen and germanium on the wiring layer, an intermetallic dielectric layer for improving reliable rdiability without causing plasma damage to the semiconductor An inter-metaldielectric 'IMD layer, and an oxide layer on the inter-metal dielectric layer' and the present invention is also a method for fabricating the aforementioned semiconductor device. [Prior Art] Two-step integrated circuits (integrated circuits, 1C) consisting of elements (eg, field-effect transistors (FETs) and bipolar elements) formed in and formed on a semiconductor substrate, and comprising a plurality of interconnected structures 'interconnected structures formed with various components The connections and the connections between the various components. In addition, 'many high-density integrated circuits contain closely spaced arrays of elements' meta-gambling formed by the base and the element One or more arrays of parallel wiring lines are accessed and connected to the arrays. ...to achieve a connection between a plurality of wiring layers, vertical interconnects (eg, "via" or "plug", ) formed between the top of the first layer wiring line and the bottom of the first-Lushi line, and # is formed by the metal-free unlanded via. Figure 1 shows the semiconductor substrate, on which A patterned first layer of gold-wiring layer 110 is formed. For the sake of good faith, the component area of the active element between the semi-conducting bottom (10) and the patterned sub-layer metal wiring layer 110 is not provided. Usually, such as 1356645 98- 03-23

A barrier layer of a Ti/TiN barrier layer 120 is formed on the patterned first metal wiring layer 110. After the formation of the first wiring layer, an inter-metal dielectric (IMD) layer 130, such as a high density plasma plasma (HDP) oxide layer, is provided. These inter-metal dielectric layers comprise poor void regions 140 formed during HDP oxide deposition between the inner metal patterns of a given layer of wiring lines. A plasma enhanced chemical vapor deposition (PECVD) process is then used to deposit oxide layer 150 on imd layer 130. After chemical mechanical polishing (CMP) of the PECVD oxide layer 150 (to reduce the topographical variation 160), a cap oxide layer 200 is formed, as shown in FIG. As shown in Fig. 3, in order to repair the defects generated after the chemical mechanical polishing, a repair layer 2〇1, which is usually an lpteos or PECVD oxide layer, is first formed on the cover emulsion layer 200. Next, a via window side opening 3GG is formed through the uvq) layer 13 to form a via, thereby exposing the - portion of the end of the first layer wiring line. Then, a metal (not shown (10) is filled in the via, and then a wiring line (not shown) is formed on the metal plug in the via to complete the connection. In the conventional via forming process, it is difficult Avoid damage to the underlying active device region and/or the substrate region caused by excessive overetching of the vias. The presence of the HDF oxidized deposition layer also causes the formation of conventional vias. The problem in the process is exacerbated. This is because the via etch process is typically designed to include a sufficient level of over-etching to ensure that the surface of the first-layer dosing path is exposed during the via etch process. Other end points (four) handsome miscellaneous 6 98-03-23 technology to the slave layer of the biliary end of the end of the technique is unrealistic. Therefore, it may be difficult to detect the _ end point with satisfactory reliability. For necessity, The side of the window is often a mosquito, which is designed to incorporate a predetermined level ^, which may cause a knowledge of the active element area and/or the base area of the bottom layer. The presence of the gap 14G provides a side to Wiring layer 110 level below subf A poor shortcut in the substrate _. Moreover, the layering of the underlying oxide film (for example, the inter-polar oxide film) is often performed in the UV f slurry, and is represented by the region 31 图 in FIG. The damage to the substrate side of the substrate is 0. In addition to the problem of excessive meal damage, when the wiring line is made close to or at the resolution limit of the lithography equipm^it (res 〇luti〇n the width of this wolf may not be able to form a layered window. The age-old window is a vertical support structure, which extends beyond the edge of the metal wiring line or other conductor that will be connected. , the W layer _ has a width equal to the width of the wiring line to which it is contacted, so the layer is free from conventional semiconductors 1 (the process is usually unavoidable. Any alignment error of the layer _ may be The portion that causes the via is located beyond the edge of the wiring line, and thus the via does not land. The via window in Figure 3 has an opening 300 indicating the absence of a landing window. In the case of a window, as shown in Figure 3, the window The portion is disposed to partially exit the metal wiring line and extends downward below the surface level of the metal distribution line. The side of the metal wiring line below the surface level is then exposed during etching. These exposed areas generally have a high aspect ratio. (aspect ratio) 'and can be extended into the substrate as shown in the area in Figure 3. In addition, the 1356455 99-5-17 exposed area lacks etch-stop material, and if the metal wiring line and substrate are in the middle When the layer window is formed, it is over-etched' then the components adjacent to the metal wiring line may malfunction. Therefore, the 'no landing via window may introduce a weak connection boor connection between the metal layers. In addition, the non-landing via window can capture impurities and can be made into a parasitic resistance between the metal layers. Moreover, the weak intervening layer can be an important failure mode in submicron elements. . Therefore, it is necessary to prevent etching through the inter-metal dielectric layer and plasma etching damage to the underlying member to improve the reliability of the component having no landing. The present invention is directed to overcoming one or more problems in the prior art. SUMMARY OF THE INVENTION Additional features and advantages of the invention will be set forth in the description which follows.

The Ltfr description and paste requirements, as well as the specific semiconductor components and manufacturing methods indicated in the context, will achieve the invention and advantages. Achieving these and other advantages, and according to the embodied and widely described invention, the 'providing a semiconductor element, including a silk bottom, a layer patterned 3 germanium layer, is provided on the substrate, and the layer is intermetallic. An electric layer, located at and around and directly in contact with the patterned metal wiring layer basin: a layer of high-density electric layer p) and containing oxygen and yttrium, the probability of exceeding the wa and layer oxide layer formed at Between the genus; In the inter-metal dielectric layer ;, - the layer diagram according to it, the gold _ = loyal gas wiring layer 'is provided on the substrate, 1356455 99-5-17 is located on and around the patterned metal wiring layer and Directly contacting j, which causes the inter-metal dielectric layer to be a high-density electro-polymerization (HDp) layer. The ratio of the atoms to the oxygen atoms is higher than that of the tantalum, the layer of oxygen, the ^milk, and the Shishi' dielectric layer. 'Inter-metal dielectric layer and oxide layer total: one = metal ^ metal landing window, its depth extends to the intermetallic degree, and a thickness. In the inter-metal dielectric layer and the oxygen "4 layered surface"; the interface unit is located at the top surface of the patterned metal wiring layer, and according to the present invention, another method for manufacturing a semiconductor is provided. Forming a layer on the substrate to form a package = for forming on and around the patterned metal wiring layer. Then, the inter-metal dielectric layer comprises a human-electric layer, wherein the shape rate exceeds that of the entire gate. The top surface of the layer of the oxide layer is formed on the top surface of the intermetallic dielectric layer on the top side of the intermetallic dielectric layer. Further, according to the present invention, a layer pattern is formed on the substrate on which the semiconductor element is fabricated. The metal wiring is formed by the combination of oxygen (4), and the intermediate surface of the intermediate layer is located on the top surface of the intermetallic dielectric layer. An oxide layer is formed. The upper "re-layered window" then extends to the inter-metal dielectric layer and the oxygen landing to the aforementioned thickness. a rolling enthalpy, the depth of the description is small, it should be understood that the above-described general description and the following detailed description 2 are for providing the proposed further steps and solutions of the present invention, only the following and other purposes, Miscellaneous and advantages can be more clear & ί real secrets, fine haqing, shouting as clear as 2 9 1356455 98-03-23 the aforementioned thickness. The above general description and the following detailed description are intended to be illustrative and illustrative and are intended to provide a further explanation of the claimed invention. The above and other objects, features, and advantages of the present invention will become more apparent and understood. [Embodiment] Reference will now be made in detail to the embodiments of the invention, Wherever possible, the same reference numerals will be used to refer to the Embodiments consistent with the present invention provide a silicon-rich oxide (SR) intermetallic dielectric (Π) in a non-landing via window of a semiconductor device and a method of fabricating the same. The SRO layer acts as an etch stop layer to prevent the interlayer from passing through the IMD layer' and thus overcomes the problems associated with previously described conventional landing screens, and improves component reliability and manufacturing yield (yidd). Further, the SRO used in the present invention has a higher extinction coefficient (expressed as "k") than the conventional HDP oxide layer, thereby effectively preventing plasma etching damage and excessive void formation. The present invention is applicable, for example, to FLASH' DRAM^nOTP (〇ne Time Programmable) PROM^.% ° to solve the problems associated with the conventional methods discussed above and consistent with an aspect of the present invention. Fig. 6 depicts a method of fabricating a semiconductor device consistent with the present invention. " Fig. 4 shows a semiconductor substrate 4' on which a patterned first metal wiring layer 410 is formed. For the sake of brevity, the active element regions between the unpatterned substrate 4 and the patterned first metal wiring layer 410 are patterned. Generally, a barrier layer such as a Ti/TiN resistor 1356455 98-03-23 layer 420 is formed on the wiring layer. After the formation of the first wiring line, an inter-metal dielectric (IMD) layer 43 is provided. The IMD layer 43 is preferably a high density plasma (HDP) rich in cerium oxide (SR 〇). The gate 1 thus uses the Μ) layer 430 to electrically isolate the wiring layer 410 from the adjacent wiring layer and use it as a low dielectric constant material (eg, "low-k dielectric to electrically isolate the metal circuit. Naa 43" can be included in the wiring The 腑SRO deposition between the metal patterns in the layer _ the hard-spaced area of the axis (_also air-gap regi〇n) 440 ° The IMD layer 43 一致 consistent with one aspect of the invention is dream-rich and can be Formed to include SRO, the ratio of the number of atoms of the SR0 与 to the number of oxygen atoms is much higher than the ratio in the number of oxygen 。 2. Therefore, the IMD layer contains a large amount of dangling silicon bonds. The SRO has a similar optical extinction coefficient. For example, the layer 43 〇 formed by SR 可 may have an optical extinction coefficient of at least 〇 5 for a wavelength of less than 4 〇〇 nm. In addition, an IMD formed by SRO The extinction coefficient of layer 43A is from about 13 to about 22. The IMD layer 430 can have a thickness of about 3 Å to 1 〇〇〇 nm and can be formed using a chemical vapor phase > CVD technique. For example, plasma enhanced or high density plasma chemical vapor deposition (HDPCVD). SiH4 and 〇2, SiH4 and = 2〇, TEOS and 〇2, or a combination of TEOS and 源3 source gases can be used for CVD, and the gas flow rate can be controlled to achieve the desired enthalpy/oxygen ratio.

As an example, the IMD layer 430 can be formed by CVD using a source gas containing SiH4, 〇2, and Ar to have a thickness of 700 nm, wherein SiH4, 〇2, and Ar are respectively about 5 〇sccm. (standard cubic centimeters per minute), about 100 verbs and about 5 〇 11 1356455 98-03-23 seem, its _ RF power is about 3 _ w. Q, the ratio of the fox flow rate gamma rate to the 〇2 flow rate is approximately 1/2. The oxide formed under these conditions has an extinction coefficient of approximately 0 at a wavelength of 248 rnn. Continuing to refer to Figure 4, a PECVD process can then be used to deposit a layer 45 on the fine layer 43. The shoe layer performs chemical grinding ((10) 曰 to reduce the morphological change 460 and flatten the IMD layer 43 。. After the CMP of the oxide layer 45 ', the capping oxide layer 5 形成 is formed, as shown in FIG. Figure 6, and then through the side via window to open the 〇 _ to form a layer о a part of the overlying oxide layer 5 〇〇 and the surface layer 〇 43 。 俨 介 介 介 金属 金属 金属The detail is similar (for example, 2_(four)' to provide a proper vertical (hg) of the vertical interconnection of the lining to expose a portion of the end of the first layer wiring line 410 and the barrier layer 420 in the via window. The ground can be completed by using a mixture of 70 Sccm of ch3F, CF4 and 1 〇〇sccm of Ar, by electropolymerization, such as human dry process. Then, metal is provided (not shown $ == layer window i Then, a wiring line is formed on the metal _ in the interlayer stomach. Preferably, the metal is copper (〇〇, !_) or tungsten (W), or ... group it 1 and can be used by Xi (4) Forming, for example, CVD or damascene filling. Referring to Figure 6 'region 61 〇, a portion of the incidental void region 44 (four) exposed between the vias _ is illustrated. The other part of _ is not excessively engraved === void area 440 and enters the base sample. Therefore, SR0 is fine ΐ 'Axis peak stop layer' because it has a familiar HDP milk on the (four) side S low money engraving rate. This lower money engraving rate considers the tolerance of the meso window and the non-landing tolerance, and makes the underlying active device area, metal wiring layer or substrate Damage is minimized. The lower scribe rate of the SRO IMD layer 430 is due to its higher enthalpy content.

Therefore, according to the present invention, the SRO IMD layer acts as an etch stop layer to prevent the landing layer window from completely passing through the IMD layer even in the presence of a region containing voids, and thus improve component reliability and manufacturing yield. This is partly because the SRO IMD layer has a lower etch rate than the conventional IMD layer. Furthermore, the SR0 used in the present invention has a higher extinction coefficient (k) than the conventional HDP oxide layer, thereby effectively preventing further plasma back end etching (backend damage and excessive void formation), although the present invention has The preferred embodiments are disclosed above, but are not intended to limit the present invention, and any one of ordinary skill in the art can be modified and retouched without departing from the scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. [Simplified description]

BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 3 illustrate cross-sectional views of a conventional method for forming a landing window. Improved Landing Membrane Patterns. Figs. 4 through 6 illustrate cross-sectional views of a method consistent with the present invention. [Main component symbol description] 100, 400: substrate 110, 410: metal wiring layer 120, 420: barrier layer 130, 430: intermetal dielectric layer 13 1356455 98-03-23 140, 440: void region 150, 450 : oxide layer 160, 460: morphological change 200, 500: oxide layer 201: repair layer 300, 600: via etch opening 310, 610, 620: region 440: void region

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Claims (1)

1356455 99-5-17 X. Patent application scope: 1. A semiconductor component comprising: · a substrate; - a patterned metal wiring layer provided on the substrate; - a gold dielectric layer, located in the case of a metal connection Contacting on the patterned metal wiring layer, the surrounding sub-straight, wherein the inter-metal dielectric layer is a high-density electrical device (HDP), Shi Xi's atomic atomic turn exceeds i; and an oxide layer is formed thereon On the inter-metal dielectric layer, in the financial-interface of the metal-aged electrical layer and the Weihua layer, it is completely located on the top of the θ-shaped metal layer. 2. The semiconductor device of claim 1, wherein the metallization layer of the graph comprises copper, and at least one of gold, the metal includes a barrier metal layer, and the gold barrier comprises titanium. And a semiconductor element according to the invention of claim 1, wherein the dielectric layer has an extinction coefficient of 1.3 to 2.2 4. A semiconductor element comprising: a substrate; a pattern a metal wiring layer is provided on the substrate; - an intermetal dielectric layer is located on and around the shed metal distribution and directly contacts the patterned metal wiring layer, wherein the inter-metal dielectric layer is a high-density plasma (HDp) layer comprising oxygen and helium, wherein a ratio of germanium atoms to oxygen atoms is exceeded; 15 1356455 99-5-17 an oxide layer formed on the intermetal dielectric layer, wherein the gold The dielectric layer and the Weihua layer are completely above the top surface of the patterned metal wiring layer. The inter-metal dielectric layer and the oxide layer together have a thick sound. The oxidized gold-blocking metal layer is emitted. The barrier metal layer comprises titanium and nitride Which makes a person to ^ 0 genus 6. The semiconductor between the item 4 of the scope of patent extinction coefficient of the dielectric layer is 1.3 to 2.2. The element, wherein the gold element is a semiconductor element as described in claim 4, wherein a gap dielectric region size is determined by the gold dielectric layer. 8. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a patterned metal wiring layer on the substrate; forming an intermetal dielectric layer on and around the patterned metal wiring layer, wherein Forming the metal tantalum dielectric layer comprising combining oxygen and helium, wherein a ratio of germanium atoms to oxygen atoms exceeds 1; performing chemical mechanical polishing on the intermetal dielectric layer such that a top surface of the intermetal dielectric layer is completely located in the pattern Above the top surface of the metal wiring layer; and forming an oxide layer on the top surface of the δ inter-metal dielectric layer. 9. The method of manufacturing a semiconductor device according to the invention of claim 8 is a method of manufacturing a semiconductor component. The method of forming a patterned metal germanium layer comprises depositing copper, and the metal is added to the first metal-blocking metal. The layer, the barrier metal layer comprises one of the Qin and the nitrites. 10. The method of manufacturing a semiconductor method as described in claim 8 of the patent application is directed to a (4) (HDP) deposition process. Also, house ice, Π. Please refer to the method of manufacturing a semiconductor device as described in the eighth item, and the extinction coefficient of the inter-metal dielectric layer is 13 to 2.2. 12. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a patterned metal wiring on the substrate; forming an intermetal dielectric layer on and around the patterned metal wiring layer, wherein the metal is formed The intervening dielectric layer comprises a combination of oxygen and lanthanum, the ratio of ytterbium atoms to more than one; ', performing chemical mechanical polishing on the intermetal dielectric layer such that the top surface of the intermetal dielectric layer is completely located on the patterned metal Above the top surface of the wiring layer; 9 people in the gold dielectric layer _ surface axis - oxide layer, the cloth. The metal between the enamel layer and the oxide layer have a thickness; and = formation - non-face layer The window, the gold dielectric layer and the oxide layer on the Wei side, the depth is less than the thickness. Λ 丨 3', as in the manufacture of a semiconductor component according to claim 12, wherein the patterned metal ruthenium layer comprises deposited copper, inscriptions and gold, wherein "imposed and blocked" A method of fabricating a semiconductor device according to claim 12, wherein the method of forming the inter-metal dielectric layer comprises performing a method of fabricating a semiconductor device as described in claim 12, wherein the barrier metal layer comprises titanium and titanium nitride. High density plasma (HDP) deposition process. 15. The method of fabricating a semiconductor device according to claim 12, wherein the first oxide layer intermetal dielectric layer has an extinction coefficient of 1.3 to 2.2. 18