200805488 rwuHi/ 15088twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件和製造方法，且特別是有 關於一種半導體元件，其包含金屬配線層(metal wiring layer)、 在配線層上包含氧和石夕的第一氧化層、用以改進可靠性 (reliabmty)而不會對半導體造成電漿損傷咖職damage)的金 屬間介電(inter-metal dielectric，IMD)層，和位於第一氧化層上 的第一氧化層’且本發明還是一種有關前述半導體元件的製造 攀 方法。 【先前技術】 、 咼密度積體電路(integrated circuits，1C)由形成於半導體基 底中和形成於半導體基底上的元件（例如場效應電晶體 (filed-effect transistors，FETs)和雙極性元件)構成，且包含多層 内連結構，内連結構用於形成與各種元件的連接並形成各種元 件之間的連接。另外，許多高密度積體電路包含緊密間隔的元 件陣列’元件陣列藉由形成於基底和元件上的平行配線線路的 _ 一個或一個以上陣列進行存取，並連接到這些陣列。 為實現多個配線層之間的連接，垂直内連線(例如“介層 窗或插基）形成於第一層配線線路的頂部與第二層配線 線路的底部之間，並藉由金屬間介電層而分離。圖1到3中說 明習知的不著陸介層窗(unlanded via)的形成。 圖1表示半導體基底1〇〇，其上形成有圖案化的第一層金 屬配線層110。為簡潔起見，未描繪半導體基底1〇〇與圖案化 第一層金屬配線層110之間的主動元件的元件區域。通常，如 200805488 ryjv iny 15088twf.doc/006BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device including a metal wiring layer (Meso Wiring Layer) ), an inter-metal dielectric (IMD) containing oxygen and a smattered first oxide layer on the wiring layer, to improve reliability (reliabmty) without causing plasma damage to the semiconductor. The layer, and the first oxide layer on the first oxide layer' and the present invention is also a method of manufacturing the aforementioned semiconductor element. [Prior Art] A germanium density integrated circuit (1C) is composed of elements (such as field-effect transistors (FETs) and bipolar elements) formed in a semiconductor substrate and formed on a semiconductor substrate. And comprising a plurality of interconnected structures for forming connections with various components and forming connections between the various components. In addition, many high density integrated circuits include closely spaced element arrays. The array of elements is accessed by one or more arrays of parallel wiring lines formed on the substrate and components and connected to the arrays. In order to realize the connection between the plurality of wiring layers, a vertical interconnect (for example, a via or an interposer) is formed between the top of the first wiring line and the bottom of the second wiring line, and is made of metal Separation by dielectric layer. The formation of a conventional unlanded via is illustrated in Figures 1 to 3. Figure 1 shows a semiconductor substrate 1 on which a patterned first metal wiring layer 110 is formed. For the sake of brevity, the element area of the active element between the semiconductor substrate 1 and the patterned first metal wiring layer 110 is not depicted. Typically, such as 200805488 ryjv iny 15088twf.doc/006
Ti/TiN阻障層(barrier layer)120的阻障層會形成在於圖案化的 第一層金屬配線層110上。在第一層配線線路形成之後，提供 金屬間介電(IMD)層130，例如高密度電漿(high-density pla隱，HDP)氧化層。這些金屬間介電層包含在配線線路給 定層的内金屬圖案之間的HDP氧化沉積期間形成的不良的空 隙區域140。隨後使用電漿增强化學氣相沉積⑼ chemical vapor deposition，PECVD)製程以在 IMD 層 13〇 上沉 積氧化層150。在對PECVD氧化層15〇進行化學機械研磨 (chemical mechanical polishing，CMP)(以减少表形變化 (topographical variati〇n)160)之後，形成覆蓋氧化層（capped oxidelayer)200，如圖 2 所示。 如圖3所示，為修補化學機械研磨後所產生之缺陷，會先 在覆盍氧化層200上形成一層修補層2〇1，其通常為LpTE〇s 或者PECVD氧化層。接著，穿過jjyQ)層13〇形成一個介層 窗餘刻開口 300，以形成-介層窗，從而暴露第一層配線線路 末端的-部分。然後’提供金屬(未圖示)以填充介層窗，且隨 • 後於介層窗内的金屬插塞上形成配線線路(未圖示)以完成連 接。在習知的介層窗形成製程中，難以避免由過度蝕刻 (overetching)介層窗槽所導致的對底層主動元件區域和/或基 底區域的損傷。在HDP氧化沉積細形成的空域14〇的 存在也使習知介層窗形成製程中的問題加劇。 這是因為通常將介層窗⑽m程設計驰含充足水平 (碰—心_過度_ ’以雜在介層紐職程中暴露 f 一層配線線路的表面。依靠光學或其他終點(endpoint)探測 6 200805488 ryjui^f^ 15088twf.doc/006 技，來確定介層窗侧製㈣終點通常是狗實際的。因此， 可能難以用滿意的可靠性來探測侧終點。出於必要性，介層 窗钱刻常為固定時間的操作’其藉由設計而合並了預定水平二 過度侧，從而可能對底層的主動元件區域和/或基底區域引 起損傷。空隙140的存在則提供一個侧到配線層m水平以 I並，入基底100中的不良捷徑。而且，常在UV電漿中執行 ”層餘亥丨，使底層氧化膜(例如閘極氧化膜)因UV電漿而退 化。由圖3中的區域310表示示範性的對基底的介層窗侧損 — 傷。 、 除了過度钱刻損傷問題之外，當使配線線路具有接近於或 處於在處理期間使用的特定平版印刷設備（lith〇graphy equipment)的分辨率極限(res〇luti〇n limit)的寬度時，將很可能 形成不著陸介層窗。不著陸介層窗為垂直内連結構，其延伸越 過即將形成所需連接的金屬配線線路或其他導體的邊緣。因為 形成的介層窗具有約等於其所接觸的配線線路的寬度，所以不 =陸介層窗在習知半導體IC製程中通常是不可避免的。介層 • 窗的任何對準錯誤都可能引起介層窗的一部分位於超過配^ 線路的邊緣處，且因此使介層窗不著陸。圖3中的介層窗蝕刻 開口 300說明不著陸介層窗的樣子。 在不著陸介層窗的情况下，如圖3所示，介層窗的部分安 置成邠分_開金屬配線線路，並向下延伸到金屬配線線路的表 面水平以下。此表面水平以下的金屬配線線路的侧面隨後在蝕 刻期間暴露。這些暴露區域通常具有較高的高寬比(aspect ratio)，並可延伸入基底中，如圖3中的區域31〇所示。另外， 200805488 i 15088twf.doc/〇〇6 暴露區域缺少钱刻停止(etch-stop)材料，且如果金屬配線線路 和基底在介層窗形成期間被過度蝕刻，則鄰近金屬配線線路的 元件可能會出現故障。 因此，不著陸介層窗可在金屬層之間引入弱連接(ρ〇〇Γ connection)。另外，不著陸介層窗可捕獲雜質，並可在金屬層 之間形成寄生電阻(parasitic electrical resistance)。而且，弱介 層固接觸可為次微米(su]3micron)元件中的重要故障模式。A barrier layer of a Ti/TiN barrier layer 120 is formed on the patterned first metal wiring layer 110. After the formation of the first layer of wiring lines, an inter-metal dielectric (IMD) layer 130, such as a high-density pla (HDP) oxide layer, is provided. These inter-metal dielectric layers comprise poor void regions 140 formed during HDP oxide deposition between the inner metal patterns of a given layer of wiring lines. A plasma enhanced chemical vapor deposition (PECVD) process is then used to deposit the oxide layer 150 on the IMD layer 13〇. After chemical vapor polishing (CMP) of the PECVD oxide layer 15 (to reduce the topographical variancy 160), a capped oxide layer 200 is formed, as shown in FIG. As shown in FIG. 3, in order to repair defects generated after chemical mechanical polishing, a repair layer 2〇1, which is usually a LpTE〇s or PECVD oxide layer, is first formed on the overlying oxide layer 200. Next, a via window opening 300 is formed through the jjyQ) layer 13 to form a via, thereby exposing the - portion of the end of the first wiring trace. A metal (not shown) is then provided to fill the via, and a wiring trace (not shown) is formed over the metal plug in the via to complete the connection. In conventional via forming processes, it is difficult to avoid damage to the underlying active device regions and/or substrate regions caused by overetching via trenches. The presence of the airspace 14〇 formed by the oxidative deposition of HDP also exacerbates the problems in the conventional via formation process. This is because the via window (10) m-process design usually has a sufficient level (bump-heart_excessive_' to expose the surface of a layer of wiring lines in the intervening layer. It relies on optical or other endpoints to detect 6 200805488 ryjui^f^ 15088twf.doc/006 technique to determine the side window (4) end point is usually the dog's actual. Therefore, it may be difficult to detect the side end point with satisfactory reliability. For necessity, the window money It is often a fixed-time operation that combines a predetermined level of two transition sides by design, thereby possibly causing damage to the underlying active component area and/or substrate area. The presence of void 140 provides a side-to-wiring layer m level With I, the poor shortcut into the substrate 100. Moreover, the layer is often performed in the UV plasma, so that the underlying oxide film (such as the gate oxide film) is degraded by the UV plasma. Region 310 represents an exemplary via-side damage to the substrate. In addition to the problem of excessive burn-in damage, when the wiring trace is made to be close to or in use in a particular lithographic apparatus used during processing (lith 〇 graphy When the width of the resolution limit (res〇luti〇n limit) is large, a landing window is likely to be formed. The non-landing window is a vertical interconnect structure that extends over the metal wiring that will form the desired connection. The edge of a line or other conductor. Because the via window is formed to have a width approximately equal to the width of the wiring line it contacts, it is generally unavoidable in the conventional semiconductor IC process. Any misalignment may cause a portion of the via to be located beyond the edge of the device and thus prevent the via from landing. The via etch opening 300 in Figure 3 illustrates the absence of a via. In the case of not landing the via window, as shown in Fig. 3, the portion of the via window is disposed as a split-open metal wiring line and extends downward below the surface level of the metal wiring line. Metal wiring below the surface level The sides of the line are then exposed during the etch. These exposed areas typically have a high aspect ratio and can extend into the substrate as shown by area 31 如图 in Figure 3. Additionally, 200 805488 i 15088twf.doc/〇〇6 The exposed area lacks etch-stop material, and if the metal wiring and substrate are over-etched during the formation of the via, the components adjacent to the metal wiring may fail. Therefore, the non-landing via window can introduce a weak connection between the metal layers. In addition, the non-landing via window can trap impurities and form parasitic electrical resistance between the metal layers. Moreover, the weak interwell contact can be an important failure mode in sub-micron (su]3micron) components.
因此，需要防止穿過金屬間介電層的蝕刻和對底層元件的 電漿蝕刻損傷，以改進具有不著陸的元件的可靠性。 本發明針對克服現有技術中的一個或一個以上問題。 【發明内容】 在以下描述中將陳述本發明的額外特徵和優點，這些特徵 =優點從描述巾可鴨看出’或可藉由本發明的實踐而瞭解。 藉由書面描述和權利要求以及附圖中特定指出半 結構和製妨法將可魏域得本發_舰和伽。Accordingly, there is a need to prevent etching through the inter-metal dielectric layer and plasma etch damage to the underlying components to improve the reliability of components having non-landing. The present invention is directed to overcoming one or more problems in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS Additional features and advantages of the invention will be set forth in the description which follows. By means of written descriptions and claims, as well as the specific designation of semi-structures and stipulations in the drawings, it will be possible to obtain the _ ship and gamma.
為實現這些和其他優點，且根據所實施和廣泛描述的本發 =目的’提供—種轉體元件，包括—個基底、—層圖案化 =2_層’其提供於基底上、—層第—氧化層，其位於圖 案化金屬配線層上和觸，其巾第—氧崎包含氧树，立中 ^原預氧原子的比率超過卜和—層第二氧化層，其 弟一氧化層上。 根據本發明還提供-種半導體元件，包括—個基底、一戶 圖案化的金屬配線層，其提供於基底上、一層第一氧化層，】 立於圖案化金屬配線層上和周圍，其中第—氧化層“ 200805488 15088twf.doc/0〇6 =::=層窗，其深度延W:氧=第一: 礼化層肀，則述淥度小於前述厚度。 不 =本發邮提供—種製造半導體元件的製程，包括提供 土底，再在基底上形成一層圖案化 ’、 ^案其中形成 引。二氧原子的比率超 二氧化声。 θ執仃化予機械研磨，再形成一層第 -個本Γ狀提供—麵造半導體元件的製程，包括提供 在圖基底上形成—層圖案化的金屬配線層。然後， ^化的金屬配線層上和厢形成一層第一氧化層，其中形 3，弟:氧化層包含結合氧和石夕’且石夕原子對氧原子的比率超 接者’對第—氧化層執行化學機械研磨，再形成第二氧 “—然後，形成一個不著陸介層窗，其深度延伸到第一氧化 I和第二氧化層巾’前述深度小於前述厚度。 應瞭解’上述一般性描述和以下詳細描述都是示範性和解 釋丨生的，並且是用於提所主張的本發明的進一步解釋。 ^為讓本發明之上述和其他目的、特徵和優點能更明顯易 廑，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 現將對本發明的實施例進行詳細參考，在附圖中說明本發 明的實例。在任何可能之處，全部附圖中將使用相同參考數字 9 200805488 15088twf.doc/006 來表示相同或類似的部分。 與本發明相一致的實施例提供在半導體元件的不著陸介 層囪中的畐含梦氧化物(8脱011-1^11(^(16,8乂0)金屬間介電 (IMD)及其製造方法。SR〇層充當蝕刻停止層以防止不著陸介 層窗穿過IMD層，並因此克服與先前描述的習知不著陸介層窗 相關的問題，且改進元件可靠性和製造產量(yidd)。此外，用 於本發明的SRO具有比習知hdp氧化層更高的消光係數 φ (extmctloncoefflcient，以“k”表示），從而有效防止電漿蝕刻 損傷和過多的空隙形成(v〇idformation)。本發明例如適用於 FLASH、DRAM和 OTP (One Time Programmable) PROM技術。 為解决與以上論述的習知方法有關的和與本發明的一方 面一致的問題，以下將請參照圖4到圖6來描述與本發明一致 的半導體元件的製造方法。 圖4表示半導體基底400，其上形成有圖案化的第一層金 屬配線層410。為簡潔起見，未描繪基底4〇〇與圖案化第一層 金屬配線層410之間的主動元件區域。通常，如Ti/TiN阻障 ⑩層420的阻障層形成於配線層上。在第一層配線線路形成 之後，提供金屬間介電(IMD)層430。IMD層430較佳妯兔古 密度電漿(HDP)富含矽氧化物(SR0)。 ^ —因此使帛IMD層細己線層彻與鄰近的配線層電學 隔離，並將其用作低介電常數材料(例如“低k電介質以恭 學隔離金屬電路。IMD層430可包含在配線層彻内全屬= 案之間的HDP SRG沉積_形成的健空随域(Qecasi〇nai air-gap region)440 ° 200805488 15088twf.doc/006 與本發明的一方面相一致的IMD層430是富含石夕的，且 可經形成為包括SRO，其中SRO中矽原子數目與氧原子數目 的比率比Si〇2中的比率高得多。因此，IMD層430含有大量 懸浮矽鍵結(dangling silicon bonds)。與 Si02相比，SRO 具有 較高的光學消光係數。例如，以SRO形成的IMD層430對於 小於400 nm的波長可具有至少為〇·5的光學消光係數。另外， 以SRO形成的IMD層430可具有約1.3到約2.2的消光係數。 • IMD層430可具有約3〇〇到1〇〇〇 nm的厚度，且可使用 化學氣相沉積(CVD)技術來形成，例如電漿增强cvT)(p；gcvD) 或高密度電漿化學氣相沉積(HDPCVD)。SiH4與〇2、SiH4與 N2〇、TEOS與〇2 ’或TE0S與〇3的源氣體組合可用於CVX) 製程，且可控制氣體的流動速率以獲得所需要的矽/氧比率。 作為只例’可使用包含SiH4、〇2和Ar的源氣體藉由CVD 來形成IMD層430使其具有700舰的厚度，其中細4、 和Ar的流動速率分別為約5〇 sccm(每分鐘標準立方厘米 (standard cubic centimeters per minute))、約 1〇〇 sccm 和約 5〇 • S_，其巾即功率約為3_ W。因此，SiH4流動速率(flow _ 與〇2流動速率的比率近似為1/2。在這些條件下形成的氧化物 具有在248 nm波長處近似為〇的消光係數。 請繼續參則4，隨後可使用PECVD製程以在！md層 430上沉積氧化層物。對氧化層视執行化學機械研磨(⑽曰 以减少表形變化46〇並使IMD層43〇平坦化。在氧化層· 的CMP之後，形成覆蓋氧化層5〇〇，如圖$所示。 杯照圖6 ’隨後藉由餞刻介層窗侧開口 _而形成介 11 200805488 ry^ViHy 15088twf.doc/006 層窗，其穿過覆蓋氧化層500和IMD層430的一部分。較佳 地，介層窗蝕刻開口 600可與金屬層410和障壁(barrier)420 的寬度類似(例如為2000 rnn)，以提供用於垂直内連的適當著 點(landing)。這道钕刻暴露介層窗内第一層配線線路41〇和阻 障層420的末端的一部分。較佳地，可使用7〇 sccm的CH3f、 45 seem的CF4和1〇〇 sccm的Ar的混合物，藉由電漿蝕刻製 程(例如幹式蝕刻製程)來完成蝕刻。接著，提供金屬(未圖示) ⑩ 以填充介層窗，且隨後在介層窗内的金屬插塞上形成配線線路 以完成連接。較佳地，此金屬為銅(Cu)、鋁或鎢，或 其組合物，且可藉由習知製程來形成，例如CVD或鑲嵌填充。 請繼續參照圖6,區域610說明在介層窗蝕刻開口 600的 钱刻期間暴露的偶然空隙區域440的一部分。區域62〇說明介 層囪蝕刻開口 600的另一部分，以證明蝕刻製程並未過度蝕刻 而牙過偶然空隙區域440且進入基底4〇〇中。因此sro j 430充當钕刻停止層，因為其對電漿钱刻具有比對習知班疋 氧化f更低的蝕刻速率。此較低的蝕刻速率考慮了介層窗蝕刻 • *不著陸中的容限，並使對底層主動元件區域、金屬配線層或 基底的損傷降至最低。SR0細層物的較低侧速率是由 於其較高矽含量而導致的。 因此，根據本發明，SR〇 IMD層充當蝕刻停止層以防止 即使在存在含有空隙的區域的情况下不著陸介層窗仍完全穿 過IMD層，並因此改進元件可靠性和製造產量。這部分是因 為SRO IMD層具有比習知副^層更低的钕刻速率。此外， 用於本發明的SRO具有比習知騰氧化層更高的消光係數 12 200805488 r 15088twf.doc/006 ⑻’從而有效防止進一步的電漿後端蝕刻(backend etch)損傷 和過多的空隙形成。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離本發 明之精神和範圍内，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 # 馨 目1麵3綱f知不著时層窗形成的方面。 ㈣到圖6說明與本發明相一致的已改進不著陸介層窗形 攻的歩驟。 【主要元件符號說明】 100、400 :基底 110、410 :金屬配線層 120、420 :阻障層 130、430 :金屬間介電層 140、440 :空隙區域 ❿ 150、450 :氧化層 160、460 :表形變化 200、500 :氧化層 201 :修補層 300、600 :介層窗钱刻開口 310、610、620 :區域 440 :空隙區域 13To achieve these and other advantages, and in accordance with the presently described and broadly described <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; - an oxide layer, which is located on the patterned metal wiring layer and touched, and the towel-oxygen is contained in the oxygen tree, and the ratio of the pre-oxygen atoms in the center exceeds the second oxide layer of the layer and the second layer on the oxide layer. . According to the present invention, there is also provided a semiconductor device comprising: a substrate, a patterned metal wiring layer provided on the substrate, a first oxide layer, standing on and around the patterned metal wiring layer, wherein - Oxide layer "200805488 15088twf.doc/0〇6 =::=Layer window, its depth is extended by W: oxygen = first: ritual layer 肀, then the degree of 渌 is less than the aforementioned thickness. The manufacturing process of the semiconductor component includes providing a soil bottom, and then forming a pattern on the substrate, and forming a lead in the case. The ratio of the oxygen atoms is super-diox. θ is applied to the mechanical grinding, and then a layer is formed. The present invention provides a process for fabricating a semiconductor device, comprising providing a metal wiring layer patterned on a pattern substrate. Then, a metal oxide layer is formed on the metal wiring layer and the chamber is formed with a first oxide layer, wherein the shape 3 , The younger brother: the oxide layer contains a combination of oxygen and Shi Xi' and the ratio of the Shi Xi atom to the oxygen atom exceeds the 'electrochemical mechanical polishing of the first oxide layer, and then forms the second oxygen" - and then forms a non-landing interlayer Window, its depth I out into the first oxide and second oxide layers towels' less than the depth of the thickness. The above general description and the following detailed description are intended to be illustrative and illustrative of the invention The above and other objects, features, and advantages of the present invention will become more apparent from the <RTIgt; [Embodiment] Reference will now be made in detail to the embodiments of the invention, Wherever possible, the same reference numeral 9 200805488 15088 twf.doc/006 will be used throughout the drawings to refer to the same or similar parts. Embodiments consistent with the present invention provide a dream oxide (8 off 011-1^11 (^(16,8乂0) intermetal dielectric (IMD)) in a non-landing interlayer of a semiconductor device. The manufacturing method thereof. The SR layer acts as an etch stop layer to prevent the landing window from passing through the IMD layer, and thus overcomes the problems associated with the previously described conventional landing window, and improves component reliability and manufacturing yield ( In addition, the SRO used in the present invention has a higher extinction coefficient φ (expressed by "k") than the conventional hdp oxide layer, thereby effectively preventing plasma etching damage and excessive void formation (v〇idformation). The present invention is applicable, for example, to FLASH, DRAM, and OTP (One Time Programmable) PROM technology. To solve the problems associated with the conventional methods discussed above and consistent with one aspect of the present invention, reference will now be made to Figures 4 through A method of manufacturing a semiconductor device consistent with the present invention will be described. Fig. 4 shows a semiconductor substrate 400 on which a patterned first metal wiring layer 410 is formed. For the sake of brevity, the substrate 4 is not depicted and patterned. level one It is an active device region between the wiring layers 410. Usually, a barrier layer such as a Ti/TiN barrier 10 layer 420 is formed on the wiring layer. After the formation of the first wiring layer, an inter-metal dielectric (IMD) layer is provided. 430. The IMD layer 430 is preferably a 妯 古 ancient density plasma (HDP) rich in cerium oxide (SR0). ^ - Therefore, the 帛IMD layer fine wire layer is electrically isolated from the adjacent wiring layer and used as Low dielectric constant materials (such as "low-k dielectrics to isolate metal circuits. IMD layer 430 can include HDP SRG deposition between the wiring layers" (the HDP SRG deposition) formed by the Qacasi〇nai air -gap region) 440 ° 200805488 15088twf.doc/006 The IMD layer 430, which is consistent with an aspect of the invention, is enriched and can be formed to include SRO, wherein the number of germanium atoms and the number of oxygen atoms in the SRO The ratio is much higher than the ratio in Si 〇 2. Therefore, the IMD layer 430 contains a large amount of dangling silicon bonds. Compared to SiO 2 , the SRO has a higher optical extinction coefficient. For example, an IMD formed by SRO Layer 430 can have an optical extinction system of at least 〇·5 for wavelengths less than 400 nm In addition, the IMD layer 430 formed with SRO may have an extinction coefficient of about 1.3 to about 2.2. • The IMD layer 430 may have a thickness of about 3 Å to 1 〇〇〇 nm, and chemical vapor deposition (CVD) may be used. Techniques are formed, such as plasma enhanced cvT) (p; gcvD) or high density plasma chemical vapor deposition (HDPCVD). The combination of SiH4 with 〇2, SiH4 and N2〇, TEOS and 〇2' or TE0S and 〇3 source gases can be used in the CVX) process, and the gas flow rate can be controlled to achieve the desired enthalpy/oxygen ratio. As an example, the IMD layer 430 may be formed by CVD using a source gas containing SiH4, 〇2, and Ar to have a thickness of 700 ships, wherein the flow rates of fine 4, and Ar are about 5 〇 sccm, respectively. Standard cubic centimeters per minute, about 1 〇〇 sccm and about 5 〇• S_, the power of the towel is about 3 _ W. Therefore, the SiH4 flow rate (the ratio of flow _ to 〇2 flow rate is approximately 1/2. The oxide formed under these conditions has an extinction coefficient of approximately 〇 at a wavelength of 248 nm. Please continue to step 4, then A PECVD process is used to deposit an oxide layer on the !md layer 430. Chemical mechanical polishing is performed on the oxide layer ((10) 曰 to reduce the morphological change 46 〇 and to flatten the IMD layer 43 。. After the CMP of the oxide layer, Forming a capping oxide layer 5〇〇, as shown in Fig. $. The cup is shown in Fig. 6' and then formed by the engraving of the via opening _200805488 ry^ViHy 15088twf.doc/006 layer window, which passes through the overlay The oxide layer 500 and a portion of the IMD layer 430. Preferably, the via etch opening 600 can be similar in width to the metal layer 410 and the barrier 420 (eg, 2000 rnn) to provide suitable vertical alignment Landing. This engraving exposes a portion of the first wiring line 41A and the end of the barrier layer 420 in the via window. Preferably, 7 〇sccm of CH3f, 45 seem of CF4 and 1 can be used. 〇〇sccm of Ar mixture by plasma etching process (eg dry etching) The process is completed to complete the etching. Next, a metal (not shown) 10 is provided to fill the via, and then a wiring line is formed on the metal plug in the via to complete the connection. Preferably, the metal is copper ( Cu), aluminum or tungsten, or a combination thereof, and may be formed by conventional processes, such as CVD or damascene filling. With continued reference to FIG. 6, region 610 illustrates exposure during the engraving of the via etch opening 600. A portion of the incident void region 440. The region 62 〇 illustrates another portion of the via etched opening 600 to demonstrate that the etch process is not over etched and passes through the incident void region 440 and into the substrate 4 。. Thus the sro j 430 acts as a 钕The etch stop layer because it has a lower etch rate for the plasma etch than for the conventional 疋 。 f. This lower etch rate takes into account the via etch and * does not land the tolerance and makes The damage of the underlying active device region, metal wiring layer or substrate is minimized. The lower side rate of the SR0 fine layer is due to its higher germanium content. Thus, according to the present invention, the SR〇IMD layer acts as an etch stop layer. To prevent The landing window does not completely pass through the IMD layer even in the presence of void-containing regions, and thus improves component reliability and manufacturing yield. This is partly because the SRO IMD layer has a lower profile than the conventional sub-layer. In addition, the SRO used in the present invention has a higher extinction coefficient 12 200805488 r 15088 twf.doc/006 (8)' than the conventional oxidized layer, thereby effectively preventing further plasma backend etch damage and excessive voids. form. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. [Simple description of the figure] # 馨目1面3纲 f I don't know the aspect of the formation of the layer window. (d) Figure 6 illustrates the improved footprint of the non-landing mesoscopic window in accordance with the present invention. [Description of main component symbols] 100, 400: substrate 110, 410: metal wiring layers 120, 420: barrier layers 130, 430: inter-metal dielectric layers 140, 440: void regions ❿ 150, 450: oxide layers 160, 460 : morphological change 200, 500: oxide layer 201: repair layer 300, 600: via window opening openings 310, 610, 620: region 440: void region 13