[0001] [0001] [0002] [0003] [0004] [0005] 096135462 100年10月13日梭正替換頁 發明說明： 【發明所屬之技術領域】 本發明侧於’齡移暫存器，餘㈣料之駆動方 法及採用該位移暫存器之液晶顯示器。 【先前技術】 目前薄膜電續心⑴^咖咖’即液晶 顯不器已逐漸成為各種數位產品之標準輸出設備然， 其需要設計適當的驅動電路以保證其穩定工作。 通：’液晶顯示器驅動電路包括一資伽動電路及一掃 描驅動電路。資料驅動電路用於控制每一像 :度’掃描驅動電路則用於控制薄膜電晶體之導通與 奮二驅動電路均應用位移暫存器作為核心電 «’位移㈣_複_暫術串聯而成， 且則一位移暫左留_ 輪入訊號/ ^之輸出訊號為後-位移暫存單元之 請參閱圖1，择— 之電助“前技術位移暫存11之位移暫存單元 no、-換^立移暫存單元m包括一第一時鐘反相電路 移暫存^路120及—第二時鐘反相電路130。該位 Oxide s"0 〇〇之各電路均由PM〇S(P_Channel Metal_ 電晶體电lmiconductor，p溝道金屬氧化物半導體）型 及-沒極。’母— PM〇S型電晶體均包括一閉極、一源極 二第_時知反相電路110包括-第—PM0S型電晶體P1、 一=日日體P2、一第三電晶體P3、一第四電晶體p4、 弟一輸出端VI 14咕 表單編號A0101 一第二輸出端V2。該第一電晶體P12 .第 5 頁/共 33 頁 1003376108-0 1356421 100年.10月13日核正替換頁 閘極接收該位移暫存單元100之前一位移暫存單元之輸出 訊號VS，其源極接收來自外部電路之高電平訊號VDD，其 汲極連接至該第二電晶體P2之源極。該第二電晶體P2之 閘極及其汲極接收來自外部電路之低電平訊號VSS。該第 三電晶體P3及該第四電晶體P4之閘極均接收來自外部電 路之反相時鐘訊號[0001] [0001] [0002] [0004] [0005] [0005] 096135462 October 13, 100 shuttle replacement page invention description: [Technical field of the invention] The present invention is sideways to the 'age shift register, The remaining method of the fourth (four) material and the liquid crystal display using the displacement register. [Prior Art] At present, the thin film electric continuous (1)^caffe's liquid crystal display has gradually become the standard output device of various digital products. It needs to design an appropriate driving circuit to ensure its stable operation. Pass: 'The liquid crystal display driving circuit includes a gamma circuit and a scan driving circuit. The data driving circuit is used to control each image: the degree 'scanning driving circuit is used to control the conduction of the thin film transistor and the second driving circuit is applied to the displacement register as the core electric «' displacement (four) _ complex _ temporary series , and the displacement of the left left _ wheel signal / ^ output signal for the post-displacement temporary storage unit, please refer to Figure 1, select - the power of the "pre-technical displacement temporary storage 11 displacement temporary storage unit no, - The shifting temporary storage unit m includes a first clock inverting circuit shifting buffer circuit 120 and a second clock inverting circuit 130. Each of the circuits of the bit Oxide s"0 is composed of PM〇S (P_Channel) Metal_transistor lmiconductor, p-channel metal oxide semiconductor type and - immersed. 'Female - PM 〇 S type transistor includes a closed pole, a source two _ _ know the inverter circuit 110 includes - - PM0S type transistor P1, a = day body P2, a third transistor P3, a fourth transistor p4, a second output terminal VI 14 咕 form number A0101 a second output terminal V2. The first transistor P12. Page 5 of 33 1003376108-0 1356421 100 years. October 13th, the replacement of the page gate receives the The output signal VS of the displacement temporary storage unit 100 before the displacement temporary storage unit 100 receives the high level signal VDD from the external circuit, and the drain is connected to the source of the second transistor P2. The second transistor The gate of P2 and its drain receive a low level signal VSS from an external circuit. The gates of the third transistor P3 and the fourth transistor P4 receive an inverted clock signal from an external circuit.
TS 者之汲極分別作為該第一時 鐘反相電路110之第一輸出端VI及第二輸出端V2，且該第 三電晶體P3之源極連接至該第一電晶體P1之汲極，該第 四電晶體P4之源極連接至該第一電晶體P1之閘極。 [0006] 該換流電路120包括一第五電晶體P5、一第六電晶體P6及 一訊號輸出端V。該第五電晶體P5之閘極連接至該第一輸 出端VI，其源極接收來自外部電路之高電平訊號VDD，其 汲極連接至該第六電晶體P6之源極。該第六電晶體P6之 閘極連接至該第二輸出端V2，其汲極接收來自外部電路 之低電平訊號VSS，其源極係該位移暫存單元100之訊號 輸出端V。 [0007] 該第二時鐘反相電路130包括一第七電晶體P7、一第八電 晶體P8、一第九電晶體P9及一第十電晶體P10。該第七電 晶體P7之閘極連接至該訊號輸出端V，其源極接收來自外 部電路之高電平訊號VDD，其汲極連接至該第八電晶體P8 之源極。該第八電晶體P8之閘極及其汲極均接收來自外 部電路之低電平訊號VSS。該第九電晶體P9之源極連接至 該第一輸出端VI，其閘極接收來自外部電路之時鐘訊號 TS，其汲極連接至該第七電晶體？7之汲極。該第十電晶 096135462 體之閘極接收外部電路之時鐘訊號TS，其源極連接至該 表單編號A0101 第6頁/共33頁 1003376108-0 1356,421 100年.10月13日修正替¥百 第二輸出端V2，其汲極連接至該訊號輸出端V。 [0008] 請一併參閱圖2，係該位移暫存單元100之工作時序圖。 在tl時段内，該前一位移暫存單元之輸出訊號VS由高電 平跳變為低電平，反相時鐘訊號;^7·由低電平跳變為高 1 〇 電平，則使該第三電晶體P3及該第四電晶體P4截止，進 而使該第一時鐘反相電路110斷開。而該時鐘訊號TS由高 電平跳變為低電平，使該第九電晶體P9及該第十電晶體 P10導通，進而使該第二時鐘反相電路130導通，而該訊 號輸出端V初始狀態之高電平經該第十電晶體P10，使該 第六電晶體P6截止，而該第八電晶體P8輸出之低電平經 由該第九電晶體P9，使該第五電晶體P5導通，進而使其 源極之高電平訊號VDD輸出至該訊號輸出端V，故該訊號 輸出端V保持高電平輸出。 [0009] 在t2時段内，該反相時鐘訊號;由高電平跳變為低電 平，則使該第三電晶體P3及該第四電晶體P4導通，進而 使該第一時鐘反相電路110導通。而該時鐘訊號TS由低電 平跳變為高電平，則使該第九電晶體P9及該第十電晶體 P10截止，進而使該第二時鐘反相電路130斷開。該輸入 訊號VS由高電平跳變為低電平，則使該第一電晶體P1導 通，其源極之高電平VDD經該第三電晶體P3截止該第五電 晶體P5 ’且該輸入訊號VS之低電平經該第四電晶體P4導 通該第六電晶體P6，使該訊號輸出端V輸出低電平。 [0010] 在t3時段内，該反相時鐘訊號;由低電平跳變為高電 1 ΰ 096135462 表單編號Α0101 第7頁/共33頁 1003376108-0 1356421 100年10月13日修正替換頁 平，則使該第三電晶體P3及該第四電晶體P4截止，進而 使該第一時鐘反相電路110斷開。而該時鐘訊號TS由高電 平跳變為低電平，使該第九電晶體P9及該第十電晶體P10 導通，進而使該第二時鐘反相電路130導通。該訊號輸出 端V之低電平導通該第七電晶體P7，其源極之高電平經該 第九電晶體P9截止該第五電晶體P5。同時，該訊號輸出 端V之低電平亦經該第十電晶體P10，導通該第六電晶體 P6，該第六電晶體P6之汲極低電平使該訊號輸出端V保持 低電平輸出。 [0011] 在t4時段内，該反相時鐘訊號;由高電平跳變為低電 1 〇 平，則使該第三電晶體Ρ3及該第四電晶體Ρ4導通，進而 使該第一時鐘反相電路110導通。而該時鐘訊號TS由低電 平跳變為高電平，使該第九電晶體Ρ9及該第十電晶體Ρ10 截止，進而使該第二時鐘反相電路120斷開。輸入訊號VS 之尚電平經該第四電晶體Ρ4截止該第六電晶體Ρ6，而該 第二電晶體Ρ 2之汲極低電平經該第三電晶體Ρ 3導通該第 五電晶體Ρ5，使其源極之高電平輸出至該訊號輸出端V， 使該訊號輸出端V之輸出由低電平跳變為高電平。 [0012] 從工作時序可見，該位移暫存單元100之輸入訊號VS為前 一位移暫存單元於tl時段與t2時段内輸出之訊號，而訊 號輸出端V於t2時段與t3時段内輸出訊號，輸入訊號VS與 輸出訊號在t2時段存在訊號重疊情況，進而導致採用該 位移暫存器作為資料驅動電路及掃描驅動電路之液晶顯 示器，在進行列掃描或欄掃描時，存在相鄰二列（Row)或 096135462 欄（Column)同時進行掃描之現象，從而載入訊號產生相 表單编號A0101 第8頁/共33頁 1003376108-0 1356.421 100年10月13日修正替換頁 互干擾，使晝面產生色差。 【發明内容】 [0013] 有鑑於此，提供一種輸出訊號無重疊之位移暫存器實為 必要。 [0014] 另，提供一種可避免訊號干擾之液晶顯示器亦為必要。 [0015] 還有，提供一種輸出訊號無重疊之位移暫存器之驅動方 法實為必要。 [0016] 一種位移暫存器，其包括複數位移暫存單元，二相鄰位 移暫存單元所接收之二時鐘訊號反相，每一位移暫存單 元均包括一訊號輸出電路、一訊號輸入電路及一邏輯電 路，該訊號輸出電路接收來自外部電路之一時鐘訊號， 其包括一時鐘電晶體，其輸出該時鐘訊號；及一穩壓電 晶體，其輸出之訊號為一恆低電平訊號；該訊號輸入電 路接收前一位移暫存單元之輸出訊號，以輸出訊號導通 該時鐘電晶體；該邏輯電路恆接收一高電平訊號及一低 電平訊號，且接收該訊號輸入電路輸出之訊號，以控制 該邏輯電路輸出該南電平訊號至該穩壓電晶體或輸出該 低電平訊號至該穩壓電晶體；其中，當該訊號輸入電路 輸出一導通訊號至該時鐘電晶體及該邏輯電路*該邏輯 電路輸出一低電平訊號，截止該穩壓電晶體，該信號輸 出電路藉由該時鐘電晶體輸出該時鐘訊號，反之》當該 訊號輸入電路輸出截止訊號至該時鐘電晶體截及該邏輯 電路時，則該邏輯電路輸出一高電平訊號以開啟該穩壓 電晶體，以維持該訊號輸出電路輸出低電平訊號。 096135462 表單編號A0101 第9頁/共33頁 1003376108-0 100年10月13日修正替換頁 種液晶顯示器’其包括一液晶顯示面板、一資料驅動 電路及一掃描驅動電路’該資料驅動電路爲該液晶顯示 面板提供資料訊號，該掃描驅動電路爲該液晶顯示面板 提供掃描訊號，該資料驅動電路及該掃描驅動電路分別 包括一位移暫存器以控制資料訊號與掃描訊號之輸出時 序，該位移暫存器包括複數位移暫存單元，二相鄰位移 暫存單元所接收之二時鐘訊號反相，每一位移暫存單元 均包括一訊號輸出電路、一訊號輸入電路及一邏輯電路 °玄訊號輪出電路接收來自外部電路之一時鐘訊號，其 包括一時鐘電晶體，其輸出該時鐘訊號；及一穩壓電晶 體，其輸出之訊號為一恆低電平訊號；該訊號輸入電路 接收前位移暫存單元之輸出訊號，以輸出訊號導通該 時鐘電晶體；該邏輯電路轉彳卜高電平訊號及一低電 平托號且接收§亥訊號輸入電路輸出之訊號，以控制該 邏輯電路輪出該高電平訊號至該穩壓電晶體或輸出該低 電平訊號至該穩壓電晶體；其中，當該訊號輸入電路輸 出導通訊號至該時鐘電晶體及該邏輯電路，該邏輯電 路輸出低電平訊號’截止該穩壓電晶體，該信號輸出 電路藉由料鐘電晶體輸出該時鐘訊號；反之，當該訊 號輸入電路輸域止訊號至料鐘電晶體截及該邏輯電 ^時貝J該邏輯電路輸出一高電平訊號以開啟該穩壓電 明體以維持該訊號輸出電路輪出低電平訊號。 種位移暫存器之驅動方法，該位移暫存器包括複數位 移暫存單元，且二相鄰位移暫存單元所接收之二時鐘訊 號反相，每—位移暫存單元均包括—訊號輸出電路、- 表單編號A0101 第丨0頁/共33頁 1003376108-0 1356.421 100年10月13日修正替換頁 訊號輸入電路及一邏輯電路；該訊號輸出電路包括一時 鐘電晶體及一穩壓電晶體，該時鐘電晶體接收該時鐘訊 號，該穩壓電晶體恆接收一低電平訊號，該邏輯電路恆 接收一高電平訊號及一低電平訊號，該位移暫存器之驅 動方法包括如下步驟：a) —移位暫存單元之訊號輸入電 路接收前一移位暫存單元之輸出訊號以輸出訊號至該時 鐘電晶體及該邏輯電路；b)該輸出訊號導通該時鐘電晶 體，該時鐘電晶體輸出該時鐘訊號，同時，該輸出訊號 控制該邏輯電路輸出低電平訊號戴止該穩壓電晶體，以 使該輸出電路輸出該時鐘訊號；c)該輸出該輸出訊號截 止該時鐘電晶體，同時，該輸出訊號控制該邏輯電路輸 出高電平訊號導通該穩壓電晶體，以使該輸出電路輸出 低電平訊號。 [0019] 相較於先前技術，該位移暫存器之每一位移暫存單元之 時鐘訊號電晶體導通輸出時鐘訊號時，其後一位移暫存 單元之時鐘訊號電晶體亦導通，亦輸出時鐘訊號，由於 相鄰二位移暫存單元接收之時鐘訊號相反，故，該位移 暫存器輸出之訊號無重疊。 [0020] 相較於先前技術，該液晶顯示器之該位移暫存器之每一 位移暫存單元之時鐘訊號電晶體導通輸出時鐘訊號時， 其後一位移暫存單元之時鐘訊號電晶體亦導通，亦輸出 時鐘訊號，由於相鄰二位移暫存單元接收之時鐘訊號相 反，該位移暫存器輸出之訊號無重疊，故，使得使用該 位移暫存器作為掃描驅動電路及資料驅動電路之液晶顯 示器在進行攔掃描或列掃描時，其輸出掃描訊號及資料 096135462 表單編號A0101 第11頁/共33頁 1003376108-0 1356421 [0021] 100年10月13日 訊號不會產生訊號干擾，從而避免顯示畫面出現色差。 相較於先前技術，純移暫衫之_方法，藉由該邏 輯電路於祕錄出電路之時鍾電晶體輪出時鐘訊號時 裁止該穩壓電晶體，以保證該移位暫存單元輸出時鐘訊 號則導通後4立移暫存單元之時鐘訊號電晶體亦導通 ，亦輸出時鐘訊號’由於相鄰二位移暫存單元接收之時 鐘訊號相反，故，該位銘蕲六怒 移暫存器之驅動方法使該位移暫 存器之輸出訊號無重叠。 【實施方式】 修正 [0022] 請參閱圖3，縣㈣位移暫料-難實施方式之結構 王架圖1¾位移暫存器2〇包括複數具有相同電路結構之 位移暫存單元，該紐位移暫存單元依:欠㈣，依次接 收外部電路提供之第_時鐘訊號ακ及與該第 一時鐘訊號 =。反相之第一時鐘訊號CUB、高電平訊號爾及低電平 S〉VGL 4位移暫存單元均由複數麵s型電晶體組成 每NMGS型電晶體均包括_閘極、源極及汲極。現以 一位移暫存單元21及與其_之第二位移暫存單元22 ^例說明該位移暫存㈣之連接_，該卜位移暫存 笛_ I括輪入訊號端STV、-第-輸出端VOUT1及- U出端V0UT2。該第二位移暫存單元22包括—訊號輸 入端VIN、一笛 —輪出端V()1及-第二輸出端V02。該第 第暫存單凡21之第一輸出端νουτι之輸出訊號作為該 暫存:元22之訊號輸入端vin之輸入訊號 :且該 兮存單元22之第二輸出端V〇2可將其輸出訊號反 °〆位移暫存單元21。該第-位移暫存單元21及 096135462 表單坞鱿A0101 笫12頁/共33頁 1003376108-0 1356.421 10 0年.10月13日梭正替換頁 該第二位移暫存單元22之第二輸出端V0UT2及V02為外部 電路（圖未示）提供訊號。 [0023] 請一併參閱圖4，係圖3所示之第一移位暫存單元21及該 第二移位暫存單元22相連接之電路圖。該第一移位暫存 單元21包括一訊號輸入電路211、一邏輯電路213、一反 饋電路215、一訊號輸出電路217及一第一節點XI。該第 ~~節點X1係該訊號輸入電路211、該邏輯電路213及該訊 號輸出電路217交匯形成。 [0024] 該訊號輸入電路211包括一第一電晶體Ml。該第一電晶體 Ml之汲極接收來自外部電路之高電平訊號VGH，其閘極作 為該位移暫存單元21之輸入端STV，其源極連接至該第一 節點XI。 [0025] 該邏輯電路213包括一第二電晶體M2、一第三電晶體M3、 一第四電晶體M4及一第五電晶體M5。該第二電晶體M2之 源極接收來自外部之低電平訊號VGL，其閘極與該第四電 晶體M4之閘極相連，且一併連接至該第一節點XI，其汲 極與該第五電晶體M5之源極相連。該第四電晶體M4之源 極接收來自外部之低電平訊號VGL，其汲極與該第三電晶 體M3之源極相連。該第三電晶體M3之閘極連接至該第二 電晶體M2之汲極，其汲極接收來自外部電路之高電平訊 號VGH。該第五電晶體M5之閘極與汲極相連，且一併接收 來自外部之高電平訊號VGH。 [0026] 該反饋電路215包括一第六電晶體M6、一第七電晶體M7、 一第八電晶體M8、一第九電晶體M9及一第二節點X2，該 096135462 表單編號A0101 第13頁/共33頁 1003376108-0 1356421 [0027] [0028] 096135462 100年.10月13日後正替换頁 第六電晶體M6之閘極接收第二位移暫存單元22之輸出訊 號，其汲極接收來自外部之高電平訊號VGH，其源極連接 至該第二節點X2。該第七電晶體M7之閘極與該第二節點 X2連接’其源極接收來自外部之低電平訊號VGL，其汲極 連接至該第—節點XI。該第八電晶體M8及該第九電晶體 M9之問極均與該第二節點X2連接，其二者源極均接收來 自外部之低電平電壓VGL，且二者之汲極均連接至該輸出 電路217。 該訊號輸出電路217包括一時鐘電晶體（未標示）及_穩壓 電晶體（未標示）。該時鐘電晶體包括一第十電晶體M10及 一第十一電晶體Mil，該第十電晶體M10及一第十一電晶 體Mil之閘極均連接至該第—節點XI，二者之及極均連接 該第時鐘訊號CLK，二者之源極則分別與該反饋電路 215之第八電晶體M8及第九電晶體M9之汲極連接以分別作 為該第一位移暫存單元21之第一輸出端V0UT1及第二輸出 端V0UT2。該第一輪出端v〇UT1之輸出訊號將輪出至該第 -位移暫存單元22之訊號輸人端。該第二輸出端v〇UT2則 輸出訊號至外部電路。該穩壓電晶體包括-第十二電晶 體”2，該第十二電晶體Μ12之閘極與該邏輯電路213之 第五電晶體Μ5之源極連接，其源極則接收外部低電平訊 號VGL ’其没極則連接至該第二輸出端V0UT2。 該第-位移暫存單元22之電路結構與該第—位移暫存單 兀21之電路結構相同’其亦包括十二個電晶體τ卜了12， 該訊號輸人端VIN、該第-輸出端V01、該第二輸出端 v〇2 0該第二位移暫存單元以與該第一位移暫存單元η之 表單編號A0101 第丨4頁/共33頁 1003376108-0 ⑶ 6421 100年.10月13日修 區別在於：該第二位㈣W純該第 單元21之第-輸出端_T1之輸出訊號作為訊號輪入端 川之輸入訊號，其第-輪出端V01與該第一位移暫存 :21之第六電晶體M6之間極連接；其第十電晶體T10與第 -電晶體Τ12之汲極均接收外部電路提供之第 號CLKB。 里訊 [0029] 請-併參閱圖5，係該第-位移暫存單元21及該第 暫存單元22之工作時序圖。在叫段前第_ 鐘訊號CLK及αο均域電平訊號VGL，該輪人端㈣二時 收之訊號為低電平訊號VGL，該第—節點χι、該第— —位移暫存早元21及22維持低電平。 [0030] 該在tl時段內，該第-位移暫存單元21接收之第 訊號CLK保持低電平訊號VGL，其接收端STv接收之輸人 訊號先為低電平訊號VGL，後為高電平訊號vgh。1 收之訊號為低電平訊號VGL時，該輸入電路2ΐι田、接 晶體Ml截止，該第一節點XI保持低電位， 一電 只孩輸出電路 217之第十及第十一電晶體Ml〇及Mu截止，該第—時鐘 訊號CLK無法輸出至該第一輸出端νουτ], ’ s亥第—輪出踹 V〇UT1保持低電位。同時，連接該第一筋 郎點XI之該邏輯電 路213之第二及第四電晶體M2及M4截止，目，丨— ⑴该第二及第四 電晶體M2及M4無法接收外部低電平訊號 然而，該邏 輯電路213之第五電晶體M5因閘極與汲極均接收外立古 平訊號VGH而導通，且將輸出該高電平訊號_以導^间電 十二電晶體M12，該第一位移暫存單元21 、 第一輸出端 V0UT2維持輸出低電平訊號VGL至外部電路。 096135462 表單編號A0101 第15頁/共33頁 1003376108-0 [0031] 卩〇〇年3^ϋΓ3日核正 在tl時間段内n位移暫存單元22接收之第二時鐘 訊號CLKB為低電平訊號VGL。此時，當該第二位移暫存單 元22之輸入端VIN接收該第一位移暫存單元21之第一輪出 端voim輸出之低電平訊號VGL，則該第二位移暫存單元 22之第一電晶體T1截止，該第—電晶體n之源極保持低 電平’則該第十及第十—電晶體T11維持截止狀態，該第 二位移暫存單元22之第-輪出端V(H及第 二輸出端V02保 持低电平《•同時，該第二及第四電晶體^及⑽持戴止 ’外部高電平訊號VGH經由該第五電晶體T5輸出至該第十 二電晶體Τ12 ’並導通該第十二電晶體m，以保持該第 -輸出端VG2輸出低電平訊號VGL至外部電路，且該第二 ，出端V02輪出之低電平訊號VGL反饋回該第一位移暫存 單兀21之第六電晶體M6之閘極，該第六電晶體保持截 止則該反館電路215之第七、第八及第九電晶體M7、M8 及M9均載止。 [0032] 在tl時間段内’备該第一位移暫存單元21之接收端爪接 平為高電平訊號VGH後，則其輸入 電路211之第-電晶體M1導通’外部高電平訊號彻經由 該第-電晶體Ml輸出至該第—節點χι，該第_節點^處 於高電平。則連接於該第-節點XI之第十及十一電晶體 Μ10及Mil導通，該第一時鐘訊號CLK經由該第十及十一 電晶體Ml 0及Mil於該第一位移暫存單元21之第一及第二 輸出端VOUT1及V〇UT2輸出。該第一輸出端…叮丨輸出該 第一時鐘訊號CLK至該第二位移暫存單元22，第二輸出 AfbV0UT2維持輸出低電平訊號VGl至外部電路。同時，連 096135462 表單編號A0101 第16頁/共33頁 1003376108-0 、以第即點χι之第一及第四電晶體被[_ 通，外部低電平訊號VGL經由該第二電晶體M2，將該第五 電晶體M5之源極電位拉低至低電平，則該輸出電路217之 第十二電晶體M12截止’該第二輪出端v〇UT2維持輪出該 第一時鐘訊號CLK。此時’該第二位移暫存單元& 輪入端VIN接收之輪入訊號仍為該第—位移暫存單元^ 出之低電平訊號VGL，其接收之第二時鐘訊號cub仍然為 高電平訊號VGH，則該第二位移暫存單元22之第一及第二 輸出端V01及V02維持輸出低電平訊號VGl。 一 _如時間段内，該第-位移暫存單元㈣收之第一時鐘 訊號CLK由低電平訊號VGL轉換為高電平訊號則。該第 -位移暫存單元21之訊號輸入端STV之輸入訊號先維持高 電平訊號VGH再跳轉為低電平訊號VGL。當該輸入訊號仍 維持高電平訊號VGH時，該第—節點^保持高電位該輸 出電路217之第十及十一電晶體μ 1〇及M11保持導通，為 高電平訊號VGH之該第一時鐘訊號CLK經由該第十及十一 電晶體Μ10、Mil於該第一位移暫存單元21之第一及第二 輸出端VOUT1及VOUT2輸出，且進一步拉高該第一節點χι 之電位。同時，該邏輯電路213之第二電晶體M2保持導通 ’該第五電晶體M5之源極保持低電位’則該輸出電路21了 之第十一電晶體Ml 2保持截止狀態，該第二輸出端ν〇υτ2 保持輸出該第一時鐘訊號CLK之高電平訊號VGh至外部電 路。 [0034] 在t2時間内，該第二位移暫存單元22接收之第二時鐘訊 號CLKB由高電平訊號VGH轉換為低電平訊號vgl。此時， 096135462 表單編號A0101 第17頁/共33頁 1003376108-0 1356421 100年10月13日修正替換頁 當該第一位移暫存單元21輸出之高電平訊號VGH輸入該第 二位移暫存單元22之訊號輸入端VIN，導通該第一電晶體 T1，則外部向電平訊號VGH經由該第一電晶體ή以導通該 第十電晶體no及該第十一電晶體Tu，該第一輸出端 νοι及該第二輸出端ν〇2輸出該第二時鐘訊號clkb，即輸 出低電平訊號VGL。同時，該第一電晶體T1輸出之高電平 訊號VGH亦導通該第二電晶體T2及該第四電晶體τ4，則該 第IL”㈣之源極電位被拉低至低電平，從而該第十 二電晶體m截止，該第二輸出端ν〇2維持輸出該第二時 鐘訊號C眼外部轉，謂該第二時鐘聰LKB反饋 :該：-位移暫存電路21之第六電晶體Μ6之閑極，該第 六電晶體Μ6保持截止’則該反饋電路215之第七八及 第九電晶體Μ7、Μ8及Μ9均截止。 [0035] STV之輪人㈣料71:21之訊號輸入端 之輸入訊唬由兩電平訊號VGH跳The drain of the TS is the first output terminal VI and the second output terminal V2 of the first clocked inverter circuit 110, and the source of the third transistor P3 is connected to the drain of the first transistor P1. The source of the fourth transistor P4 is connected to the gate of the first transistor P1. The commutation circuit 120 includes a fifth transistor P5, a sixth transistor P6, and a signal output terminal V. The gate of the fifth transistor P5 is connected to the first output terminal VI, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the sixth transistor P6. The gate of the sixth transistor P6 is connected to the second output terminal V2, and the drain thereof receives the low level signal VSS from the external circuit, and the source thereof is the signal output terminal V of the displacement temporary storage unit 100. The second clocked inverter circuit 130 includes a seventh transistor P7, an eighth transistor P8, a ninth transistor P9, and a tenth transistor P10. The gate of the seventh transistor P7 is connected to the signal output terminal V, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the eighth transistor P8. The gate of the eighth transistor P8 and its drain receive a low level signal VSS from the external circuit. The source of the ninth transistor P9 is connected to the first output terminal VI, the gate of which receives the clock signal TS from the external circuit, and the drain of which is connected to the seventh transistor? 7 bungee jumping. The gate of the tenth crystal 096135462 body receives the clock signal TS of the external circuit, and the source thereof is connected to the form number A0101. Page 6 / Total 33 pages 1003376108-0 1356, 421 100 years. October 13 correction for ¥ The second output terminal V2 has its drain connected to the signal output terminal V. [0008] Please refer to FIG. 2 together, which is a working sequence diagram of the displacement temporary storage unit 100. During the tl period, the output signal VS of the previous displacement temporary storage unit is changed from a high level to a low level, and the clock signal is inverted; ^7·from a low level to a high level 1 , level, The third transistor P3 and the fourth transistor P4 are turned off, and the first clocked inverter circuit 110 is turned off. The clock signal TS is changed from a high level to a low level, so that the ninth transistor P9 and the tenth transistor P10 are turned on, and the second clock inverting circuit 130 is turned on, and the signal output terminal V is turned on. The sixth state of the initial state is passed through the tenth transistor P10, and the sixth transistor P6 is turned off, and the low level of the output of the eighth transistor P8 is passed through the ninth transistor P9 to make the fifth transistor P5. Turning on, and then outputting the high level signal VDD of the source to the signal output terminal V, the signal output terminal V maintains a high level output. [0009] in the t2 period, the inverted clock signal; jumping from a high level to a low level, turning on the third transistor P3 and the fourth transistor P4, thereby inverting the first clock Circuit 110 is turned on. When the clock signal TS is changed from a low level to a high level, the ninth transistor P9 and the tenth transistor P10 are turned off, and the second clocked inverter circuit 130 is turned off. When the input signal VS is changed from a high level to a low level, the first transistor P1 is turned on, and the source high level VDD is turned off by the third transistor P3 to the fifth transistor P5 ′ and the The low level of the input signal VS is turned on by the fourth transistor P4 to turn on the sixth transistor P6, so that the signal output terminal V outputs a low level. [0010] In the t3 period, the inverted clock signal; from low level to high power 1 ΰ 096135462 Form number Α 0101 Page 7 / Total 33 page 1003376108-0 1356421 October 13, revised correction page flat Then, the third transistor P3 and the fourth transistor P4 are turned off, and the first clocked inverter circuit 110 is turned off. The clock signal TS is changed from a high level to a low level, and the ninth transistor P9 and the tenth transistor P10 are turned on, thereby turning on the second clock inverting circuit 130. The low level of the signal output terminal V turns on the seventh transistor P7, and the high level of the source thereof is turned off by the ninth transistor P9 to the fifth transistor P5. At the same time, the low level of the signal output terminal V is also turned on by the tenth transistor P10 to turn on the sixth transistor P6, and the lower level of the sixth transistor P6 keeps the signal output terminal V low. Output. [0011] in the period of t4, the inverted clock signal; from a high level transition to a low power 1 level, the third transistor Ρ3 and the fourth transistor Ρ4 are turned on, thereby making the first clock The inverter circuit 110 is turned on. The clock signal TS is changed from a low level to a high level to turn off the ninth transistor Ρ9 and the tenth transistor Ρ10, thereby causing the second clock inverting circuit 120 to be turned off. The level of the input signal VS is turned off by the fourth transistor Ρ4, and the second transistor Ρ2 is turned on to the fifth transistor through the third transistor Ρ3. Ρ5, the high level of the source is output to the signal output terminal V, and the output of the signal output terminal V is changed from a low level to a high level. [0012] It can be seen from the working sequence that the input signal VS of the displacement temporary storage unit 100 is the signal output by the previous displacement temporary storage unit during the t1 period and the t2 period, and the signal output terminal V outputs the signal during the t2 period and the t3 period. The input signal VS and the output signal have signal overlap in the t2 period, thereby causing the liquid crystal display using the displacement register as the data driving circuit and the scanning driving circuit. When performing column scanning or column scanning, there are two adjacent columns ( Row) or 096135462 column (Column) simultaneous scanning phenomenon, so load signal generation phase form number A0101 Page 8 / Total 33 page 1003376108-0 1356.421 October 13, 2014 revised replacement page mutual interference, make the face Produces a color difference. SUMMARY OF THE INVENTION [0013] In view of the above, it is necessary to provide a displacement register with no overlapping output signals. [0014] In addition, it is also necessary to provide a liquid crystal display that can avoid signal interference. [0015] Furthermore, it is necessary to provide a driving method for a displacement register in which the output signals are not overlapped. [0016] A displacement register includes a plurality of displacement temporary storage units, and two adjacent clock temporary signals received by the adjacent displacement temporary storage unit are inverted. Each displacement temporary storage unit includes a signal output circuit and a signal input circuit. And a logic circuit, the signal output circuit receives a clock signal from an external circuit, and includes a clock transistor that outputs the clock signal; and a voltage stabilizing transistor whose output signal is a constant low level signal; The signal input circuit receives the output signal of the previous displacement temporary storage unit, and the output signal turns on the clock transistor; the logic circuit receives a high level signal and a low level signal, and receives the signal output by the signal input circuit. Controlling the logic circuit to output the south level signal to the voltage stabilizing transistor or output the low level signal to the voltage stabilizing transistor; wherein, when the signal input circuit outputs a conduction signal to the clock transistor and the Logic circuit* The logic circuit outputs a low level signal to turn off the voltage stabilizing transistor, and the signal output circuit outputs the time through the clock transistor Signal, or vice versa. When the signal input circuit outputs a cutoff signal until the clock transistor intercepts the logic circuit, the logic circuit outputs a high level signal to turn on the voltage regulator transistor to maintain the output of the signal output circuit. Level signal. 096135462 Form No. A0101 Page 9 of 33 1003376108-0 October 13, 2014 Correction of a replacement liquid crystal display 'which includes a liquid crystal display panel, a data driving circuit and a scan driving circuit' The liquid crystal display panel provides a data signal, and the scan driving circuit provides a scan signal for the liquid crystal display panel. The data driving circuit and the scan driving circuit respectively comprise a shift register for controlling the output timing of the data signal and the scan signal. The memory includes a plurality of displacement temporary storage units, and the two adjacent clock temporary signals received by the two adjacent displacement temporary storage units are inverted. Each of the displacement temporary storage units includes a signal output circuit, a signal input circuit and a logic circuit. The output circuit receives a clock signal from an external circuit, and includes a clock transistor that outputs the clock signal; and a voltage stabilizing transistor whose output signal is a constant low level signal; the signal input circuit receives the pre-displacement The output signal of the temporary storage unit is turned on by the output signal; the logic circuit is switched a high level signal and a low level number and receiving a signal outputted by the input signal to control the logic circuit to rotate the high level signal to the voltage regulator transistor or output the low level signal to the stable a piezoelectric crystal; wherein, when the signal input circuit outputs a communication signal to the clock transistor and the logic circuit, the logic circuit outputs a low level signal to cut off the voltage stabilizing transistor, and the signal output circuit is driven by a clock transistor Outputting the clock signal; otherwise, when the signal input circuit stops the signal to the clock transistor and intercepts the logic circuit, the logic circuit outputs a high level signal to turn on the voltage regulator to maintain the The signal output circuit rotates a low level signal. The driving method of the displacement register, the displacement register comprises a complex displacement temporary storage unit, and the two clock signals received by the two adjacent displacement temporary storage units are inverted, and each displacement temporary storage unit comprises a signal output circuit - Form No. A0101 Page 0 of 33 pages 1003376108-0 1356.421 October 13th, 100th revised replacement signal input circuit and a logic circuit; the signal output circuit comprises a clock transistor and a voltage regulator transistor, The clock transistor receives the clock signal, and the voltage regulator transistor receives a low level signal. The logic circuit receives a high level signal and a low level signal. The driving method of the shift register includes the following steps. : a) - the signal input circuit of the shift register unit receives the output signal of the previous shift register unit to output a signal to the clock transistor and the logic circuit; b) the output signal turns on the clock transistor, the clock The transistor outputs the clock signal, and the output signal controls the logic circuit to output a low level signal to wear the voltage regulator transistor, so that the output circuit outputs the clock signal. ; C) the output signal of the output of the clock cutoff transistor, while the output signal of the control logic circuit outputs a high level signal of the regulator transistor is turned on, so that the output circuit outputs a low level signal. [0019] Compared with the prior art, when the clock signal transistor of each displacement temporary storage unit of the displacement register turns on the output clock signal, the clock signal transistor of the subsequent displacement temporary storage unit is also turned on, and the clock is also output. The signal, because the clock signals received by the adjacent two-displacement temporary storage unit are opposite, the signals output by the displacement register are not overlapped. [0020] Compared with the prior art, when the clock signal transistor of each displacement temporary storage unit of the displacement register of the liquid crystal display turns on the output clock signal, the clock signal transistor of the subsequent displacement temporary storage unit is also turned on. The clock signal is also output. Since the clock signals received by the adjacent two displacement temporary storage units are opposite, the signals outputted by the displacement register are not overlapped, so that the displacement register is used as the liquid crystal of the scan driving circuit and the data driving circuit. When the display is performing an intercept scan or a column scan, its output scan signal and data 096135462 Form No. A0101 Page 11 of 33 1003376108-0 1356421 [0021] The signal on October 13, 100 will not cause signal interference, thus avoiding display The color difference appears on the screen. Compared with the prior art, the method of purely shifting the temporary shirt, the logic circuit is used to cut the voltage regulator transistor when the clock transistor of the secret recording circuit rotates the clock signal to ensure the output of the shift register unit. After the clock signal is turned on, the clock signal transistor of the 4-stage shifting temporary storage unit is also turned on, and the clock signal is also output. 'Because the clock signal received by the adjacent two-displacement temporary storage unit is opposite, the bit 蕲 怒 怒 怒 暂 器The driving method makes the output signals of the displacement register have no overlap. [Embodiment] Correction [0022] Please refer to Figure 3, the county (four) displacement temporary material-difficult implementation of the structure of the king frame diagram 13⁄4 displacement register 2〇 includes a plurality of displacement temporary storage units with the same circuit structure, the new displacement temporarily The memory unit is owed (four), and sequentially receives the first clock signal ακ provided by the external circuit and the first clock signal=. Inverted first clock signal CUB, high level signal and low level S>VGL 4 displacement temporary storage unit are composed of complex surface s-type transistors. Each NMGS type transistor includes _ gate, source and 汲pole. Now, a displacement temporary storage unit 21 and a second displacement temporary storage unit 22 thereof are used to illustrate the connection of the displacement temporary storage (4), and the displacement temporary storage flute _I includes the wheeled signal terminal STV, - the first output Terminals VOUT1 and -U are at the end of V0UT2. The second displacement temporary storage unit 22 includes a signal input terminal VIN, a flute-round terminal V()1, and a second output terminal V02. The output signal of the first output terminal νουτι of the first temporary storage unit 21 is used as the input signal of the signal input terminal vin of the temporary storage unit 22: and the second output terminal V〇2 of the storage unit 22 can output the signal The signal is reversed to the displacement register unit 21. The first displacement temporary storage unit 21 and the 096135462 form docking station A0101 笫 12 pages / total 33 pages 1003376108-0 1356.421 10 0. October 13 shuttle replacement page the second displacement temporary storage unit 22 second output V0UT2 and V02 provide signals for external circuits (not shown). [0023] Referring to FIG. 4 together, a circuit diagram of the first shift temporary storage unit 21 and the second shift temporary storage unit 22 shown in FIG. 3 is connected. The first shift register unit 21 includes a signal input circuit 211, a logic circuit 213, a feedback circuit 215, a signal output circuit 217 and a first node XI. The first node X1 is formed by the signal input circuit 211, the logic circuit 213, and the signal output circuit 217. [0024] The signal input circuit 211 includes a first transistor M1. The drain of the first transistor M1 receives a high level signal VGH from an external circuit, the gate of which is the input terminal STV of the shift register unit 21, and the source thereof is connected to the first node XI. [0025] The logic circuit 213 includes a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The source of the second transistor M2 receives the low level signal VGL from the outside, and the gate thereof is connected to the gate of the fourth transistor M4, and is connected to the first node XI, and the drain is The source of the fifth transistor M5 is connected. The source of the fourth transistor M4 receives a low level signal VGL from the outside, and its drain is connected to the source of the third transistor M3. The gate of the third transistor M3 is connected to the drain of the second transistor M2, and the drain thereof receives the high level signal VGH from the external circuit. The gate of the fifth transistor M5 is connected to the drain and receives the high level signal VGH from the outside. The feedback circuit 215 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a second node X2. The 096135462 form number A0101 page 13 / Total 33 pages 1003376108-0 1356421 [0028] [0028] 096135462 100 years. After October 13th, the gate of the sixth transistor M6 is replaced by the output of the second displacement temporary storage unit 22, and the drain receiving is from The external high level signal VGH has its source connected to the second node X2. The gate of the seventh transistor M7 is connected to the second node X2. The source receives a low level signal VGL from the outside, and its drain is connected to the first node XI. The eighth transistor M8 and the ninth transistor M9 are connected to the second node X2, and both of the sources receive the low-level voltage VGL from the outside, and the drains of the two are connected to The output circuit 217. The signal output circuit 217 includes a clock transistor (not shown) and a Zener transistor (not shown). The clock transistor includes a tenth transistor M10 and an eleventh transistor Mil, and the gates of the tenth transistor M10 and the eleventh transistor Mil are connected to the first node XI, and the two The poles are connected to the first clock signal CLK, and the sources of the two are respectively connected to the drains of the eighth transistor M8 and the ninth transistor M9 of the feedback circuit 215 to respectively serve as the first displacement temporary storage unit 21 An output terminal VOUT1 and a second output terminal VOUT2. The output signal of the first round of the output terminal v〇UT1 will be rotated to the signal input end of the first-displacement temporary storage unit 22. The second output terminal v〇UT2 outputs a signal to an external circuit. The voltage stabilizing transistor comprises a twelfth transistor "2", the gate of the twelfth transistor Μ12 is connected to the source of the fifth transistor Μ5 of the logic circuit 213, and the source thereof receives an external low level. The signal VGL 'the pole is connected to the second output terminal V0UT2. The circuit structure of the first-displacement temporary storage unit 22 is the same as that of the first-displacement temporary storage unit 21', which also includes twelve transistors τ 12, the signal input terminal VIN, the first output terminal V01, the second output terminal v〇2 0, the second displacement temporary storage unit and the first displacement temporary storage unit η form number A0101 4 pages/total 33 pages 1003376108-0 (3) 6421 100 years. The difference between October 13 and October is that the second (four) W pure output signal of the first-output _T1 of the first unit 21 is used as the input of the signal wheel The signal, the first-round terminal V01 and the first displacement temporary storage: 21, the sixth transistor M6 is connected to the pole; the tenth transistor T10 and the first transistor of the first transistor T12 are received by an external circuit. No. CLKB. Lixun [0029] Please - and refer to FIG. 5, the first displacement register unit 21 and the temporary storage unit 22 Working timing diagram. Before the segment is called the _ clock signal CLK and αο the average level signal VGL, the round end of the round (4) two times the signal is the low level signal VGL, the first node χι, the first shift The temporary signal 21 and 22 are maintained at a low level. [0030] During the tl period, the first signal received by the first-displacement temporary storage unit 21 holds the low-level signal VGL, and the receiving end STv receives the input signal. First, the low level signal VGL, then the high level signal vgh. 1 When the signal is low level signal VGL, the input circuit 2ΐι, the crystal M1 is cut off, the first node XI is kept low, one electric The tenth and eleventh transistors M1〇 and Mu of the output circuit 217 are turned off, and the first clock signal CLK cannot be output to the first output terminal νουτ], and the shai-first round-out 踹V〇UT1 remains low. At the same time, the second and fourth transistors M2 and M4 of the logic circuit 213 connected to the first rib point XI are turned off, and the second and fourth transistors M2 and M4 cannot receive the external low. Level signal However, the fifth transistor M5 of the logic circuit 213 receives the external dynasty due to both the gate and the drain. The signal VGH is turned on, and the high level signal _ is outputted to guide the 12th transistor M12, and the first displacement register unit 21 and the first output terminal V0UT2 maintain the output low level signal VGL to the external circuit. 096135462 Form No. A0101 Page 15 of 33 1003376108-0 [0031] The third clock signal CLKB received by the n-displacement temporary storage unit 22 in the tl time period is a low-level signal. VGL. At this time, when the input terminal VIN of the second displacement temporary storage unit 22 receives the low-level signal VGL outputted by the first round-out terminal voim of the first displacement temporary storage unit 21, the second displacement temporary storage unit 22 The first transistor T1 is turned off, the source of the first transistor n is kept at a low level, and the tenth and tenth transistors T11 are maintained in an off state, and the first wheel end of the second displacement register unit 22 is maintained. V (H and the second output terminal V02 are kept at a low level. • At the same time, the second and fourth transistors ^ and (10) are held. The external high level signal VGH is output to the tenth via the fifth transistor T5. The second transistor Τ12' turns on the twelfth transistor m to keep the first output terminal VG2 outputting the low level signal VGL to the external circuit, and the second, the output terminal V02 rotates the low level signal VGL feedback Returning to the gate of the sixth transistor M6 of the first displacement temporary storage unit 21, the sixth transistor remains off, and the seventh, eighth and ninth transistors M7, M8 and M9 of the reverse circuit 215 are both loaded. [0032] After the receiving end claw of the first displacement temporary storage unit 21 is leveled to the high level signal VGH in the time period of tl, The first transistor M1 of the input circuit 211 is turned on, and the external high level signal is output to the first node 经由ι via the first transistor M1. The _th node is at a high level, and is connected to the first node. The tenth and eleventh transistors XI of the XI are turned on, and the first clock signal CLK is passed through the tenth and eleventh transistors M10 and Mil to the first and second outputs of the first displacement temporary storage unit 21. VOUT1 and V〇UT2 output. The first output terminal ... outputs the first clock signal CLK to the second shift register unit 22, and the second output AfbV0UT2 maintains the output low level signal VG1 to the external circuit. 096135462 Form No. A0101 Page 16 of 33 1003376108-0, the first and fourth transistors of the first point χι are [_ pass, the external low level signal VGL via the second transistor M2, the first When the source potential of the fifth transistor M5 is pulled low to the low level, the twelfth transistor M12 of the output circuit 217 is turned off. The second round terminal v〇UT2 maintains the first clock signal CLK. 'The second displacement temporary storage unit & the round-in terminal VIN receives the round-in signal is still the first The low-level signal VGL of the displacement temporary storage unit is still the high-level signal VGH, and the first and second output terminals V01 and V02 of the second displacement temporary storage unit 22 are maintained. The low-level signal VG1 is output. In the time period, the first-displacement temporary storage unit (4) receives the first clock signal CLK and is converted from the low-level signal VGL to the high-level signal. The first-displacement temporary storage unit The input signal of the signal input terminal ST of 21 first maintains the high level signal VGH and then jumps to the low level signal VGL. When the input signal still maintains the high level signal VGH, the first node ^ remains high. The tenth and eleventh transistors μ 1 〇 and M11 of the output circuit 217 remain turned on, which is the level of the high level signal VGH. A clock signal CLK is output to the first and second output terminals VOUT1 and VOUT2 of the first shift register unit 21 via the tenth and eleventh transistors Μ10 and Mil, and further increases the potential of the first node χι. At the same time, the second transistor M2 of the logic circuit 213 remains turned on 'the source of the fifth transistor M5 remains low', then the eleventh transistor M12 of the output circuit 21 remains off, the second output The terminal ν〇υτ2 keeps outputting the high level signal VGh of the first clock signal CLK to the external circuit. [0034] During the time t2, the second clock signal CLKB received by the second displacement temporary storage unit 22 is converted from the high level signal VGH to the low level signal vgl. At this time, 096135462 Form No. A0101 Page 17 / Total 33 Page 1003376108-0 1356421 October 13th, 100th Correction Replacement Page When the first displacement temporary storage unit 21 outputs the high level signal VGH, the second displacement is temporarily stored. The signal input terminal VIN of the unit 22 turns on the first transistor T1, and the external level signal VGH passes through the first transistor 导 to turn on the tenth transistor no and the eleventh transistor Tu, the first The output terminal νοι and the second output terminal ν〇2 output the second clock signal clkb, that is, output a low level signal VGL. At the same time, the high-level signal VGH outputted by the first transistor T1 also turns on the second transistor T2 and the fourth transistor τ4, and the source potential of the first IL" (4) is pulled low to a low level, thereby The twelfth transistor m is turned off, and the second output terminal ν〇2 maintains outputting the second clock signal C eye external rotation, that is, the second clock Cong LKB feedback: the: sixth displacement of the displacement temporary storage circuit 21 The sixth transistor Μ6 remains off, and the seventh and ninth transistors Μ7, Μ8 and Μ9 of the feedback circuit 215 are all turned off. [0035] STV wheel (4) material 71:21 The input signal of the signal input is jumped by the two-level signal VGH
後/低電平訊號VGL W… 電晶_截止，該第 -即點XI保持南電位，則該第一 該第 輸出端讀1及第高糊T2維持輪H1之第一 VGH，該第十二電晶體川仍然截止/電+訊琥 端VOUT2之輪出。因此，此時，該第二影響該第二輸出 接故之訊號未改變，故，其第一輸7位移暫存單元22所 V02輸出之訊號保持不變。 ㈣01及第二輸出端 [0036] 隹吟間段内 096135462 议移瞀存早元21 持接收該低電平訊號VGL，當第_時Α 。琥輪入端STV保 訊號VGH轉換為低電平由高電平 4苐一位移暫存單 表單編號A0101 第丨8頁/共33頁 元 1003376108-0 1356.421 100年10月13日按正替k頁 21之第-電晶舰保持戴止，該第—節點χι保持高電位 ’該第十電晶體Ml0及該第十一電晶體Mu保持導通該 第一輸出端麵1及該第二輸出端VOUT2輪出該第一時鐘 訊號CLK，即輸出低電平訊號VGL。 [0037] 此時’該第二位移暫存單⑽純之第二時鐘訊號CLKB 由低電平訊號VGL轉換為高電平訊號⑽，其訊號輸入端 VIN魏該第-位移暫存單切輪出之低電平訊號似， 則該第二位移暫存單元22之第—電晶體n截止其第十 電晶體τιο及第十一電晶體T11保持導通狀態該第一輸 出端νοι及該第二輸出·2輸出該第二時鐘訊號clkb， 即’輸出該高電平訊號VGHe該第二輸出端輸出之高 電平訊號VGH輸出至外部電路，且反饋回該第一位移暫存 單元21之第六電晶體M6 ’該第六電晶體M6導通，接收外 部高電平訊號則，以導通該第七、第八及第九電晶體m7 、M8M9，則該第七、第八及第九電晶體M7、M8及M9接 收外部低電平訊號VGL ’將該第—節點χι、該第一輸出端 V0UT1及第二輸出端V0UT2拉低至低電平。從而，該輸出 電路217之第十電晶體M10及第十一電晶體Mu截止該 邏輯電路213之第二電晶體M2戴止，該第五電晶體妣恆接 收之高電平訊號VGH導通該第十二電晶體M12，保證該第 二輸出端V0UT2輸出低電平訊號VGL，不產生任何雜訊 (ripple) » 在t3時間段後，該第一位移暫存單元2丨之接收端gTV接收 之訊號保持低電平訊號VGL ’且其第一節點χι保持低電位 ，則該輸出電路217之第十電晶體Ml〇及第十一電晶體 096135462 表單编號A0101 第19頁/共33頁 1003376108-0 [0038] 1100 年·10 月After/low level signal VGL W... The transistor _ off, the first point XI is maintained at the south potential, then the first output terminal 1 and the first paste T2 maintain the first VGH of the wheel H1, the tenth The second transistor is still cut off / electricity + signal aussie VOUT2 round out. Therefore, at this time, the second signal affecting the second output is not changed, so the signal outputted by the V02 of the first transmission 7 displacement temporary storage unit 22 remains unchanged. (4) 01 and the second output end [0036] 隹吟 096 21 21 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 The input signal of the STV protection signal VGH is converted to a low level by the high level 4苐 one displacement temporary storage form number A0101 page 8/33 pages 1003376108-0 1356.421 October 13th, according to the positive k page In the 21st - the electro-crystal ship remains worn, the first node χι maintains a high potential. The tenth transistor M10 and the eleventh transistor Mu remain conductive to the first output end face 1 and the second output end VOUT2 The first clock signal CLK is rotated, that is, the low level signal VGL is output. [0037] At this time, the second shift temporary register (10) pure second clock signal CLKB is converted from the low level signal VGL to the high level signal (10), and the signal input terminal VIN is the first-displacement temporary storage single-cutting wheel The first output terminal νοι and the second output are turned on by the first transistor τιο and the eleventh transistor T11 of the second shift register unit 22 are turned off. 2 outputting the second clock signal clkb, that is, 'outputting the high level signal VGHe, the high level signal VGH outputted by the second output terminal is output to the external circuit, and is fed back to the sixth power of the first displacement temporary storage unit 21 The crystal M6 'the sixth transistor M6 is turned on, and receives the external high level signal to turn on the seventh, eighth and ninth transistors m7, M8M9, then the seventh, eighth and ninth transistors M7, M8 and M9 receive the external low level signal VGL 'to pull the first node χι, the first output terminal V0UT1 and the second output terminal V0UT2 to a low level. Therefore, the tenth transistor M10 of the output circuit 217 and the eleventh transistor Mu cut off the second transistor M2 of the logic circuit 213, and the fifth transistor continuously receives the high level signal VGH to turn on the first The twelve transistor M12 ensures that the second output terminal VOUT2 outputs a low level signal VGL without generating any ripples. » After the t3 time period, the receiving terminal gTV of the first displacement temporary storage unit 2 receives The signal keeps the low level signal VGL 'and its first node χ is kept low, then the tenth transistor M1 〇 of the output circuit 217 and the eleventh transistor 096135462 Form No. A0101 Page 19 / Total 33 Page 1003376108- 0 [0038] 1100 October
Mll截止，該第一時鐘訊號CLK無法藉由第十電晶體M10 及第十一電晶體Mil輸出，且該第五電晶體M5恆導通，以 輪出高電平訊號VGH導通該第十二電晶體M12以保持該第 二輪出端V0UT2保持輸出低電平訊號VGL。同理可知，該 第二位移暫存單元22於第十電晶體Ml 0及第十一電晶體 Ml1保持輸出低電平訊號VGL。 [0039] 自工作時序來看，由於該第一位移暫存單元21之時鐘訊 號電晶體M10及Mil導通輸出時鐘訊號時，該第二位移暫 存單元22之時鐘訊號電晶體T1〇&Tn導通’亦輸出時鐘 訊號，由於該第一位移暫存單元21及第 > 位移暫存單元 22接收之時鐘訊號相反，故，該第一位務暫存單元21及 第一位移暫存單元22輸出之訊號無重叠β另’當該第二 位移暫存單元22輸出之訊號為高電平訊號VGH，即可藉由 S亥反饋電路215對該第一位移暫存單元21進行重置，使該 第一位移暫存單元21之第十電晶體Ml〇與該第十一電晶體 MU截止，從而保證該第一位移暫存單元21之藉由該第十 二電晶體M12輸出低電平訊號VGL，與該第二位移暫存單 元22輸出之訊號相反，不重疊。 [0040] 另，該第一位移暫存單元21之反饋電路215藉由該第七電 曰日體M7、第八電晶體M8及第九電晶體㈣〆i對該第一位 移暫存單元21進行重置，從而重置所需時間短。 [0041] 096135462 請參閲圓6，係應用圖3所示之位移暫存器2〇之液晶顯示 器之結構示意圖。該液晶顯示器30包括〆液晶顯示面板 31、一資料驅動電路32及一掃描驅動電路33。該液晶顯 示面板31包括一上基板（圖未示）、—下恭板（圖未示）及M11 is turned off, the first clock signal CLK cannot be output by the tenth transistor M10 and the eleventh transistor Mil, and the fifth transistor M5 is always turned on to turn on the high level signal VGH to turn on the twelfth electricity. The crystal M12 keeps the output of the low level signal VGL while keeping the second round end V0UT2. Similarly, the second displacement temporary storage unit 22 keeps outputting the low level signal VGL in the tenth transistor M10 and the eleventh transistor M11. [0039] From the working timing, when the clock signal transistors M10 and Mil of the first displacement temporary storage unit 21 turn on the output clock signal, the clock signal transistors T1〇&Tn of the second displacement temporary storage unit 22 The turn-on 'outputs the clock signal. Since the clock signals received by the first displacement temporary storage unit 21 and the third displacement temporary storage unit 22 are opposite, the first temporary storage unit 21 and the first displacement temporary storage unit 22 The output signal has no overlap β. When the signal output by the second displacement temporary storage unit 22 is the high level signal VGH, the first displacement temporary storage unit 21 can be reset by the S-new feedback circuit 215. The tenth transistor M1〇 of the first displacement temporary storage unit 21 and the eleventh transistor MU are turned off, thereby ensuring that the first displacement temporary storage unit 21 outputs a low level signal by the twelfth transistor M12. The VGL is opposite to the signal output by the second displacement temporary storage unit 22 and does not overlap. [0040] In addition, the feedback circuit 215 of the first displacement temporary storage unit 21 is configured to the first displacement temporary storage unit 21 by the seventh power semiconductor body M7, the eighth transistor M8, and the ninth transistor (four) 〆i. Reset is performed so that the reset takes a short time. [0041] 096135462 Please refer to circle 6, which is a schematic structural diagram of a liquid crystal display using the displacement register 2 shown in FIG. The liquid crystal display 30 includes a liquid crystal display panel 31, a data driving circuit 32, and a scan driving circuit 33. The liquid crystal display panel 31 includes an upper substrate (not shown), a lower panel (not shown), and
表單編號A010I 苐20頁/共33頁 1003376108-0 1356421 月13日核IE雜ΈΓ 一夾持於上基板與下基板間之液晶層（圖未示），且於該 下基板鄰近液晶層一側設置有一用於控制液晶分子扭轉 狀況之薄膜電晶體陣列（圖未示）。該掃描驅動電路33輸 出掃描訊號以控制該液晶顯示面板31之薄膜電晶體矩陣 之導通與截止狀態，該資料驅動電路32輸出資料訊號控 制該液晶顯示面板31顯示畫面變化。該掃描駆動電路μ 及該資料驅動電路32皆利用該位移暫存器2〇控制掃描訊 號與資料訊號之輸出時序’從而控制該液晶顯示面板31 之顯示。該位移暫存器20可與該液晶顯示器3〇之薄臈電 晶體陣列於同一製程内形成。 [0042] 由於該位移暫存器20之各級位移暫存單元之輸出不存在 訊號重疊現象’故使得使用該位移暫存器2〇作為掃描駆 動電路32及資料驅動電路33之液晶顯示器3〇在進行攔掃 描或列掃描時，其輸出掃描訊號及資料訊號不會產生訊 號干擾，從而避免顯示畫面出現色差。 [0043] 綜上所述，本發明確已符合發明專利之要件，爰依法提 出專利巾請。惟，以上所述者僅為本發明之較佳實施方 式，本發狀關衫以上述實施^㈣，舉凡熟头 本案技藝之人士援依本發明之精神所作之等效修飾或變 化’皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0044] Μ係-種先前技術位移暫存器之位移暫存單元之電路圖 〇 圖2係圖1所示之位移暫存單元之工作 吓時序圖。 096135462 表單编號Α0101 第21頁/共33頁 1003376108-0 [0045] 1356421 100年10月13日按正替換頁 [0046] [0047] [0048] [0049] [0050] [0051] [0052] [0053] [0054] [0055] [0056] [0057] [0058] [0059] [0060] [0061] [0062] 096135462 圖3係本發明位移暫存器一較佳實施方式之結構框架圖。 圖4係圖3所示之第一移位暫存單元及該第二移位暫存單 元之電路圖。 圖5係圖4所示第一位移暫存單元及第二位移暫存單元之 工作時序圖。 圖6係應用圖3所示之位移暫存器之液晶顯示器之結構示 意圖。 【主要元件符號說明】 位移暫存器：20 訊號輸入電路：211 邏輯電路：213 反饋電路：215 訊號輸出電路：217Form No. A010I 苐 20 pages / Total 33 pages 1003376108-0 1356421 13th Nuclear IE ΈΓ A liquid crystal layer (not shown) sandwiched between the upper substrate and the lower substrate, and adjacent to the liquid crystal layer side of the lower substrate A thin film transistor array (not shown) for controlling the twist state of the liquid crystal molecules is provided. The scan driving circuit 33 outputs a scan signal to control the on and off states of the thin film transistor matrix of the liquid crystal display panel 31. The data driving circuit 32 outputs a data signal to control the liquid crystal display panel 31 to display a picture change. The scan flip-flop circuit μ and the data drive circuit 32 both control the display timing of the scan signal and the data signal by using the shift register 2 to control the display of the liquid crystal display panel 31. The displacement register 20 can be formed in the same process as the thin-film array of the liquid crystal display. [0042] Since the output of the displacement register unit of the displacement register 20 has no signal overlap phenomenon, the displacement register 2 is used as the liquid crystal display 3 of the scan squeezing circuit 32 and the data driving circuit 33. When performing an intercept scan or a column scan, the output scan signal and the data signal do not cause signal interference, thereby avoiding chromatic aberration on the display screen. [0043] In summary, the present invention has indeed met the requirements of the invention patent, and the patent towel is required according to law. However, the above description is only a preferred embodiment of the present invention, and the present invention is based on the above-mentioned implementation (4), and the equivalent modification or variation made by the person skilled in the art of the present invention in accordance with the spirit of the present invention should be It is covered by the following patent application. [Simple diagram of the diagram] [0044] The circuit diagram of the displacement temporary storage unit of the prior art displacement register 〇 Figure 2 is the operation timing diagram of the displacement temporary storage unit shown in Fig. 1. 096135462 Form No. 1010101 Page 21 of 33 1003376108-0 [0045] 1356421 October 13th, 100th, according to the replacement page [0046] [0048] [0049] [0052] [0052] [0058] [0058] [0062] FIG. 3 is a structural block diagram of a preferred embodiment of the displacement register of the present invention. 4 is a circuit diagram of the first shift register unit and the second shift register unit shown in FIG. FIG. 5 is a timing chart showing the operation of the first displacement temporary storage unit and the second displacement temporary storage unit shown in FIG. 4. Fig. 6 is a view showing the construction of a liquid crystal display to which the shift register shown in Fig. 3 is applied. [Main component symbol description] Displacement register: 20 signal input circuit: 211 logic circuit: 213 feedback circuit: 215 signal output circuit: 217
訊號輸入端：STV、VIN 第一電晶體：Ml、T1 第二電晶體：M2、T2 第三電晶體：M3、T3 第四電晶體：M4、T4 第五電晶體：M5、T5 第六電晶體：M6、T6 第七電晶體：M7、T7 表單編號A0101 第22頁/共33頁 1003376108-0 1356421 [0063] 第八電晶體：M8、T8 [0064] 第九電晶體：M9、T9 [0065] 第十電晶體：M10、T10 [0066] 第十一電晶體：Mil、 T11 [0067] 第十二電晶體：M12、 T12 [0068] 高電平訊號：VGH [0069] 低電平訊號：VGL [0070] 第一時鐘訊號：CLK [0071] 第二時鐘訊號：CLKB [0072] 第一節點：XI [0073] 第二節點：X2 [0074] 液晶顯不' . 3 0 [0075] 液晶顯不面板.31 [0076] 掃描驅動電路：32 [0077] 資料驅動電路：33 [0078] 第一位移暫存單元：21 [0079] 第二位移暫存單元：22 [0080] 第一輸出端：VOUT1、 V01 [0081] 第二輸出端：VOUT2、 V02 096135462 表單編號A0101 第23頁/共33頁 100年.10月13日修正替換頁 1003376108-0Signal input: STV, VIN First transistor: Ml, T1 Second transistor: M2, T2 Third transistor: M3, T3 Fourth transistor: M4, T4 Fifth transistor: M5, T5 Sixth Crystal: M6, T6 Seventh transistor: M7, T7 Form No. A0101 Page 22 / Total 33 1003376108-0 1356421 [0063] Eighth transistor: M8, T8 [0064] Ninth transistor: M9, T9 [ 0065] Tenth transistor: M10, T10 [0066] Eleventh transistor: Mil, T11 [0067] Twelfth transistor: M12, T12 [0068] High level signal: VGH [0069] Low level signal :VGL [0070] First clock signal: CLK [0071] Second clock signal: CLKB [0072] First node: XI [0073] Second node: X2 [0074] Liquid crystal display is not '. 3 0 [0075] Liquid crystal Display Panel. 31 [0076] Scan Drive Circuit: 32 [0077] Data Drive Circuit: 33 [0078] First Displacement Temporary Unit: 21 [0079] Second Displacement Temporary Unit: 22 [0080] First Output :VOUT1, V01 [0081] Second output: VOUT2, V02 096135462 Form number A0101 Page 23 of 33 100 years. October 13 revision replacement page 1003 376108-0