1354335 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種具有雙金屬閘極(dual metal gate) 之互補式金氧半導體(complementary metal-oxide semiconductor，以下簡稱為CMOS)元件之製作方法，尤指 一種實施後閘極(gate last)製程之具有雙金屬閘極CMOS元 件之製作方法。 【先前技術】 隨著CMOS元件尺寸持續微縮，傳統方法中利用降低閘 極介電層，例如降低二氧化>5夕層厚度，以達到最佳化目的之 方法’係面臨到因電子的穿遂效應(tunneling effect)而導致漏 電流過大的物理限制。為了有效延展邏輯元件的世代演進， 南介電常數（以下簡稱為High-K)材料因具有可有效降低物 理極限厚度，並且在相同的等效氧化厚度(equivalent 〇xide thickness ’以下簡稱為EOT)下，有效降低漏電流並達成等 效電谷以控制通道開關荨優點’而被用以取代傳統二氧化碎 層或氮氧化矽層作為閘極介電層。 此外，傳統的多晶矽閘極則因硼穿透（b〇r〇n penetrati〇n) 效應’導致元件效能降低等問題；且多晶石夕閘極更遭遇難 以避免的空乏效應（depletion effect)，使得等效的閘極介電 層厚度增加、閘極電容值下降，進而導致元件驅動能力的 6 1354335 衰退等困境。故目前便有新的閘極材料被研製生產，例如 利用雙功能函數(double work function)金屬來取代傳統的 多晶碎閘極’用以作為匹配High-K閘極介電層的於制電 極。 雙功能函數金屬閘極一需與NMOS元件搭配，—則需與 PMOS元件搭配，因此使得相關元件的整合技術以及製程 控制更形複雜’且各材料的厚度與成分控制要求亦更形嚴 苛。雙功能函數金屬閘極之製作方法係概分為前閘極(gate first)製程友後閘極(gate last)製程兩大類。其中前閘極製程 會在形成金屬閘極後經過源極/>及極超淺接面活化回火以 及形成金屬矽化物等製程，而在如此嚴苛的熱預算環境 下，常會發現高溫回火製程後元件的平帶電壓（flat band voltage，以下簡稱為vy與EOT並未呈現預期的線性關 係，反而在EOT減小時突然發生下降(r〇U_0ff)的情形。 由於Vfb下降以及High-K閘極介電層在高溫環境中結晶 導致漏電流增加之問題，導致High-K閘極介電層與金屬閘 極的材料選擇須面對較多的挑戰，也因此業界係提出以後 閘極製程取代前閘極製程之方法。 【發明内容】 因此，本發明之一目的係在於提供一種實施後閘極製程 7 1354335 的具有雙金屬閘極之互補式金氧半導體元件製作方法 根據本發明所提供之申請專利範圍，係提供一種具有雙 金屬閘極之互補式金氧半導體(〇河〇8)元件之製作方法。咳 方法包含有k供一基底，該基底表面形成有一第一導電型 電晶體、-第二導電型電晶體、以及一覆蓋該第一導電型 電晶體與該第二導電型電晶體之介電層。接下來平坦化該 介電層至分別暴露出該第-導電型電晶體之一第一開極^ 該第二導電型電晶體之一第二閘極之間極導電層’並於^ 基底上形成-覆蓋該第二導電型電晶體及暴露出該第一導 電型電晶體之圖案化阻擋層(patterned blocking la㈣。隨後 進行一第-1虫刻製程，用以移除該第—間極之該間極導電 二^ 一第一開口 (。pening)。待第一開口鲁 =第-開口内依序形成一第一金屬層與一第二金屬層。 並進！：覆蓋該第二導電型電晶體之該圖案化阻播層， 、進仃-第二蝕刻製程’用以移 電層，而形成間極之δ亥閘極導 第-開口内伊皮開口形成後，係於該 第-·内依序形成—第三金屬層與1四金屬層。 根據本發明所提供之 導趙元件之㈣方法，各導電型互補式金氧半 法製作而成，故此體皆是利用後閉極方 裎皆已完成。因 到上述製程的高 此填入第 、第二開口的金屬層均不會受 而要“熱預异的製程皆… 8 1354335 熱預算影響，因而可降低元件的下降問題；此外更享 有廣泛的金屬閘極材料選擇之優點。 【實施方式】 請參閱第1圖至第13圖’第1圖至第13圖係為本發明 所提供之具有雙金屬閘極之CMOS元件之製作方法之一較 佳實施例之示意圖。如第1圖所示，首先提供一基底2〇〇， • 如一石夕基底、含石夕基底、或石夕覆絕緣(silicon-on-insulator， SOI)基底等，基底200表面定義有一第一主動區域21〇與 一第二主動區域212 ’且基底200内係形成有一用以電性 隔離第一主動區域210與第二主動區域212之淺溝絕緣 (shallow trench isolation，STI) 202。接下來於基底 200 上 依序形成一閘極介電層204、一閘極導電層如一多晶石夕層 206、與一硬遮罩層（圖未示）。其中閘極介電層204可為一 傳統的二氧化矽層或氮氧化矽層，亦可為一高介電常數（以 鲁 下簡稱為High-K)材料層。此外，亦可於多晶石夕層206上 選擇性地形成一覆蓋層（cap layer)(圖未示）或一反射層 (ARC layer)(圖未示）。隨後係藉由一微影暨蝕刻製程圖案 化此硬遮罩屬，以形成如第1圖所示之用以定義閘極位置 之圖案化硬遮罩層208。 請參閱第2圖。接下來係透過圖案化硬遮罩層208進行 一蝕刻製程，蝕刻多晶矽層206與閘極介電層204，而於 9 1354335 第一主動區域210與第二主動區域212内分別形成一第一 閘極220與一第二閘極222。請繼績參閱第2圖，接下來 係利用不同導電型之離子佈植製程於第一閘極220與第二 閘極222兩侧之基底200内分別形成一第一輕摻雜沒極1354335 IX. Description of the Invention: [Technical Field] The present invention relates to the fabrication of a complementary metal-oxide semiconductor (hereinafter referred to as CMOS) device having a dual metal gate. The method, in particular, is a method for fabricating a bimetal gate CMOS device that implements a gate last process. [Prior Art] As the size of CMOS components continues to shrink, the conventional method utilizes a method of lowering the gate dielectric layer, for example, reducing the thickness of the dioxide layer, to achieve the purpose of optimization, which is faced with the wear of electrons. The tunneling effect leads to physical limitations of excessive leakage current. In order to effectively extend the evolution of logic components, the South Dielectric Constant (hereinafter referred to as High-K) material has an effective reduction in physical limit thickness and the same equivalent oxidized thickness (EOT). In order to effectively reduce the leakage current and achieve the equivalent electric valley to control the channel switch, it is used to replace the conventional dioxide layer or the yttria layer as the gate dielectric layer. In addition, the conventional polycrystalline germanium gates cause problems such as reduced element efficiency due to the boron penetration (b〇r〇n penetrati〇n) effect; and the polycrystalline stone gate is more difficult to avoid the depletion effect. The thickness of the equivalent gate dielectric layer is increased, and the gate capacitance value is decreased, which leads to the dilemma of the component driving capability of 6 1354335. Therefore, new gate materials have been developed and produced, for example, by using a double work function metal instead of a conventional polycrystalline gate to serve as a electrode for matching the High-K gate dielectric layer. . The dual function metal gates need to be paired with NMOS components—and they need to be paired with PMOS components, which makes the integration of the related components and process control more complex, and the thickness and composition control requirements of each material are more stringent. The bi-function function metal gate is divided into two major categories: the gate first process and the gate last process. The front gate process will pass through the source/> and the ultra-shallow junction activation tempering and the formation of metal telluride after the formation of the metal gate, and in such a harsh thermal budget environment, high temperature is often found. The flat band voltage of the component after the fire process (hereinafter referred to as vy and EOT does not exhibit the expected linear relationship, but a sudden drop (r〇U_0ff) when the EOT decreases. Due to the Vfb drop and High-K The problem that the gate dielectric layer crystallizes in a high temperature environment leads to an increase in leakage current, which leads to more challenges in the material selection of the High-K gate dielectric layer and the metal gate. Therefore, the industry has proposed a later gate process. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a complementary MOS device having a bimetal gate having a post gate process 7 1354335 in accordance with the present invention. The patent application scope provides a method for fabricating a complementary metal oxide semiconductor (〇河〇8) component having a bimetal gate. The cough method includes k for a substrate, and Forming a first conductivity type transistor, a second conductivity type transistor, and a dielectric layer covering the first conductivity type transistor and the second conductivity type transistor on the bottom surface. Then planarizing the dielectric layer Up to exposing one of the first conductive electrodes of the first conductive type transistor to the first conductive electrode of the second conductive type transistor, and forming a second conductive layer between the second gate and forming a second conductive type a transistor and a patterned blocking layer (four) of the first conductivity type transistor; and then performing a first -1 etching process for removing the inter-electrode conductive layer of the first-electrode An opening (. pening). A first metal layer and a second metal layer are sequentially formed in the first opening Lu = first opening. Advance!: covering the patterned blocking layer of the second conductive type transistor , the second etching process is used to transfer the electric layer, and the inter-electrode opening of the inter-electrode forming the inter-electrode is formed in the first--the third metal a layer and a four-metal layer. According to the method of the present invention, The electric complementary type is made by the gold-oxygen semi-method, so the body is completed by using the closed-pole method. Because the above process is high, the metal layers filled in the first and second openings are not accepted. The process of heat pre-existing is... 8 1354335 The influence of thermal budget can reduce the drop of components; in addition, it has the advantage of wide selection of metal gate materials. [Embodiment] Please refer to Figure 1 to Figure 13 '1st FIG. 13 is a schematic view showing a preferred embodiment of a method for fabricating a CMOS device having a bimetal gate according to the present invention. As shown in FIG. 1, a substrate 2 is first provided, such as a stone. a base substrate, a stone-like substrate, or a silicon-on-insulator (SOI) substrate, etc., the surface of the substrate 200 defines a first active region 21〇 and a second active region 212′ and the substrate 200 is formed There is a shallow trench isolation (STI) 202 for electrically isolating the first active region 210 from the second active region 212. Next, a gate dielectric layer 204, a gate conductive layer such as a polycrystalline layer 206, and a hard mask layer (not shown) are sequentially formed on the substrate 200. The gate dielectric layer 204 can be a conventional germanium dioxide layer or a hafnium oxynitride layer, or a high dielectric constant (referred to as High-K for short) material layer. In addition, a cap layer (not shown) or an ARC layer (not shown) may be selectively formed on the polycrystalline layer 206. The hard mask genus is then patterned by a lithography and etching process to form a patterned hard mask layer 208 for defining the gate locations as shown in FIG. Please refer to Figure 2. Next, an etching process is performed through the patterned hard mask layer 208 to etch the polysilicon layer 206 and the gate dielectric layer 204, and a first gate is formed in the first active region 210 and the second active region 212 respectively. The pole 220 and a second gate 222. Please refer to FIG. 2 for the succession. Next, a first lightly doped immersion is formed in the substrate 200 on both sides of the first gate 220 and the second gate 222 by using different conductivity type ion implantation processes.
(light doped drain，以下簡稱為 LDD) 230 與一第二 LDD 232。隨後係於第一閘極220與第二閘極222之側壁分別形 成一側壁子234。侧壁子234可為一利用矽烷 (Bis(tert-butylamino)silane，以下簡稱為 BTBAS)作為前趨 物(precursor)之包含有氧化物-氮化物-氧化物之偏位側壁 子（ONO offset spacer)。最後再利用不同導電型之離子佈植 製程於第一閘極220與第二閘極222兩側之基底200内分 別形成一第一源極/汲極240與一第二源極/汲極242，而於 第一主動區域210與第二主動區域220内分別形成一第一 導電型電晶體250與一第二導電型電晶體252。另外，在 本較佳實施例中，亦可利用選擇性磊晶成長(selective epitaxial growth，SEG)方法來製作第一源極/没極240與第 二源極/汲極242，例如，當第一導電型電晶體250為一 N 型電晶體，而第二導電型電晶體252為一 P型電晶體時， 係可利用包含有碳化石夕（SiC)之磊晶層以及包含有鍺化矽 (SiGe)之磊晶層分別製作第一源極/汲極240與第二源極/汲 極242，以利用磊晶層與閘極通道矽之間的應力作用來加 速载子遷移率，並改善源極引發能帶降低(drain induced :. . barrier lowering ’ DIBL)效應與鑿穿（punchthrough)效應，以 1354335 及降低截止態漏電流、減少功率消耗。 請參閱第3圖與第4圖。在形成第一導電型電晶體250 與第二導電型電晶體252之後，係進行一自對準金屬石夕化 物（salicide)製程’以於第一源極/没極24〇與第二源極/波極 242之表面分別形成一金屬矽化物244。隨後基底2〇〇上依 序形成一利用BTBAS作為前趨物而形成之膜層260與一 介電層262。此外如第4圖所示，藉由一第一平坦化製程， 其包含有一 CMP製程，用以平坦化介電層262至暴露出第 一吶極220與苐二閘極222之多晶矽層206。然而，為了 避免CMP製程過度研磨介電層262與膜層26〇，甚至損及 下方第一閘極220與第二閘極222之輪廓，亦可如第3圖 所示’膜層260可作為介電層262在第一平坦化製程中的 餘刻停止層。 請參閱第4圖。對介電層262進行CMP製程後，第一 平坦化製程更可包含一回蝕刻製程，用以移除蝕刻停止層 260、第一閘極220與第二閘極222上方之圖案化硬遮罩層 208、部分側壁子234、以及部分介電層262，以致暴露出 第一閘極220與第二閘極222之多晶矽層206。回蝕刻製 程可為一包含有稀釋氫氟酸(diluted HF’，DHF)與磷酸 (phosphoric acid，H3P〇4)之濕式蚀刻製程，亦可為一包含 有六氟化石兔(SF6)、六氟乙烧(perfluoro ethane，C2F6)、氟曱 1354335 烷（fluoroform ’ CH3F)、氧氣（〇2)、二氧化碳（C〇2)、氦氣 (He)、與氬氣(Ar)等之乾式蝕刻製程。 請參閱第5圖。接下來係於基底200上形成一阻擋層 (blocking layer) 270。阻擋層270可為一包含有非晶碳 (amorphous carbon，APF)單一膜層；亦可如第5圖所示， 為包含有一乳化石夕層272與一氮化梦層274之複合膜層， 且此乳化石夕層272與鼠化石夕層274之厚度具有一 1.3之比 例。例如，氧化矽層272之厚度為1〇〇埃（angstr〇m);而氣 化矽層274之厚度則為300埃。 請參閱帛5圖與第6圖。利用一光阻276圖案化阻擋層 270,以移除覆蓋第-導電型電晶體⑽及位於第一主動區 域210内之ψ分阻播層270，ra u* is也 田曰z川，因此圖案化阻擋層27〇係將 第一閘極220之多晶矽層2〇6 士入里♦，Λ(light doped drain, hereinafter referred to as LDD) 230 and a second LDD 232. Then, a sidewall 234 is formed on the sidewalls of the first gate 220 and the second gate 222, respectively. The sidewall spacer 234 may be a biased sidewall spacer containing an oxide-nitride-oxide using a bismuth (tert-butylamino silane, hereinafter referred to as BTBAS) as a precursor. ). Finally, a first source/drain 240 and a second source/drain 242 are respectively formed in the substrate 200 on both sides of the first gate 220 and the second gate 222 by using different conductivity type ion implantation processes. A first conductive type transistor 250 and a second conductive type transistor 252 are formed in the first active region 210 and the second active region 220, respectively. In addition, in the preferred embodiment, the selective source epitaxial growth (SEG) method may also be used to fabricate the first source/ditpole 240 and the second source/drain 242, for example, when When the conductive transistor 250 is an N-type transistor and the second transistor 252 is a P-type transistor, an epitaxial layer containing carbon carbide (SiC) and a germanium containing germanium can be used. The epitaxial layer of (SiGe) is respectively formed with a first source/drain 240 and a second source/drain 242 to accelerate the carrier mobility by utilizing the stress between the epitaxial layer and the gate channel ,, and Improve the drain induced:. barrier lowering 'DIBL' effect and the punchthrough effect to 1355335 and reduce the off-state leakage current and reduce power consumption. Please refer to Figures 3 and 4. After forming the first conductive type transistor 250 and the second conductive type transistor 252, a self-aligned metal salicide process is performed to make the first source/drain 24 〇 and the second source The surface of the /pole 242 forms a metal halide 244, respectively. Subsequently, a film layer 260 and a dielectric layer 262 formed by using BTBAS as a precursor are sequentially formed on the substrate 2 . In addition, as shown in FIG. 4, a first lithography process includes a CMP process for planarizing the dielectric layer 262 to expose the polysilicon layer 206 of the first drain 220 and the second gate 222. However, in order to prevent the CMP process from excessively grinding the dielectric layer 262 and the film layer 26, or even the lower first electrode 220 and the second gate 222, the film layer 260 can be used as shown in FIG. The dielectric layer 262 stops the layer in the remainder of the first planarization process. Please refer to Figure 4. After the CMP process is performed on the dielectric layer 262, the first planarization process may further include an etch back process for removing the etch stop layer 260, the patterned gate of the first gate 220 and the second gate 222. The layer 208, a portion of the sidewall spacers 234, and a portion of the dielectric layer 262 expose the polysilicon layer 206 of the first gate 220 and the second gate 222. The etch back process can be a wet etching process comprising diluted HF' (DHF) and phosphoric acid (H3P〇4), or a hexahedral rabbit (SF6), six Dry etching process of perfluoroethane (C2F6), fluoroform 1354335 alkane (fluoroform 'CH3F), oxygen (〇2), carbon dioxide (C〇2), helium (He), and argon (Ar) . Please refer to Figure 5. Next, a blocking layer 270 is formed on the substrate 200. The barrier layer 270 may be a single film layer containing an amorphous carbon (APF); or as shown in FIG. 5, it may be a composite film layer comprising an emulsifying stone layer 272 and a nitride layer 274. And the thickness of the emulsified layer 272 and the ratified layer 274 has a ratio of 1.3. For example, the thickness of the yttrium oxide layer 272 is 1 angstrom; and the thickness of the vaporized ruthenium layer 274 is 300 angstroms. Please refer to Figure 5 and Figure 6. The barrier layer 270 is patterned by a photoresist 276 to remove the first conductive type transistor (10) and the germanium blocking layer 270 located in the first active region 210, and the pattern is The barrier layer 27 is formed by inserting the polysilicon layer of the first gate 220 into the inner layer ♦
曰凡全暴露出來。隨後，係進 行一第一 敍刻製程，用以移降篦一門士 砂丨示弟閘極220之多晶矽層 206，而於第一主動區域21〇内形$ _ 門心成一第一開口（opening) 280。值得注意的是，在進行笸一為 丁弟餘刻製程時，圖案化阻擋 層270係可保護第二主動區域2丨？ 埤212内之第二導電型電晶體 252’避免移除第一閘極220之容a + 艾夕日日矽層206時傷害到第二 閘極222。 請參閱第7圖 接下來係於第-開口 280内依序形成一 12 1354335 第一金屬層290與一第二金屬層292。第一金屬層290包 含有氮化鉬鋁（MoAIN)、鑛（W)、氮化鉬（M〇N)、碳氮氧化 組(TaCNO)、或氮化鎢(wn)等金屬材料。由於上述金屬填 洞能力較差，為避免填補完畢產生縫隙（seam)，更係利用 第二金屬層292作為填補第一開口 280之主要材料；而第 一金屬層290則可用以調節功函數。第二金屬層292包含 有鋁（A1)、鈦(Ti)、组(Ta)、鶴（W)、铌(Nb)、鉬（Mo)、氮化 鈦(TiN)、碳化鈦（TiC)、氮化钽(TaN)、鈦鎢（Ti/W)、或鈦與 氮化鈦(Ti/TiN)等複合金屬。另外，為避免閘極介電層204 與第一金屬層290產生反應或擴散效應，更可於形成第一 金屬層290之前，先於第一開口 280内形成一阻障層（barrier layer)(圖未示）’阻障層係可包含有高溫過渡金屬、貴重金 屬、稀土金屬等元素及其碳化物、氮化物、矽化物、鋁氮 化物或氮矽化物等。 請參閱第8圖。隨後利用另一光阻278覆蓋第一主動區 域210，並進行一乾蝕刻製程以移除覆蓋第二導電型電晶 體252之第二金屬層292、第一金屬層290、以及氮化矽層 274,而停留於氧化矽層272上。此乾蝕刻製程係可包含有 氟（CI2)、二亂化哪（boron trichloride，BC13)、六氟化石宁 (SF6)、氮氣、與氬氣等。 請參閱第9圖。接下來係移除位於第二主動區域212内 13 1354335 覆蓋第―于電型電晶體252之圖案化阻擋層謂，即移除 氧化夕層272 ’而暴路出第二閘極222之多晶石夕層細。並All the people are exposed. Subsequently, a first engraving process is performed to transfer the polysilicon layer 206 of the gate of the gate of the first gate of the gate, and the first opening of the gate of the first active region 21 is formed into a first opening (opening) ) 280. It is worth noting that the patterned barrier layer 270 can protect the second active area 2 when the first process is performed. The second conductivity type transistor 252' in the crucible 212 avoids damage to the second gate 222 when the first gate 220 is removed. Referring to FIG. 7, a 12 1354335 first metal layer 290 and a second metal layer 292 are sequentially formed in the first opening 280. The first metal layer 290 contains a metal material such as molybdenum aluminum nitride (MoAIN), mineral (W), molybdenum nitride (M〇N), carbon oxynitride (TaCNO), or tungsten nitride (wn). Since the metal filling ability is poor, in order to avoid the seam from being filled, the second metal layer 292 is used as the main material for filling the first opening 280; and the first metal layer 290 can be used to adjust the work function. The second metal layer 292 includes aluminum (A1), titanium (Ti), group (Ta), crane (W), niobium (Nb), molybdenum (Mo), titanium nitride (TiN), titanium carbide (TiC), Tantalum nitride (TaN), titanium tungsten (Ti/W), or a composite metal such as titanium and titanium nitride (Ti/TiN). In addition, in order to avoid the reaction or diffusion effect of the gate dielectric layer 204 and the first metal layer 290, a barrier layer may be formed before the first metal layer 290 before the first opening 280 is formed ( The barrier layer may include elements such as a high temperature transition metal, a precious metal, a rare earth metal, and a carbide, a nitride, a telluride, an aluminum nitride or a nitrogen halide. Please refer to Figure 8. Then, the first active region 210 is covered by another photoresist 278, and a dry etching process is performed to remove the second metal layer 292, the first metal layer 290, and the tantalum nitride layer 274 covering the second conductive type transistor 252. It stays on the yttrium oxide layer 272. The dry etching process may include fluorine (CI2), boron trichloride (BC13), hexafluoride (SF6), nitrogen, argon, and the like. Please refer to Figure 9. Next, the patterned barrier layer covering the first electro-active transistor 252 in the second active region 212 is removed, that is, the poly-oxidation layer 272' is removed, and the polycrystal of the second gate 222 is violently exited. Shi Xi layer is fine. and
Ik即進仃-第二㈣製程，用以移除第二閘極之多晶石夕層 206,而於第二主動區域攻内形成一第二開口加。 睛參閱第H)圖。接下來，於第二開口挪内依序形成 T第三金屬層294與一第四金屬層挪。第三金屬層294 #係可包含有碳化钽。由於碳化麵填洞能力較差，為避免填 補完畢產生缝隙，更係利用第四金屬層挪作為填補第二 開口 282之主要材料：第三金屬層294則可用以調節功函 數。而第四金屬層296之金屬材料可同於第二金屬層。如 前所述’為避免開極介電層204與第三金屬層294產生反 應或擴散效應，更可於形成第三金屬層2叫之前 二開口 282内形成一阻障層（圖未示）。 、The Ik is a second (four) process for removing the polysilicon layer 206 of the second gate and forming a second opening plus for the second active region. See Figure H) for the eye. Next, a T third metal layer 294 and a fourth metal layer are sequentially formed in the second opening. The third metal layer 294 may be comprised of tantalum carbide. Due to the poor filling ability of the carbonized surface, in order to avoid gaps in the filling, the fourth metal layer is used as the main material for filling the second opening 282: the third metal layer 294 can be used to adjust the work function. The metal material of the fourth metal layer 296 can be the same as the second metal layer. As described above, in order to avoid the reaction or diffusion effect of the open dielectric layer 204 and the third metal layer 294, a barrier layer may be formed in the second opening 282 of the third metal layer 2 (not shown). . ,
另外]辑♦㈣之另—較佳實施例，在第—茲刻製 第第=職程之後，射分別進行n 盘 之 =製程’以移除包含有二氧切層 層 層綱。而在第三_製程與第喊刻製 再为別進行一形成一 High_K閉極 後 統的二氧切層錢氧切層料 低物理極限厚度。並期在相_的 Μ降地 並達成等效電容以控制通道_。 以降低漏電流 1354335 此外值得注意的是，在本較佳實施例中，製作第一導電 型電晶體250與第二導電型電晶體252時，係直接以High-K 材料層作為閘極介電層204。因此在第一蝕刻製程與第二 蝕刻製程之後，閘極介電層204係可保留並依序分別暴露 於第一開口 280與第二開口 282之底部。由於一般在形成 包含有High-K材料之閘極介電層204之前，會在閘極介電 層204與基底200之間利用化學鍵結或加熱至850 °C而形 ® 成之氧化矽層、氮氧化矽層、或氮化矽層等作為一介面層 (interface layer)(圖未示）以增進通道區的電子遷移率。而在 本較佳實施例中，由於閘極介電層204並未於第一蝕刻製 程與第二蝕刻製程中移除，因此亦可保護該介面層不被破 壞。此外在步入45奈米（nm)線寬的半導體製程時，更可省 卻源於移除閘極介電層204，而必須在如此微小的第一、 第二開口 280、282中重新再形成時，所必須面對的薄膜厚 • 度控制與均勻度控制等考量。 請參閱第11圖。在用以填滿孔洞282的第四金屬層296 形成之後，係進行一第二平坦化製程，用以移除多餘的第 一金屬層290、第二金屬層292、第三金屬層294、與第四 金屬層296，而獲得一約略平坦之表面，並完成第一導電 型電晶體250與第二導電型電晶體252之金屬閘極之製作。 15 1354335 在本較佳實施例中，介電層262可由氧化物或摻有硼、 磷之氧化矽等材料構成，用以作為内層介電層（inteMayer dielectric，ILD layer)。介電層262亦可為利用高深寬比填 溝製程(high aspect ratio process ’以下簡稱為HARp，）製作 之氧化層。由於HARP氧化層具有易於蝕刻而可作為一犧 牲層之特性，因此採用harp氧化層作為介電層.262時， 係更可於本較佳實施例中採用一選擇性應力系統(selective φ strain scheme，SSS)來增進電晶體驅動電流。請參閱第12 圖。在第.一平坦化製程之後，係可進行不同的钱刻製程， 以分別移除介電層262與蚀刻停止層260，使得第一導電 型電晶體250與第二導電型電晶體252暴露於基底2〇〇之 上。 請參閱第13圖。待移除介電層262與蝕刻停止層260 後’係於基底200上形成一接觸洞触刻停止層（c〇ntact hole etch stop ’ CESL layer) 264 ’並藉由施加一紫外光或熱能之 步驟，以使CESL 264產生一應力而作為選擇性應力系統， 以期提昇第一導電型電晶體250與第二導電型電晶體252 之效能。‘In addition, the other preferred embodiment, after the first-step process, performs the n-disk = process' to remove the layer containing the dioxy-cut layer. In the third process and the first call, the other is to form a high_K closed-end dioxin layer of oxygen cut layer material with low physical limit thickness. Concurrently, the phase is lowered and the equivalent capacitance is reached to control the channel _. In order to reduce the leakage current 1354335, it is also worth noting that in the preferred embodiment, when the first conductive type transistor 250 and the second conductive type transistor 252 are fabricated, the High-K material layer is directly used as the gate dielectric. Layer 204. Therefore, after the first etching process and the second etching process, the gate dielectric layer 204 can be retained and sequentially exposed to the bottoms of the first opening 280 and the second opening 282, respectively. Since the gate dielectric layer 204 is generally formed before the formation of the gate dielectric layer 204 containing the High-K material, a yttrium oxide layer is formed between the gate dielectric layer 204 and the substrate 200 by chemical bonding or heating to 850 ° C. An yttrium oxynitride layer, or a tantalum nitride layer or the like serves as an interface layer (not shown) to enhance electron mobility in the channel region. In the preferred embodiment, since the gate dielectric layer 204 is not removed in the first etching process and the second etching process, the interface layer can also be protected from being damaged. In addition, when stepping into a semiconductor process of 45 nm (line) line width, it is possible to dispense with the removal of the gate dielectric layer 204, which must be reformed again in such minute first and second openings 280, 282. At the time, the film thickness control and uniformity control must be considered. Please refer to Figure 11. After the fourth metal layer 296 for filling the holes 282 is formed, a second planarization process is performed to remove the excess first metal layer 290, the second metal layer 292, the third metal layer 294, and The fourth metal layer 296 obtains an approximately flat surface and completes the fabrication of the metal gates of the first conductive type transistor 250 and the second conductive type transistor 252. 15 1354335 In the preferred embodiment, the dielectric layer 262 may be formed of an oxide or a material doped with boron or phosphorus, such as yttrium oxide, as an inner dielectric layer (ILD layer). The dielectric layer 262 may also be an oxide layer formed using a high aspect ratio process (hereinafter abbreviated as HARp). Since the HARP oxide layer has the characteristics of being easy to etch and can be used as a sacrificial layer, when a harp oxide layer is used as the dielectric layer 262, a selective stress system (selective φ strain scheme) can be used in the preferred embodiment. , SSS) to enhance the transistor drive current. Please refer to Figure 12. After the first planarization process, different etching processes may be performed to separately remove the dielectric layer 262 and the etch stop layer 260 such that the first conductive type transistor 250 and the second conductive type transistor 252 are exposed to Above the substrate 2〇〇. Please refer to Figure 13. After the dielectric layer 262 and the etch stop layer 260 are removed, a contact hole etch stop 'CESL layer 264' is formed on the substrate 200 and an ultraviolet light or heat energy is applied. The step is to cause the CESL 264 to generate a stress as a selective stress system in order to improve the performance of the first conductive type transistor 250 and the second conductive type transistor 252. ‘
根據本發明所提供之較佳實施例，因考量PM0S電晶體 熱預算較NMOS更為狹小，故第一導電型電晶體250係為 一 NM0S電晶體；而第二導電型電晶體252係為一 PM0S 16 1354335 電晶體，然其製作之順序亦可相反。但本發明中不論是第 一導電型電晶體250或第二導電型電晶體252皆是利用後 閘極方法製作而成，故此時需要較高熱預算的製程，例如 製作LDD、源極/汲極時需要之退火，或者金屬矽化物製程 等製程皆已完成，因此填入第一、第二開口 280、282的金 屬層均不會受到上述製程的高熱預算影響，因而可降低 NMOS元件以及PMOS元件的Vfb下降問題；且更享有廣 $ 泛的金屬閘極材料選擇之優點。此外，本發明更可藉由整 合CESL等之選擇性應力系統來提高MOS元件的性能。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 【圖式簡單說明】 • 第1圖至第13圖係為本發明所提供之具有雙金屬閘極之 CMOS元件之製作方法之一較佳實施例之示意圖。 【主要元件符號說明】 200 基底 202 淺溝絕緣 204 閘極介電層 206 多晶碎層 208 圖案化硬遮罩層 210 第一主動區域 212 第二主動區域 220 第一閘極 17 1354335 222 第二閘極 230 第一輕摻雜汲極 232 第二輕摻雜汲極 234 側壁子 240 第源極/汲極 242 第二源極/汲極 244 金屬砍化物 250 第一導電型電晶體 252 第二導電型電晶體 260 #刻停止層 262 介電層 264 接觸洞蝕刻停止層 270 阻擋層 272 氧化矽層 274 氮化矽層 276、 光阻 278 280 第一開口 282 第二開口 290 第一金屬層 292 第二金屬層 294 第三金屬層 296 第四金屬層 18According to the preferred embodiment of the present invention, since the thermal budget of the PMOS transistor is narrower than that of the NMOS, the first conductive transistor 250 is an NMOS transistor; and the second conductive transistor 252 is a PM0S 16 1354335 Transistors, but the order of fabrication can be reversed. However, in the present invention, both the first conductive type transistor 250 and the second conductive type transistor 252 are fabricated by using the back gate method, so a high thermal budget process is required at this time, for example, LDD, source/drainage is fabricated. The annealing process is required, or the metal germanium process is completed, so that the metal layers filled in the first and second openings 280, 282 are not affected by the high thermal budget of the above process, thereby reducing the NMOS device and the PMOS device. The Vfb drop problem; and the advantages of the wide-ranging metal gate material selection. Further, the present invention can improve the performance of the MOS device by integrating a selective stress system such as CESL. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the invention are intended to be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 13 are schematic views showing a preferred embodiment of a method for fabricating a CMOS device having a bimetal gate according to the present invention. [Main component symbol description] 200 substrate 202 shallow trench insulation 204 gate dielectric layer 206 polycrystalline layer 208 patterned hard mask layer 210 first active region 212 second active region 220 first gate 17 1354335 222 second Gate 230 first lightly doped drain 232 second lightly doped drain 234 sidewall 240 240 source/drain 242 second source/drain 244 metal slab 250 first conductivity type transistor 252 second Conductive transistor 260 #刻止层层262 dielectric layer 264 contact hole etch stop layer 270 barrier layer 272 yttrium oxide layer 274 tantalum nitride layer 276, photoresist 278 280 first opening 282 second opening 290 first metal layer 292 Second metal layer 294 third metal layer 296 fourth metal layer 18