1353498 九、發明說明： 【發明所屬之技術領域】 本發明係有關穩壓器電路，特別是有關必須進行大電流輸出的系列穩 壓器1C。 【先前技術】1353498 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a voltage regulator circuit, and more particularly to a series of voltage regulators 1C that must perform high current output. [Prior Art]
穩壓器電路是一種用來安定由外部供給之電源電壓，並向輸出端子供 給一安定輸出電壓之電路。把輸出電容器連接在穩壓器電路的輸出端子上 之後，將負載連接在穩壓器電路的輸出端子上。由此，可提供一以穩壓器 電路來穩定並以輸出電容器平滑化輸出電壓之負載。 作爲連接在穩壓器電路的輸出側的輸出電容器co，一般是電解電容器 或组質電容器，但是爲了適應小型化要求，正向使削、容量的喊電容器 發展。 可是’電容器根據種類具有不同的等效㈣電阻值(EquivalentSeriesThe regulator circuit is a circuit for stabilizing the supply voltage supplied from the outside and supplying a stable output voltage to the output terminal. After connecting the output capacitor to the output terminal of the regulator circuit, connect the load to the output terminal of the regulator circuit. Thereby, a load which is stabilized by the regulator circuit and smoothes the output voltage with the output capacitor can be provided. The output capacitor co, which is connected to the output side of the regulator circuit, is generally an electrolytic capacitor or a component capacitor. However, in order to meet the demand for miniaturization, a capacitor for forward cutting and capacity has been developed. However, 'capacitors have different equivalent (four) resistance values depending on the type (EquivalentSeries)
Resistance，ESR)。例如，電解電容器的咖值隨頻率或溫度而變化且 有大約〇. 1〜100〔 Ω〕的ESR值；组質電容器具有〇 Η⑻的哪值。 2究電合器具有請1〜0.1〔Ω〕的卿值。在穩壓器電路的輸出端子上 田的輸出電谷器的ESR值與穩壓器電路的相位補償範圍之間會因不適之 LI系^而居峰湯。 圖1為習知穩壓器電路的構成。 的3器！:路是具有電源端子Vdd、接地端子GND和輸出端子^ 以上的ϋ二(系列穩壓器1〇<>圖示的穩壓器電路是輸出電流150mA 晶體的穩壓器電路’所以構成該電路的電晶體是雙極性電 的集極和』St有作爲控制端子的基極以及作爲一對主要電極端子 第2電流源11、第1到第10電晶體㈣10、第1及 电丨且K1 'R2和相位校正用電容器C1。 定電流源11和第1至第8電晶體_構成產生誤差信號的誤差信號 5 相位容限裕度必須保證在例如45。以上。 圖2中表示出在從@丨的穩壓器電路内除掉了校正用電容扣的麵 攸从路中，輸出電谷C〇的咖爲〇.〇1Ω、輸出電流爲500mA時的穩壓器電 $開迴路特性。從圖2可知，在不具校正用電容器ci的穩壓器電路中， =毋增益之祕的頻率下的相位容限裕度。因此，無校正用電容器C1的穩 壓器電路會産生振盪。 圖3中表不在圖1的穩壓器電路中，輸出電容器⑺的哪狀〇1门、 輸出電流爲5GGmA時的穩壓器電路_路特性^從圖3可知，即使具備校 =用電容器C1的穩壓器電路中’也沒有增益爲議的頻率下的相位容限。 因此有校正用電容器C1的穩壓器電路也會振盪。 祕’輸出電容Co的ESR低的情況下，即使設置了相位校正用電容器 C1 ’穩壓器電路也會振盪。 二[非專利文獻1]電晶體技術98·〇8號p4〇9 [非專利文獻2] ‘‘實用類比電子電路設計法”，渡邊一雄 人 出版社發行’ 1996· 6. 22 ’第1版4章低電壓設計法和設計要點pU〇 如上所述’現有的穩壓器電路很難適應輸出電容器c〇的低化 ESR 化。 - 【發明内容】 (發明要解決之課題） 由此可知習知穩壓器電路中，對於輸出電容c〇之低容量化及低等效串 聯電阻（Equivalent Series Resistance，ESR)之對應處理綠有困難。 本發明的目的是提供-種能夠處理輸出電容器c〇的低容量化、低哪 的穩壓器電路之問題。 按照本發明，具有端子VDD、輸㈣子Vwr和接地端子的穩壓器電路 具備連接在電職子與輸出端子之間的輸出電晶體_、將該輸出端子與接 地端子之_輸出電壓分魅從中間節點N1生成分M M的分麼電路則、 R2、産生對應於基準電齡所述分壓電壓的差㈣誤差信號的誤差信號放 大器Q1~Q8、11和配合誤差信號控制所述輸出電晶_控制電晶體Qg，並 且控制所述輸出電晶體峨輸出電壓穩定化；其特徵在於在穩壓器電路中 1353498 1相位校正 第2相位校正繼3端 姐爛規定㈣職之間的 制端中誤差信號放大器由具有供給所述基準電壓的控 ίΪΐΪϋ 述第2電晶體的—端的主要電極端子與所述接地端 端子丄間:第接在第1電晶體的另-端的主要電極端子與電源 電路⑽、以、連接在第2電晶體的另-端的主要電 極端子與電源端子之間的第2電流鏡電路奶、⑶、連接在第丨電$ 鏡電路與接地端子之間的第3電流鏡電路Q7、颂構成。第1電 ΐί路的連接點是輸出誤差信號的輸出節點N3。第3 電路包含其1的主要電極端子連接到輸出節點上的電晶體町該 電曰曰體的控制端子是所述規定的節點似。 β 曰驴ίί麵轉電路中’構成縣錢放Afi㈣晶體最好由雙極性電 明體構成。如此則13電魏包含連接在所料2電錄電路 地端子之間的另外的電晶體Q8，具有相同電阻值的2個電阻烈 ^ 接在該電晶體的控制端子與所定的節點之間，最 7 與所述另外的電晶體的-端的主要電極端子直接連接。個電阻的連接點 ΐί ’第2相位校正用電容器c2最好具有秘姆 範圍的電合值’兩個電阻R3、R4最好具有咖嫌Ω範圍的阻值。按所 w㈣_電阻值和所述第2相位校正用電容 常數由要實施超前相位補償的頻率來決定。电讀之確疋的時間 上述括狐内的符號是爲了更好的理解本發明而添加的，並不限 明。 爲了防止穩壓n電路振1 ’不僅設置有第丨相位校正用電容器 =:正用電容器，所以能夠提供可適應低容量化:低‘ 【實施方式】 (發明效果） 9 1353498 本發明為了防止穩壓器電路之振盪，不只具備第丨相位補償電容器 亦具備第2相位補償電容器，而提供一可解決低容量、低ESR問題之 穩壓器β 具趙實施方式 以下參照附圖詳細說明本發明的實施例。 =圖4是本發明的一個實施例的穩壓器電路（系列穩壓器Ic)的電路圖。 該穩壓器電路具有與現有的穩壓器電路基本姻的構成，不同的是具有包 含第2相位校正用電容器C2的相位校正電路4〇。 ' ^ 詳細地說，該穩壓器電路具有定電流源i卜第！到第1〇電晶體以〜⑽、 第1及第2電阻m、R2、第i相位校正用電容器π和相位校正電路仙。 相位校正電路40由第3及第4電阻R3、R4 (例如，5〔ΚΩ〕、5⑽〕）， 和第2相位校正用電容器C2 (例如，3〔成〕）所構成。 換言之’圖示的穩壓！I電路具備有連接在電源端子和輸出端子、 之間的輸出電晶體⑽、將該輸出端子—與接地端子間的輸出電壓分壓: 從中間節點N1生成分M壓的分壓電路（R1，R2)、産生對應於基準電壓 與^壓電壓的差值的誤差信號的誤差信號放大器（Q1〜Q8、Qu)和根據誤 差信號控制輸出電晶體_的控制電晶體Q9。穩壓器電路是通過控制輸出 電晶體Q10來穩定輸出電屡的電路；圖示的穩壓器電路還具備連接在輪出 端子L與分麼電路（R1，R2)的中間節點犯之間的第i相位校正用電容 ㈣和包含連接在輸出端子與誤差信號放大器規定的節點^後述） 之間的第2相位校正用電容器C2的相位校正電路4〇。 由於的穩壓||電路是必須是__大電流輸出的穩壓器電路，所以構 成該穩壓器電路的電晶體全都是雙極性電晶體。衆所周知，雙極性電晶體 具有^爲㈣端子的基極和作爲—對主要電極端子的集極和射極。 认二電流源U和第1至第8電晶體㈣8乃由根據兩個輸人信號（後述 刀電麼及基準電壓）的差值生成誤差信號的誤差信號放大器所構成。 第1及第2電晶體Q1及Q2都由聊型雙極性電晶體構成。這些電晶 1353498 Ω、輸出電流為5〇〇mA時的穩壓器電路的開路特性。從圖6可知，在圖4 的穩壓器電路中，增益為〇dB的頻率下的相位容限裕度約為6〇。。而且，在 相位為〇的頻率以上的頻帶内，由於增益為負值，所以穩壓器電路不產生 振盪》 如上所述’本實施例的穩壓器電路不僅設置有第1相位校正電容器C卜 還》又置有包含第2相位校正用電容器C2的相位校正電路4〇，所以能夠適應 低容量、低ESR的輸出電容器Co。 因為必須使構成第3電流鏡電路的第7和第8電晶體Q7、Q8的基極-射極電位相同，所以構成相位校正電路4〇的第3和第4電阻器R3、R4具 有相同的電阻值。最好選用200Q~60kQ範圍的電阻值作第3和第4電阻 器R3、R4的電阻值。設定下限電阻值2〇〇〇，是為了不受流經第3及第4 電阻器R3、R4的電流為約l"A、第7及第8電晶體叩及⑽的射極的電阻 為約26Ω的影響。設定上限電阻值6_，是因爲製造具有比這更高的電 阻值的電阻時，其製造偏差值大，很難製造出具有相同電阻值的電阻。 另-方面，最好選擇範圍0.5pF~20pF的電容值，作第2相位校正用電 容C2的f容值。辦導體領域製造具有上述電容值的電容^方面的問題考 慮，將上述電容C2的電容值取在5pF〜50pF範圍，是合適的值。 —按第3及第4電阻R3、R4的電阻值和第2相位校正用電容器C2的電 谷值確定的時財數，其由要實施超前她補償的鮮來決定。 日本發明人確認’在圖4所示的穩壓器電路中，把電容器連接在第7電 晶，Q7的基極和集極之間’就能夠進—步提高超前相位麵果。作該 電容的電容值，適當的範圍是〇· 5pF~20pF。 本發明不被限定於上述的實施例，在不錄本發_宗旨的範圍内卷 化更Γ。例如在上述實施例中，是說明由雙極性電晶體構成的i 。路在輸出電流為5〇mA~100mA的範圍的小輸出電流用的情況 :’本發明同樣也可適用於由丽ET構成的穩壓器電路。各膽et 作為控制端子侧細及作為-對主要奸驗極和雜。這種情況 13 下’除第1相位校正電容器之外， 容器。 還可以至少設置-個第2她校正用電 【圖式簡單說明】 圖1是習知穩壓器電路的一例的電路圖； =2疋從圖1祕虔器電路除掉相位校正用電容器的穩壓器電路，在 咖=〇·〇1 Ω、輸出電流爲500mA情況下的開路特性曲線圖； 開路==的穩峨路在®=°·°1Ω、輸出電流爲5隱情況下的 圖4是本發明的一個實施例的穩壓器電路的電路圖. =是從目4的穩壓器電路中除掉了她校正用電路的兩個電阻器的 ^ ’路在ESR-0.01Q、輸出電流爲5〇_情況下的開路特性曲線圖； =是圖4的穩壓器電路在ESR=〇.〇1Q 開路特性曲線圖。 π < v 【主要元件符號說明】 C1〜C2相位校正用電容器Resistance, ESR). For example, the coffee value of the electrolytic capacitor varies with frequency or temperature and has an ESR value of about 1 to 100 [Ω]; the composition capacitor has a value of 〇 Η (8). 2 The power analyzer has a value of 1 to 0.1 [Ω]. At the output terminal of the regulator circuit, the ESR value of the output battery of the field and the phase compensation range of the regulator circuit may be due to the discomfort of the LI system. Figure 1 shows the construction of a conventional voltage regulator circuit. 3 devices! : The circuit is a power supply terminal Vdd, a ground terminal GND, and an output terminal ^ or more. (The series regulator 1〇<> The voltage regulator circuit shown in the figure is a regulator circuit that outputs a current of 150 mA crystal. The transistor of this circuit is a bipolar electric collector and "St has a base as a control terminal, and a pair of main electrode terminals, a second current source 11, a first to tenth transistor (four) 10, a first and an electric K1 'R2 and phase correction capacitor C1. The constant current source 11 and the first to eighth transistors constituting the error signal 5 generating the error signal must have a phase margin margin of, for example, 45 or more. From the @丨's voltage regulator circuit, the surface of the calibration capacitor is removed from the circuit, and the output of the electric grid C〇 is 〇.〇1Ω, and the output current is 500mA. As can be seen from Fig. 2, in the regulator circuit without the correction capacitor ci, the phase margin margin at the frequency of the 毋gain is secret. Therefore, the regulator circuit of the non-correction capacitor C1 oscillates. In Figure 3, the table is not in the regulator circuit of Figure 1, where is the output capacitor (7)? The voltage regulator circuit when the output current is 5 GGmA is shown in Fig. 3. Even in the voltage regulator circuit including the calibration capacitor C1, there is no phase margin at the frequency at which the gain is discussed. Therefore, the regulator circuit of the correction capacitor C1 also oscillates. When the ESR of the output capacitor Co is low, even if the phase correction capacitor C1 is installed, the regulator circuit oscillates. [Non-Patent Document 1 ]Transistor technology 98·〇8# p4〇9 [Non-Patent Document 2] ''Practical analog electronic circuit design method》, issued by Watanabe Ishiguro Publishing House' 1996· 6. 22 '1st edition 4 chapter low voltage design method And design point pU〇 As described above, the conventional voltage regulator circuit is difficult to adapt to the low-output ESR of the output capacitor c. - [Discussion] (Problems to be Solved by the Invention) It is known from the conventional regulator circuit It is difficult to handle the green of the output capacitor c〇 and the low equivalent series resistance (ESR). It is an object of the present invention to provide a low-capacity, low-capacity capable of handling the output capacitor c〇. Which regulator According to the present invention, a voltage regulator circuit having a terminal VDD, a (four) sub-Vwr, and a ground terminal includes an output transistor _ connected between the electric power and the output terminal, and the output terminal and the ground terminal The output voltage is divided into the sub-circuits of the sub-Ms from the intermediate node N1, R2, the error signal amplifiers Q1~Q8, 11 which generate the difference (four) error signals corresponding to the divided voltages of the reference electric age, and the matching error signal control station. Outputting the transistor_control transistor Qg, and controlling the output transistor 峨 output voltage stabilization; characterized by 1353498 1 phase correction of the second phase correction in the regulator circuit, followed by the third end of the rule (four) The error signal amplifier in the terminal is provided between the main electrode terminal having the end of the second transistor for supplying the reference voltage and the ground terminal: the main electrode connected to the other end of the first transistor a terminal and a power supply circuit (10), a second current mirror circuit milk connected between the main electrode terminal and the power supply terminal at the other end of the second transistor, and (3) connected to the third power mirror circuit A third current mirror circuit between the ground terminal Q7, Chung configuration. The connection point of the first electric circuit is the output node N3 that outputs the error signal. The third circuit includes a transistor in which the main electrode terminal of the first electrode terminal is connected to the output node. The control terminal of the electric body is similar to the predetermined node. In the β 曰驴ίί face-turn circuit, the Afi (4) crystal is preferably composed of a bipolar electrical body. Thus, the 13-electrode includes an additional transistor Q8 connected between the terminals of the 2-recording circuit, and two resistors having the same resistance value are connected between the control terminal of the transistor and the predetermined node. The most 7 is directly connected to the main electrode terminal of the -end of the other transistor. The connection point of the resistors ΐί ′ The second phase correction capacitor c2 preferably has an electrical connection value in the range of the secret. The two resistors R3 and R4 preferably have a resistance value in the range of Ω. The w (four) _ resistance value and the second phase correction capacitance constant are determined by the frequency at which the advanced phase compensation is to be performed. The exact time of the reading of the above-mentioned symbols in the above-mentioned foxes is added for a better understanding of the present invention, and is not limited. In order to prevent the voltage regulation n circuit vibration 1' from being provided not only with the second phase correction capacitor =: a positive capacitor, it is possible to provide an adaptable low capacity: low' (embodiment) (effect of the invention) 9 1353498 The oscillation of the voltage regulator circuit not only includes the second phase compensation capacitor but also the second phase compensation capacitor, and provides a voltage regulator that can solve the problem of low capacity and low ESR. Embodiments Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. Example. = Fig. 4 is a circuit diagram of a regulator circuit (series regulator Ic) of one embodiment of the present invention. This regulator circuit has a configuration that is substantially incompatible with the conventional voltage regulator circuit, and is different from the phase correction circuit 4 that includes the second phase correction capacitor C2. ' ^ In detail, the regulator circuit has a constant current source i Bu! To the first transistor, the voltage is ~(10), the first and second resistances m, R2, the i-th phase correction capacitor π, and the phase correction circuit. The phase correcting circuit 40 is composed of third and fourth resistors R3 and R4 (for example, 5 [ΚΩ], 5 (10))) and a second phase correcting capacitor C2 (for example, 3 [成]). In other words, the illustrated voltage regulation! The I circuit includes an output transistor (10) connected between the power supply terminal and the output terminal, and a voltage division between the output terminal and the ground terminal: a voltage dividing circuit that generates a divided M voltage from the intermediate node N1 (R1) , R2), an error signal amplifier (Q1 to Q8, Qu) that generates an error signal corresponding to a difference between the reference voltage and the voltage, and a control transistor Q9 that controls the output transistor_ according to the error signal. The voltage regulator circuit is a circuit that stabilizes the output power by controlling the output transistor Q10; the illustrated voltage regulator circuit is also provided between the intermediate node of the wheel terminal L and the circuit (R1, R2). The i-th phase correction capacitor (4) and the phase correction circuit 4A including the second phase correction capacitor C2 connected between the output terminal and the node defined by the error signal amplifier (described later). Since the voltage regulator || circuit is a regulator circuit that must be a __ high current output, the transistors that make up the regulator circuit are all bipolar transistors. As is well known, a bipolar transistor has a base which is a terminal of (4) and a collector and an emitter which serve as a pair of main electrode terminals. The second current source U and the first to eighth transistors (4) 8 are constituted by error signal amplifiers that generate an error signal based on the difference between the two input signals (the later-mentioned tool power and the reference voltage). Both the first and second transistors Q1 and Q2 are composed of a chat type bipolar transistor. The open circuit characteristics of these regulators are 1353498 Ω and the output current is 5 mA. As can be seen from FIG. 6, in the regulator circuit of FIG. 4, the phase margin margin at a frequency of 〇dB is about 6 〇. . Further, in the frequency band above the frequency of the phase 〇, since the gain is a negative value, the regulator circuit does not generate oscillation. As described above, the voltage regulator circuit of the present embodiment is not only provided with the first phase correction capacitor C. Further, since the phase correction circuit 4A including the second phase correction capacitor C2 is provided, it is possible to accommodate the output capacitor Co having a low capacity and a low ESR. Since the base-emitter potentials of the seventh and eighth transistors Q7 and Q8 constituting the third current mirror circuit must be the same, the third and fourth resistors R3 and R4 constituting the phase correction circuit 4A have the same. resistance. It is preferable to use the resistance value in the range of 200Q to 60kQ as the resistance value of the third and fourth resistors R3 and R4. The lower limit resistance value is set to 2 〇〇〇 in order to prevent the current flowing through the third and fourth resistors R3 and R4 from being approximately 1 " A, the seventh and eighth transistors 叩 and the resistance of the emitter of (10) are about The effect of 26Ω. The upper limit resistance value 6_ is set because when a resistor having a higher resistance value is manufactured, the manufacturing variation value is large, and it is difficult to manufacture a resistor having the same resistance value. On the other hand, it is preferable to select a capacitance value ranging from 0.5 pF to 20 pF as the f-capacitance value of the second phase correction capacitor C2. In the case of manufacturing a capacitor having the above capacitance value in the field of conductors, it is a suitable value to take the capacitance value of the capacitor C2 in the range of 5 pF to 50 pF. - The amount of time determined by the resistance values of the third and fourth resistors R3 and R4 and the valley value of the second phase correction capacitor C2 is determined by the freshness of the compensation to be advanced. The Japanese inventor confirmed that in the voltage regulator circuit shown in Fig. 4, the capacitor is connected to the seventh transistor, and the base and collector of Q7 can further improve the leading phase effect. As the capacitance value of the capacitor, the appropriate range is 〇·5pF~20pF. The present invention is not limited to the above-described embodiments, and is not limited to the scope of the present invention. For example, in the above embodiment, i is composed of a bipolar transistor. When the output current is small output current in the range of 5 mA to 100 mA: The present invention is also applicable to a regulator circuit composed of MN. Each of the gallbladders is fine as a control terminal side and acts as a pair of majors. In this case, the container is replaced by the first phase correction capacitor. It is also possible to set at least a second electric power for correction. [Simplified illustration of the drawing] Fig. 1 is a circuit diagram of an example of a conventional voltage regulator circuit; =2疋 removing the stability of the phase correction capacitor from the secretor circuit of Fig. 1. The circuit diagram of the open circuit of the voltage regulator circuit in the case of coffee = 〇 · 〇 1 Ω and the output current is 500 mA; Figure 4 of the case where the open circuit == is stable at ®=°·°1Ω and the output current is 5 una. Is a circuit diagram of the regulator circuit of one embodiment of the present invention. = is the two resistors of the circuit for correcting the circuit of the regulator from the target 4, the ESR-0.01Q, the output current The open circuit characteristic diagram for the case of 5〇_; = is the open circuit characteristic curve of the regulator circuit of Fig. 4 at ESR=〇.〇1Q. π < v [Description of main component symbols] C1 to C2 phase correction capacitor
Co輸出電容器 N1〜N3節點 Q1〜Q10電晶體 R1〜R4電阻 RL負載電阻 ESR等效串聯電阻 11定電流源 電源端子 Vw輸出端子 1353498 40相位校正電路Co output capacitor N1~N3 node Q1~Q10 transistor R1~R4 resistor RL load resistor ESR equivalent series resistance 11 constant current source power terminal Vw output terminal 1353498 40 phase correction circuit