TWI345595B - Nh3 plasma treating method for forming poly-crystalline - Google Patents

Nh3 plasma treating method for forming poly-crystalline Download PDF

Info

Publication number
TWI345595B
TWI345595B TW95146542A TW95146542A TWI345595B TW I345595 B TWI345595 B TW I345595B TW 95146542 A TW95146542 A TW 95146542A TW 95146542 A TW95146542 A TW 95146542A TW I345595 B TWI345595 B TW I345595B
Authority
TW
Taiwan
Prior art keywords
amorphous
ammonia
layer
vapor deposition
annealing
Prior art date
Application number
TW95146542A
Other languages
Chinese (zh)
Other versions
TW200825220A (en
Inventor
Ching Lin Fan
Original Assignee
Univ Nat Taiwan Science Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Nat Taiwan Science Tech filed Critical Univ Nat Taiwan Science Tech
Priority to TW95146542A priority Critical patent/TWI345595B/en
Publication of TW200825220A publication Critical patent/TW200825220A/en
Application granted granted Critical
Publication of TWI345595B publication Critical patent/TWI345595B/en

Links

Landscapes

  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Chemical Vapour Deposition (AREA)

Description

1345595 九、發明說明: 【發明所屬之技術領域】 本案係指一種形成多晶矽的氨電漿處理方法,尤其指 一種應用於半導體製程中以形成多晶矽的氨電漿處理方 法0 【先前技術】1345595 IX. Description of the invention: [Technical field to which the invention pertains] This invention refers to a method for treating ammonia plasma which forms polycrystalline germanium, and more particularly to an ammonia plasma processing method for forming polycrystalline germanium in a semiconductor process. [Prior Art]

對於現今的平面顯示器產業而言,非晶矽薄膜電晶體 多半廣泛應用在通常的平面顯示器中,而低溫製(Low Temperature Processed,LTP)多晶石夕(polycrystalline silicon, poly-Si)薄膜電晶體(Thin Film Transistor,TFT)則多應用在 大面積顯示電子裝置(large area display electronics),如:主 動式矩陣液晶顯示(Active Matrix Liquid Crystal Sisplays, AMLCDs)及主動式有機電激發光顯示(Active Matrix Organic Light Emitting Displays,AMOLEDs)。但由於低溫 多晶石夕薄膜電晶體相較於習知的非晶石夕(am〇rph〇US silicon,a-Si)薄膜電晶體具有較高的驅動電流,且對於n 型與P型通道的TFT而言均易於生產製造等優點,因此能 夠有效促使互補金屬氧化物半導體(Complementary Metal Oxide Semiconductor,CMOS)與其週邊元件(peripheral drivers)整合於同一基板中,因此CM〇s的外連接(extemal connection)數將有效減少,能夠增加CM〇s相關產品的可 靠度及降低製造成本。因此以多晶矽為主的相關研究為平 面顯示器產業的重點研發面向之一。 生成多晶矽的過程大略如下述:沉積一層非晶矽相 (amorphousphase)薄膜’再經過結晶化程序而成為具有低密 5 1345595 度顆粒邊界(low grain-boundary density)的大顆粒 (large-grain)的多晶矽。習知上存在許多將非晶矽結晶成為 大顆粒多晶矽的技術,如:固相結晶法(s〇lid Phase Crystallization ’ SPC)、準分子雷射結晶(excimer iaser crystallization)及電子束感應結晶(electr〇n_beam_indueed crystallization)。SPC法係將薄膜置於高溫(6〇〇。〇爐中經過 固定時間(通常為20至60小時)的退火處理(31111邱1_)以進 行結晶,由於操作簡單且成本低又具有生成光滑表面的能 力,且按SPC方法生產的薄膜具有高度的可重製性,故廣 泛的受到採用,但由於SPC法須維持600。(:的溫度約20至 60小時以確保產生具有大顆粒的多晶矽薄膜,因此spc並 不利於商業化的生產及製造。因此許多用於縮短spc法之 結晶時間的改良方法被提出’如:金屬誘發(metal_indueed) 結晶法、鍺誘發(germanium-induced)結晶法及結晶前電漿處 理法(plasma treatment before crystallization)等,其中結晶前 電漿處理法能夠有效的在600。(:的環境下將結晶時間縮短 至4小時。其他還有如氫化法(hydr〇genati〇n)等的方法亦被 提出以減少多晶矽的能階以提高多晶矽構成元件的表現。 =以上述該等方法形成多晶矽結構多半需要消耗較多的結 晶時間(12〜24小時)’且因所形成的多晶矽結構中具有弱 Si-H鍵結導致其整體結構並不可靠。 職是之故,申請人鑑於習知技術中所產生之缺失,經 過悉心試贿研究,並—本麵不捨之精神,終構思出本 ,「形成多晶梦的氨魏處理方法」,能夠克服習知製造多 晶矽結構技術中的弱矽氫鍵結及長結晶時間等的缺陷,以 6 下為本案之簡要說明。 f發明内容】 本發明係以高密度電黎化學氣相沈積(High Density asma - Chemical Vapor Deposition » HDP-CVD)^AA^ » 結縣《於氨«中,相準分子熱 源持、錢射非晶石夕結構物至少3〇分鐘,以進行氨電聚處 ^復翻通常敎處斯可得料晶機構物。由於本 2係在财退火處理程稍先對非晶雜構物進行氨電 聚處理,故該等氨電漿處理又稱預處理。 經該等預處理後,可明顯減少非晶石夕結構物轉換至多 晶石夕結構物所需的結(本㈣2〜12小時,f知技術 12〜24小時)’而且經預處理後的非晶石夕結構物所產生的氫 自由基可幫助形成多晶石夕晶種,同時利用該等預處理亦可 形成較強的Si-N鍵結以取代習知上較脆弱的贴鍵結或 SA鍵結,如此可更進—步改#電晶體的熱載子效應㈣ earner effect) ’以提咼電晶體元件的電性及可靠度。 根據本發明的構想,提出一種形成多晶石夕的氨電聚處 理方法’其包括步驟形成—非晶雜—基層上;曝露該非 晶石夕於乳電渡;投射準分子雷射於該非晶石夕;以及退火該 非晶矽而形成一多晶石夕。 較佳地’本發明所提供之該獅成多晶卵氨電浆處 理方法’其中該基層為緩衝氧化層。 車乂佳地’本發明所提供之該種形成多晶料氨電聚處 理方法’其巾該氨係由純魏形成,該非_係經由 γ化學氣相沈積(CVD)製程而曝露在該氨電漿之中,該化學 ^相沈積製程為—電子猶共振化佩城娜CR-CVD) ;程、一電漿辅助化學氣相沈積(PECVD)製程或者一高密 度電漿化學氣相沈積(HDP-CVD)製程。 較佳地’本發明所提供之該種形成多晶矽的氨電漿處 理方法,其中該氨電漿為密度大於10”ions/m3的電漿。 較佳地’本發明所提供之該種形成多晶矽的氨電漿處 理方法’其_進行該曝露步驟時,該基板的溫度維持在300 〇C。 較佳地’本發明所提供之該種形成多晶矽的氨電漿處 理方法,其中進行該曝露步驟時,RF功率密度設定為 〇.6W/cm2 〇 較佳地’本發明所提供之該種形成多晶矽的氨電漿處 理方法,其中該曝露步驟持續至少30分鐘。 較佳地’本發明所提供之該種形成多晶矽的氨電漿處 理方法’其中該退火步驟係應用一固相結晶法、一準分子 雷射結晶法、一電子束感應結晶法、一爐管退火或者一雷 射退火。 根據本發明的構想,提出一種形成多晶石夕的氨電漿處 理方法,其包括步驟:形成一非晶矽於一基層上;以氨電 裝處理該非晶矽;以及退火該非晶矽而形成一多晶矽。 較佳地,本發明所提供之該種形成多晶矽的氨電漿處 理方法’其中該氨電漿處理步驟更包括步驟:曝露該非晶 砂於氨電漿;以及投射準分子雷射於該非晶矽。 較佳地’本發明所提供之該種形成多晶矽的氨電漿處 理方法’其巾該基層為緩衝氧化層。 較佳地’本發明所提供之該種形成多晶矽的氨電漿處 __方法γ其中該氨電毁係由純氨氣形成,該非晶石夕係經由 f化學乳相沈積(CVD)製程㈣露在魏電漿之巾,該化學 5 /尤積s程為—電子迴旋共振化學氣相沈積(ecr_cvd) ’長、-電襞輔助化學氣相沈積(PECVD)製程或者一高密 度電漿化學氣相沈積(hdp_cvd)製程。 、車父佳地’本發明所提供之該種形成多晶矽的氨電漿處 方法其中該氣電漿為密度大於10,,ions/m3的電漿。 較佳地,本發明所提供之該種形成多晶矽的氨電漿處 。理方法,其中進行該曝露步驟時該基板的溫度維持在3㈨ C 〇 較佳地,本發明所提供之該種形成多晶矽的氨電漿處 理方法,其中進行該曝露步驟時,RF功率密度設定為 〇.6W/cm2 ° 較佳地,本發明所提供之該種形成多晶矽的氨電漿處 理方法,其中該曝露步驟持續至少3〇分鐘。 較佳地,本發明所提供之該種形成多晶矽的氨電漿處 理方法,其中該退火步驟係應用一固相結晶法、一準分子 雷射結晶法、一電子束感應結晶法、一爐管退火或者一雷 射退火。 【實施方式】 ^本案將可由以下的實施案例說明而得到充分瞭解,使 斗于熟驾本技藝之人士可以據以完成之,然本案之實施並非 1345595 可由下列實例而被限制其實施型態。For today's flat panel display industry, amorphous germanium thin film transistors are widely used in common flat panel displays, and low temperature process (LTP) polycrystalline silicon (poly-silicon) thin film transistors. (Thin Film Transistor, TFT) is widely used in large area display electronics such as Active Matrix Liquid Crystal Sisplays (AMLCDs) and Active Organic Electroluminescent Display (Active Matrix) Organic Light Emitting Displays, AMOLEDs). However, since the low-temperature polycrystalline slab thin film transistor has a higher driving current than the conventional amorphous silicon wafer (am-rph〇US silicon, a-Si) thin film transistor, and for the n-type and P-type channels The TFT is easy to manufacture and the like, so that the complementary metal oxide semiconductor (CMOS) and its peripheral drivers can be effectively integrated in the same substrate, so the external connection of the CM〇s (extemal) The number of connections will be effectively reduced, which will increase the reliability of CM〇s related products and reduce manufacturing costs. Therefore, research related to polycrystalline germanium is one of the key research and development aspects of the flat panel display industry. The process of forming polycrystalline germanium is roughly as follows: depositing a layer of amorphous phase film' and then undergoing a crystallization process to become a large-grain having a low density of 5 1345595 low grain-boundary density. Polycrystalline germanium. There are many techniques for crystallizing amorphous germanium into large-grain polycrystalline germanium, such as: s〇lid Phase Crystallization 'SPC, excimer iaser crystallization, and electron beam induced crystallization (electr) 〇n_beam_indueed crystallization). The SPC method places the film at a high temperature (6 〇〇 in a crucible oven for a fixed time (usually 20 to 60 hours) annealing treatment (31111 Qiu 1_) for crystallization, due to simple operation and low cost, and has a smooth surface. The ability and the film produced by the SPC method have a high degree of reproducibility and are widely used, but the SPC method must be maintained at 600. (The temperature is about 20 to 60 hours to ensure the production of polycrystalline germanium film with large particles. Therefore, spc is not conducive to commercial production and manufacturing. Therefore, many improved methods for shortening the crystallization time of the spc method have been proposed, such as metal_indueed crystallization, germanium-induced crystallization, and crystallization. Pre-plasma treatment before crystallization, etc., wherein the pre-crystallization plasma treatment method can effectively reduce the crystallization time to 4 hours in an environment of 600. Others such as hydrogenation (hydr〇genati〇n) The method is also proposed to reduce the energy level of polycrystalline germanium to improve the performance of the polycrystalline germanium constituent elements. = The formation of polycrystalline germanium structures by the above methods requires more consumption. The crystallization time (12~24 hours)' and the weak Si-H bond in the formed polycrystalline germanium structure make the overall structure unreliable. The job is due to the lack of the prior art. After careful research on bribery, and the spirit of reluctance, I finally conceived the book, "the method of treating ammonia in the process of forming polycrystalline dreams", which can overcome the weak hydrogen bonding and long crystallization in the conventional polycrystalline germanium structure technology. The defect of time, etc., is a brief description of the case. The present invention is based on high density Density asma - Chemical Vapor Deposition (HDP-CVD) ^AA^ » In ammonia «, the phase-by-molecular heat source holds, and the carbon-emitting amorphous stone structure is at least 3 minutes, in order to carry out the ammonia electricity gathering, and the compound structure is usually obtained. The annealing process first performs ammonia electropolymerization on the amorphous heterostructure, so the ammonia plasma treatment is also called pretreatment. After the pretreatment, the conversion of the amorphous stone structure to the polycrystalline stone can be significantly reduced. Structure required knot (this (four) 2 to 12 hours , f know the technology 12~24 hours)' and the hydrogen radicals generated by the pre-treated amorphous stone structure can help form the polycrystalline sprite, and at the same time, the pretreatment can also form a strong Si-N bonding to replace the weaker bonding bond or SA bonding, so that it can be further improved - the thermal carrier effect of the transistor (4) earner effect) 'to improve the electrical properties of the transistor component And reliability. According to the concept of the present invention, an ammonia electropolymerization treatment method for forming polycrystalline spine is proposed, which comprises the steps of forming an amorphous hetero-base layer; exposing the amorphous rock to the milk electric ferry; projecting the excimer mine Shooting on the amorphous stone; and annealing the amorphous germanium to form a polycrystalline stone. Preferably, the lion is a polycrystalline egg ammonia plasma treatment method provided by the present invention, wherein the base layer is a buffer oxide layer.车乂佳地'The present invention provides a method for forming a polycrystalline ammonia electropolymerization process. The ammonia system is formed by pure Wei, which is exposed to the ammonia via a gamma chemical vapor deposition (CVD) process. Among the plasmas, the chemical phase deposition process is - electron resonance resonance Peicheng CR-CVD), a plasma-assisted chemical vapor deposition (PECVD) process or a high-density plasma chemical vapor deposition ( HDP-CVD) process. Preferably, the present invention provides a method for treating a polycrystalline silicon-forming ammonia plasma, wherein the ammonia plasma is a plasma having a density greater than 10"ions/m3. Preferably, the polycrystalline germanium is formed by the present invention. The ammonia plasma treatment method 'when the exposure step is performed, the temperature of the substrate is maintained at 300 〇 C. Preferably, the present invention provides the polycrystalline hydrazine-forming ammonia plasma treatment method, wherein the exposure step is performed The RF power density is set to 〇.6 W/cm 2 〇 preferably the present invention provides a method for treating a polycrystalline ruthenium ammonia slurry, wherein the exposure step lasts for at least 30 minutes. Preferably, the present invention provides The ammonia plasma treatment method for forming polycrystalline germanium 'where the annealing step is applied by a solid phase crystallization method, a quasi-molecular laser crystallization method, an electron beam induction crystallization method, a furnace tube annealing or a laser annealing. The invention provides a method for treating a polycrystalline petrochemical ammonia slurry, comprising the steps of: forming an amorphous germanium on a substrate; treating the amorphous germanium with ammonia; and annealing the non- Preferably, the present invention provides a method for treating a polycrystalline strontium-containing ammonia plasma, wherein the ammonia plasma treatment step further comprises the steps of: exposing the amorphous sand to an ammonia plasma; and projecting an excimer The invention is characterized in that the substrate is a buffer oxide layer. Preferably, the polycrystalline germanium is provided by the present invention. Ammonia plasma __ method γ, wherein the ammonia electricity is formed by pure ammonia gas, the amorphous stone is deposited by the f chemical emulsion deposition (CVD) process (4) exposed to the Wei plasma, the chemical 5 / s is - electron cyclotron resonance chemical vapor deposition (ecr_cvd) 'long, - electric auxiliary chemical vapor deposition (PECVD) process or a high density plasma chemical vapor deposition (hdp_cvd) process. The method for forming a polycrystalline ruthenium ammonia slurry according to the present invention, wherein the gas plasma is a plasma having a density of more than 10, ions/m3. Preferably, the polycrystalline strontium-forming ammonia plasma provided by the present invention is provided. Method, where the exposure is performed In the step, the temperature of the substrate is maintained at 3 (nine) C. Preferably, the method for treating a polycrystalline silicon-forming ammonia plasma provided by the present invention, wherein the exposure step is performed, the RF power density is set to 〇.6 W/cm 2 °. Preferably, the method for treating a polycrystalline silicon-forming ammonia plasma provided by the present invention, wherein the exposing step is continued for at least 3 minutes. Preferably, the present invention provides the polycrystalline silicon-forming ammonia plasma processing method, wherein The annealing step is applied by a solid phase crystallization method, a quasi-molecular laser crystallization method, an electron beam induced crystallization method, a furnace tube annealing or a laser annealing. [Embodiment] This case will be explained by the following implementation case. Fully understood, so that people who are skilled in the art can do it, but the implementation of this case is not 1345595. The following examples can be used to limit their implementation.

以下將本發明提出的該種形成多晶矽的氨電漿處理 方法用在低溫多晶矽薄膜電晶體(LTP poly-Si TFT)的製程 中為例,進行本發明實施例的說明。請參照第一圖,為本 發明提出的該種形成多晶矽的氨電漿處理用在LTP P〇ly-SiTFT製程中的實施步驟流程圖。第一圖中所示為正 在製造中的LTP poly-Si TFT,其為一種自對準(self-aligned) 的N型通道TFT ’其包括:基板1〇、缓衝氧化層11、非 晶矽層12、多晶矽層13、閘極介電層14、主動層15、多 晶矽閘極16及氨(NH3)電漿17,其中基板10可為一般通 常的矽材質基板。 實施本發明所揭露的方法時,首先提供基板1〇,並 在基板10上方沉積(depositing)—層緩衝氧化層11。接著 利用電樂輔助化學氣相沈積系統(Plasma EnhancedHereinafter, the method for treating polycrystalline germanium-forming ammonia plasma proposed by the present invention is used in the process of low-temperature polycrystalline germanium film transistor (LTP poly-Si TFT) as an example, and the description of the embodiments of the present invention is carried out. Referring to the first figure, a flow chart of the implementation steps of the polycrystalline germanium-forming ammonia plasma treatment used in the LTP P〇ly-SiTFT process proposed in the present invention is shown. The first figure shows an LTP poly-Si TFT being fabricated, which is a self-aligned N-channel TFT 'which includes: substrate 1 缓冲, buffer oxide layer 11, amorphous 矽The layer 12, the polysilicon layer 13, the gate dielectric layer 14, the active layer 15, the polysilicon gate 16 and the ammonia (NH3) plasma 17, wherein the substrate 10 can be a generally common germanium substrate. In carrying out the method disclosed in the present invention, a substrate 1 is first provided, and a layer-up buffer oxide layer 11 is deposited over the substrate 10. Next, using the Electro-Assisted Chemical Vapor Deposition System (Plasma Enhanced)

Chemical Vapor Deposition,PECVD)並配合純 SiH4 作為 反應氣體’環境變數設定於反應溫度為250。(:、壓力為Chemical Vapor Deposition (PECVD) was combined with pure SiH4 as the reaction gas' environmental variable at a reaction temperature of 250. (:, the pressure is

500mTorr(lTorr=133.3Pa)、及 RF 功率密度為 〇.25W/cm2, 以沉積一層厚度為115nm由Si:H所構成的非晶矽層12於 緩衝氧化層11上方,作為稍後進行氨電漿處理的先導層 (precursor layer)。接著利用高密度電漿(係指密度大於 10”ions/m3 之電漿 ’ High Density Plasma,HDP)化學氣相 沈積(Chemical Vapor Deposition,CVD)系統並以純氨氣 (ΝΗχ)作為反應電漿,對非晶矽層12進行氨電漿處理’其 係先將非晶石夕層12暴露(exposed)於氨電漿中,其中環境 變數的設定為基板10溫度為300°C、RF功率密度為500 mTorr (lTorr = 133.3 Pa), and an RF power density of 〇.25 W/cm2, to deposit a layer of amorphous germanium layer 12 composed of Si:H having a thickness of 115 nm over the buffer oxide layer 11 as a later ammonia gas The precursor layer of the slurry treatment. Then use high-density plasma (referred to as plasma density of 10"ions / m3 plasma 'High Density Plasma, HDP' chemical vapor deposition (CVD) system and pure ammonia gas (ΝΗχ) as the reaction plasma, The amorphous ruthenium layer 12 is subjected to ammonia plasma treatment. The amorphous slab layer 12 is first exposed to the ammonia plasma, wherein the environmental variable is set to a substrate temperature of 300 ° C and an RF power density of

晶(ciystallization),約需耗時2至12小時。 以作為主動層15。再以 二方沉積一層厚度為12〇nm (individual active device)層,以作為 HDP-CVD方法’在主動層15上方沉^ 的四乙基氧化石夕(tetraethyl orthosilicate oxide,TEOS/Cy 層,以作為閘極介電層14。 重複上述氨電聚處理及退火處理,以形成_層多晶石夕 層於閘極介電層14上方以作為多晶㈣極16。再利用反 應性離子乾蝕刻(reactive i〇n dry etching)以形成閘電極 (gate electrode,未示於圖中)。再者,以磷⑽沉沖⑽那) 作為摻質(dopant)再利用自對準P+型離子佈植(i〇n implantation)法,以5xl015cm2的植入劑量形成源極、汲極 與閘極(均未示於圖中)。再利用準分子雷射(excimer laser) 退火程序以能量密度2〇〇mJ/cm2在室溫的環境下活化離子 摻質(implanted dopant)區。在300°C的環境下沉積一層 500nm厚的hdp-cvd TE0S鈍氧化〇xide)層 (未示於圖中)。最後在適當位置形成接觸孔(contact holes, 未示於圖中),並形成紹電極(未示於圖中)而完成LTP P〇ly-Si TFT 的製作。 以上所述的製程當中,在進行退火處理形成多晶矽層 月1J,均對作為先導層的非晶石夕層進行氨電漿處理,經該等 氨電漿處理後可明顯減少非晶矽層12轉換至多晶矽層13 所需的結晶時間,而且經預處理後的非晶矽層所產生的氫 自由基可幫助形成多晶矽晶種,同時利用此預處理亦可形 成較強的Si-N鍵結以取代習知上較脆弱的si_H鍵結或 Si-Si鍵結,如此可更進一步改善電晶體的熱載子效應作说 carrier effect),以提高電晶體元件的電性及可靠度。 請繼續參照第二圖’係為本發明形成多晶矽的氨電漿 處理方法的實施步黯侧。以上_氨電祕理的部分 可整合如以下步驟: 步驟一.曝露非晶石夕層12於氨電漿17中; 步驟二:持續30分鐘投射準分子雷射於該非晶石夕層 12上;以及 。步驟三:利用SPC方法持續4至12小時以至少600 C退火處理非00碎層12,將非晶發層轉換為多晶石夕層 以上步驟-及步驟二又可合稱為氨電漿預處理 (pretreatment)。以上所揭露的三個步驟已如帛二圖中所示。 以上所述者,僅為本發明之最佳實施例而已,當不能 以之限定本㈣所實施之細。本案得由麟技藝之人任 施匠思而麟般修飾,然皆视如㈣職騎欲保護 者。即大驗本㈣ψ請專纖騎作之均等變化盘修 飾,皆應仍屬於本發明專利涵蓋之範圍内,謹請貴^查 委員明鑑,並祈惠准,是所至禱。 一 1345595 【圖式簡單說明】 第一圖係為本發明提出的形成多晶矽的氨電漿處理 用在LTPpoly-SiTFT製程中的實施步驟流程圖;以及 第二圖係為本發明形成多晶矽的氨電漿處理方法的 實施步驟流程圖。 【主要元件符號說明】Cinstallization takes about 2 to 12 hours. Take the active layer 15. A layer of 12 〇nm (individual active device) is deposited in two layers to serve as a HDP-CVD method 'tetraethyl orthosilicate oxide (TEOS/Cy layer) over the active layer 15 As the gate dielectric layer 14. The above-mentioned ammonia electropolymerization treatment and annealing treatment are repeated to form a _ layer polycrystalline layer above the gate dielectric layer 14 as a polycrystalline (tetra) pole 16. Reuse of reactive ion dry etching Reactive i〇n dry etching to form a gate electrode (not shown in the figure). Further, phosphorus (10) sinking (10) is used as a dopant to reuse self-aligned P+ ion implantation. (i〇n implantation) method, the source, the drain and the gate were formed at an implant dose of 5xl015cm2 (all are not shown in the figure). The ionized dopant region is then activated at an energy density of 2 〇〇 mJ/cm 2 at room temperature using an excimer laser annealing procedure. A 500 nm thick layer of hdp-cvd TE0S ruthenium oxide xide) was deposited in an environment of 300 ° C (not shown). Finally, contact holes (not shown in the figure) were formed at appropriate positions, and electrodes (not shown) were formed to complete the fabrication of the LTP P〇ly-Si TFT. In the above-mentioned process, the polycrystalline germanium layer 1J is formed by annealing treatment, and the amorphous austenite layer as the lead layer is subjected to ammonia plasma treatment, and the amorphous germanium layer 12 can be significantly reduced by the ammonia plasma treatment. The crystallization time required for conversion to the polysilicon layer 13 and the hydrogen radicals generated by the pretreated amorphous germanium layer can help form polycrystalline germanium seeds, and the use of this pretreatment can also form strong Si-N bonds. In order to replace the more fragile si_H bond or Si-Si bond, the carrier effect of the transistor can be further improved to improve the electrical and reliability of the transistor component. Please continue to refer to the second figure, which is the implementation side of the ammonia plasma processing method for forming polycrystalline germanium. The above part of the ammonia electrolysis can be integrated as follows: Step 1. Exposing the amorphous layer 12 to the ammonia slurry 17; Step 2: projecting the excimer laser onto the amorphous layer 12 for 30 minutes ;as well as. Step 3: using the SPC method for 4 to 12 hours to at least 600 C annealing the non-00 layer 12, converting the amorphous layer to the polycrystalline layer above the step - and the second step may be collectively referred to as ammonia slurry pre- Pretreatment. The three steps disclosed above are as shown in the second figure. The above is only the preferred embodiment of the present invention, and the details of the implementation of (4) cannot be limited. This case has to be modified by the philosophers of the literary arts, and they are all like the (4) ritual protectors. That is to say, the big test (4) ψ 专 专 专 专 骑 骑 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a flow chart of the implementation steps of the process for forming polycrystalline germanium in the plasma processing of LTP poly-SiTFT proposed by the present invention; and the second figure is the ammonia lamp forming polycrystalline germanium in the present invention. Flow chart of the implementation steps of the slurry processing method. [Main component symbol description]

10 :基板 12 :非晶矽層 14 ··閘極氧化層 16 :多晶矽閘極 11 :緩衝氧化層 13 :多晶矽層 15 :主動層 17 :氨電漿10 : substrate 12 : amorphous germanium layer 14 · gate oxide layer 16 : polysilicon gate 11 : buffer oxide layer 13 : polysilicon layer 15 : active layer 17 : ammonia plasma

e 13e 13

Claims (1)

_、申請專利範圍: 係-在-半導 晶導其包括㈣咖製料元件的一非 於一基層上形成該非晶矽層; 曝路该非晶石夕層於該氨電聚; 投射準分子雷射於該非晶石夕層;以及 退火該非晶石夕層而形成一多晶石夕層。 1製項所述的方法’射該半導體前 单而Γ為 則段製程㈣如姻細,FE0L) — 顺程(㈣yp聰ss)、—太陽能板前段 程。絲-主動矩陣有機發光二極體_⑽D)前段製 i::專利範圍第1項所述的方法,其中該基層為- ·#_, the scope of the patent application: the in--a semi-conductive crystal guide comprising a (4) coffee material component on a non-base layer to form the amorphous germanium layer; exposing the amorphous rock layer to the ammonia electropolymer; A molecular laser is irradiated on the amorphous layer; and the amorphous layer is annealed to form a polycrystalline layer. The method described in the 1st item “shoots the semiconductor pre-order and becomes the process of the segment (4), such as the marriage, FE0L) — the process ((4) yp Css), the front section of the solar panel. Wire-active matrix organic light-emitting diode _(10)D) The method described in the first aspect of the invention, wherein the base layer is -# 4由純=^咖第1項職的枝,其巾魏電漿係 奸而痕+ ί ’ 5轉抑祕經由—化學氣相沈積(CVD) 製私而曝路在該氨賴之中,該化學氣相沈積製程為 學氣相沈積(ECR_CVD)製程、—電_助化 ㈣度電聚化學氣相沈 L==r:』r的方法’其中該麵為 6牛範圍第1項所述的方法,其中進行該曝露 步驟時,該基板的溫度維持在30(rc。 14 步驟時,RF_=2=^f;,射進行該曝露 8. 如_請專利範園第1項所#^ 持續至少3G分鐘。 財法,射該曝露步驟 9. 如申請專利範圍第1項所述### 係應用-in減晶法、-準該退火步驟 應結晶法、一爐瞢谓、m 一、日日法、一電子束感 曰、X J田町、.'口 £ -日日法、一爐管退火或者—雷射 «SjI. 刖 矽 =-氨電漿處理尚未被製作為元件二 於一基層上形成該非晶梦,· 11. 以該氨電漿處職非晶梦;以及 退火該非晶石夕而形成一多晶石夕。 前段圍第1G項所述的方法’其中該半導體 二=ί: _段製程(細财“彻,臟)、 段製程】别&陣列製程(array pr〇cess)、一太陽能板前 製程。2 絲矩陣有機發光二極體“MOLED}前段 處理牛H利細第1G項所述的方法,其中該氣電聚 吟理步驟更包括步驟: 曝露該非晶石夕於氨電衆;以及 缸射準分子雷射於該非晶石夕。 緩衝㈣賴咖,其中該基層為 H如申請專利範圍第10或項所述的方法,其中該氧 15 (==:氨-化學氣相沈積 f V *私魏之巾,該辨氣相沈積製程 為一電子迴製振化學氣概積(ECR-CVD)製程、一電聚 輔助化學氣相沈肇CVD)製程或者—高密度電聚化學 軋相沈積(HDP-CVD)製程。 15. 如申請專利範圍第1〇或12項所述的方法其中該氨 電漿為密度大於10”i〇ns/m3的電樂^。 16. 如中請專利範圍第1G項所述的方法,其中進行該曝 露步驟時,該基板的溫度維持在3〇〇。匚。 17·如申請專利範圍第10項所述的方法,其中進行該曝 露步驟時’ RF功率密度設定為〇 6w/cm2。 18.如申請專利範圍第10項所述的方法,其中該曝露步 驟持續至少30分鐘。 19.如申請專利範圍第10項所述的方法,其中該退火步 驟係應用一固相結晶法、一準分子雷射結晶法、」電子束 感應結晶法、一爐管退火或者一雷射退火。4 by the pure = ^ coffee 1st branch, its towel Wei plasma traitor and trace + ί '5 turn the secret through the chemical vapor deposition (CVD) system private exposure in the ammonia, The chemical vapor deposition process is a method of vapor deposition (ECR_CVD), a method of electro-chemical-assisted (four-degree) electro-chemical vapor deposition, L==r:』r, wherein the surface is the first item of the 6-bovine range. The method of the present invention, wherein the temperature of the substrate is maintained at 30 (rc. 14 steps, RF_=2=^f;, the exposure is performed. 8. For example, _ please patent Fanyuan first item# ^ Continue for at least 3G minutes. Financial method, shoot the exposure step 9. As described in the first paragraph of the patent application scope ### application-in-reduction method, the quasi-annealing step should be crystallization, a furnace, m 1. Japanese and Japanese law, an electron beam sensation, XJ Tamachi, . 'mouth-day-day method, one furnace tube annealing or - laser «SjI. 刖矽=- ammonia plasma treatment has not been made as component two Forming the amorphous dream on a base layer, 11. using the ammonia plasma to work on an amorphous dream; and annealing the amorphous rock to form a polycrystalline stone. The method described in the first paragraph of the 1G item The semiconductor two = ί: _ segment process (fine "cheek, dirty", segment process] other & array process (array pr〇cess), a solar panel front process. 2 silk matrix organic light-emitting diode "MOLED} front section The method of claim 1 , wherein the gas electropolymerization step further comprises the steps of: exposing the amorphous stone to the ammonia electricity; and discharging the cylinder excimer laser to the amorphous rock. Lai, wherein the base layer is H, as in the method of claim 10, wherein the oxygen 15 (==: ammonia-chemical vapor deposition f V * private Wei towel, the vapor deposition process is An electron-reducing chemical gas accumulation (ECR-CVD) process, an electropolymerization-assisted chemical vapor deposition (CVD) process, or a high-density electropolymerization chemical vapor deposition (HDP-CVD) process. The method of claim 1 or 12, wherein the ammonia plasma is an electric music having a density greater than 10"i〇ns/m3. 16. The method of claim 1G, wherein the exposing step is performed When the temperature of the substrate is maintained at 3 〇〇. · 17 · As described in claim 10 The method wherein the RF power density is set to 〇6w/cm2. 18. The method of claim 10, wherein the exposing step lasts for at least 30 minutes. The method of the present invention, wherein the annealing step is performed by a solid phase crystallization method, a quasi-molecular laser crystallization method, an electron beam induced crystallization method, a furnace tube annealing or a laser annealing.
TW95146542A 2006-12-12 2006-12-12 Nh3 plasma treating method for forming poly-crystalline TWI345595B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW95146542A TWI345595B (en) 2006-12-12 2006-12-12 Nh3 plasma treating method for forming poly-crystalline

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW95146542A TWI345595B (en) 2006-12-12 2006-12-12 Nh3 plasma treating method for forming poly-crystalline

Publications (2)

Publication Number Publication Date
TW200825220A TW200825220A (en) 2008-06-16
TWI345595B true TWI345595B (en) 2011-07-21

Family

ID=44771792

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95146542A TWI345595B (en) 2006-12-12 2006-12-12 Nh3 plasma treating method for forming poly-crystalline

Country Status (1)

Country Link
TW (1) TWI345595B (en)

Also Published As

Publication number Publication date
TW200825220A (en) 2008-06-16

Similar Documents

Publication Publication Date Title
TWI291235B (en) Low temperature process for TFT fabrication
CN103828061B (en) Carry out the method for deposit silicon-containing materials using argon-dilution
CN1310335C (en) Thin membrane transistor and producing method thereof
CN1638043A (en) Method for producing polycrystal silicon thin film and method for producing transistor using the same
TW200849465A (en) Manufacturing method of SOI substrate and manufacturing method of semiconductor device
TW200915395A (en) Method of manufacturing thin film semiconductor device
US7186663B2 (en) High density plasma process for silicon thin films
JP2009277908A (en) Semiconductor device manufacturing method and semiconductor device
US20090155988A1 (en) Element of low temperature poly-silicon thin film and method of making poly-silicon thin film by direct deposition at low temperature and inductively-coupled plasma chemical vapor deposition equipment therefor
JP5681354B2 (en) Method for manufacturing SOI substrate
JP2003068757A (en) Active matrix substrate and manufacturing method thereof
CN1716552A (en) Method of fabricating semiconductor device and semiconductor fabricated by the same method
JP2002198364A (en) Manufacturing method of semiconductor device
TWI345595B (en) Nh3 plasma treating method for forming poly-crystalline
JP3443909B2 (en) Semiconductor film forming method, semiconductor device manufacturing method, and semiconductor device
JP2004288864A (en) Thin film semiconductor, method of manufacturing thin film transistor, electro-optical device, and electronic equipment
US7026226B1 (en) Method of hydrogenating a poly-silicon layer
JP4461731B2 (en) Thin film transistor manufacturing method
JP5199954B2 (en) Manufacturing method of semiconductor device
JP4337554B2 (en) Manufacturing method of semiconductor device
JPH04186634A (en) Manufacture of thin film semiconductor device
JP3173758B2 (en) Semiconductor device and manufacturing method thereof
CN101487114B (en) Low-temperature polycrystalline silicon thin film device and manufacturing method thereof
JP2009111302A (en) Semiconductor device and manufacturing method thereof
JP3445573B2 (en) Semiconductor device

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees
MM4A Annulment or lapse of patent due to non-payment of fees