TWI344686B - Circuit component and process for forming the same - Google Patents

Description

1344686

MEGA06-015TWB IX. Description of the invention: • Technical field to which the invention pertains. The present invention relates to a circuit component, and more particularly to a protective layer (passively) on an integrated circuit (1C) wafer. The metal line or plane formed above the layer transmits signals from a chip built-in circuit (〇n_chip drcuit) unit to other circuit units, or a structure in which a power supply voltage or a ground reference voltage is transmitted to other circuit units and a method thereof. [Prior Art] Many of today's electronic components require operation at high speeds and/or low power consumption. In addition, today's electronic systems, modules or boards (c) rcub〇arcj contain many different types of wafers, such as Central Processing Units (CPUs), Digital Signal Processors (Digital Signal).

Processors, DSPs, analog chips, dynamic random access memory (DRAMs), static random access memory (SRAMs), or flash memory (F丨ashs). Each chip is loaded with different types and/or different generations of integrated circuit process technology. For example, 'in today's notebook personal computer' the central processing unit may be manufactured using an advanced 65 nanometer (nm) technology with a power supply voltage of 1.2 volts (V), analog wafer system use. A .25 micron (//m) integrated circuit process technology is fabricated with a power supply voltage of 33 volts. 'Dynamic random access memory chips use a 9-inch nanoscale integrated circuit process technology to manufacture 'power. The supply voltage is 1.5 volts, while the flash memory chip is fabricated using a 0. 18 micron technology's power supply voltage of 25 volts. Due to a single

The MEGA 06-015TWB system has a supply of materials, so it needs to have (9) shout ((10)_ehip) stable φ ° " ( age regUlator), transformer (v〇ltage converter) or circuit containing voltage regulator and II voltage Designs, such as DRAM chips, require a chip built-in transformer to convert 3.3 volts to 15 volts, while flash memory chips require a chip built-in transformer to convert 3 3 volts to 2 5 volt. Among them, the chip built-in voltage regulator H, transformer II or circuit design with voltage regulation and variable I is reported by the built-in power/grounding 彳 舰 舰 — — 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定Position of the semiconductor component. 3. If a voltage regulator, transformer, or circuit with voltage regulation and voltage transformation is built into a chip, a low-resistance power/ground reference voltage line is added. In addition to minimizing the energy consumption of the converter, the Φ can be reduced. The noise caused by the fluctuation of the capacitance and resistance of the load. In U.S. Patent No. 6,495,442, a post-passivation structure on the top of a wafer is disclosed. The back cover structure on the integrated circuit protection layer is used as a global, power, ground reference voltage or signal distribution network. Where the 'power/ground reference voltage is from an external (out-of-wafer) power supply. An embossing process for forming a post-passivation interconnection structure on a protective layer of an integrated circuit is disclosed in U.S. Patent No. 6,649,509, which can be used as a power supply, a ground reference voltage, A comprehensive distribution of the clock or signal. • SUMMARY OF THE INVENTION One object of the present invention is to pass through a metal line on a protective layer or 1344686

The MEGA 06-015TWB plane allows the chip built-in circuit cells under the protective layer to transmit signals to several components or circuit elements on the same chip φ (IC chip). The object of the present invention is to pass through the metal lines or planes on the protective layer so that the wafers underneath the protective layer are internally built to ensure that power is transferred to a plurality of components or circuit elements on the same wafer. SUMMARY OF THE INVENTION The object of the present invention is to enable a power source within a wafer to transmit power to a plurality of components B or circuit elements on a wafer through a metal trace or plane on the protective layer. The object of the present invention is to lose the signal transmitted to several components or circuit units by the parasitie effect. The object of the present invention is to reduce the power loss to a number of components or circuit units caused by a drop of a button. The object of the present invention is to transmit power to a singular element or circuit unit through a protective layer opening and a metal circuit or plane formed on the protective layer.

The object of the present invention is to distribute the ", power supply, or ground reference voltage" from at least one internal circuit or internal component to at least the other internal circuit or internal component through a metal line or plane on the layer. The purpose of this month is to distribute the signal, power, or ground reference voltage from at least the internal circuit or internal components to at least one other internal circuit or internal component through the metal lines or planes on the protective layer. Connect to an ESD protection circuit, driver circuit, or receiver circuit. Electric discharge 1344686

MEGA 06-015TWB

From to == electric = inside the metal circuit or plane on the protective layer, the external circuit). The internal circuit or internal components are produced by the outer or outer part of the butterfly li (the invention is designed to pass through the fine-line metal structure gamma metal under the tilting layer) and the metal line or plane on the protective layer. The signal is transmitted to an external circuit. • One of the objects of the present invention is to distribute a signal, power supply, or ground reference voltage output from at least an internal circuit or internal component to at least another internal circuit or internal component through a metal line or plane on the protective layer. The contact Lu structures on the protective layer are respectively connected to a chip external (〇 ff_chip) circuit and an external circuit. The object of the present invention is to distribute the external power supply to the internal f-path and the contact power supply to the external power supply and the ground reference voltage. • For the purposes of the present invention, a line component includes a gold layer line or plane on a protective layer and can be utilized to distribute the voltage and/or current to the internal circuitry of the voltage regulator. For the purposes of the present invention, a line component includes a metal line or plane on a protective layer, and the signal, power, or ground reference voltage output from at least one internal circuit or internal component can be distributed to at least the metal line or plane. An internal internal circuit or internal component. 1344686

MEGA06-0I5TWB according to the purpose of the invention

A line component includes a metal line or plane on a protective layer, and the Jinlin road surface can be distributed from at least the signal, power supply, or ground reference output of the internal circuit or internal component to at least the other internal circuit or internal The component 'clear-contact structure connection on the protective layer—the wafer is connected to the external circuit. According to the purpose of the invention, the line component comprises a metal line or plane on the protective layer, and the Jinlin road or plane is distributed - the external power supply to the internal circuit and the contact structure to the external power supply Power and ground reference voltage. [Embodiment] The circuit component of the present invention includes a wafer (_〇1_尔(四), a chip® (chip) or a package unit, etc.. Over-paeeivation of a voltage regulator or transformer. Power/ground reference voltage busbars. • Please refer to FIGS. 1B to 1C, 2B to 2C, and 3B to 3D, respectively, which reveal the first embodiment of the present invention. In the drawings and FIG. 1C, a simplified circuit schematic is shown, which uses a metal line or plane 81 on the protective layer 5 and/or a metal line or plane 82 to connect a voltage regulator or a transformer ( Vdtage c〇nverter) 4i and internal circuit 2〇 (including 2 卜 22, 23, 24) 'and use this metal line or plane 8 ι and / or • ^ line or plane 82 distribution - voltage regulator ϋ 41 The output voltage and/or a ground reference. The second and second graphs show the mth and the

MEGA 06-015TWB The circuit shown in the figure is not intended. Fig. 3B and Fig. π are schematic cross-sectional views showing the circuits of Figs. 1B and 1C, respectively. In addition, in the first series and the second county, the protective layer 5 is indicated by a broken line, and the line or plane formed on the protective layer 5 is indicated by a thick line, and the line is under the protective layer 5. It is represented by "thin line". The silk type representation is also in all embodiments of the present invention. In this embodiment, the power supply is made up of a built-in voltage regulator or transformer 41 via a protective layer. A metal circuit or plane is transferred to several components (circuits) on the same-integrated circuit chip (IV). The metal line or planar 'power source deposited on the protective layer can be transmitted under low loss conditions. In the component or circuit unit, the design of the voltage regulation and the transmission of the voltage on the metal line or the plane above the protective layer can control the voltage miscellaneous wire connected to the circuit to a voltage level. The output voltage of the device is between plus or minus 10% of the set target voltage in the regulator (ie, when the regulator outputs a voltage value, the difference between the voltage value and the set target voltage value is divided by the setting. Target voltage value The percentage is less than 10%) 'and preferably between 5% and 5% of the target voltage, wherein the set target voltage of the regulator is between 0 5 volts and 10 volts or 疋Between 0.5 volts and 5 volts, so 'in this way, the input node can be prevented from being subjected to voltage surges generated by external power supply or large voltage fluctuations'. Therefore, this design can be improved. Circuit performance. However, in some applications 'because the chip needs to be different from the voltage supplied by the external supply,

MEGA 06-015TWB Therefore, in addition to the stability (4) in the chip, it is also necessary to use a transformer to convert the voltage supplied by the external power supply into the required voltage. This (four) device can convert the - input voltage into - output voltage 'and turn out _ different from the input voltage value, and the input voltage and the input (four) _ difference continuation of the ridge pressure of the hundred sisters greater than the secret 'where the output voltage is such as Between the 1V volts of the rafter or between volts and 5 volts. In addition, the type of the transformer can be a step-down transformer or a booster transformer. Fig. 1A, Fig. 2A and Fig. 3A show how a conventional voltage regulator or transformer W is connected to an internal circuit 2 (including a schematic diagram of a circuit diagram of η, μ, and so on, a plan view and a cross-sectional view. The prior art is a thin line metal structure 619, 6191 and 61 under the protective layer 5 (including 618, 6111, 6121 and 6141, wherein 6121 includes 6121a, 6121b and 6121c) to connect the regulator or transformer 41 to the outside. The power supply input voltage Vdd, the output-voltage vee, and the transfer voltage Vcc are supplied to the internal circuit 20 (including 21, 22, 23, and 24). However, the thin circuit is formed under the protective layer 5 and fabricated using the wafer process and material. The metal structure 61 does not easily provide a thick metal layer (for example, a metal layer having a thickness of 5 μm) or a thick dielectric layer (for example, a dielectric layer having a thickness of 5 μm). In addition, the high unit length resistance of the thin wiring metal layer Capacitance with high unit length can cause IR voltage drop, noises, signai distortion, propagation time delay, high power consumption, and high heat generation ( High he At generation) 〇 1344686

MEGA 06-015TWB Referring to Figure IB, it is a schematic diagram of the circuit of the present invention. In this embodiment, a voltage regulator or transformer 41 receives the voltage of the external power supply input via the protective layer opening and the fine line metal structure 619, and outputs the voltage Vcc to the internal circuit 2 (including 2 η, 23 And the voltage Vcc that the voltage regulator or transformer 41 rotates at the node p is distributed to the voltage nodes Tp, Up, Vp, Wp of the internal circuit 2, 22, 23, 24 by the following method, which is first through the thin line The road metal structure 619' passes upward through the protective layer opening 519' of the protective layer 5, and then passes through a metal line or plane 8 on the protective layer 5 and then passes through the protective layer to open π 511, 512, 514, after After passing through the fine-line metal structure 61, (including 6A, 612, 614, wherein 612 includes 612a, 612b, 612c) to the internal circuit 20, which passes through the thin-line metal structure 611 to the internal circuit 2; through the fine-line metal structure 612a and The fine line metal structure 612b to the internal circuit 22; through the fine line metal structure 612a and the thin line metal structure 612c to the internal circuit 23, and through the fine line metal structure 614 to the internal circuit 24. • In addition, internal electricity The circuit 2〇 (including 21, 22, 23, 24) is composed of at least one MOS transistor, and the above-mentioned fine-line metal structure is connected to the internal circuit 2〇 (including 2, 22, Z3) And 24) a gold-oxygen semi-transistor, such as a source of a MOS transistor, and the MOS transistor may be "Channel width / Channel length," An N-type MOS transistor with a ratio between 〇丨5 or between 0.2 and 2, or a channel width/channel length ratio of 0 2 to 1 〇 between or between 0.4 and 1344686

-P-type gold oxide semi-transistor _〇S transis (4) between MEGA 06-015TWB 4. In addition, the current flowing through the metal line or plane 8 is between 5 〇 microamperes to 2 milliamps or between 100 microamps and 1 milliamperes. Therefore, the structure shown in FIG. 1B uses a metal line or plane 81 as a power supply line or plane, and since the metal line on the protection 5 is a thick metal conductor, the *thick metal conductor has a low power. Riga, so it can greatly reduce the voltage drop (v〇ltage dr〇p) generated by the metal line or plane 81, and can stabilize the supply voltage provided by the metal line or plane 81. In FIGS. 1B to 1C, 2B to 2C, and 3B to 3D, the internal circuit 20 includes an internal circuit 2, an internal circuit 22, an internal circuit 23, and an internal circuit 24, wherein the internal circuit 22, 24 is for the opposite or between ^ (10) Na), and the internal circuit 23 is for the opposite and _ Na _, riding - a domain and a closed node have three input nodes Ui, Wi, Vi, an output node u〇, W〇, v〇, a voltage Vcc power supply node up, Wp, Vp and a ground reference voltage Vss are connected to the ground nodes Us, Ws, Vs, and the internal circuit 21 has an input node illusion, an output node X〇, An electric M Vcc power supply node Tp is connected to a ground reference voltage Vss ground node s s. Therefore, the internal circuit 2〇 (including 2 卜 22, and 2 sentences usually -, has a signal node (signal n〇de), a power supply node (ρ〇·(10) also), and a ground node (gromidnode). However, 'internal circuit 2〇 (Including 2, 22, 23, and 2 sentences, the turtle can be any type of integrated circuit. The content of this part will be - and the internal circuit 20 will be described in the following series of 15 (including 2, 22, 23, and 24). ) narrative; another related to 13 a

1344686

Some of the application examples of the MEGA 06-015 TWB circuit 21 will be described later in the 5C to 5j and φ 5M to 5R drawings. Please refer to FIG. 2B and FIG. 3B at the same time, which are respectively a schematic plan view and a cross-sectional view of the first drawing of the present invention. In g 3B, the fine-line metal structures 6U, 612, 614, 619, 619 may be formed by a fine-circuit metal layer 6〇 and a plug (10) filled in the opening ^, for example, in a manner of The quasi-stacking method forms 'that is, the upper and lower openings 30' are substantially aligned, and the upper and lower two thin lines are substantially aligned between the line metal layers 60, and the upper and lower conductive plugs 6〇, which are also approximate Aligned, the fine-line metal layer 6 分开 is separated by a thin-line dielectric layer 3_ such as oxidized oxide ') and the description of the fine-line metal structure is also applicable to all embodiments of the present invention. In FIG. 2B, the metal line or plane 81 on the protective layer 5 may be a single layer of patterned metal layer (for example, the patterned metal layer S(1) of the SB diagram or the multilayer patterned metal layer (not shown)). When the metal line or plane 81 is a multi-layer patterned metal layer, the 'patterned gold is separated by a polymer layer, and the poly-condensate layer can be polyimide (PI), phenyl ring Benzocydobutene (BCB), poly(p-phenylene benzene) 7 (iv), epoxy-based material 'e.g. epoxy resin or ph〇t〇 provided by Sotec Microsystems, which is located in Switzerland. Ep〇xy su_8, an elastomer (elastomer), such as an anthracene (siliC0ne). In addition, the metal line or plane 81 includes an adhesion/barrier/seed layer and a thick metal layer. Lu, for example, in the 3B towel 'patterned metal layer 811 includes an adhesion/barrier/seed layer 1344686

MEGA 06-015TWB 8111 and - thick metal layer 8112. As for the method of _ into metal lines or planes, and the metal line or plane _ fine refinement will be described in the series of drawings, the 16th series, the 17th series, the 18th series and the 19th series. In addition, the fine-line metal structure 612 includes a fine-line metal structure coffee, a fine-line metal structure (four), and a metal structure of a road, which is used as a regional power PGW, and is distributed, and the gold secret road or the plane 81 is used as a comprehensive The power (gk > balP〇wer) is allocated and connected to the fine-line metal structure ^, (including μ Bu• 612, 614) and the fine-line metal structure 619. Please also refer to FIG. 1B, FIG. 2B and FIG. 3B®, the external power supply is provided with a voltage Vdd ' at the contact pad 811 并 and after passing through the protective layer opening 519 and a thin line metal structure _ The voltage regulator or the device W' wherein the thin-line metal structure (10) includes a metal interface (metal _619〇) at the topmost layer of the thin-line metal layer 60, and is connected to the contact through the protective layer opening 519 to expose the metal pad 6190 Pad 811. The present invention utilizes a top polymer layer 99 to cover the metal lines or planes 8. The top polymer polymer layer 99 may be polyimine, phenylcyclobutene, poly(p-nonylbenzene), epoxy. A material (such as epoxy or photoepoxy SU-8), an elastic material (such as 矽_), such as shown in Fig. 3B, the patterned metal layer 811 covers a top polymer layer 99. In addition, the protective layer 5 and the metal line Alternatively, a polymer layer 95 may be selectively added between the planes 81. The polymer layer 95 may be a polyimide, a phenylcyclobutene, a polyparaphenylene or an epoxy material (such as an epoxy resin or Photoepoxy SU-8), elastic material (such as fluorenone) 'for example, 3D Shown 'in the protective layer 5 of the metal layer 811 is patterned (S) Λ 15 1344686

A polymer layer 95 is added between MEGA 06-015TWB, wherein the polymer layer openings 9519, 9519, 9511, I 9512, 9514 are respectively aligned with the protective layer openings 519, 519, 511, 512 in the protective layer 5, 514. In the present invention, the size of the bottom of the opening of the polymer layer may be smaller than the size of the opening of the lower protective layer, and the polymer layer covers the exposed portion of the opening of the protective layer, for example, in the 3D view, the opening of the polymer layer 9519, 9519, the size of the bottom is smaller than the size of the lower protective layer openings 519, 519', respectively, and the polymer layer 95 covers part of the protective layer openings 519, 519, the exposed metal pads 619 〇, φ 6190' , the additional protective layer openings 519, 519, the size is between 20 microns and 1 〇〇 micron ' and the polymer layer openings 9519, 9519, the size is between 2 〇 micrometers to 100 micrometers, however, In some designs, the size of the opening of the polymer layer may also be larger than the size of the opening of the underlying barrier layer and expose all portions of the opening of the protective layer through the opening of the polymer layer, such as the opening of the polymer layer 9511. The dimensions of 9512, 9514 are respectively larger than the dimensions of the lower protective layer openings 511, 512, 514, and the polymer layer openings 9511, 9512, 9514 are exposed by the protective layer openings 5n, φ 512, 514, respectively. All of the 'other protective layer openings, 512, 514 are between 10 microns and 50 microns in size' and the polymer layer openings 9511, 9512, 9514 are between 20 microns and 1 micron. between. The above description is also applicable to all embodiments of the invention. Alternatively, the metal line or plane 81 used to distribute the stabilizing or switching voltage VCC may be a polymer layer other than the patterned metal layer of the soap layer (such as the patterned metal layer an shown in FIG. 3B). Multilayer patterning 1344686 deposited between each metal layer

MEGA06-015TWB metal layer, and the multilayer patterned metal layer can penetrate the openings between the polymer layers to connect the patterned metal layers of different layers together. Then, please refer to Figure 1A, Figure 2A and Figure 3A, which are related technologies. As shown in the figure, the external power supply is provided with a voltage regulator or transformer in the following manner. The required input voltage is: the metal pad 619 received by the protective layer opening 519 receives the voltage vdd from the external power supply input, and then passes down the fine line metal structure 619, and finally the voltage Vdd wheel • Go to the regulator or transformer 4 and continue to distribute the output voltage Vcc of the voltage regulator or transformer 41 to the internal circuit 2 via the thin-line metal structure 61 (including 618, 6111, 6121, 6141) 22, 23, 24 Voltage Vcc node. However, this prior art has significant energy loss (energy 1 〇 ss) and slow speed (speed she has the disadvantage of (4). In the 1B, 2B, 3B and 3D, ground reference The voltmeter is not Vss, but its circuit, layout and structure are not described in detail. Please refer to the 1C, 2C and 3C diagrams for the present invention. Above the layer, the metal line or plane distributes the voltage Vcc and the ground reference voltage," the circuit shows gj, a top view and a cross-sectional view. In addition to the regulator or transformer 41 and the internal circuit 2 (including 2, 22, 23, 24) In addition to the common-ground reference voltage, that is, except that the internal circuit 20 and the regulator or the transformer 41 are connected, the points Ts, us, Vs, Ws, and Rs are all connected to the same ground reference voltage node Es. The structure and connection method of the ground reference voltage Vss is the voltage 1344686 mentioned above.

MEGA 06-015TWB VCC is similar. In the 1Cth, 2Cth, and 3Cth drawings, the ground node Es receiving the ground reference voltage Vss is connected to the voltage regulator via the protective layer opening 529 of the protective layer 5 and the thin line metal structure 629 under the protective layer 5. Grounding node Rs of the transformer or transformer ^, and via metal line or plane 82 (patterned metal layer 82 in FIG. 3C, protective layer opening cut, S22, 汹 and fine line metal structure 621, magic 622a, 622b) , 622c), 624 are connected to the ground nodes Ts, Us, Vs, Ws of the internal circuits 21, 22, 23, 24. • Referring now to Figure 3C, which reveals two layers of patterned metal layers 812 and 82 above the protective layer for use as a power/ground reference voltage structure, wherein the patterned metal layer 821 of the underlying layer is a metal trace or Plane illusion, used to distribute a ground reference _ voltage Vss route, bus bar or plane, while the top layer of patterned metal layer is used for the metal line or plane 8 as a distribution - hybrid Vee line, bus or plane. Also in the 3C®, the number 821 is represented by a patterned metal layer as a ground reference voltage, wherein the number 1 to the right of the number 821 represents the first metal layer, and the number 2 in the middle of the number 821 represents the ground (reverse (four), The number 8 to the left of the number 821 indicates the metal above the protective layer. Similarly, in the πth figure, the number 812 is used to represent the patterned metal layer as the power source, where the number 2 to the right of the number indicates the second metal layer. The number in the middle of the number MS indicates the power ^Power), and the number 8 on the left of the number 812 indicates the metal above the protective layer. Continuing, a polymer layer 98 separates the two patterned metal layers 821 and 812, and a top polymer layer " overlying the patterned metal layer m, wherein the polymer layer 兕 1344686

MEGA 06-015TWB may be a polyimine, a phenylcyclobutene, a parylene, an epoxy material (e.g., a cyclic oxy resin or Photo^oxy SU-8), or an elastomeric material (e.g., an anthrone). Alternatively, a polymer layer 97 (not shown in FIG. 3C) may be selectively formed between the protective layer 5 and the bottommost end of the patterned metal layer 821, and the polymer layer 97 may be a polyimide or a phenyl group. Cyclobutene, parylene, epoxy resin (10) such as ring fraction minus ph_pGxy SU 8), elastomeric materials (such as anthrone). The materials and processes for the polymer layers 97, 98, and 99 in Fig. 3C are the same as those in Figs. 3B and 3D, and the related description will be described in the subsequent Fig. 15 series. In addition, the patterned metal layer 821 for distributing the ground reference voltage Vss in FIG. 3C is through the protective layer openings 52 522, 524, 529 and the fine-line metal structures 621, 622, 624, and must be connected to the inside of the protective layer. The ground nodes ts, Us, Vs, Ws of the circuits 21, _ 22 23, 24 and the ground node Rs ' of the voltage regulator or transformer w are used to distribute the patterned metal layer 812 of the Vcc through the polymer layer opening ( Not shown in the figure), the protective layer opening (not shown) and the thin-line metal structure (® towel not shown) are connected to the bottom of the tilting layer. 2, 22, 23, the power supply of the point is Tp, Up, Vp, Wp and the power supply node of the polygonizer or transformer w (not shown in the figure). The current flowing through the metal line or plane m is between % microamperes to 2 milliamperes or between (10) microamps to 1 milliamperes. In a second application, the metal line or plane 81 can be used to transmit data or signals (e.g., digital or analog signals) in addition to the power supply design. Similarly, in addition to the grounding design of the metal line or plane 82, the gold road or plane 82 _ line or plane can also be used to 1344686

MEGA 06-015TWB transmits data or signals (such as digital signals or analog signals). • There are many other types of structures above the protective layer, which are described as follows: (1) Patterned metal layer 812 and patterned metal layer in high performance circuits or high percision analog circuits. A patterned metal layer (not shown) for transmitting a signal (such as a digital signal or an analog signal) may be added between the 821, and a polymer layer is formed below and above the patterned metal layer (in the figure) Not shown) 'separating the patterned metal layer from the patterned metal layer 812 and the patterned metal layer 821 φ; (2) patterning in applications of high current or high percision circuits A patterned metal layer (not shown) for distributing a ground reference voltage may be added over the metal layer 812 and a polymer layer is formed between the patterned metal layer and the patterned metal layer 812, and The patterned metal layer is covered with a top polymer layer. In other words, the patterned metal layer 812 is intermediate the patterned metal layer 821 and the patterned metal layer, thereby forming a Vss/Vcc/Vss structure over the protective layer 5; (3) if necessary, may further Above the patterned metal layer added in the above (2), another patterned metal layer (not shown) for distributing a power source is formed and the patterned metal layer and patterning added in the above (2) are formed. A polymer layer is formed between the metal layers 812, another polymer layer is formed between the patterned metal layer and the further patterned metal layer added in the above (2), and a top polymer layer is covered in another pattern. On the metal layer, a power/ground reference voltage structure of Vss/Vcc/Vss/Vcc (stacked from bottom to top) is thus produced. For high current circuits, high precision analog circuits, high speed circuits, low power circuits, power 20 (S> 1344686

The MEGA06-015TWB source management (powermanagement) circuit and high-performance circuit, the above structure φ can provide a stable power supply. Referring to Fig. 4, an example of a regulator or transformer 41 shown in Figs. 1B to id, 2B to 2C, and 3B to 3D is exposed. This example circuit is a transformer with both voltage regulation and voltage transformation functions, and is commonly used in "Semiconductor Memories ·· A handbook of Design, Manufacture φ and by John Wiley & Sons as in 1991 by B. Prince. Modern dynamic random access memory (Applycation) in a book (Dynamic)

Random Access Memory (DRAM) is designed. As shown in Fig. 4, through the voltage regulation and voltage transformation function of the transformer, the voltage vdd input from the external power supply can be converted into an output voltage Vcc' and the difference between the output voltage vcc and a set target voltage vcc〇 The percentage divided by the set target voltage VccO is less than 1%, and less than 5% is preferred. As described in the "Prior Art" section, more modern integrated circuit chips need to be converted into a voltage supplied by an external (system, board, module, or circuit card) supply by means of a built-in transformer on the chip. The voltage required for the wafer. In addition, some wafers, such as a DRAM chip, require twice or three times the voltage on the same wafer, for example, the peripheral control circuit uses 33 volts (V), and the memory in the memory cell array region The body unit (mem〇^ceU) uses 1 5 volts. In Fig. 4, the transformer includes two circuit blocks (c[rcuitbi〇ck), which are referred to as a reference voltage generator (v〇ltagereferencegenerat〇r) 41〇 and a current mirror circuit 1344686

MEGA 06-015TWB (current mirror cirCuit) 410'. The reference voltage generator 41 产 can generate a reference voltage VR at the node R to avoid being affected by the voltage fluctuation of the external power supply voltage Vdd of the node 4199. In addition, the external power supply voltage V (Jd is also the input supply voltage of the reference voltage generator 410. The reference voltage generator 410 includes two voltage dividers (v〇itage path, one includes three P-type MOS transistors 41〇1, 41〇3, 41〇5 connected together, and the other two P-type MOS transistors 41 〇2, 4]〇' continue The reference voltage can be regulated by the connection of the drain of the P-type MOS transistor 4103 to the gate of the p-type MOS transistor 4104. Therefore, when the external power supply voltage Vdd fluctuates When rising, the voltage of node G rises, causing the opening degree of Ba|f 4104 to be lower, and thus the reference voltage % is lowered. Similarly, when the external power supply voltage drops, the reference voltage is 100% old. Up to this point, the above description explains the adjustment characteristics of the reference voltage generator. The output of the reference generator 410 is used as a reference Φ voltage for the current mirror circuit. For an integrated circuit chip, the current mirror The circuit is complete and can output stable electricity. The ability to compress and have a large current, and by avoiding the direct high current path from the external power supply voltage to the ground reference voltage Vss, the current mirror circuit can eliminate huge power consumption or waste. In addition, through p-type gold The oxygen semi-electrode is connected to the gate of the p-type MOS transistor 41〇6, and the output voltage is connected to the voltage mirror (reference e 曰 - - - - , , , , , , , 电流 电流 电流41., can be output: two = 22 8

The voltage Vcc of MEGA 06-015TWB is controlled at a specified voltage. In addition, the conductance transistor 4112 is a small P-type MOS transistor, and its gate is connected to the ground reference voltage Vss, so the electrically conductive crystal 4112 is always on; and the electrically conductive crystal 4111 is It is a large P-type MOS transistor, and its gate is controlled by a signal Φ. When the internal circuit is in the active cycle, the electrically conductive crystal 4111 is turned on, and the p-type MOS transistor is turned on. The current path formed by 4109 and N-type MOS transistor 4107 and the current path formed by P-type MOS transistor 4110 and N-type MOS transistor 4108 have a fast response. In addition, the internal circuit can be turned on by the opening of the electrically conductive crystal 4111 (for example, the internal circuits 21, 22, 23, 24 in FIGS. 1B to 1C, 2B to 2C, and 3B to 3D). The transient instability of the output voltage Vcc caused by the large transient current demand is minimized. When the internal circuit is in an idle cycle, the transistor 4111 is turned off to avoid power consumption. Pen-2 Embodiment: An over-passivation interconnection connected to an internal circuit. As disclosed in the prior patents by the present patentee, for example, U.S. Patent No. 6,657,310 and U.S. Patent No. 6,495,442, the thick metal conductor of the present invention (or Baoxian Jinjin Road or Plane) can be used. Assign a signal, voltage or ground reference voltage. In addition, the phrase "above the protective layer ("ver-passivati〇n"" used in the present invention is the patentee of the present invention in the prior patent, for example 1344686

MEGA 06-015TWB, such as U.S. Patent No. 6,495,442, Tiger, has chosen to use the word "post-protection #", and the metal line or plane above the "protective layer" can be used as the Wei-Electronic circuit (10) to connect the line _nx&gt ;nnection). In this case, the 'thick metal conductor (or the metal line or plane above the protective layer) can be used to send data or signals from an output node of a first internal circuit. An input node of the internal circuit says n〇de). It is designed to connect a pair of two nodes (such as the data, location, or signal address) of the internal power of the two. A metal line, for example, is used to connect 8-bit, 16-bit, ^bit, 64-bit, I28-bit, 256-bit, 5-bit, between the processor unit and the memory unit on the same wafer. Metal lines, usually referred to as bus bars, which are used in the memory (w_ bus or bit) _ busbars additionally provide a thick metal conductor (or protective layer) over the protective layer The upper metal circuit or plane) is connected to a plurality of internal circuits, and the thick metal conductor can be separated from the semiconductor component' so that the signal can be reduced when the signal passes through the thick metal conductor (or the metal line or plane above the protective layer) The situation of disturbing the underlying semiconductor component 'either can reduce the situation in which the lower semiconductor component interferes with the signal, so that the signal has better integrity. However, in this embodiment, the thick metal conductor above the protective layer (or The metal line or plane above the protective layer is only connected to the node of the internal circuit, and is not connected to an external circuit through any of the external input/output drucit's. Also, the present invention 24 8 1344686

MEGA 06-015TWB The thick metal conductor above the protective layer (or the metal line or plane above the protective layer) is designed differently than the conventional pad redistribution design. In addition, because the thick metal conductor (or the metal line or plane above the protective layer) has the advantage of low resistance and the parasitic capacitance caused is very low, the signal will not be drastically attenuated' making the invention very suitable Used in high speed, low power, high current or low voltage applications. In most cases, the present invention does not require an additional amplifier, driver/receiver or signal repeater to help maintain signal integrity, φ. In some cases, an internal driver, An internal receiver (internalreceiver), a signal relay or an internal imemal tri-state buffer 'to transmit signals over long distances' and internal drivers, internal receivers, internal tri-state buffers H or signal relays are included A MOS transistor with a size smaller than the MOS transistor of the external circuit of the wafer, as for the internal circuit, the internal driver, the internal receiver, the internal tri-state buffer, and the gold-oxide half of the external circuit of the chip. The size of the transistor will be described and compared in detail later. • Referring now to Figures 5B, 6B, and 7B, the first embodiment of the present invention is disclosed. Figure 5B shows a simplified circuit diagram which uses internal wiring or metal 83 on the protective layer 5 and thin metal structures 63 632a, 632b, 632c, 634 under the protective layer 5 to connect the internal circuits 2 (including 2 Bu 22, 23, 24). In FIG. 5B, the internal circuit 21 has an input node phantom and an output node X〇' and sends a signal through the output node, and the signal can be borrowed from the metal line or plane 83 and the fine line metal structure Nabu,

A 25 1344686

The MEGA 06-015TWB 634 is transmitted to the input nodes of the internal circuits 22, 23, 24, and the internal φ circuit 21 can be a logic gate (i〇gic gate), such as a reverse or a slamming gate, a reverse ( NAND) gate, or (OR) gate, and (AND) gate, or an internal buffer (such as inverters, internal drivers, or internal tristate buffers as shown in Figures 5C, 5D, and 5E) ). Figure 6B shows a top plan view of the circuit shown in Figure 5B. Fig. 7B shows a schematic cross-sectional view of the circuit shown in Fig. 5B. In addition, in the figure and FIG. 6B, 'the line or plane formed on the protective layer 5 is represented by "thick line," and the line structure formed under the protective layer 5 is "thin line," Said. In the present invention, the internal driver for driving the metal line above the protective layer is the same as the intra_chip driver described in U.S. Patent No. 2,899,951 (the prior patent of the present patentee). . Through the metal lines or planes 83 on the protective layer 5, the protective layer openings 532, 534 in the protective layer 5, and the thin line metal structures 631, 632a, 632b, 632c, 634 under the protective layer 5, three internal logic circuits (internal The circuits 22 and 24 are inverted or gated, and the internal circuit 23 is connected to the received data or signal transmitted by the internal circuit 21. Since the metal line or plane 83 above the protective layer has low resistance and can produce low parasitic capacitance characteristics, the voltage swing between the input points Ui Vi and Wi between Vdd and Vss has very small attenuation and Noise. In addition, in this implementation, the metal lines or planes do not need to be connected to any external circuit of the chip that will be used to connect to an external circuit in the subsequent U-series series, such as electrostatic discharge (ESD) protection circuits, and wafers. Driver, chip external receiver or chip external buffer circuit (eg wafer tristate buffer 26 1344686

MEGA 06-015 TWB circuit), so this embodiment can improve speed and reduce power consumption. φ Please refer to FIG. 5A, FIG. 6A and FIG. 7A simultaneously, which are related art of the embodiment. As shown in the figure, the internal circuit 21 located under the protective layer 5 is through the fine line. The metal structures 6311, 638, 6321a, and 6321b are connected to an internal circuit 22 (e.g., a reverse or gate), connected to an internal circuit 23 (e.g., a reverse gate) through the thin wiring metal structures 6311, 638, 6321a, and 6321c, and through The thin line metal structures 6311, 638, 6341 are connected to other internal circuits 24 (e.g., a reverse or φ gate). Therefore, it is conventional to rely on the fine line metal structures 638, 6311, 6321, 6341 located under the protective layer 5 to transfer the data output from the internal circuit 21 to the other internal circuits 22, 23, 24. However, conventional designs can cause signal degradation, performance degradation, high power consumption, and high heat. Next, referring to FIGS. 5B and 6B, it is to establish a metal line or plane 83 on the protective layer 5, and replace the 5A and the third through the metal line or plane 83 located on the protective layer 5. The thin-circuit metal structure 638 in Fig. 6A is such that the internal circuits 2, 22, 23, 24 are connected by metal lines or planes 83, as shown by an output node of the internal circuit 21 (usually internal). The output of the MOS of the circuit 21 is 'transmitted' then through the thin-line metal structure 63 under the protective layer 5, the protective layer opening of the protective layer 5, and the metal line or plane 83 on the protective layer 5' (1) The protective layer opening through the protective layer 5 and the fine-line metal structure 634 under the protective layer 5 are finally transferred down to the internal circuit paste such as - anti- or _-input node (usually the internal circuit 24 - the golden oxygen half-electric Crystal

A 1344686

The gate of MEGA 06-015TWB, such as the gate of one of the MOS/semi-transistors of the anti-gate or the gate; (2) the protective layer of the repaired layer 4 532 and the thin-line metal structure under the protective layer 5 632a, 632b, 632c), the last input node to the internal circuit 22 (such as a reverse or gate) and the internal circuit 23 (such as a reverse gate) - usually the internal circuit and the internal circuit 23 - the golden oxygen half The electro-crystals are, for example, the gates of the anti-gate and anti-gate and one of the MOS transistors. Therefore, in summary, an output node of the internal circuit 21 (usually the internal circuit _ 21 - the secret of the MOS transistor) is connected to the fine line metal structure (3) under the protective layer 5, and then passes through the protective layer 5 The protective layer opening 531 is connected to the metal line or plane 83 on the protective layer 5, and finally the protective layer opening s32, 534 of the protective layer 5 is connected to the fine line metal structure Μ2, 634 under the protective layer 5, and further to the internal circuit η, An input node of 23, 24 (usually the internal circuit 22, 23, the gate of one of the MOS transistors) is connected. Wherein, the internal circuits 21, 22, 23, 24 comprise an anti- or inter-, one- or inter-, - (four) or - anti-gate, and the internal circuit 2, 22, 23, 24 are at least • by a metal oxide semi-transistor The composition is constituted, that is, the anti- or inter-, or-close, and inter- or anti-gate 7C is composed of at least a gold-oxygen semi-transistor, and the MOS semi-transistor is, for example, a size (the width of the tiif is divided by the length of the track) Ratio) a ν-type MOS transistor between 5 ι to 5 or between 2, or the size (channel width divided by the ratio of the length) between 0.2 and 1 或 or between Ρ4 to 4 between a ρ-type Jinlu, a semi-transistor, another current flowing through a metal line or a plane 比如, such as a range between % microamperes) to 2 milliamperes, or between 1 〇〇 micro amps to! mAh 28 8 1344686 MEGA 06-015TWB between the trains. • 'Continue', please also refer to the 7th acid diagram of Figure 7B, which is the two implementations of the circuit structure shown in Figure 5B. As shown in the two figures, the metal line above the protective layer is φ 83 The phase is a single layer _ ing jin lang (such as the single layer patterned metal layer 831 shown in Figure π), or a multilayer patterned metal layer with a polymer layer between each adjacent patterned metal layer For example, the first % broken red two-layer patterned metal layer 831 (including (3) read 8; ^) and coffee, and between the two patterned metal layers such as germanium and 832 has a polymer layer 98. Alternatively, the metal line or plane 83 above the protective core may cover a top polymer layer 99 (as shown in the f 7β diagram, a top polymer (4) overlies the metal layer 831; as shown in Figure 7C, a top polymer Layer #99 overlies the patterned metal layer 832)' and the top polymer layer 99 does not have openings exposing the metal lines or planes 83' so the metal lines or planes 83 above the protective layer 5 (eg, patterned gold touch mi or pattern The metal layer cannot be connected to an external circuit. In other words, in this embodiment, the metal line or plane 83 (e.g., the patterned gold-rubber layer 831 or the patterned metal layer 82) has no contact pads for connecting external circuits. In Figure 7B, the numbers of the patterned metal layer 831 are each represented by: "8" represents the metal above the protective layer, "3" represents the signal line, and "1," represents the protection. The first metal layer above the layer. Similarly, it is inferred that in the 7th C, the number of the patterned metal layer 832 is represented by .8 is the metal above the protective layer, ♦ is the representative-signal line, and “2, is the representative. Above the protective layer Metal ⑧ 29 1344686

MEGA 06-015TWB layer. In addition, the patterned metal layer 831 on the protective layer 5 includes an adhesion/barrier/seed layer 8311 and a thick metal layer 8312, and a polymer layer 95 is selectively formed to protect. Between layer 5 and the bottom layer of patterned metal layer 831, as shown in Figure 7D. Similarly, in FIG. 7C, the patterned metal layers 831a, 831b, 832 on the protective layer 5 include an adhesion/barrier/seed layer 83Ua, 8311b, 8321 and a thick metal layer 8312a, 8312b, 8322, and also A polymer layer 95 can be selectively formed between the protective layer 5 and the patterned metal layer 831 (including 831a, 831b) φ the bottom layer. Figure 7C is similar to Figure 7B except that the structure above the protective layer includes two patterned metal layers 83 and 832. In Figure 7C, it is in two patterns

A metal layer 831 (including 831a, 831b) and a patterned metal layer 832 are substituted for the single patterned metal layer 831 of FIG. 7B, and a polymer layer 98 is used to separate the patterned metal layer 831 and the patterned metal layer. In addition, in signal transmission, a signal is output from an output node of the internal circuit 21 (usually a drain of a metal oxide half transistor of the internal circuit 21), and then transmitted through a thin line metal structure 63 under the protective layer 5. A protective layer opening 531 in the protective layer 5 and the patterned metal layer 831b over the protective layer 5, followed by (1) in the first path: through the open polymer layer 9831 in the polymer layer 98, patterned The metal layer 832 passes down through a polymer layer opening 9834, passes through the patterned metal layer 831a, passes through a protective layer opening 534 of the protective layer 5, passes through the fine-line metal structure 634 under the protective layer 5, and finally passes down to the Lu An input node of internal circuitry 24 (eg, an inverse or gate) (usually one of internal circuitry 24)

MEGA 06-015TWB gold oxygen semi-electric crystal __, for example, anti-langu / * Chu - 々 々 rK ‘ oxygen semi-transistor gate); (2)

= under the protective layer 5 - the protective layer is opened and passed through: 5 fine wire metal junctions 'finally transferred to the internal circuit 2 such as the reverse or gate" and internal circuit 23 (such as the gate) - the input node (usually They are the internal η and the internal circuit — - the gate of the MOS transistor, for example, the reverse or the gate and the opposite - the idle pole of the MOS transistor. In addition, the portion of the metal line or plane, the polymer layer and the internal circuit above the protective layer according to the second embodiment of the present invention will be in the subsequent 15th series, the third series, the 17th column, the 18th column. Repeatedly with the 19th _ column. In addition, 'in the 5th, 6th, 6th, 100th and 1st claws' metal lines or flats 83 (including 831 and / or slave) are not connected to the crystal used to connect - external circuits >} The circuit is connected, and there is no significant voltage drop (v〇ltagedr〇p) or signal attenuation on the line or plane 83. In addition, the size of a MOS transistor can be defined as the ratio of channel width divided by channel length, or precisely the ratio of effective channel visibility divided by effective channel length. 'This definition applies to all embodiments of the invention. Referring now to FIGS. 5C-5E, the internal circuit 21 is shown as an example of an internal buffer, wherein the internal buffer is at least a MOS transistor (M〇). s transistor) constituting 'and this MOS semi-electric crystal such as including channel twist / channel length ratio between 3 and 60 or between 5 31 8 1344686

A p-type pO〇s transistor between MEGA06-015TWB and 20, or a channel wide parameter/channel length ratio between 1.5 and 3〇 or between 25 and 1 An N-type NMOS transistor between turns, and the current flowing through the metal line or plane 83 is between 500 microamps to 10 milliamps or between 7 microamperes to Between 2 milliamperes. Figure 5C reveals an inverted internal n-circuit for use as an internal circuit for the first, sixth, seventh, seventh, and seventh. In the first application, the size of the N-type oxy-halide transistor and the p-type MOS transistor 21〇2 can be the same as the size of the MOS transistor used in the internal circuit, so in the inverter In 211, the size of the N-type MOS transistor 21〇1 is between 〇1 and 5, and is preferably between 〇·2 and 2, and the type of MOS transistor is ruthless. The size is between 0.2 and 1 , and is preferably between 〇4 and 4. In addition, the current output by the reverse phase H 211 and passing through the metal line or plane 83 above the protective layer 5 is in the range of 50 microamperes (μΑ) to 2 milliamperes, and is between 100 microamperes and 1 millimeter. The range between amps is preferred. In the second application #, the inverter 211 needs to output a large drive current, for example, when the internal circuits 22, 23, 24 require a high load (heayy 1 〇 ad), or when the internal circuit 22 , 23, 24 and the internal circuit 21 are greater than! In millimeters or 3 mm, it is necessary to connect the metal lines over long distances, and the inverting H 211 requires a large drive current. In addition, the current from the output of the inverter 211 is higher than that of a general internal circuit, and the current, for example, 1 milliamperes (mA) or 5 milliamperes, is in the range of 500 microamperes to 10 milliamps. And between 3 〇〇 micro amps to 2 mA amps 32 1344686

The range of MEGA06-015TWB is preferred. Therefore, in the second application [inverter 2u^n type MOS oven 2101 size is in the range between U and 3 ,, and is between 2 5 and 10 Preferably, the size of the P-type MOS transistor is in the range between 3 and 60' and is preferably in the range between 5 and 2 。. The details of the size of the semi-transistor of the (-) internal circuit or the internal circuit used to drive other high-load internal circuits will be detailed in the subsequent series (4). • In addition, in Figure 5C, the metal line or plane 83 above the non-polar system of the N-type MOS transistor and the protective layer 5 (eg, 5th, 6b, 7b, 7C, and The connection in the 7D diagram), and the secret of the p-type MOS transistor 21〇2 is the metal line or plane 83 above the protective layer 5 (as in Figure 5b, the first map, the climbing 7B, the 7C) The figure is connected to the 7D). In most cases, the metal circuits or planes above the domain shield have a small impedance, so the complex internal circuits formed by the smaller metal oxide semi-transistors can be interconnected by metal lines or planes on the protective layer. , wherein the internal circuits include a size (channel ratio divided by the length of the channel) between 〇.1 to 5 or between 0.2 and 2, a Ν-type MOS transistor, or a size (channel) The width is divided by the ratio of the length of the channel)" between 0.2 and 1 或 or between 〇4 and 4, a p-type MOS type 曰 曰. In addition, in some applications, when the internal circuit 22, ΜWhen a high load is required, or when the distance between the circuit 22, 23, 24 and the internal circuit 21 is greater than 1 φ mm or 3 mm and a long distance is required, a larger 33 1344686 is required.

The drive current of MEGA 06-015TWB. Therefore, in the case of high load, an internal driver (intemal spring drive} or an internal buffer is required. Figures 5D and 5E show that the internal driver 212 or the internal tristate buffer 213 is used as the internal driver. The internal circuit 21 and the internal driver 212 or the internal tristate buffer 213 drive the metal lines or planes 83 on the protective layer 5 as shown in FIGS. 5B, 6B, 7B, 7C and 7D. And other internal circuits 22, 23, 24. Examples of the circuits shown in Figures 5D and 5 are (1) internal driver φ 212 or internal binary buffer 213 not connected to an external circuit; and (2) internal driver 212 Or the size of the MOS transistor of the internal tristate buffer 213 is smaller than the size of the MOS transistor of the wafer external driver or the wafer tristate buffer, and the others are respectively described in the following 11th and 11th. The chip external circuit (〇ff_chipdrcuit) is similar. The internal driver 212 in Fig. 5D is an example of the intra_chip driver described in the U.S. Patent No. 20040089951. The tristate buffer 213 provides the capability of amplifying the signal φ (drive capability) and the ability to turn on or off (switch capabiiity) and the internal tristate buffer 213 is particularly useful as a protection layer for the data or address bus. a metal line or plane transmits a data signal or a bit signal in a memory chip. In Figure 5D, the size of the N-type MOS transistor 2103 is between 15 and 30, and Preferably between 2.5 and 10, and the size of the p-type MOS transistor _ 2104 is between 3 and 60' and is preferably between 5 and 2 34 34

1 J^000 MEGA 06-015TWB

Further, the current of the metal line or plane 83 of Φ~ and the output of the internal driver 212 are output through the gold (10) 2 on the protective layer 5. (usually the current system is between the micro-replacement, the secret of the thorough reading) output to the range between 109 amps fine = milliamperes for her. In addition, in the first Jing, the second two-year-old I exit the node XG - the signal, and after passing through the protective layer 5 line or plane 83, the input to the internal circuit 22, 23, 24 is the point U Bu Vl, Wi, but not transmitted to - external circuitry. In Fig. 5E, it is preferred that the size of the N-type MOS transistor 2107 is between K5 and 21 2 25 to 1 G, and the 尺 phase of the 金-type MOS transistor j is Preferably, between 3 and 2, and between 5 and 2, and more preferably through the metal line or plane 83 above the protective layer 5 and the output node X of the internal 1 buffer. The output current ranges from 鄕 microamperes to 10 mA1 and ranges from 7 〇〇 microamps to 2 milliamps. In Figure 5E, the internal tristate buffer 213 can be driven. A signal from the output point X〇 output, and after passing through the metal line or plane 83 above the protection layer $, is transmitted to the ingress nodes Ui, Vi, Wi of the internal circuits 22, 23, 24, but is not transmitted. To an external circuit.

° Circuits 22, 23, 24 require high load, or when the internal circuit, 23 24 and internal circuit 21 are more than 1 wire or 3 mm apart and require a long distance of 2 metal lines, 'internal drive 212 and internal The output node Xo of the tristate buffer 213 is to rotate a large drive current. (3⁄4 35

MEGA 06-015TWB One of the important applications of metal lines or planes above the protective layer is to connect a memory cell with a segment distance from a memory chip (1_machi_ with internal circuits (eg logic thorns. See _ 5F _ Show, _ _ _ memory unit how to avoid the 5 on the Jinguan Road solution face 83 Qian Lai layer 5 under the fine line metal structure connected to the internal circuit of the logic circuit howl 5b, 6B , the πth diagram, the 7th diagram and the 7th diagram), wherein the logic circuit includes, for example, a -re-gate, - or a gate, and a gate or a sluice gate, and the internal circuits a, 23, 24 may be At least consisting of a gold-oxygen semi-transistor, and the thin-line metal structure described above is a gold-oxide semi-transistor connecting the circuit circuits 22, 23, 24, for example, connected to a source of a MOS transistor (source) ), drain or gate (d) e), and the MOS transistor may be a -N-type gold oxide having a channel width/channel length ratio between Q l and 5 or between 0.2 and 2. Semi-transistor, a p-type oxy-half-oxygen with a channel twist/channel length ratio between 0.2 and 1 或 or between 〇4 and 4. Body, or in addition to flow through the metal line 83 such as the current plane is between 5〇 microamps to 2 milliamps or culture interposed between 1〇〇 microamps to milliamps Shu. In this application, the metal lines or planes 83 on the protective layer 5 act as a data bus (e.g., a one-line line) bus bar or a reverse bit line (~line) bus bar. In the design of connecting a memory array and a logic circuit, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 or 4096 may be formed on the protective layer 5 in parallel. a metal line or plane 83, as a data bus of a memory chip, and using these metal lines or planes 83 to pass 1344686

MEGA 06-015TWB Data signal between the memory unit and the logic circuit. The metal φ line or plane 83 above the protective layer 5 is particularly suitable for the transmission of a wide-bit data, for example, 64, 128, 256, 512, 1024 bit width data. In addition, when transmitting a signal between the δ-resonant unit and the logic circuit (l〇giccircujt), the metal line or plane 83 above the protective layer 5 can be used as the address in addition to the above-mentioned data bus. An address bus is used to transmit an address signal. In addition, the signal transmitted by the metal line or the plane 83 on the δ layer 5 also includes the clock signal. The fifth FF is an example of a static random access memory unit 215 as a memory unit. However, the memory unit may be other memory units in the embodiment, such as a dynamic random access memory (DRAM). Unit, eliminates programmable read only memory (EPROM) unit, electronically erasable read only memory (EEPROM) unit, flash memory (Flash) unit, read only memory (ROM) unit, and magnetic random Access memory (magnetic RAM ' MRAM) unit. The SRAM cell 215 includes six MOS transistors, which are two N-type MOS transistors 2115, 2117, and two P-type MOS transistors 2116. 2118, and two word-line-control N-type MOS transistors 2119, 2120. Alternatively, in a memory chip, a memory array can be formed by repeating the SRAM cell 215. When the SRAM cell 215 is in the read state, the 'SRAM device 215 outputs complementary data, such as bit data) and the inverted bit 〇v) data, and respectively passes through the N-type MOS half. Transistor 2119 ® and N-type MOS transistor 2120 transmit complementary data to the bit line and reverse 37 8

The MEGA06-015TWB bit (W) line, followed by the bit 〇·,) data and the reverse bit (W) data are passed through the column selection (CS) transistors 2122, 2123 and input to a sense amplifier ( Sense amplifier) 214. Then, the bit line of the memory cell is connected to the gate of the N-type MOS transistor 2113 in the sense amplifier 214, thereby controlling the opening or closing of the N-type MOS transistor 2113 of the sense amplifier 214. When the N-type MOS transistor 2113 of the sense amplifier 214 is turned on, the sense amplifier 214 can initially amplify the inverted bit 使其·〇 data to have a better waveform or a better voltage level, and output the same. The amplified reverse bit (smart) data is initially transferred to the internal tristate buffer 213. In Fig. 5F, 'a differential amplifier is used as an example of the sense amplifier 214'. This differential amplifier contains four transistors, including two n-type MOS transistors 2111, 2113. And two P-type MOS transistors 2112, 2114, wherein the differential amplifier uses the N-type MOS transistor 2121 to isolate the differential amplifier and the ground reference voltage Vss ' and control the differential by a row selection signal Amplifier to avoid power consumption. When the SRAM cell 215 is not in the read state, that is, when both the word line and the bit line connecting the SRAM cell 215 are not selected, the N-type MOS transistor 2121 is closed. The reverse bit (and) data output from the gate of the N-type MOS transistor 2113 of the sense amplifier 214 is transferred to the internal driver, internal buffer or internal tristate buffer 213 (as shown in Figure 5F). The input node Xi. In addition, the control signal 仏, 5 series output from a read (than & (1 enable) circuit (not shown), and use this control signal 仏, to control the internal tristate buffer 213 on or off. In Fig. 5F, the internal tristate buffer 213 is 1344686.

MEGA 06-015TWB output node Xo outputs more megabytes of bit data to internal circuits 22, 23, 24 through metal lines or plane a on protection layer 5 (eg, map, 6β, 7B, Figure 7C and Figure 7D). Therefore, in summary, a static random access memory cell 215 is protected by the sense amplifier 214, the internal three-way 213, the thin-line metal structure 63 under the protective layer 5, and the protective layer opening 53 in the protective layer 5. The metal lines or planes 83 on the layer 5, the protective layer openings n 532, 534 in the protective layer 5, and the thin circuit metal structures 632, 634 are connected to the internal circuits 22, 23, 24 on the same wafer, such as the first map, Fig. 6, Fig. 7, Fig. 7C and Fig. 7D are shown. The internal circuit 21 is here an internal tristate buffer 213, but the internal circuit 21 can also be the internal driver 212 (as shown in FIG. 5D) or other internal circuits such as the inverse or gate (NOR _). , AND gate, AND gate, OR gate, adder multiplexer, diplexer, multiplier, complement Metal oxide semiconductor, bi-carrier complementary MOS or bi-carrier circuit (bip〇lar_circuit)', and when internal circuit 21 is internal driver 212, internal circuit 21 is composed of at least one MOS transistor. And the MOS semi-transistor includes a P-type MOS transistor or a channel channel length/channel length ratio with a channel width/channel length ratio between 3 and 60 or between 5 and 20. An N-type oxy-halide transistor between 1.5 and 30 or between 25 and 10, and the current flowing through the metal line or plane 83 is between 500 microamps to 1 milliamperes or It is between 7 〇〇 microamperes # to 2 milliamps; the other 'when the internal circuit 21 is the other internal circuits mentioned above, 1344686

MEGA06-0J5TWB This is the inside. The P road 21 includes at least a channel width/channel length ratio between 〇ι and 5 or between 0.2 and 2, or a channel width/channel length ratio of 0.2. a p-type MOS transistor between 10 or between 〇4 and 4 and the current flowing through the metal line or plane 83 is between 5 〇 microamperes to 2 mA or Between 1 〇〇 microamperes and 丨 milliamperes. Referring to Figure 5G, the reverse bit (10) data output by sense amplifier 214 will pass through a circuit circuit 216 before it reaches the output node of internal circuit 21, where the internal circuit 21 is the pass circuit 216. The pass circuit 216 can be a simple MOS transistor, such as an N-type MOS transistor 2124, and controlled by a read signal. In this design, a static random access memory cell 2 is transmitted through the sense amplifier 214, through the circuit 216, the thin line metal structure 631 under the protective layer 5, the protective layer opening 531 in the protective layer 5, and the protection layer. Metal lines or planar phantoms on layer 5, protective layer openings 532, 534 in protective layer 5, and thin line metal structures 632, 634 under protective layer 5 are connected to internal circuits φ 22, 23, 24, as shown in FIG. 5B, Fig. 6B, Fig. 7B, Fig. 7C and Fig. 7D are shown. Referring to FIG. 5H, the reverse bit (product) data output by the sense amplifier 214 will pass through a latch circuit 217 before reaching the output node X of the internal circuit 2, where The internal circuit 21 is a latch circuit 217. The flash lock circuit 217 can be a static random access memory unit for temporarily storing the data before the sense amplifier 214_output data is sent to the logic circuit (such as the internal circuits 22, 23, 24).

MEGA 06-015TWB stores the data output from sense amplifier 214 (ie, the data is latched). In addition, the N-type gold oxide/half transistor 2129, 2130 can be controlled by a read signal. In this design, a static random access memory cell 215 is transmitted through the sense amplifier 214, the latch circuit 217, the thin line metal structure 631 under the protective layer 5, the protective layer opening 531 in the protective layer 5, and the protective layer 5. The upper metal line or plane 83, the protective layer openings 532, 534 in the protective layer 5, and the thin line metal structures 632, 634 are connected to the internal circuits 22, 23, 24, as shown in Fig. 5B, Fig. 6B, Fig. 7B, Figure 7C and Figure 7D show. However, the pass circuit 216 of the 5G diagram or the latch circuit 2 of the 5H diagram does not provide a large drive capability. In order to drive an internal circuit 22, 23, 24' or a long distance transmission requiring a high load, the reverse bit (5) data outputted by the circuit 216 or the bit (5) output from the latch circuit 217 is transmitted to the internal circuit 22, 23, 24, an internal driver 212 mentioned above may be added at the output node of the circuit (as shown in the figure) or the output node of the flash lock circuit (as shown in FIG. 5J) to utilize the inside. The portion driver 212 amplifies the bit (10) data output by the reverse bit (10) data output by the circuit or the flash lock circuit 217. Referring to FIG. 5K, except that the internal circuit 21 receives signals from the internal circuit 24 (here, the -reverse or gate), instead of driving the internal circuit μ, the remaining circuit design is similar to that of the fifth drawing. The internal circuit 24 (the reverse or the middle) is a thin-line metal structure 634 under the protective layer 5, the protective layer opening 534 in the protective layer 5, the metal line on the protective layer 5 or the flat Φ 83, Protection in protective layer 5 1344686

Mega 06-015TWB layer opening 531' and thin line metal structure 631 under the protective layer 5, transmitting a signal or data sent by the wheel _ point w 到 to the input node 内部 of the internal circuit 21, The gate of the MOS transistor of the internal circuit 21, while the internal circuit 24 (here, a reverse or gate) also passes through the thin-line metal structure 634 under the protective layer 5, and the protection in the protective layer 5. The layer opening 534', the metal line or plane 上 on the protective layer 5, the protective layer opening 532' in the protective layer 5, and the thin line metal structures 632a', 632b under the protective layer 5, send the output node/point Wo The signal or data is transmitted to the input node Ui of the internal circuit 22 (here, a reverse or gate). Furthermore, the internal circuit 24 (here, the -reverse or gate) also passes through the thin line metal structure 634' under the protective layer 5, the protective layer opening 534' in the protective layer 5, the metal line on the protective layer 5 or The plane 83, the protective layer opening 532 in the protective layer 5, and the thin line metal structures 632a', 632C under the protective layer 5, transmit the signal or data sent by the output node Wg# to the internal circuit 23 (here One is the input node % of the gate. Wherein, the fine-line metal structures 634', 631' may be formed of a metal secret and a plane, and in this example, the thin-line metal structures 634, 631 are made of a conductive plug and a metal joint and a thin layer in the dielectric layer. The secret metal layer is formed, for example, in a stacking manner. In some integrated circuit technologies, the conductive plug is Tungsten plug η (4) or inlaid ^^(damascene copper) ^^ 21.22,23 ^ χ., ^

Ui, Vi receive the signal, and at the output node X. ', υ〇, % output the signal to the straight circuit. Correction (10) circuit 21 sister can sigh - 峨 rape batch (such as the 5L figure does not), - internal tristate buffer 213, (such as the 5M figure or other 42 1344686

MEGA 06-015TWB internal circuit, such as NOR gate, NAND gate, AND Sate, OR gate (ORR gate), operational amplifier {operational amplifier}, adder ( Adder), multiplexer, diplexer, multiplier, analog/digital converter, digital/analog converter, complementary metal oxide semiconductor, double a carrier complementary MOS or a bipolar circuit, and when the internal circuit 21 is an internal receiver 212', the internal circuit 21 is composed of at least a MOS transistor, and the MOS transistor Includes a P-type semi-transistor with a channel width/channel length ratio between 3 and 60 or between 5 and 2 或者 or a channel width/still length ratio between 1.5 and 30 or between 2.5 a -n-type MOS transistor between 1 〇, and φ current flowing through the metal line or plane 83 is between 500 microamps to 10 milliamps or between 700 microamperes and 2 milliamps Between; in addition, when the internal circuit 21 is the other internal circuit described above The second path 21 includes at least an N-type MOS semi-electric φ crystal having a channel width/channel length ratio between 0.1 and 5 or between 〇2 and 2 or a channel twist/channel length ratio between 〇 a p-type MOS transistor between 2 and 1 或 or between 〇* and 4, and the current flowing through the metal line or plane 83 is between 5 〇 microamperes to 2 milliamperes or Between micro-ampere to 1 milliamperes. In addition, the internal circuit 21 also includes a static, random access memory unit (SRAM (4)), __ access counter unit (M_, non-volatile (four) unit (nGn_v phase e (four)), flash Memory unit ^, can eliminate programmable read only memory single _PROM cell)

J 43 1344686

MEGA06-0I5TWB Read-only memory cell (ROM cell), magnetic random access memory ((4) coffee _ RAM 'MRAM) unit or sense amplifier (face eamplifier). The input node of the internal circuit 21 is typically the gate of a MOS transistor. Referring to the first ride, the 'internal receiver commit' can accept the -signal via the metal line or plane 83 on the protective layer 5 and from the output node X. 'Output—signal to other internal circuits, but does not output this signal to an external circuit. Referring to Figure 5M, the internal tri-state buffer is arbitrarily facing the layer 5 or the plane Μ 峨: and voicing the output node X. 'Output-signal to other internal circuits, but does not output this signal to an external circuit. In Figure 5L, the N-type MOS transistor should have a size between 1 $ and 30' and preferably between 2.5 and 10, while the p-type MOS transistor 2104 The size of the input node Xi is between 3 and 6 并 and is preferably between $ and 或 'in addition to the metal line or plane 83 above the protective layer 5 and the input internal receiver 212. The current system ranges from 5 〇〇 micro amps to 1 〇 milliamperes and is preferably in the range of from micro amps to 2 mA. In addition, the input node Xi of the internal receiver 212 can receive a signal output from the rounding node of the internal circuit via the metal line or plane 83 on the protective layer 5, but does not receive the signal. The signal output by the p circuit is as shown in the figure, the first map, the ninth graph, the seventh graph, and the seventh graph. In the 5Nth to 5thth diagrams, it is revealed that the output of the internal circuit 24 (logic gate) is written to the -wei body array-memory unit. Please also 1344686

MEGA 06-015TWB Referring to Figures 5K and 5N, the internal circuit 21 can be an internal three-state buffer 213'. The internal tristate buffer 213 has an amplification data and a power-on-control signal of the switch, and is outputted from a read circuit (not shown), and uses the control number «£« to control the internal tristate The buffer 213 is turned on or off. In addition, the one-bit (10) data can be transferred to the input node xi of the internal tri-state buffer 213 through the metal line or plane 83 on the aquifer layer 5, and when an enlarged inverted bit (6) data is When the -f source is light, the inverted bit of the A (four) dragon is output from the p-type gold oxide half-transistor 2110' to the inverted bit (8) line' and when an enlarged inverse bit (four) is the material is - When the ground reference voltage is applied, the 'inverted reverse bit (8) data is output from the N-type MOS transistor 21〇9' to the inverted bit (10) line. The output node χ〇, the output • the amplified inverse bit (product) data can be transmitted to the static random access memory via the row selection transistor 2122 controlled by a row selection (CS) signal and the 金 type MOS transistor 2119. Body unit 215. Please also refer to Figure 5 and Figure 5, the internal circuit 24 (here, a reverse or gate) is through a thin line metal structure, 4, a protective layer opening 534', above the protective layer 5 a metal line or plane 83, a protective layer opening 531', a thin line metal structure 631', and an internal tristate buffer 213 for transferring data to a static random access memory unit 215 in a memory array. . Referring to FIG. 50, the bit data rotated by the internal circuit 24 (here, a reverse or gate) is connected to the bit line of the SRAM cell array after passing through the circuit 216. Then, the static random access memory unit 215 is written by selecting the transistor through the row. Among them, the internal circuit 21 in the fifth diagram is a passing electricity 45 1344686

MEGA 06-015TWB circuit 216', and this through circuit 216, can be - a simple gold oxide semi-transistor, such as ^ 金 MOS transistor 2 丨 24', and by a write enable signal (write enable signal) control. In this design (please refer to both the SK diagram and the fifth diagram), a data output from the output node w〇 of the internal circuit 此 in this is an inverse or gate is written to - static random Access memory unit 215: from a thin line metal structure 634' up through the protective layer opening 534, through a metal line or plane 83 on the protective layer $, down through a protective layer opening, A fine line metal junction structure 631, a bit iL line 'connected to the SRAM cell array through the circuit plus '' is then written to the SRAM cell 215 through the row select transistor. • Refer to Figure 5P, which is similar to the first picture. The input bit line data can be temporarily stored or locked in the -lock circuit 2Π before being written to the static memory unit 215. . In addition, Ν-type MOS transistors 2129, 213 〇 are used as control for writing. In this design (please refer to both the sk map and the 5th ρ from the output node w of the internal circuit 24 (here, the -reverse or gate). The output of a data is written to a static random access by the following means. In the memory unit 215: starting from the thin-line metal structure 634, starting up, passing through a protective layer opening 534, passing through a metal line or plane 83 on the protective layer 5, passing through a protective layer opening, - The thin line metal structure 631, the flash lock circuit 217, the missing bit line, the bit line of the random access memory cell array, are written to the SRAM cell 215 through the row select transistor. 1344686

MEGA 06-015TWB However, the pass circuit 216 of Fig. 50, or the flash lock circuit of Fig. 5p, φ can not provide sufficient sensitivity to detect weak signals at the input node. In order to restore the weak data signal, it can be increased - the internal receiver commits 'at the input of the circuit 216' (as shown in Figure 5Q) or at the input of the flash lock circuit ( As shown in Figure 5R). Another important factor in the continuous-age road above the protective layer is to provide the reliability and caPacitanCe per unit 丨ength characteristics of the metal line or plane above the analog signal. A digital analog analog signal with low signal distortion. Please refer to the % map, which reveals the metal _ or plane 83 connection analog _ = analogy design. The circuit 2, 22, 23, 24 is an analog circuit or a mixed circuit (mixed-mode circuit), the signal transmitted by the metal line or the plane 83 is a digital analog analog signal, and the signals output/received by the internal circuits 21, 22, 23, 24 In addition to a digital analog analog signal, the design of the 5S picture is similar to that of Figure 5B. ♦ In Figure 5S, an output node γ of the internal circuit 21 is connected to the thin line metal structure 631 'and then goes through the protective layer. The protective layer opening 531 of 5 is connected to the metal line or plane 83 on the protective layer 5, and then connected to the fine line metal structure 632 (including 632a, 632b, 632c) through the protective layer openings 532, 534, 634 Finally, a fine line metal, 632 (including 632a, 632b, 632c), 634 is connected to an input node of internal circuits 22, 23, 24, Ui', Vi, Wi, 'which serves as the interior of the analog circuit Circuit calls 21, 22, 23, 24 series include -P type MOS semi-transistor, an N-type MOS semi-electric crystal 1344686

MEGA 06-015TWB body, a NOR gate, a NAND gate, an AND gate, an OR gate, a sense amplifier, Operational Amplifier, A/D converter, D/A Converter, pulse reshaping circuit, switching Capacitor filter (switched-capacit〇r filter), a resistor-and-resistor filter (RC filter) or other types of analog circuits, etc. For other relevant parts, please refer to Figure 5B, which will not be described in detail here. .

Referring to FIG. 5T, an example in which the internal circuit 21 in FIG. 5S is an operational amplifier 218 and the output node γ〇 is connected to the metal line or plane 83 on the protective layer 5 is disclosed. The calculator is designed according to a complementary metal oxide semiconductor (CMOS) technology. Please refer to the "CM0S Digka丨Circuit Techn〇1〇gy" issued by PrenMall in 1987. The differential analog signal is input to a differential circuit (diff (10) tiai _19 input node Yi+ formed by two N-type MOS transistors 2125, 2127 and two P-type MOS transistors, 2128 In Yi_, the input nodes Yi+ and Yi are respectively connected to the gate of the P-type MOS transistor 2126 and the p-type MOS transistor. The differential circuit is applied to the N-type MOS transistor. The drain of the pole and the p-type MOS transistor 2128 is connected to the gate of the N-type MOS transistor 2135 and the capacitor (the first electrode of the eapato 33). An output node γ 〇 is connected to the capacitor The second electrode of 2133, the 没 of the Ν-type MOS transistor and the 汲 of the p-type MOS transistor 2136. Therefore, the signal at the input (four) point can be 5 48

MEGA 06-015TWB is controlled by the degree of opening of the N-type MOS transistor, and the n-type MOS transistor 2135 is also controlled by the output of the differential circuit. The power node P of the differential circuit 219 is connected to the drain of the P-type MOS transistor, wherein the differential circuit is a P-type MOS transistor and a MOSFET-type MOS transistor 2128. The source is connected to the power supply node p. In addition, the voltage level of the p-type MOS transistor is controlled by the resistor 2134. Further, the signal output from the differential circuit 219 can be amplified by the capacitor 2 (3). The capacitor 2133 is often used in the - analog circuit of the analog circuit and is usually a gold oxide half capacitor _ _s. Ah (4) or on the eve of the evening, on the eve of the day, the day of the night, the stone 电 电 & & 〇 _ _ _ _ _ _ _ 〇 〇 〇 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The two electrodes of the capacitor 2133, and the polycrystalline spine to the polycrystalline silicon capacitor, use a first polysilicon (P〇丨y silicon) and a second polysilicon as the two electrodes of the capacitor 2133. Used in analog-like circuits, and usually in the impurity-doped diffilsi〇n area, such as n-well, p-well, N-diffusion, P+-diffusion, and/or impurity-doped polycrystals Shi Xi (4) is a silicon) to form. Poor Embodiment: The complete structure of the present invention. The technique of opening/forming a thick metal conductor above the protective layer (or a metal line or plane above the protective layer) can provide additional wafers. Benefits: The material of the thick metal conductor above the protective layer (or the metal line or plane above the layer) consists of gold, copper, silver, palladium, rhodium, enamel or nickel, which can be formed not only as a conductor body but also as a conductor body. Formed as other connections

MEGA 06-015TWB Touch structure. Use a variety of different types of contact structures, such as solder bumps, solder pads, solder balls (s〇Wer baU), gold bumps (Au ^^^, gold connections) Pad (four) shirt ^ 塾 塾 ^ 加布绍 pads (eight) ping 1 or wire bonding pad (wafer can easily use different methods to join the external circuit. In Figure 5B, 5K, In the 5S diagram, 7B diagram, the diagram and the 7D diagram, the metal line or plane above the protection layer is used to transmit the signal output or input from the internal circuit, and the internal circuit is not connected to the external circuit. The only chip must be Connected to an external circuit and transmitted to an external circuit. Next, please refer to the 8th to 8th, 9th to 9D, and 10th to 1st 1th drawings. A complete structure, and as a third embodiment of the present invention. Figures 8 through 8F, 9 through 9D, and ι to 101 show the internal circuits. How the signal passes through the metal line or plane above the protective layer and the thin line metal junction under the protective layer The signal transmitted to the external circuit or the external circuit is transmitted to the internal circuit through the metal line or plane above the protective layer and the thin line metal structure under the protective layer. Figure 8 to Figure 8F, Figure 9 to Figure 9D and 10th to 1st are respectively a circuit structure, a top view and a cross-sectional view of the present embodiment, which are an internal wafer design in which an internal circuit is connected to an external circuit to reveal that the present invention uses a fine-line metal structure and The complete structure of the metal above the protective layer. In addition, the internal circuits 2〇 (including 21, 22, 23, 24) described in Figures 5 to 5, 6 and 7 to 7D also apply. Internal circuit 2〇 in this embodiment (including 21, 22, 1344686

MEGA06-015TWB 23'24)〇 In the present embodiment, the signal of the internal structure 200 is transmitted to an external circuit (not shown) through an off-chip structure 400, as shown in FIG. 8B. The signal of the external circuit (not shown) is transmitted to the internal structure 200 by the 〇fif-chip structure 4' as shown in FIG. 8C. The metal line or plane 83r above the protective layer 5 can be used as a reconfiguration line for the (input/output) pads of the fine-line metal structure (for example, the metal pads 639 in Figure 10B), in other words, the thin lines. The (input/output) pads of the metal structure are repositioned to a different location of the pads (eg, contact pads 831〇 in Figure 1) using a reconfigured line, and then a wire placed on the pads is utilized Or the bump is connected to the external circuit, so the position of the pad is different from the (input/output) pad position of the thin-line metal structure, for example, in FIG. 10B, by a top perspective view. In view, the position of the contact pads 831〇 is different from the position of the metal pads 6390. In addition, the thickness of the reconfigured lines for forming the contact pads 831 is greater than 15 microns. Alternatively, the metal lines on the protective layer 5 or the surface 8 can be formed simultaneously with the metal lines or planes 83 on the protective layer 5. The current flowing through the metal line or plane 83 is then between 50 microamps and 1 milliamperes. The contact pads 8310 exposed by the polymer openings 9939 located in one of the top polymer layers 99 can be connected to an external circuit using wire bonding or other bonding methods as described in the subsequent series of Figure 15. In addition, for flip chip assembly (flip_chip assemb丨, Tape Automated Bonding (TAB) or other as follows 15

CD 51 1344686

The bonding method described in the series of MEGA 06-015TWB, which can selectively form a contact structure 89 on the contact pad 831 and the polymeric layer opening "39, as to the method of forming the contact structure 及其 and its detailed description It will also be explained in the subsequent series of Figure 15. The contact pads 831A can be connected to the wafer external circuit 40. Accordingly, in conjunction with the above description, the wafer termination structure includes a wafer-external circuit 40, a metal interface, a contact structure 89 (selective), and a reconfiguration line 83r (selective) over the protective layer. The wafer external circuit 40 includes a wafer external/input/input/0) circuit as the wafer external circuit 42, and at least one electrostatic discharge (ESD) protection circuit as the wafer external circuit 43, for example As shown in Fig. 8D, the wafer external circuit 43 includes two scale electric discharge protection circuits. In the above, the external input/output circuit of the wafer can be a chip external driver, a chip external receiver or a wafer external buffer (for example, a wafer tristate buffer), and the related content is respectively 11A, 11B @, lie diagram and UE UE description; in addition, the ESD protection circuit may be a structure composed of two reverse bias diodes frewse_biased _ diode) 433 b 4332 'such as the nF The figure shows. The size of the MOS semi-transistor in the external input/output circuit of the wafer versus the internal circuit _ MOS crystal size will be described in the subsequent series of Fig. 15. 8A, 9A, and ι〇Α are the design structures of the conventional wafer, as shown in the figure, all the circuits (including the internal circuit 2, 22, 23, 24 and the external circuit 40) pass through the thin line. The road metal structure is called (10) (one), lc) 6341 63SM are connected to each other, but there is no use protection 52 1344686

MEGA 06-015TWB above the layer of Jinlin Road or plane to connect the financial circuit, f know only in

When the tin is in the wrong position, the position of the metal wire on the top of the secret layer is the position of the external connection pad. _Please also refer to Figure 9B and Figure 1B, which are schematic top and cross-sectional views of the circuit design of the first case. The internal circuit is connected to the contact pad 831 or the contact structure through the path described below, and the signal generated by the internal circuit 21 is transmitted to the external circuit: the internal circuit 21 first passes through a thin metal. The structure 631 'passes up—the protective layer 53 continues to pass through a single layer (such as the patterned metal layer in the urn diagram) or a plurality of metal lines or flat (four), and then stays through the protective layer opening 539, and - the thin line The metal structure 639 is connected to the input node of the external circuit 42 of the wafer, and the thin circuit metal structure 69 is used to connect the input (four) point of the external circuit 42 to the "external circuit" as the electrostatic discharge protection circuit.

The signal contact of 43 is then passed up through a thin line metal structure 639 and a protective layer opening, and finally through a metal line or plane 83r as a reconfiguration line above the protective layer to the contact pad 83ι or contact structure. 89. In addition, the connection between the external circuit 42 and the "outer circuit" can also be achieved by a metal line or plane above the layer, that is, the metal line or the plane above the protective layer. Replace the fine line metal structure 69.

. Referring to the figure ioc, it is revealed that the metal line or plane 83 has two patterned metal layers 831, 832 as shown in Fig. 7C. In addition, the 10th figure #10E is added between the protective layer 5 and the bottommost end of the patterned metal layer 831 53 5 1344686

MEGA 06-0I5TWB A polymer layer 95 is similar to the 10B® and 1GC charts, respectively. Referring to Figure 10D, the original metal pad 6390 can be reconfigured to the contact pad 8310 on the protective layer 5 using a metal line or plane as a reconfigured line. Reconfiguring input/output pads using reconfiguration lines is especially useful in stacked packaged flash memory, dynamic random access memory or SRAM chips. In addition, the input/output pads of a DRAM chip are typically placed along the centerline of the wafer, so they cannot be used in stacked packages. However, the use of metal lines or planes as reconfigured lines to reconfigure the central pads to the periphery of the wafer allows the wafer to be used in wire bonding in packages such as stacked packages. Φ Ming is also shown in the 1st and 1GG drawings, which are specific examples of the contact bonding 8310 having a wire bonding. In the figure and the figure, a static access control unit, a "flash" (four) unit or a secret random access memory unit is connected to the input node Xi in the internal circuit 2, and the internal electric circuit 21 and the method of connecting the internal circuit 2! to the memory unit have been described in the figures to 5J, respectively. First, as shown in Figure 1, F, a static random access memory cell, a flash (four) cell, or a -dynamic random access memory (four) cell is connected to an external circuit via: (1) a sense amplifier; (2) internal Buffer, pass circuit, Q lock circuit, pass circuit and internal driver or flash lock circuit and internal driver, (3) fine line metal structure 6; (4) fine line metal structure 638; (7) via thin line metal structure 6391, connected to a chip is connected to an input node of the external circuit 42; (6)

54 (U mega 06-0 i5twb The output node of the external circuit 42 is connected to the fine-wire metal structure 6391, and the H-line metal structure 69 is connected to the external circuit of the chip as an electrostatic discharge protection circuit 43 '(7)-protection Layer opening 539; (8) passes through a metal line or plane 83r as a reconfigured line; (9) passes through a contact interface 8310' and (1〇) exposed by a polymer layer opening 9939 through a contact potential 83丨〇 The upper wire of the wire is connected to the two circuits. Referring again, please refer to the 1GG display, the static random access memory unit, the flash memory unit or the secret access unit to the external circuit. It is via: (1) sense amplifier; (2) internal tristate buffer, pass circuit, flash lock circuit, drive line detail drive (10) circuit and internal drive; (3) fine line metal structure 631; (4) upward After the protective layer is opened 53; (3) the polymer layer is opened π coffee; the cased metal layer 831; (7) is passed down through the polymer layer opening 9539 '(8) protective layer opening 539'; (9) through the fine line metal structure 639, connected To a chip to external circuit 4 An input node of 2; (10) a fine-wire metal structure 639 connected via a turn-out node of the wafer-external circuit, and a die-attached external circuit 43 as an electrostatic discharge protection circuit through a thin-line metal structure; (1) a protective layer opening 539; (12) polymer layer opening 9539; (13) through a metal line or plane 83Γ as a reconfigured line: (14) through a contact pad 8310 exposed by a polymer layer opening 9939; and (15 Through a pair of wire conductors on the contact pad 8310, connected to an external circuit. Further, a polymer layer may be formed below or above the metal line or plane 83r as a reconfiguration line, for example, in the 10G, metal Line or flat version 1344686

A polymer layer 95' is formed under the MEGA 06-015TWB and a top layer of the ruthenium layer 99 is formed on the metal line or the plane electrode. Another 'metal line or flat φ as a reconfigured line can be formed from a gold layer with a thickness between 1.5 microns and 3G microns (preferably between 2 microns and 1 〇 micro). (formed by electricity or electroless plating), or formed by a copper layer having a thickness between 2 microns and 100 microns (preferably between 3 microns and 2 microns) (formed by electroplating) ). Wherein, the top of the copper layer has a nickel layer (having a thickness between 0.5 micrometers and 5 micrometers) and a gold, a ruthenium or a shovel (_Fu Li # metal layer (the thickness of which is between micrometers and 5 micrometers) One wire bonding is performed on the surface of the gold, cadmium or germanium layer on the contact pad 8310. When the signal is transmitted to an external circuit or component, some of the external circuit of the chip needs to be removed ()) ^ driving an external circuit requiring a large current load a circuit or component; (2) detecting a noisy signal from an external circuit or component; and (3) protecting the internal circuit from damage caused by a surge signal from an external circuit or component. Please refer to FIG. 11A, FIG. 11B and FIG. 11E and FIG. 11G, respectively, which are respectively exposed. The external driver 421, the external driver 422 and the internal tristate buffer are used as the external circuit of the wafer. An example of 42. In Figure 11A, it is a two-stage cascade of one of the externally mounted drivers 42 for driving an external circuit (package, other wafer or component, etc.) that requires a heavy load. Etc.), the wafer is connected to the external driver 42 1 is designed to generate large currents. Alternatively, the external driver of the wafer can be formed using a complementary metal-oxide-semiconductor series driver. This series driver can include a number of inverters. The output of a chip is connected to the external driver. Current is with level 56 1344686

The number of MEGA 06-015TWB and the size of the transistor used in the external driver of each stage of the wafer (W/L, the ratio of the channel diameter to the length of the channel, more precisely refers to the gold oxide semi-transistor The effective channel width is proportional to the ratio of the effective channel length). In FIG. 11A, the first stage 421 of the external driver 421 is an inverter formed by an N-type MOS transistor 4201 and a P-type MOS transistor 42 〇 2, and N. The size of the MOS semi-transistor 42〇1 and the gt; type MOS transistor 42〇2 is larger than the size of the internal circuit (as in the first embodiment, the second embodiment, the third embodiment φ, and the subsequent The dimensions of the internal circuits 21, 22, 23, 24 of the four embodiments). In addition, the first stage 421' of the wafer-external driver 421 receives a signal from the internal circuitry 21, 22, 23, 24 at the input node F. In addition, the second stage 421 of the wafer external driver 421 is also an inverter formed by a larger size N-type MOS transistor 4203 and a P-type MOS transistor 4204. The wafer external driver 421 provides a drive current 'this drive current range is between 5 milliamperes (mA) to $amper's and is between 10 milliamps and milliamperes. The range between the two is preferred. In order to achieve these target output drive currents, the second stage 421" (in other words, the output stage of the wafer-external driver 421) has a size of between 2 〇 and 20,000. The range between 3 〇 and 300 is preferred. In addition, since the driving current of a p-type MOS transistor is about half of the driving current of an N-type MOS transistor, the second stage 42 Γ (In other words, that is, the output stage of the external driver 421 of the wafer), the size of the p^ type MOS transistor 4204 is in the range of 40 to 40,000, and 5 1344686

MEGA 06-015TWB is preferably in the range of between 60 and 600. However, for a power chip, or a power management chip, the drive current must be larger, such as 10 amps or 20 amps, and the drive current is between 5 mA and 50 amps. The range between amperes and preferred ranges from 5 (8) milliamps to 5 amperes. Therefore, the size of a N-type MOS transistor of a power chip or a power management chip is between 2, 〇〇〇 to 2 〇〇, and the range between 〇〇〇 is The range between 2,000 and 20,000 is preferred, while the size of the p-type + MOS transistor is between 4,000 and 400,000, and ranges from 4, face to 40, between faces. In addition, please refer to the HD picture, the external driver 421 can be connected in parallel with the plurality of inverting φ devices in the second stage 421", so that the driver of the second stage 421" can provide the size (channel The width of the channel divided by the ratio of the length of the channel) is larger for the N-type MOS transistor and the p-type MOS transistor, so the external driver 421 can provide a larger drive current, wherein the driver at the second stage 421 In the middle, a plurality of inverter N-type oxy-halide transistors are connected to the gate of the p-type galvanic semi-transistor, and a plurality of inverters of the N-type oxy-oxide semi-transistor and the P-type gold The neutrons of the oxygen semiconductor are connected. 8E, 9C, and 10H are respectively a circuit diagram, a top view, and a cross-sectional view of the circuit design of the 11D drawing of the embodiment. Referring to FIG. 11G, the external driver 421 can also form a cascade driver by serially connecting a plurality of inverters after the first stage 421', and through the step-by-step size reversal. The phase device is used to make the crystal_chip connected to the external driver 421 to amplify the signal step by step, wherein the inverter of the latter stage is 1^ type gold oxygen 58 1344686

MEGA 06-015TWB The size of the semi-transistor and P-type MOS transistor (channel width divided by channel length ratio φ) is greater than the N-type MOS transistor and p-type gold of the inverter of the previous stage. The size of the oxygen semi-transistor (the ratio of the channel width divided by the length of the channel) is preferably a natural index (e, natural exponem), and the connection mode is the N-type gold oxide half of the inverter of the previous stage. The gate of the transistor and the p-type MOS transistor is connected to the gate of the N-type MOS transistor and the p-type MOS transistor of the inverter of the latter stage. The 8F, 9D, and 1st drawings are respectively a circuit schematic, a top view, and a plan view of the circuit design of the embodiment φ applied to the embodiment. Referring to FIG. 11B, it is a two-stage series connected to the external receiver 422. The external receiver 422 can receive a signal from an external circuit (not shown) and output the signal to the internal circuit. Input node. The first stage 422' of the wafer external receiver 422 (near the external circuit) is an inverter formed by an N-type MOS transistor 4205 and a P-type MOS transistor 4206, and this N The MOS semi-transistor 4205 and the P-type MOS transistor 42〇6 are designed to detect the size of the external signal containing the miscellaneous signal. The first stage 422' of the chip-out receiver 422 receives a signal from an external circuit or component containing noise at point E (which may be a signal from another chip). The second stage 422" of the chip-out receiver 422 is also an inverter' which is formed by a larger size N-type oxy-oxygen transistor 4207 and a P-type MOS transistor 4208. The second stage 422" of the 422 is used to restore the integrity of the external signals containing noise to the internal circuitry. • See Figure uc, which is a wafer tristate buffer as a wafer. 59 1344686

The NiEGA06-015TWB is connected to the external drive nm, and the m-up buffer can output the signal to a bus φ bus (bus), and then to multiple logic gates. The wafer tristate buffer in Figure 11C can be considered a gated inverter. When the enabling signal (enabling ton (four) 仏 is high level (calling low level), the 'tri-state buffer' allows the signal from the internal circuit to be sent to the external circuit, and when the signal 仏 is at the low level, the internal circuit Then, it is disconnected from the external circuit. In this case, the wafer tristate buffer 疋 is used to drive the external data bus. The other three-state buffers are used as the N-type oxy-half of the wafer-external driver. The range of transistor 4209 size and P-type MOS transistor 4210 size is described in Figure 1A and will be further illustrated in Figure 15. ^ See Figure HE, which is a The chip tristate buffer is used as an example of a chip external receiver. When the enable signal 仏 is high level low level, the chip tristate buffer transfers signals from the external circuit to the internal circuit. When the signal £« is at a low level, the internal circuit is disconnected from the external circuit. In this case, the wafer tristate buffer receives the signal from the external data bus at node E. The range of the N-type MOS transistor 4209 size and the p-type MOS transistor 4210 size of the wafer tri-state buffer as the wafer-terminated receiver is described in FIG. 11B and will be in the 15th series. Further explanation. The above example is for a complementary metal oxide semiconductor level signal (CM〇s level signal). If the external signal is a transistor-transistor logic (TTL) level, then a CMOS/TTL buffer is required. 60 1344686

MEGA 06-015TWB 'If the external signal is for the emitter turn logic (emitter, call ECL), _ _ CMOS / ECL interface buffer. In the internal circuit and the chip two states An inverter of one or more poles may be added between the buffers. 凊 Referring to FIG. 11F, it is further disclosed that a wafer-terminated receiver 422 has an external acceptance as an electrostatic discharge protection circuit. In this example, the wafer external circuit 43 as the electrostatic discharge protection circuit includes two reverse-biased dipoles 433. The bottom-end reverse biased body 2131 can be Reverse bias is applied between the external input voltage (the power at point E) and the ground reference voltage ,, and the reverse anti-dust diode at the top is reverse biased between the external input voltage and the power supply I. When the external input from the external circuit is increased to exceed the supply voltage, the current will be dumped through the top reverse bias body 4332, and when the external input voltage is lower than the ground reference voltage Vss, the electricity will be Discharged_Bottom_Reverse Touch Dipole 4331. The input transistor in the internal circuit will be transferred between the power supply dragon and the ground reference voltage Vss, and the semiconductor components in the external receiver like 2 or the internal circuit 2 will be protected from the semiconductor components. In the first embodiment of the present invention, an external power supply is input to the internal circuit via a voltage regulator or transformer 41 (including 21, ^, force). 2 sentences, and in the present embodiment, 'the external power supply is directly input to the internal circuit Μ including 21, 22, 23, 24), but in this case, it is necessary to utilize an electrostatic discharge protection 61 1344686

MEGA 06-015TWB circuit 44 prevents voltage or current surges generated by externally supplied power. φ First, please refer to the UA diagram, which is a related art of the present embodiment. In Fig. 12A, 'an external voltage vdd is input through a protective layer opening 549, and then distributed to the inside through fine-line metal structures 618, 6111, 6121 (including 6121a, 6121b, 6121c) and 6141 located under the protective layer 5. A power supply node Tp, Up, Vp, Wp of the circuits 21, 22, 23, 24. The power supply node Dp of an ESD protection circuit 44 is connected to the thin line metal structure 618 via a thin line metal structure 6491. Fig. 13A and Fig. 14A are schematic plan and cross-sectional views corresponding to Fig. 12A. 2B to 12C, 13B to 13C, and FIG. 4 to 14D are respectively a schematic structural view, a top view, and a cross-sectional view of the circuit according to the fourth embodiment of the present invention. As shown, an ESD protection circuit 44 is connected in parallel with the internal circuits 21, 22, 23, 24 through a metal line or plane 81 on the protective layer 5 and/or a metal line or plane 82, wherein the internal circuit 2, 22, 23, 24 are, for example, a NOR gate, a NAND gate, an AND gate, or a gate (OR gate), an operational amplifier (〇perati〇nal amplifier), addition Adder, multiplexer (ipiexer), duplexer (djpiexer), multiplier, analog/digital converter (A/D converter), digital/analog converter (D/AConverter), Complementary metal oxide semiconductor, doubly-supported MOS, bipolar circuit, SRAM cell, DRAM cdl, Non-volatile record 62 1344686

MEGA 06-015TWB non-volatilememoiy cell, flash memory single s (flash mem〇ry 馨 cell), can eliminate programmable read-only memory unit (EpR〇M cd〇, read-only memory unit (ROM cell), magnetic random access memory (magnetic unit or sense amplifier). The internal circuit 2i, 22, 23, 24 is at least a channel width / channel length ratio between αι to 5 Or a 金-type MOS transistor _0S between 〇2 and 2, or a p-type channel/channel length ratio between 0.2 and 10 or between 〇4 and 4. The current formed by the PM 〇S transistor and the current flowing through the metal line or plane 8 82 is, for example, between 50 filaments and 2 milliamps or between ι microamperes. Between 1 milliamperes, the metal lines or planes 81, 82 are formed on the metal lines or planes 81, 82 by, for example, a wire, and are electrically connected to an external power source. Further, the electrostatic discharge protection circuit 44 is one domain. The reverse-biased diode 4333' is shown in Figure 12E, which has a power contact and Grounding contact. In addition, the first _ woman wipes shown in the first, second and third series can also add an ESD protection circuit and connect the regulator or transformer 41 in parallel. Internal circuits 21, 22, 23, 24. In Figures 12B and 13B, the ESD protection circuit 44 and the internal circuit 〇 (including 21 22, 23, 24) each include a - power node (p〇wer n〇) De) and a ground node, wherein an external voltage input node Ep is via a metal line on the protective layer 5 or a protective layer opening 5 of the protective layer 5 of the protective layer 5, 5, 5, and 5! 4 and the fine-line metal structure under the protective layer 5, including Xian, (10),

63 (D 1344686

MEGA 06-015TWB 612c), 614, connected to a power supply node of the internal circuit 2, 22, 23, 24 ^ 鲁 node node) Tp, Up, Vp, Wp, and then the external voltage vdd is assigned to the internal circuit 21, 22, 23, 24 power nodes Tp, Up, Vp, Wp. In addition, the node Qiu is connected to a power supply node Dp of the "Wei discharge protection circuit 44" via a metal line or plane 81 on the protective layer 5, a protective layer opening 549 of the protective layer 5, and a fine metal structure under the protective layer 5. Fig. 14B is a schematic cross-sectional view corresponding to Fig. 12B. In Fig. 14B, the patterned metal layer 811 as a metal line or plane 81 includes an adhesion/barrier/seed layer 8111 and a thick metal layer 8112. In addition to revealing the connection of the external voltage view as shown in Fig. 12B, Fig. 12C also discloses the connection of a ground reference voltage Vss. In FIGS. 12C and 13C, the node Eg of the ground reference voltage Vss input passes through the metal line or plane 82 on the protective layer 5, the protective layer openings 521, 522, 524 of the protective layer 5, and the thin lines under the protective layer 5. The land metal structures 621, 622 (including • 622a, 622b, 622 〇), 624 are connected to a ground node Ts, Us, VS, Ws of the internal circuits 21, 22, 23, 24. Further, the node Eg is also connected to a ground node Dg of the electrostatic discharge protection circuit 44 via the metal 82 on the protective layer 5, the protective layer opening 549' of the protective layer 5, and the fine line metal structure 649' under the protective layer $. Fig. 14C is a schematic cross-sectional view corresponding to Fig. 12C. Figure 14c discloses that there are two patterned metal layers above the protective layer, wherein the patterned metal layer 821 is used for the ground reference voltage Vss connection, and the patterned metal layer is smashed, and is used in electricity.

64 (D 1344686

MEGA 06-015TWB source Vdd is connected. The patterned metal layer 821 includes an adhesion/barrier/seed layer 82ΐ and a thick metal layer 8212, while the patterned metal layer 812 includes an adhesion/barrier/seed layer S121 and a thick metal layer. Item (10) is similar to Figure 14B except that a polymer layer 95 is formed between the protection of J and the bottommost end of the patterned metal layer 811 as a metal line or plane 81. δ month is shown in Fig. 12D, which is similar to Fig. 12C. The difference is that the 12Cth view only has the -electrostatic discharge protection circuit 44' and the 12th figure has two electrostatic discharge protection circuits 44, 45, wherein the electrostatic discharge The protection circuit 45 is, for example, a reverse biased diode. In FIG. 12D, the 'electrostatic discharge protection circuits 44, 45 and the internal circuit 2' (including 2, 22, 23, 24) each include a power supply node and a ground node, and an external voltage I Vdd is via the protective layer 5. The metal lines or planes 81, the protective layer openings 511, 512, 514 of the protective layer 5 and the thin line metal structures 611, 612a, 612b, 612e, 614 ' under the protective layer 5 are input to the internal circuits 21, 22, 23, 24 A power supply node Tp, Up, Vp, Wp' further distributes the external voltage Vdd to the power supply nodes TP, Up, Vp, Wp of the internal circuit 2, 22, 23, 24. In addition, the external voltage vdd is also input to the electrostatic discharge protection via the metal line or plane 8 on the δ layer 5, the protective layer openings 549 and 559 of the protective layer 5, and the fine line metal structures 649 and 659 under the protective layer 5. A power supply node Dp, Dp of the circuits 44, 45. In addition, a ground reference voltage Vss is via a metal line or plane 82 on the protective layer 5, protective layer openings 521, 522, 524 of the protective layer 5, and fine-line metal structures under the protective layer 5, 622a, 622b, 622c, 624 are input to a ground node of the internal circuits 21, 22, 23, and 24.

65 (D 1344686

MEGA 06-015TWB

Ts, Us, Vs, Ws. In addition, the ground reference voltage Vss is also connected to the electrostatic discharge protection circuit via the metal occupant 82 on the protective layer 5, the protective layer openings 549 of the protective layer 5, 559', and the thin-line metal structures 649', 659' under the protective layer 5. A ground node Dg, Dg' of 44, 45. The other related content of this embodiment is the same as that of the first embodiment, the second embodiment, and the third embodiment, and will be in the following series of 15th, 16th, 3rd, and 18th series. This is described in further detail in the series of Figure 19. Further, the reconfiguration line described in the third embodiment can also be applied to the first embodiment and the fourth embodiment of the present invention, that is, in the first embodiment and the fourth embodiment, for accepting the outside The contact pads of the voltage Vdd or the ground reference voltage Vss (for example, the contact pads 8110, 8120 in FIGS. 3B to 3D, and the contact pads 811, 812 in the 14B to 14D) are also The re-configuration line can be used to relocate the contact pads to a different location, such that the contact pads at different locations and the metal pads of the thin-line metal structure (eg, metal pads in Figures 3B through 3D) • 6190 6,290, the metal pads 64%, 6490, in the 14B to 14D are different in position, and then connected to the external circuit by a wire or bump on the contact pads located at the different positions.

In all of the embodiments (first embodiment, second embodiment, third embodiment, and fourth embodiment) of the present invention, the main feature of the over-passivation structure is that a thick patterned metal layer (thickness between 2 microns and 200 microns) and thick (DI-minute j 1344686

MEGA 06-015TWB Dielectric layer (thickness from 2 microns to 3 microns). The 15th and 14th series respectively disclose an emb〇ssing process and a double embossing process, which can be used to make a pattern above the hood of the hair duck. Metal layer and dielectric layer. In both processes (figure 15 and series 16), the polymer material is used (p〇lymer materi continues as a dielectric layer and is formed on each-patterned metal layer, each patterning Between the metal layers and/or under the per-patterned metal layer. In addition, the '15th series and the 16th series are based on the 10E figure in the third embodiment, and the invention is illustrated by way of example. All of the methods for forming the structure above the 4 layers are formed. In other words, the method described below can be applied to all the embodiments of the present invention with the relevant description. φ The process for forming the structure above the protective layer is in the integrated circuit wafer (IC) Wafer) begins after the end of the process. Please refer to the figure, which reveals a starting material (starting materiai) as the structure above the protective layer. As shown in the figure, the process of forming the structure above the protective layer begins. A conventional semiconductor manufacturing factory (IC fab) manufactures an integrated circuit wafer 10 of Lucheng. The wafer 10 includes: (1) a substrate 1 The substrate 1 is usually a silicon substrate. This Shi Xi base can An intrinsic (intrinsic#, a p-type slate base or an n-type slate base. For high-performance wafers, use 矽锗(SiGe) or insulating layer over 矽iSilieon_On-Insulat〇r ' SOI a substrate, wherein the ruthenium substrate comprises an epitaxial _ on the surface of the ruthenium substrate, and the ruthenium substrate on the other insulation layer comprises

(D 67 1344686

MEGA06-015TWB

An insulating layer (preferably yttrium oxide) is on one of the substrates, and a tantalum or tantalum layer is formed on the insulating layer. (2) Device layer 2 The device layer 2 usually includes at least one semiconductor device, and the device layer 2 is in the surface of the substrate 1 and/or on the surface. The semiconductor component may be a MOS transistor 2, such as an NMOS transistor 'n-channel MOS transistor or a P-type MOS transistor PMOS transistor. P-channel MOS transistor), and the MOS transistor 2' includes a source 201, a drain 202 and a gate 203, and the gate 203 is usually a poly silicon or a polycrystalline metal. Tungsten (rungsten), tungsten silicide, titanium silicide, cobalt silicide or a salicide gate. In addition, the semiconductor component may also be a bipolar transistor, a diffused metal oxide semiconductor (Diffiised MOS, DM0S), a laterally diffused metal oxide semiconductor # (Lateral Diffbsed MOS' LDM0S), a charge coupled component (Charged -Coupled Device 'CCD), complementary metal oxide semiconductor (CM〇s) sensing element, photo-sensitive diode, resistive element (formed by a polysilicon layer or diffusion region in a germanium substrate). Various circuits can be formed by using these semiconductor elements, such as a complementary metal oxide semiconductor (CMOS) circuit, an N-type MOS circuit, a p-type MOS circuit, and a bi-carrier complementary metal oxide semiconductor (BiCM〇s). Cycling, Complementary Metal Oxide Semiconductor Sensor Circuit, Diffused Metal Oxide Semiconductor

68 1344686

MEGA 06-015TWB body power supply circuit, laterally diffused metal oxide semiconductor circuit, etc. In addition, component layer 2 also includes internal circuit 20 (including 2, 22, 23, 24). In all embodiments, voltage regulator or transformer 41 In the first embodiment, the wafer external circuit 4 (including 42, 43) is in the third embodiment, and the electrostatic discharge protection circuit 44 is in the fourth embodiment. (3) Fine-line scheme 6 This fine line structure includes a plurality of fine-line metal layers (f|ne_iine metal layer) 60, a plurality of fine-line dielectric layers (fine_nne dielectric layers) 30, and a complex number φ in thin lines. The opening 30 of the dielectric layer 30 has a fme_iine via plug 60'. The other 'fine line metal structure 63 includes a thin line metal layer 60 and a conductive plug 60, and the thin line metal structure 63 structure includes in the present invention: (1) fine line metal structures 611, 612 (including 612a, 612b, and 612c) ), 614, 619, 619, repair 62 622 (including 622a, 622b, and 622c), 624, 629 in the first embodiment; (2) fine-line metal structures 631, 632 (including 632a, 632b, and 632c), 634 in the second embodiment; (3) fine line metal structure 63 632 (including 632a, 632b and 632c), φ 634, 639, 639' in the third embodiment; (4) fine line metal structure 61 612 ( 612a, 612b, and 612c), 614, 649, 659, 62, 622 (including 622a, 622b, and 622c), 624, 649', and 659' are included in the fourth embodiment. The fine wiring metal layer 60 may be an aluminum layer or a copper layer, or more specifically, may be a layer formed by a Tibetan bond or a copper layer formed in an inlaid manner. Therefore, the fine-line metal layer 60 may be: (1) all of the fine-line metal layers 60 are aluminum layers; (2) #all of the fine-line metal layers 60 are copper layers; (3) the bottom layer of fine-line metal layers 60 is i

The MEGA06-015TWB layer is the thin layer metal layer 60 of the page layer is a copper layer; or (4) the fine line metal layer 60 of the bottom layer is a steel layer, and the fine line metal layer 60 of the top layer is an aluminum layer. In addition, each thin-line metal layer 60 has a thickness of between 微米. 5 micrometers (ym) and 2 micrometers, and a thickness of between 0.2 micrometers and 1 micrometer is preferred. If layer 60 is a line, its lateral design standard (width) is between 20 nanometers and 15 micrometers, and preferably between 2 nanometers and 2 micrometers. In the above, the aluminum layer is usually formed by physical vapor deposition (PhysicalVap〇r

Deposition, pvd) is formed, for example, by means of sprtering, followed by deposition of a thickness between 0.1 micrometers and 4 micrometers (preferably between 0.3 micrometers and 2 micrometers). The photoresist layer is patterned by the photoresist layer, and then the aluminum layer is subjected to a wet etching or a dry etching. Preferably, the dry plasma is etched (usually containing fluorine). Plasma). In addition, an adhesion/barrier layer may be selectively formed under the aluminum layer, wherein the adhesion/barrier layer may be a Qin, a tungsten alloy, a titanium nitride or the like. A composite layer; and an anti-reflective layer (for example, titanium nitride) may be selectively formed on the aluminum layer. In addition, the 'opening 30 can be selectively filled with chemical vapor deposition (the 丨1叩〇(;叩〇叩〇11, CVD) tungsten metal, followed by chemical mechanical polishing (chemical mechanical polish) , CMP) grinds the tungsten metal layer to form the metal plug 60. In the above, the copper layer is usually formed by means of electroplating and damascene process, which is described as follows: (1) deposition one Copper diffusion barrier (eg 1344686)

MEGA 06-015TWB Nitrogen oxide layer or nitride layer with a thickness between 0.05 μm and 0.25 μm); _ (2) Using plasma enhanced CVD (PECVD), spin coating (spin) -on coating) or high-density plasma chemical vapor deposition (HDPCVD) to deposit a thin-line dielectric layer 3〇 with a thickness between 〇1 μm and 2.5 μm. The electrical layer is preferably between 0.3 microns and 1.5 microns thick; (3) the thin line dielectric layer is patterned using a photoresist layer having a thickness between 0.1 microns and 4 microns. , wherein the thickness of the photoresist layer is preferably between micrometers and 2 micrometers, and then the photoresist layer is exposed and developed to form a plurality of openings of the photoresist layer and/or a plurality of trenches. Removing the photoresist layer; (4) depositing an adhesion/barrier layer and a seed layer by sputtering or chemical vapor deposition. Wherein, the adhesion/barrier layer comprises a button, a nitride button, a titanium nitride, a titanium or a titanium tungsten alloy, or a composite layer formed of the above materials. In addition, the seed layer is usually a copper layer, and the copper layer may be formed by using copper metal, chemical vapor deposition of copper metal, or by chemical vapor deposition - copper metal and then copper. Forming; (5) a copper layer having an electric ore thickness between 0.05 micrometers and 2 micrometers on the seed layer, wherein the copper layer having a thickness of the copper layer between G, 2 micrometers and 1 micrometer is further (9) The method of polishing (preferably CMP) wafers removes the copper layer, the seed layer, and the adhesion/barrier layer that are not in the openings or trenches of the thin-line dielectric layer 30 until exposed. Out of the thin dielectric layer 3G under the adhesion/barrier layer. After chemical mechanical grinding, only the metal in the opening or trench is left, and the remaining metal is used (|>j 71

MEGA 06-015TWB acts as a metal conductor (line or plane) or a conductive plug (9) (connects two adjacent thin-line metal layers 60). In addition, it is also possible to simultaneously form a conductive plug 6〇 and a metal wire metal plane by using the “d〇ubie_damascene” process in the secondary-mineral process and the secondary chemical mechanical polishing. Time (4) (10) (10) 丨-Qing (4) process and two key-key processes are on the dual damascene process. The dual damascene process adds more steps to deposit and pattern another dielectric layer between the step (3) of patterning the dielectric layer in the single enemies process and the step (4) of depositing the metal layer. The fine-line dielectric layer 30 is formed by chemical vapor deposition, plasma_chemical vapor deposition, high-density chemical vapor deposition, or spin coating. The material of the fine-line dielectric layer 30 includes silicium oxide (xic), tantalum nitride (9) nitride, silicon oxynitride, tetraethoxy group formed by plasma-assisted chemical vapor deposition. CVD (PECVD TEOS), spin-on glass (s〇g, yttrium oxide or yttrium oxide), Fluorinated Silicate Glass (FSG) or a low dielectric constant (9) ~ called material 'such as black diamond film out (7) 丨 ( (10) is the product of the 卯丨 (6) Materials, the company translated as Applied Materials (

Novellus's product) or SiLK (IBM) low dielectric constant dielectric material. Cerium oxide formed by plasma-assisted chemical vapor deposition, tetraethoxydecane formed by plasma-assisted chemical vapor deposition, or oxide formed by high-density plasma having a dielectric constant between 3.5 and 4.5 K; fluorocarbon glass formed by plasma-assisted chemical vapor deposition or fluorocarbon glass formed by high-density plasma having a dielectric constant value between 3 〇 and 35 λ, and a low dielectric constant dielectric material Then have a gate between 丨.5 and 3 5

Mega "Electricity value of 06-015TWB. A low-k dielectric material, such as a black diamond, is porous, and includes hydrogen, carbon, stagnation and oxygen, and its molecular formula is called. The thin-line dielectric layer 3〇 typically includes an inorganic material (in〇rganicma) to achieve a thickness greater than 2 microns. The thickness of each fine-line dielectric layer 3〇 is between 微米 5 μm and 2 μm. The opening 30 in the thin-line dielectric layer 30 is formed by patterning the photoresist layer by means of hard or dry etching, wherein a preferred residual mode is dry. The dry money type includes flu〇rineplasma. Lu (four) protective layer (passivation 丨ayer) 5 protective layer 5 plays a very important role in the present invention. The protective layer 5 is an important component in the integrated circuit industry, such as the year by sw〇lf, and is issued by the Lattice press "Silic〇n Ρ γ__ 出出幻幻(10)" Book 2 The 'protective layer 5' is defined as a final layer in the integrated circuit process and is deposited on the entire upper surface of the wafer. The protective layer 5 is an insulating and protective layer that prevents mechanical and chemical damage during assembly and packaging. In addition to preventing mechanical marks, the protective layer 5 can also prevent mobile ions (mobile i〇n), such as sodium ions and transition metals (transiti〇nmeta丨), such as gold, copper, penetrating. Enter the integrated circuit components below. In addition, the protective layer 5 can also protect the underlying components and connection lines (fine line metal structure and fine line dielectric layer) from moisture intrusion. The protective layer 5 generally comprises a siiicon nitride layer and/or a silicon oxynitride layer and has a thickness of between 〇2 μm and 丨5 μm 73 1344686

It is preferred that the MEGA is between 06-015 TWB and has a thickness of between 0.3 micrometers and 1.0 micrometers. Other materials using Lu in protective layer 5 are oxidized stone formed by plasma-assisted chemical vapor deposition. Plasma-reinforced tetraethyl silicate is used as (4) 〇rtho.ate 'PETE0S) The oxide, the broken glass (10) which h secret her coffee s, PSG), the butterfly frequency teacher (10) coffee ring. Addition, BpsG), oxide formed by high density plasma _>). Next, the protective layer $ is composed of a composite layer: In some examples, the bottom to top order is: (1) the thickness is between 〇1 μm and 1 〇 micro# meters (the preferred thickness is between 〇·3 μm) Nitride 11 having an oxide/thickness between 0.25 μm and L 2 μm (preferably between 〇35 μm and 1 μm), this type of protective layer 5 Tongnu covers the hybrid line formed by the hybrid. The metal connection line of Nacheng usually includes the process of reducing the amount of money. (2) The thickness is between 0.05 micrometers and 〇.35 micrometers. 〇 〇. 1 μm to 0.2 μm) NOx / thickness between Μ micron to! 2 microns (preferably thickness between (H micron to 〇 · 2 microns) oxide / thickness between • 〇. 2 microns to U micro-thickness is between 〇.3 micro to 〇.5 Between the micron) the thickness of the oxide/thickness between 0.2 microns and 1 > 2 microns (preferably between 〇 3 microns and 〇 6 microns). This type of protective layer 5 is usually covered On a metal connection line formed of copper, a metal connection line formed of copper generally includes an electroplated dry mechanical grinding and damascene process. In addition, the oxide layers of the above two examples may be oxygen-cut, plasma-enhanced dioxygenated tetraethyl ortho-acids formed by paste-assisted chemical vapor deposition _ secret enh_d _%1. Pool. Canvas, 74 1344686

MEGA 06-015TWB PETEOS) oxide, oxide formed using high density plasma. The above is applicable to all of the embodiments (first embodiment, second embodiment, third embodiment, and fourth embodiment) of the present invention. The protective layer opening 50 is formed by means of etching or dry etching, wherein the dry name is preferred. In the present invention, the protective layer opening 50 includes: (1) protective layer openings 51 512, 514, 519, 519, 52, 522, 524, and 529 in the first embodiment; (2) protective layer opening 53 532 and 534 are in the second embodiment; (3) protective layer openings 53 532, 534, 539 and 539, in the third embodiment; (4) protective layer openings 51 512, 514, 549, 52 522 , 524, 549, 559, and 559' are in the fourth embodiment. In addition, the size of the protective layer opening 5〇 is between micrometers and 200 micrometers, and is between! Between micron to 1 〇〇 micron or between 5 micron and 30 micron, the shape of the other protector σ % % can be round, square, rectangular ❹ ,, so the size of the upper secret layer σ 5G is Refers to the diameter of the circle, the length of the square, the longest diagonal of the polygon, or the width of the rectangle. The length of the rectangle is between i cm and preferably between 5 and 200 microns. . For internal circuits, the size of the protective layer openings 531, 532, 534 is between 〇丨 micrometers to (10) micrometers 'and preferably between 0.3 micrometers and 30 micrometers, for a voltage regulator or The protective layer openings 519, 519 of the transformer 41, the protective layer openings 539, 539 of the outer or outer circuits 42, 43 of the yoke or the yoke, or the protective layer openings 549, 549 for the nickel ray 559, 559, for example, the size of the 闽σ dip opening is larger, and its range is 75 1344686

MEGA 06-015TWB is between 1 micron and 150 micron and is preferred between 5 micrometers and 1 micrometer. In addition, the protective layer opening % exposes the metal line or plane of the metal layer of the uppermost layer of the fine line metal layer (transmission 1 _ for electrically connecting the upper layer of the protective layer - passivation).曰曰片1 〇, for example, s丨丨icon wafer, is fabricated using different generations of integrated circuit process technology, such as 1 micron, 〇.8 micron, ο.6 micron, 0. 5 micron, 0.35 micron, 〇 '25 micron, 〇 18 micron, 〇 25 micron, 〇 13 micron, % yue not ((10)) 65 m, 45 nm, 35 nm, 25 nm technology, and these integrated circuit processes The generation of technology is defined by the gate length of the MOS transistor 2, or the length of the effective channel. The size of the other wafer is, for example, 5 吋, 6 吋, 8 忖, 12 忖 or 18 吋. Wafer 10 is fabricated using a lithography process that includes coating (exposure, exposure, and developing photoresist). The photoresist used to make the wafer has a thickness of Between 1 micron and 0.4 micron, and exposed by a five-times stepper (10) or a scanner. Wherein, the multiple of the stepper is when the light beam is projected onto the wafer from a reticle (usually composed of quartz), the ratio of the pattern on the reticle is reduced on the wafer, and five times (5X) is It means that the proportion of the pattern on the mask is five times that of the pattern on the wafer. Scanners that use the advanced generation of integrated circuit process technology are usually scaled down by a factor of four (4X) to improve resolution. The beam wavelength used by the stepper or scanner is 436 nm (g-Hne), 365 nm, 248 nm (deep UV 'duv;, 丨93 nm (DUV), 丨57奈Rice (DUV)

76 (D 1344686

MEGA 06-015TWB or 13.5 nm (very short UV, EUV, .Η. & Qing) ° In addition, the Southern Index Invasive (high-index _ nnm surface η) lithography technology can also be used to complete wafer 1细 fine line features. In addition, the wafer ίο疋 is fabricated in a clean room (9)_) having a rating of 1 〇 (dass 1 〇) or better (for example, level 1). The clean room of class 1〇 allows the maximum number of dust particles per cubic inch to be: no more than one dust particle containing 1 micron or more, containing more than or equal to 0.5 micron, no more than ig dust particles, containing more than Or equal to G.3 micro-weight dust particles * more than 3 (four), containing no more than or equal to ^ # microns of dust particles no more than 75, containing more than or equal to 〇 1 micron of dust particles no more than 350, and grade 丨 clean room The maximum number of dust particles allowed per cubic inch of suction is: no more than or equal to α5 micron of dust particles, no more than 3 particles of dust particles greater than or equal to 〇.3 micrometers, containing greater than or equal to 0.2. No more than 7 dust particles are required, and no more than 35 dust particles containing 大于1 μm or more. Referring to Figure 15, when using copper as the thin-line metal layer 6〇, you need to use a metal cap 66 (including 66 662, 664, 669, and 669) to protect the vine The copper pad exposed by the opening 50 (c〇pper pa(j) is used to protect the copper bond from oxidation and damage, and can be used as a wire bonding of the subsequent wafer. The metal top layer 66 includes an aluminum. (aiuminum) layer, a gold (g〇ld) layer, a titanium (Ti) layer, a titanium-tungsten alloy layer, a button (Ta) layer, a nitride button (TaN) layer or a nickel layer. When the metal top layer 66 is an aluminum layer, a barrier layer is formed between the copper pad and the metal top layer 66, and the barrier layer comprises titanium, titanium tungsten alloy, and nitride (i) j. 77 1344686

MEG A 06-015T WB Titanium, button 'nitride button, chrome (Cr) or tantalum. A, Flying Snail In all embodiments of the invention, the wafer 选择性 can selectively form a metal top layer 66. Referring to the first to fifteenth KK, the process step of fabricating a structure sche_ above the protective layer of the wafer 10i as shown in FIG. 15A or (9) is revealed, wherein the process step is above the protective layer. Two patterned metal layers are formed, and the two patterned metal layers are used to connect the internal circuits and connect the external circuits. However, this method reveals that there are two patterned metal layers above the protective layer, but it is also possible to use the same or similar manner as described in the lsc to 15K, above the protective layer. A layer, a two-layer patterned metal layer, a four-box metalized layer, or a plurality of patterned metal layers. In addition, the contents described below are applicable to all embodiments of the present invention. Referring to the 15th figure, a structure 8 above the protective layer is formed on the starting material (4), and the starting Na is a semiconductor manufacturing-wafer (1) (such as the 15th or the first 15Β)). In addition, the structure 8 above the protective layer includes a patterned metal layer 8G and a polymer layer (or insulating layer) 9G. The patterned metal layer 8 includes one layer, two layers, three layers, four layers or more layers. Habitually, and the patterned metal layer 80 can be, for example, except that the topmost pattern of the germanium layer is a gold layer, and the rest are copper layers and their adhesion/barrier layers (eg, or all embodiments of the invention are Taking the patterned metal layer 80 including an exposed metal layer as an example, the system includes: 5 two-layer map (g > 78 1344686

MEGA 06-015TWB (i) Patterned metal layer 801, including (1) 811 and 821 in the first embodiment; ^ (2) 831 (including 831a, 831b) in the second embodiment; (3) 83r, 831 (including 831a, 831b) is in the third embodiment; and (4) 811 and 821 are in the fourth embodiment. (ii) patterned metal layer 802, including (1) 812 in the first embodiment; (2) 832 in the second embodiment; (3) 832 (including 832a, 832b) in the third embodiment; (4) 812 In the fourth embodiment. Further, the material of the patterned metal layer 80 includes gold, silver, copper, palladium, platinum, rhodium, φ 钌, and nickel, and the patterned metal layer 80 constituting the metal wiring or the plane is usually a composite layer in which metal is stacked. In FIG. 15K, both the patterned metal layer 801 and the patterned metal layer 802 are a composite layer, wherein the underlying layer of the composite layer is an adhesion/barrier/seed layer 8011, 802. The system includes: (1) 8111, ^ 8121 and 8211 in the first embodiment; (2) 831 831 la, 831 lb and 8321 in the second embodiment; (3) 83U, 831 la, 831 lb, 8321a and 8321b are in the third embodiment; and (4) 8111, 8211 and 8121 are in the fourth embodiment; in addition, the top layer of the composite φ layer is a thick metal layer 8012, 8022, which includes: (1) 8112, 8122 and 8212 in the first embodiment; (2) 8312, 8312a, 8312b and 8322 in the second embodiment; (3) 8312, 8312a, 8312b, 8322a and 8322b in the third embodiment; and (4) 8112 , 8212 and 8122 are in the fourth embodiment. In the above, the 'adhesive/barrier/seed layer 8011, 8021 includes an adhesion/barrier layer (not shown) and a seed layer on the adhesion/barrier layer (not shown in the figure). )] The material of the adhesion/barrier layer can be titanium, tungsten, cobalt, nickel, titanium nitride, 79 30 1344686

MEGA 06-015TWB 鈥Tungsten alloy, slave, chrome, copper, chrome-copper alloy, neon, nitride button, alloy of the above-mentioned materials, or a composite layer composed of the above materials. Another 'adhesive/barrier layer can be formed by electroplating, electroless piating, chemical vapor deposition or physical vapor deposition (such as sputtering), wherein physical vapor deposition is preferred. The way of formation 'for example, metal splash key process. Further, the thickness of the adhesion/barrier layer is between 0.02 μm and 〇.8 μm, and preferably between 〇.05 μm and 〇 2 μm. • The seed layer of the top layer of the adhesion/barrier/seed layer 8011, 8021 can facilitate subsequent plating processes, and the seed layer is typically grown by physical vapor deposition or sputtering processes. In addition, the material used for the seed layer may be gold, copper, silver, ruthenium, palladium, iridium, platinum or rhodium, and is usually the same material as the thick metal layer in the subsequent electroplating process. In addition, the 'seed layer can be formed by means of electro-recording, electro-pneumatic electricity, chemical vapor deposition or physical vapor phase "L product (for example, Lai), in which physical vapor deposition is preferred, such as metal splashing. Plating process. The thickness of the seed layer is between 〇〇5 μm and Å 2 μm and the thickness between 〇 5 μm and 〇 g μm is preferred. . Thick gold Gu 8〇12, 8〇22 are Wei resistance conductor shafts, and are usually formed by electric ore. In addition, the thickness of the thick metal layer is usually between 〇5 μm and 100 μm, and The thickness is preferably between 3 micrometers and 2 micrometers, and the thick metal layer can be made of gold, copper, silver, or the like: gold, silver, and The preferred thickness of money, inscription or tantalum is between 1.5 micrometers and micrometers, and the preferred thickness of copper is between 15 micrometers and 5 micrometers.

The preferred thickness of nickel between MEGA06O15TWB is between 〇 5 microns and 6 microns. #, Optionally, a protective/blocking layer (not shown) is formed on the thick metal layers 8〇12, 8022 for protection or diffusion barrier. The protective/barrier layer may be formed by means of electromineral, electroless ore, chemical vapor deposition or physical vapor deposition (10) such as ore quenching, and deposited by electroplating to form a preferred one. Further, the thickness of the protective/barrier layer is in the range of from 0.05 μm to 5 μm, with a thickness of between 〇 5 μm and 3 μm being preferred. The protective/barrier layer can be a nickel layer, a cobalt layer or a starved layer. In addition, an assembly-contact layer (not shown) may be selectively formed on the thick metal layer 8〇12, 8〇22 or the protective/resistive layer on the assembly or package (Fig. The upper portion is 'in particular, formed on a thick metal layer or a protective/barrier layer (not shown) on the topmost layer of the patterned metal layer. The assembled contact layer can be used as a wire bond or as a solder wettable, which can be used for wire bonding, gold connection, solder ball soldering or solder connection. ). Alternatively, the assembled contact layer can be gold, silver, Ming, Ji, recorded or 钌. Polymer layer opening 990 in the top polymer layer 99 (including 9919 and 9929 in the first embodiment; 9939 and 9939, in the third embodiment; and 9949 and 9949, in the fourth embodiment) Example) exposing a contact pad 8000 at the topmost patterned metal layer 80 (including 8110 and 8120 in the first embodiment; 8310 and 8320 in the third embodiment; and 8110 and 8120) In the fourth embodiment) the surface. The assembled contact layer exposed to the polymer layer opening 99〇 may be a bonding wire, a solder ball (with a key 1344686)

MEGA 06-015TWB formed solder balls or soldered to a solder ball), a metal ball (such as tin-silver alloy formed by electroplating or soldered to a tin-silver alloy), on other substrates or wafers One metal bump, one gold bump on another substrate or wafer, one metal pillar on its substrate or wafer (which is p〇st) or other substrate or wafer One of the copper posts (copperp〇st). For an integrated circuit formed by aluminum formed by an erase bond or copper formed by electroplating (formed by a chemical mechanical polishing process), the metal line or plane above the protective layer can be One of the following types, from bottom to top, is: (1) titanium tungsten alloy / gold seed layer formed by sputtering / gold formed by electroplating; titanium / gold seed formed by sputtering Layer / gold formed by electroplating; (3) button / gold spring layer formed by sputtering / gold formed by electroplating; (4) chromium / copper seed layer formed by sputtering / electric clock Copper formed; (5) titanium tungsten alloy / copper seed layer formed by demineralization / copper formed by electric bonding; (6) group / copper seed layer formed by sputtering / copper formed by electroplating; (7) titanium /Secondary seed layer formed by sputtering/copper formed by electroplating; chromium, titanium tungsten; gold, titanium or tantalum/copper seed layer formed by sputtering/copper formed by electroplating/plating Nickel; (9) Chromium, titanium-tungsten alloy, titanium or neon/pre-bonded copper seed layer/electricity Formed copper / nickel formed by electroplating / gold, silver, platinum, palladium, rhodium or ruthenium formed by electroplating; and (10) chromium, titanium tungsten alloy, titanium or tantalum / copper seed layer formed by sputtering / Copper formed by electroplating / Nickel formed by electroplating / Gold, silver, platinum, palladium, rhodium or ruthenium formed by electroless plating. The thickness of each patterned metal layer 80 is between 2 microns and 50 microns, and is preferably between 3 microns and 20 microns thick. 1 82 1344686

MEGA 06-015TWB Degree of patterned metal layer 80, if it is a metal line, its lateral design standard (width) Φ system; 丨 between 1 micron and 200 microns, and preferably between 2 microns and 50 microns Whereas the patterned metal layer 80 is a metal plane, it is used as a power source or ground reference electric county, and its lateral design standard (width) is preferably greater than 2 〇 0 μm. In addition, the minimum distance between two adjacent metal lines or planes is between 丨 micrometers and 500 micrometers, and preferably between 2 micrometers and 15 micrometers. In some applications of the invention, the metal lines or planes may comprise only aluminum in the thickness of between 2 microns and 6 microns (preferably between 3 microns and 5 microns) formed by sputtering. A selective adhesion/barrier layer (including titanium, titanium tungsten alloy, titanium nitride, tantalum or tantalum nitride layer) under the aluminum layer. Continuing, a contact structure 89 can be selectively formed on the pads 8 of the patterned metal layer 80. The contact structure 89 can be a metal bump, a solder bump ( S〇ider bump), a solder ball, a gold bump, a copper bump, a metal pad, a solder pad (s〇) A lder pad, a gold pad, a metal post, a solder post, a gold post, or a copper post. An under bump metal (UBM) layer is disposed under the contact structure 89. The underlayer metal layer of the bump includes titanium, titanium tungsten alloy, titanium nitride, chromium, copper, chrome-copper alloy, group, nitride.钽, nickel, nickel sharp alloy, hunger or initial layer, or a composite layer composed of the above materials. The contact structure 89 (including the underlying metal layer of the bump) may be one of the following types: from bottom to top: (1) titanium/gold pads (gold)

83 (D 1344686

MEGA 06-015TWB layer thickness between 1 micron and 15 microns); (2) titanium tungsten alloy / gold pad (gold layer φ thickness is between 1 micron and 15 microns); (3) Nickel/gold pads (the thickness of the nickel layer is between 0.5 μm and 1 μm, and the thickness of the gold layer is between 〇2 μm and 15 μm); (4) Titanium/gold bumps (gold layer) The thickness is between 7 micrometers and 4 micrometers); (5) titanium tungsten alloy/gold bumps (the thickness of the gold layer is between 7 micrometers and 4 micrometers); (6) recording/gold bumps (The thickness of the nickel layer is between 〇5 μm and 1 μm, and the thickness of the gold layer is between 7 μm and 40 μm); (7) Titanium, Titanium-Tungsten Alloy or Chromium/Copper/Record/Gold • • 塾 (the thickness of the copper layer is between 1.1 μm and 10 μm, and the thickness of the gold layer is between 0.2 μm and 15 μm); (8) Titanium, titanium tungsten alloy, chromium, chromium copper Alloy or nickel vanadium alloy / copper / nickel / gold bumps (the thickness of the copper layer is between 〇丨 micron and 1 〇 micron, the thickness of the gold ruthen layer is between 7 microns and 40 microns); (9 Titanium, titanium alloy, chromium, copper alloy or nickel vanadium alloy / copper / recorded / solder pads (the thickness of the copper layer is between microns and 10 microns - the thickness of the layer is between 0.2 microns and 30 microns); (1) Qin, titanium tungsten alloy, chromium, chromium copper Alloy or nickel-vanadium alloy/copper/nickel/twist bump or solder ball (the thickness of the copper layer is between 0.1 micron and 1 micron, and the thickness of the solder layer is between 10 and 500 microns) ((1) Titanium, titanium tungsten alloy, chromium, chrome-copper alloy or hunger alloy/copper column (the thickness of the copper layer is between 10 micrometers and 300 micrometers); (12) Qin, 1 tungsten alloy, chromium , chrome-copper alloy or nickel-vanadium alloy/copper column/recorded (the thickness of the copper layer is between 10 microns and 300 microns); (13) titanium, titanium tungsten alloy, chromium, chrome-copper alloy or hungry alloy/copper Column / nickel / solder (the thickness of the copper layer is between 10 microns and 300 microns - the thickness of the solder layer is between 1 micron and 20 microns); (10) titanium, titanium tungsten 84 1344686

MEGA 06-015TWB Gold, Chromium, Chromium-Copper or Nickel-Vanadium Alloy/Copper Column/Nickel/Solder (The thickness of the copper layer is between 1 μm and 300 μm, and the thickness of the solder layer is 2 μm. Between 1 〇〇 micron). Another 'assembly method can be wire bonding, tape automatic bonding (Tape Aut〇mated

Bonding 'TAB), chip flip chip package (chip_〇n_glass, c〇G), chip-on-board (COB), flip chip on BGA substrate, film Chip-on-fiim 'c〇F, chip-〇n-chip stack interconnection, chip-on-Si-substrate stack Interconnection) and so on. Another important feature of the structure 8 above the protective layer is that a polymeric material is used as a dielectric layer or an insulating layer on, under or between the patterned metal layers 8〇. The use of polymeric materials allows the fabrication of dielectric layers having a thickness greater than 2 microns. The polymer layer formed of a polymeric material may have a thickness between 2 microns and 100 microns and is preferably between 3 microns and 30 microns thick. The polymer layer 90 (including 95, 98, 99) used on the protective layer 5 may be polypyridinium (PI), benzocyelobutene (BCB), or parylene ( "paryiene", epoxy-based material such as epoxy resin or ph〇t〇epoxy SU-8, elastomeric material (elastomer) supplied by Sotec Microsystems, Renens, Switzerland, such as anthrone ( Silicone). Alternatively, a solder mask material used in the printed circuit board industry can be used as the top polymer layer 99 (the topmost polymer layer on all of the patterned metal layers 80). The polyimine can be a photosensitive Φ material. In addition, 'polyimine can be a nonionic

(D 85 1344686

MEGA06-015TWB Poly-imine (non-_epGiymide), for example, is provided by Japan's ^^(10)丨(3)丨, which is supplied to the base of the base of the imine (IV) Shen Ruji-Cai (4), pim £ltM. In addition, since copper does not diffuse or penetrate into the nonionic polyimide lens, it allows direct contact between copper and polyimine, and the structure above the protective layer due to the relationship of nonionic polyimine. The distance between the copper lines or planes in 8 may be close to 1 micron, such as between 1 micrometer and 5 micrometers. In other words, the distance between the two metal lines or planes may be greater than 1 micrometer. In addition, when the metal line or the plane of the copper material and the polymer layer covering the metal line or the plane are non-ionic polyimide, the metal line or the plane may be selectively free of the protective layer. Tecti〇ncap), such as a nickel cap layer. Of course, when a metal line or a plane is formed, it is also possible to form a protective layer such as a recording layer on the copper layer, and it is possible to prevent copper ions from diffusing into the polymer layer. As shown in Fig. 15K, 'the purpose of forming openings in the polymer layer is to interconnect different patterned metal layers 8 〇, to connect the underlying thin metal layer 6 〇 or to connect external circuits ( Extemal c〗 rcuit). The polymer layer opening package φ includes 0) 9919, 9929, 9829, 9519, 9519', 95U, 9512 and 9514 in the first embodiment; (2) 9831, 9834, 9531, 9532 and 9534 in the second embodiment (3) 9939, 9939', 9831, 9834, 9839, 9539, 9539, 953, 9532 and 9534 in the third embodiment; and (4) 9949, 9949', 9849, 9549, 9511, 9512 With 9514 in the fourth embodiment. The polymeric material can be photo-sensitive or non-photo-sensitive. For photosensitive polycarbonates, which are defined and patterned by exposure and development 86 1344686

MEGA 06-015TWB, and for non-photosensitive polymers, the opening is defined by the first coating of a photoresist layer on the poly-composite layer, and then the photoresist is exposed and developed to form an opening. In the photoresist, the polymer layer exposed by the photoresist opening is secretly engraved or dried to form an opening in the polymer layer, and finally the formation of the polymer layer opening is completed by removing the photoresist. The size of the opening of the polymer layer is between 2 microns and 1 inch and is preferably between 5 microns and 200 microns. However, in some designs, the polymer layer opening may also exceed the size of the 〇〇〇 micron. Alternatively, the polymer layer opening can be designed as a circle, a comer-rounded square, a rectangle or a polygon. The polymer layer 95 is located between the protective layer 5 and the bottommost end of the patterned metal layer 8〇1. The signal, power supply (Vdd or Vcc) and/or ground reference voltage (Vss) can be transferred between the thin wiring metal layer 6 and the patterned metal layer 80 through the polymer layer opening 950 in the polymer layer %. For the internal circuit 2〇 (including 21, 22, 23, 24), the polymer layer openings 9531, 9532, and 9534 are respectively aligned with the protective layer openings 53 532, 534, and the polymer layer openings 9531, 9532, 9534 The size is between 1 micrometer and 300 micrometers' and is preferably between 3 micrometers and 1 micrometer. For the regulator or transformer 41, the polymer layer openings 9519, 9519, 95U, 9512, 9514 are respectively aligned with the protective layer openings 519, 519', 511, 512, 514; for the wafer external circuit 40 (including 42, 43), the polymer layer openings 9539, 9539, 9531, 9532, 9534 are respectively aligned with the protective layer openings 539, 539', 531, 532, 534; spring for the electrostatic discharge protection circuit 44, the polymer layer openings 9549, 9511 , 9512, 9514 87

MEGA 06-015TWB is respectively aligned with the protective layer openings 549, 511, 512, 514, the other polymer layer openings 9519, 9519'' 9511, 9512, 9514, or the polymer layer openings 9539, 9539', 953, 9532, 9534 Alternatively, the polymer layer openings 9549, 9511, 9512, 9514 may be larger in size - between 5 microns and 1 inch, and preferably between 1 and 2 microns. By. The polymer layer opening 950 on the protective layer opening 5 has two open patterns. In the first open type, the polymer layer is open, for example, the polymer layer opening 9531 is larger than the lower protective layer opening 531, and is polymerized. The polymer sidewall of the layer opening 9531 is located on the protective layer 5. In this version, a smaller protective layer opening 531 can be formed, thereby forming a smaller contact interface at the top of the thin wiring metal layer, so that the open pattern allows fine lines of the finest fine metal layer at the top end. Having a higher winding density; in the second opening pattern, the 'bottom of the polymer layer opening', such as the bottom of the polymer layer opening 9539, is smaller than the lower protective layer opening p 539, and the polymerization (10) The polymer sidewall of the opening (e.g., polymer layer opening 9539) is on the metal interface at the top of the thin wiring metal layer. In this type of towel, the polymer layer 95 covers the opening of the protective layer, and the slope of the polymer layer opening (for example, the polymer layer opening σ 9539) is smaller than the slope of the sidewall of the opening of the protective layer and the subsequent metal is sputtered. The formed adhesion/barrier/seed layer_ has a good step coverage (clear c_ge). Better adhesion/barrier/seed metal step coverage is important for wafer reliability, which is due to the Nakasaki/Seed metal ladder stepping over the metal extension of the thick gold touch or polymer 1344686

MEGA 06-015TWB layer 'to prevent the intermetallic compound _ Γ side allicc 〇 mp_d; IMQ generation ^ or metal diffusion phenomenon occurs. The polymer layer opening 98 in the polymer layer 98 is between the patterned metal layer 8〇1 and the patterned metal layer 802. For internal circuits 21, 22, 23, 24, the size of the polymer layer opening 983, 9834 is between! It is preferred that the micron is between 3 microns and between 3 microns and 1 inch. For the polymer layer opening 9829 of the voltage regulator or transformer μ, or the polymer layer of the wafer external circuit 4 (including 42, 43), the opening 983, 9834, 9839 or the polymer layer opening of the ESD protection circuit 44 The size of 9849' can be larger 'with a range between 5 microns and microns, and preferably between 10 microns and 2 microns. • The topmost pad of patterned metal layer 802 exposed by polymer layer opening 990 in top polymer layer 99 can be used to connect external circuitry or as a contact point for probes in chip testing . The polymer layer opening is not provided for the internal circuit 21, ^, ^, 24' top polymer layer 99; in addition, the polymer layer opening 9919, 9929 of the stabilization or transformer 41, or the wafer external circuit 4 The polymer layer opening 9939 of 〇 (including 42, 43) or the polymer layer opening 9949, 9949' of the ESD protection circuit 44 may be larger in size, ranging from 5 micrometers to 2 micrometers, and It is preferred between 1 μm and 2 μm. The signal, power or ground reference voltage in the structure 8 above the input protection layer is transmitted to the internal circuit 20, the voltage regulator or the transformer 41, the wafer/external circuit 4A, or the ESD protection circuit 44 through the fine line structure 6. . In addition, fine line metal knot 89 1344686

The MEGA 06-015 TWB structure 63 may be a thin line metal layer 60 and a conductive plug 60' formed in a shortest path manner (for example, in a roughly aligned stacking manner), as shown in ISA, 631, 632, 634, 639 and 639'. The lithography technique for fabricating the structure 8 above the protective layer is significantly different from the lithography technique for fabricating the integrated circuit under the protective layer. The lithography process above the protective layer also includes coating, exposure and development photoresist. There are two types of photoresist used to form the structure 8 above the protective layer, which are: (1) liquid photoresist, which utilizes single or multiple multiple spin coating or printing methods. form. The thickness of the wet film photoresist is between 3 microns and 60 microns, and preferably between 5 microns and 40 microns; and (2) dry film photoresist, It is formed by a laminating method. The thickness of the dry film photoresist is between 30 microns and 300 microns' and is preferably between 50 microns and 150 microns. Further, the photoresist may be a positive-type or a negative-type, and in order to obtain a better resolution, a p-sitive-type thick photoresist is preferred. When the polymer layer is a photosensitive material, the polymer layer can be patterned using only a lithography process (without etching process). The photoresist is exposed using an aligner or a double (IX) stepper. This double (1X) refers to the ratio of the pattern on the reticle to the wafer when the light beam is projected onto the wafer from a reticle (usually composed of quartz or glass), and the pattern on the reticle The ratio is the same as the pattern on the wafer. The beam wavelength used by the aligner or double stepper is 436 nm (g line), 397 nm (h-line), 365 nm (i-line), g/h line (combined G-line with 90 1344686

MEGA 06-015TWB h-line) or g/h/i line (combined with g-line, h-line and i-line). Using a double stepper (or double aligner) with a wavelength of guangdong or Une can provide greater light imensity on exposure to thick photoresist or thick photosensitive polymer. Since the protective layer 5 can protect the underlying metal oxide semiconductor and the fine circuit structure 6 from moisture intrusion and penetration of sodium or other mobile ions and gold, copper or other transition metals, an integrated circuit wafer The upper protective layer structure 8 can be processed in a clean room of a level 10 or a less stringent environment (e.g., level 1). A Class 1 clean room allows the maximum number of dust particles per cubic inch to be: no more than 1 gray yarn greater than or 5 micrometers, no more than 1 micron dust particles greater than or equal to 1 micron. Particles containing more than _ or equal to 0.5 μm of dust particles not exceeding 丨 (8), dust particles containing 于 3 μm or less, no more than 3 、, dust particles containing 大于 2 μm or more, not exceeding 75 〇 Particles containing more than or equal to 1 micron of dust particles do not exceed the number of particles. • Component layer 2 includes internal circuitry 2 (including 2, 22, 23, and 24) in all embodiments 'and (1) voltage regulator or transformer 41 in the first embodiment; (2) wafer external circuitry 40 (including 42 43) In the third embodiment; (3) Electrostatic discharge protection circuit 44 is in the fourth embodiment. In all embodiments of the present invention, the internal circuit 2 (including 21, 22, 23, 24) includes a - signal node (signal n (the signal node (5) (four) node) is not connected to the external circuit) . When the signal of the internal circuit needs to be connected to the external σ卩 circuit, the city must pass 1344686 before connecting the circuit.

MEGA 06-015TWB A chip-terminated external circuit such as a wafer tri-state buffer, a wafer-terminated external driver, a wafer-terminated external receiver, or other external-input/output (1/0) circuit. Therefore, the internal circuit does not include a chip-terminated circuit.

In the present invention, the internal circuit 2 (including 2, 22, 23, 24) may be an inverter (NOR gate) or a reverse gate (nAND gate), or may be an inverter ( Inverter, AND gate, one or gate (Rgate), a static random access memory cell (SRAM cell), a dynamic random access memory cell (DRAM • ceU), a non-volatile memory Non-volatile memory cell, a flash memory cell, an erasable programmable read-only memory cell (EPROMcell), a read-only memory cell (R0Mcell), a magnetic random memory Take a magnetic RAM (MRAM) unit, a sense amplifier, an op amp (0perati〇nai ampijfier, Amp, opa), an adder, a multiplexer (multiplexer), a dipiexer, a multiplier, an analog/digital converter (A/D converter), a digital/# analog converter (D/A converter), a complementary metal a CMOS sensor cell, a photo-sensitive diode, and a mutual A complementary metal oxide semiconductor, a two-carrier complementary MOS, a bipolar circuit or an analog circuit. In addition, the internal circuit 20 (including 2, 22, 23, 24) is composed of at least one MOS transistor (such as a reverse thyristor, or a gate, and a gate or a gate) is at least one gold Oxygen semi-transistor, another gold-oxygen semi-transistor can be "channel 92 (I) 1344686

MEGA06-015TWB Width (Channel length) / Channel length * 'An N-type MOS semi-transistor with a ratio between 〇, 1 to 5 φ or between 0.2 and 2, or ' A 'Phase Width/Channel Length' ratio is between 〇2 and 1 或是 or a P-type MOS transistor between 〇4 and 4. In the first embodiment, the internal circuit 2〇 21, 22'23, 24) may be a power management chip or a power supply chip (p0Wer SUpply chip), the power management chip and the power supply chip are composed of at least one MOS transistor And the MOS transistor may be a p-type MOS transistor or a "p-channel width/channel length" ratio between 4,000 and 400,000 or between 4,000 and 40, or " A N-type MOS transistor with a channel width/channel length ratio between 2,000 and 200,000 or between 2, 〇〇〇 to 2 〇, and flowing through a metal line or plane 81 The current of 82 is between 500 mA and 5 amps or between 5 mA and 5 mA. . Alternatively, internal circuit 20 can be defined by its peak input or output current (i.e., current flowing through a gold line or plane) or by its MOS half-transistor size (channel width divided by channel length ratio) ) to define. A wafer-terminated external circuit 4〇 (including 42, 43) ' can also be defined by its peak input or output current (ie, current flowing through a metal line or plane), or by its MOS half-crystal size ( The channel width is divided by the ratio of the channel lengths to define. The definition of the internal circuit 2 and the external circuit 40 (including 42, 43) is applicable to all embodiments of the present invention. • Therefore, the present invention can penetrate the fine line metal structure and protective layer under the protective layer 93 1344686

The Jinguan Road or the plane above WEGA06-015TWB is connected to the same line - the line tree towel is at least two gold and a half

The gate and gate of the crystal, the gate and source, the _ and drain, the source and source, the source and drain, or the drain and drain. The dimensional characteristics between the patterned metal (4) and the fine-line metal layer 60 of all the embodiments of the present invention will be described below: electrical characteristics. (1) Thickness of metal wiring • The thickness of each patterned metal layer 80 is between 2 micrometers and 150 micrometers, and is preferably "3 micro-syntax 2 micro-gains, and each fine metal The thickness of the layer 6 则 is between G.05 and 2 μm, and is preferably between Q 2 and μm. For a wafer designed according to an embodiment of the present invention The thickness of the patterned metal layer above a protective layer is greater than the thickness of the fine-layer metal layer, and the ratio is between 2 and 250, and between 4 and 2 The range is • preferably. (2) Thickness of Dielectric Layer The thickness of the dielectric layer (usually an organic material such as a polymer) above each protective layer, such as the thickness of the polymer layer 90, is between 2 μm and Between 5 μm and between 3 μm and 30 μm is preferred, and the thickness of each fine-line dielectric layer (usually an inorganic material such as an oxide or nitride) is between 〇 Between 5 microns and 2 microns, and preferably between 〇 2 microns and 丨 microns. 94 1344686

MEGA 06-015TWB For a wafer designed according to an embodiment of the present invention, the thickness of the dielectric layer above a protective layer is greater than the thickness of any fine wiring dielectric layer, and the thickness ratio of the two is between 2 and A range between 250, and a range between 4 and 20 is preferred. (3) Sheet resistance and resistance of a metal layer The sheet resistance of a metal layer is obtained by calculating the metal resistivity divided by the thickness of the metal. The sheet resistance of a patterned metal layer over a protective layer of copper (5 micron thick) is approximately 4 milliohms per square (miii_〇hm), and is equivalent to one gold (thickness of 4 microns) The sheet resistance of the patterned metal layer above the protective layer of the material is approximately 5.5 milliohms per square. The sheet resistance of the patterned metal layer over a protective layer ranges from 0.1 milliohms per square to 1 milliohm per square, and is between 1 milliohm per square to 7 milliohms per square. The range is preferred. A fine-line metal layer formed by sputtering (0.8 micron thickness) has a sheet resistance of about 35 milliohms per square, and a thin line metal formed of a copper (thickness 〇9 μm) material in a damascene process. The layer has a sheet resistance of approximately 20 milliohms. The sheet resistance of a fine-line gold-based layer is between $1 milliohms per square to 400 milliohms per square, and is between 15 milliohms per square to 1 milliohm per square. The range between the two is preferred. The resistance per unit length of a metal line is divided by its width and resistance by a factor of six. The lateral design standard (width) of the @案化金>| layer above the protective layer is between μm and 2μm, and preferably between 2 microns and 5 μm. The horizontal design standard (width) of the fine-line metal layer is 95 1344686

MEGA 06-015TWB is between 20 nm and 15 microns and is preferably between 2 and 2 microns. The resistance per mm of the patterned metal layer above a protective layer is between 2 milliohms of resistance per mm length to 5 ohms per millimeter and is 5 inches per millimeter. Between milliohms and 25 ohms per millimeter is preferred, and the resistance per millimeter of a thin-line metal layer is between 500 milliohms per millimeter and 3,000 ohms per millimeter, and is between millimeters per millimeter. It is preferred to be between 5 ohms and ohms to 5 ohms per millimeter. • For a wafer designed in accordance with an embodiment of the present invention, the unit length resistance of the patterned metal layer over a protective layer is less than the unit length resistance of any thin line metal layer, and the unit length resistance ratio of both (fine lines The metal layer is in the range of between 3 and 250 than the patterned metal layer above the protective layer, and is preferably in the range of between 1 and 3 Torr. (4) The capacitance per unit length of the metal line (capacitance A _ 1 as her) The capacitance per unit length is related to the type and thickness of the dielectric, the width of the metal line, the distance and thickness of the metal, and the egg metal in the horizontal and vertical directions. . The polyaniline has a dielectric constant of about 3.3, while the phenylcyclobutadiene has a dielectric constant of about 25. Next, please refer to FIG. 20, which is exposed on the same patterned metal layer 802'-the patterned metal layer 8〇2χ has two adjacent patterned metal layers 8 kiss and patterned metal layer 8G2z And having a patterned metal layer 801w under the patterned metal layer 8() 2, and the patterned metal layer 8〇lw is separated from the patterned metal layer 802 by a polymer layer 98. Similarly, the second map is also revealed in the same fine line gold 96 1344686

On the MEGA 06-015TWB genus layer 602, a thin line metal layer 602x has two adjacent fine line metal layer ruins 602y and fine line metal layers 〇2z, and has a fine line metal under the thin line metal layer 〇2 Layer 601w, and the thin line metal layer 601W is separated from the thin line metal layer 602 by a thin line dielectric layer 30. The unit length capacitor of the patterned metal layer 802x and the thin line metal layer 6〇2x includes two components: (1) plate capacitance, Cxw (pF/mm), which is divided by metal line or plane width. a function of the ratio of the thickness of the dielectric; • Coupling cacacitance, CcxKVH:), which is the ratio of the metal line or plane thickness divided by the spacing between adjacent metal lines or planes (Kne spacing). A function: and (7) edge capacitance 汾 (4) (four) (3) ^ plus (four), ^ ^ ^ ^, _ which is the thickness of the metal line or plane, the spacing between adjacent metal lines or planes and the thickness of the dielectric material Each wire capacitance is between 0.1pF (pico Farads) per mm and 2pF per mm, and is between JpF and mm per mm long! Between the chats is better, and the thickness of each wire of the fine-line metal layer is between 2pF per mm long and 4 centimeters per mm, and is between 4pF and mm per mm. It is better between 2pF and longer. . . For a wafer designed in accordance with an embodiment of the present invention, the unit length capacitance of a patterned metal layer is less than the unit length capacitance of any of the fine line metal layers and the unit length capacitance ratio of the two (fine line metal layer ratio patterning) Metal layer) is between! A range between 5 and 5 is preferred as a range between 2 and 1 G. ♦ (5) Resistance and capacitance constant of metal lines (RC _tam) 97 1344686

MEGA 06-015TWB - The signal transmission time on the metal line is delayed by Rc dqing. Based on the contents of (3) and (4) above - the retardation delay of the patterned metal layer is between _3 and (7) lengths per minute (7), and 0.25 to 2 pS per millimeter ( The range between piC0 second) is preferred, and the resistance of a thin-line metal layer is between 1 () n_ps (pieQ se (xmd) range) and between mm and mm. A range of 40 to 500 ps (pic〇sec〇nd) is preferred. ~ • For a wafer designed in accordance with an embodiment of the present invention, a patterned metal layer has a unit length resistance transfer time (RC paopagation) Time) is less than the resistance transfer time per unit length of any fine-line metal layer, and the ratio of the RC Paopagation delay time of the unit length (the thin-line metal layer to the patterned metal layer) is Between 5 and 500, and between 1 〇 and 3 为 is preferred. Again, please refer back to Figure 15C to Figure 15L, which is revealed in the Yuancheng On the wafer 10 (as shown in FIG. 15A or FIG. 15B), a fabrication step of the top layer 8 of the protective layer is formed. Each patterned metal layer The 80 series is formed using an embossing process (as opposed to the inlaid copper process under the protective layer 5). Referring to Figure 15C, a polymer layer 95 is deposited on the protective layer 5 and exposed through the polymer layer opening 950. The metal pad 600 exposed by the protective layer opening 50. If the polymer is in a liquid form, it can be formed by spin coating or printing, and if the polymer is a dry film (dry film), the dry film can be formed by a bonding method. For the photosensitive polymer, the polymer layer 95 is made by using an alignment machine 1344686

KtEGA〇6-〇i5TWB or 倍 (IX) stepper is exposed through the light of the reticle, and through the development, the polymer layer opening 950 is formed in the polymer layer 95; when the polymer is non-photosensitive , you must use the photoresist and pattern the polymer layer D 950 through the traditional lithography process. The manner in which the polymer layer is patterned may be in the following manner: a hard mask (for example, a layer of oxidized stone, not shown) in the polymer layer 95 may be selectively deposited before the photoresist is applied. The hard mask has a slow etch rate during the opening of the etched polymer layer. In addition, the square pattern of the patterned polymer layer 95 (ie, the polymer layer 95 has the polymer layer opening 950) may also utilize a screen printing method by using patterned holes (h〇ie). One of the metal screens is formed, and the method of screen printing does not require exposure and development. In addition, if the polymer layer is a dry film, holes can be formed in a dry film before bonding to the wafer, so exposure and development are not required in this manner. In addition, since the polymer layer 95 can be formed on the protective layer 5, the lowermost patterned metal layer 80 on the protective layer 5 can be formed on a relatively flat surface provided by the upper surface of the polymer layer 95. Therefore, it is possible to prevent leakage current from occurring between adjacent lines of the patterned metal layer 80, and to prevent coupling between the patterned metal layer 8 and the fine-line metal structure under the protective layer, thereby providing better Electrical performance. However, in some applications, the polymer layer 95 may also be omitted to save cost. The polymer layer opening 950 is aligned with the protective layer opening 50, and the polymer layer opening 950 may be larger or smaller than the protective layer opening. ® In addition, the formation of the protective layer opening and the polymer layer opening 950 may also be the first 99 1344686

MEGA 06-015TWB deposit polymer layer 95 on protective layer 5, followed by formation of polymer layer opening 95〇, and finally forming conformal opening 50, in this manner, polymer layer opening 950 is approximately the same size The protective layer openings 50 are the same size. "Monthly, as shown in Figs. 15D to 15H, which exposes a embossing process for forming the patterned metal layer 801. In Fig. 15D, an adhesion/barrier/seed layer 8011 is deposited on the polymer layer 95, in the polymer layer opening 950, and in the protective layer opening 50, wherein the adhesion is deposited by sputtering to form an adhesion/barrier/ The preferred mode of the seed layer 8〇11. When the material for forming the thick metal layer is gold, the adhesion/barrier/seed layer 8〇11 is formed by sputtering to form a thickness of 3, one of the titanium alloys or the adhesion of titanium. The barrier layer' is then sputtered to form a gold seed layer having a thickness of L000 angstroms. When the material for forming a thick metal layer is copper, the adhesion/barrier/seed layer is formed by sputtering to form an adhesion/barrier layer of a thickness of 500 angstroms of chromium metal to form a thickness of 1, Å. - Titanium hybrid/transfer layer or formation of a thickness of 3, the adhesion/barrier layer of the titanium-tungsten alloy, followed by a bond to form a copper seed layer having a thickness of 5, Å. Figure 15E reveals that the photoresist layer 71 is deposited and patterned on the seed layer of the adhesion/barrier/seed layer 8011. The photoresist layer 71 is formed by spin coating, and then exposed by a _-aligner or a 1-step (1 Å) stepper, and then developed to form a photoresist layer in the photoresist layer 71. The opening 71 is closed. The photoresist layer opening 71 is used to define the formation of a metal line or plane in contact with the polymer layer opening 95 and the protective layer opening Deng in a subsequent process, and the contact is on the exposed metal pad 600 and connected This exposed metal pad is fine. The first picture shows the electric mine 100 1344686

The MEGA 06-015TWB pattern forms a thick metal layer 8012 on the seed layer φ exposed by the photoresist layer opening 7i. The thick metal layer 8012 can be a gold layer having a thickness between -5 micrometers and 5 micrometers or a copper layer having a thickness between 2 micrometers and 200 micrometers. A cap/barrier layer (not shown) may be selectively formed on the thick metal layer 8012 by electroplating or electroless plating. An assembly/contact layer (assemb丨y/c〇mact layer, not shown) may also be further selectively formed on the thick metal layer 8012 and the barrier/barrier layer by electroplating or electroless plating. The assembly/contact layer can be: a gold layer, a palladium layer or a layer of germanium having a thickness between 0.01 microns and 5 microns. Next, as shown in Fig. 15G, the photoresist layer 71 is removed. Continuing, in Figure 15H, the adhesion/barrier/seed layer 8011 that is not covered by the thick metal layer 8012 is removed by self-aligned wet or dry etching. When the removal by wet etching is performed, 'undercut 8011' is formed at the bottom of the sidewall of the patterned metal layer 801, wherein the depressed portion 8011' is located below the thick metal layer 8〇12, and when the anisotropic is used In the case of an anis〇tr〇pies dry etch, there is no such thing as the depression 8011. Please also refer to FIGS. 151 and 15J for the steps of forming a polymer layer 98 and patterning metal reed 802 by the process described in FIG. 15 to FIG. 15H. The process shown in FIG. 151 and FIG. 15J may be repeatedly used to form a third metal layer, a fourth metal layer or more metal layers. If the structure 8 above the protective layer includes only two metal layers (patterned metal layer 8) 〇1 and the patterned metal layer Lu 8〇2), a cap polymer layer" deposited on the patterned metal layer 101

MEGA 06-015TWB 802 (now the topmost) and polymer layer 98 not covered by patterned metal layer 8〇2, as shown in Figure 15K. The polymer layer opening is formed in the top polymer layer 99 and exposed as a contact interface for connecting an external circuit. In some applications, the top polymer layer 99 may optionally be omitted, such as when thick gold is used as gold. Fig. 15K reveals that the wafer having both the fine wiring structure 6 and the structure 8 above the protective layer is opened by the polymer layer opening _ of the top polymer layer 99. The wafer ore is cut (cut) into a plurality of individual wafers, and the contact pad surface of the individual wafers can be connected to an external circuit by means of a lower contact, which is: (1) a wire bonding wire of one wire manufacturing process (gold wire, Ming wire) Or copper wire); (2) bumps on other substrates (gold bumps, steel bumps, solder bumps or other metal bumps), which may be Shi Xi wafer, Shi Xi base, pottery base, organic a substrate, a ball grid array (BGA) substrate, a flexible (_clear substrate, a flexible tape or a glass substrate), and the bumps on the substrate are between 1 micron and Between 30 microns, preferably between 5 microns and 2 microns; (3) Columns on other substrates (gold, copper, solder or other metal columns), the substrate can be a germanium wafer, a germanium substrate, a ceramic substrate, an organic substrate, a spherical grid array (BGA) substrate, a flexible substrate, a flexible tape or a glass substrate, and located on the substrate The height of the cylinder is between 1 μm and 200 μm' and between 3 〇μm and 丨2 〇μm Preferably, (4) a lead frame or a bump on a metal wire end of a flexible tape (flexibie tape) (gold bump, copper bump, solder bump or other metal bump) ), this base

The height of the bumps on MEGA 06-015TWB is between Cong and 3G microns, and between 5 microns and 2 microns is preferred. In some applications, the contact structure 89 formed on the contact pad surface can be used for connection. The 卩 circuit is as shown in the first figure. A bump underlayer metal layer is formed under the contact structure 89, and the rib acts as an adhesion and diffusion barrier. The contact structure 89 can be: (1) a solder pad formed by electroplating or screen printing (thickness is 〇·1) Fresh to 30 microns, preferably between 丨 micro green (1) micron), or solder bumps (between 1 〇 micron and 2 〇〇 micron, and 3 〇 micron) To 2) between the micron is preferred). Then, using a reflow process (four), such as reflow process, it is formed into a spherical ball of sputum. The sputum will be soldered or the solder bumps can be: 1. High-distortion solder (scream (10) (10) (four), For example, tin-lead alloy (pbSn) containing more than 85% by weight of lead component; 2 eutectic solder, such as tin-lead alloy containing about 37% by weight of lead component and about 63% by weight of solder component; 3. Lead-free solder (1 from (1_& sink 5〇1 as 1), such as tin-silver alloy (SnAg) or tin-copper-silver alloy (SnCuAg). Further, the under bump metal layer 891 may be a composite as described below Layer (from bottom to top), including: titanium / record, titanium / copper / nickel, titanium tungsten alloy / record, titanium tungsten alloy / copper / record, titanium / record / gold, titanium / copper / nickel / gold, Titanium-tungsten alloy/nickel/gold, titanium-tungsten alloy/copper/nickel/gold, titanium/copper/nickel/palladium, titanium-tungsten alloy/copper/recorded/copper, chromium/chromium-copper alloy, nickel-vanadium alloy/copper, nickel/ Copper, nickel-vanadium alloy/gold, nickel/gold or nickel/bar; (2) gold pads formed by electroplating (thickness between 01 micron and 1 micron, and between 1 micron and 5 micron) Better Or gold bumps (height between

MEGA 06-015TWB is between 5 microns and 40 microns, and preferably between 10 microns and 20 microns. In addition, the under bump metal layer 891 may be: titanium, titanium alloy, group, nitrided layer, titanium/copper/nickel composite layer (from bottom to top) or titanium tungsten alloy/copper/recorded composite layer (Arrangement from bottom to top); (3) Metal ball formed by ball mounting. The metal ball may be a solder ball, a copper ball coated with a nickel layer on the surface, a copper ball coated with a nickel layer and a solder layer, or a nickel layer and a gold layer coated on the surface. a copper ball. Further, the diameter of the metal sphere is between 1 Å and 500 μm, and preferably between 50 μm and 300 μm. In addition, the metal ball may be directly soldered on the surface of the contact pad 8000 exposed by the polymer layer opening 990 or on the under bump metal layer 891, and the under bump metal layer 891 formed to solder the metal ball may be Composite layers (from bottom to top) as described below, including: titanium/nickel, titanium/copper/nickel, titanium tungsten alloy/nickel, titanium tungsten alloy/copper/nickel, titanium/nickel/gold, titanium /copper/nickel/gold, titanium tungsten alloy/nickel/gold, titanium tungsten alloy/copper/record/gold, titanium/copper/nickel/palladium, titanium tungsten alloy/copper/nickel/palladium, chromium/chromium copper alloy, nickel Vanadium alloy / copper, nickel / copper, nickel vanadium alloy / gold, nickel / gold or nickel / K. In addition, after the metal ball is adhered, a s〇lder reflow process is usually required. After the contact structure 89 is formed, 'the wafer on the wafer is sliced or cut by sawing or cutting' to perform package miscellaneous to be connected to the parallel circuit, wherein the method of assembly may be wire bonding (connecting to external organic, ceramic, glass) The pendant on the substrate is either connected to the lead frame or the flexible tape, the tape automatic bonding (TAB), the tape reel (9) *^(taPe_ehiP_earrier· 'TCP), glass-sealed 1344686

MEGA 06-015TWB (COG), crystal >; direct package (c〇B), flip-chip array substrate flip-chip package (under-bGA substrate), film flip-chip bonding (c〇F), thin film flip chip package (〇 〇 n flex) stacked 曰曰 片 package structure (chip_〇n chip he into interc〇nnecti〇n), 矽 substrate stacked chip package structure (chip_〇n_Si substrate possible connection) and so on. In the embossing process shown in the UC to the first drawing, the step of exposing the formed-patterned metal layer is to form the adhesion/barrier/seed layer once, and then to form a photoresist layer. And the plating of the patterned metal layer is also only once, and finally the photoresist layer is removed and the wire side gold/overlay/turn/xuan layer is removed. This type of process is called a single embossing process (singl_b〇ss process), which means that the process includes only one lithography process and one time before removing the adhesion/transfer/seed layer covered by the unreversed metal layer. Electroplating process.

A double-embossing process can be formed by the same-persuasion/barrier/seed layer-patterned metal layer and a metal plug (9) (4), while removing the adhesion not covered by the patterned metal layer Before the barrier/seed layer, complete the two a lithography process and the electro-mine process 'the first lithography process and electricity: two to form the patterned metal layer' and the second lithography process and electroplating process : At the same time, please refer to Figure 16A, Figure 16D, which reveals that the structure above the protective layer is formed on the wafer 1() shown in Fig. 15B. The double embossing process has the same single process as shown in Fig. 15C to Fig. 15G = the same 105 1344686

MEGA 06-015TWB

Production steps. In Figure 15G, it removes the photoresist and leaves the transition/seed layer that is not under the thick metal layer. The double embossing (4) step starts from the early sub-convex process, please At the same time, as shown in Fig. 16a to the chaotic diagram, it is revealed that the pattern metal layer is formed by using the double embossing process and the metal plug is just the same as the metal plug 8 and the use of a single embossing system is the best gold system. The method of 2: forming an example of the structure of the brewed metal layer above all of the radiation protection layers of the present invention is completely inferior to the shadow process and the quota (4) of the metallization layer 1 as shown in the first to the fifteenth. Then, please refer to the 'Funding/Blocking/Seed Layer 8 (4) seed layer and the thick metal layer 8G12 formed by the electric ore to form the 'deposition-new layer 72' and the photoresist The layer 72 is patterned to make the photoresist layer 72: (1) forming a photoresist layer on the thick metal layer and exposing the thick metal layer_2 by using the photoresist layer opening 720; and/or () bonding a photoresist layer opening emblem is formed on the seed layer of the barrier/seed layer_

The seed layer of the adhesive/morph/seed layer was exposed using this light π 720'. Continued before the photoresist layer 72 is removed, a second electroplating process is performed to open the metal plug 898 within 72 开 of the photoresist layer. In addition, the type of adhesion/barrier/seed layer 8011

The metal layer 898 can also be formed on the sub-layer to have a horizontal level lower than that of the metal plug. The metal layer 898 may be thinner than the thick metal layer 8012 or may be thicker than the thick metal layer. When the thickness of the metal layer 898' is less than the thickness of the thick metal layer 8012, for example, less than 5 microns (in the preferred case) Is between! Micron to 3 micro*) 'Metal layer can be finer than thick metal layer 8012 106 8 1344686

MEGA06-015TWB is a high-density connection, however, when the thickness of the metal layer is greater than the thickness of the thick metal layer 8012, for example, greater than 5 microns (preferably between 5 microns and 1) Between the micron), the metal layer 898 can be used to make a lower resistance than the thick metal layer 8012. Then, referring to FIG. 16c, the photoresist layer 72 is removed to expose the thick metal layer 8012, the metal plug 898, the metal layer 卯8, and the adhesion under the thick metal layer 8012 and the metal layer 898. Barrier/seed 8〇n. Referring to Figure 16D, the adhesion/barrier/seed layer 801 under the thick metal layer 8012 and the metal layer 898 is removed by using the wet etch and/or the dry etch. The patterned metal layer 80, the metal plug 898 and the metal layer 898, are formed in this stage as shown in Fig. 16D. Continuing to see Figure 16E, a polymer layer 98 is formed over metal plug 898, metal layer 898, patterned metal layer 8 and exposed first polymer layer 95. Referring to Figure 16F, the surface of polymer layer 98 is planarized by a grinding, mechanical or chemical mechanical polishing process until metal plug 898 is exposed. Further, please refer to the description of Fig. 16G to Fig. ́, which shows the fabrication steps of forming a patterned metal layer 802 by the same single embossing process as described in the first to the first FIG. Continuing, refer to the final deposition and patterning of a top polymer layer 99 as shown in Figure 16L to complete a protective layer over structure 8 having two patterned metal layers 801, 802. In addition, a contact structure 89 may be formed on the contact pads 8 (8) exposed by the polymer layer openings 990, as shown in the figures, on the assembly and/or the package. In addition, the first 15D to 15G and the 16A to the i6D are used to form the pattern 1344686

MEGA 06-015TWB metal layer 801 and metal plug 898 double embossing process can also be used to form a second patterned metal layer (topmost metal layer) and a second metal plug (not shown) The second metal plug can be used as a contact structure for connection to an external circuit. Finally, the description and illustration of Figures 16A through 16L are applicable to all embodiments of the present invention. Referring to FIGS. 17A to 17J, a process step of forming a patterned metal layer 8 (H, a patterned metal layer 8〇2, and a patterned metal layer 803) is disclosed. The patterned metal layer 801 and the patterned metal layer 8〇2 are formed by a double embossing process, and the patterned metal layer 8〇3 is formed by a single embossing process. First, as shown in FIG. 15D 15G and 16A to φ16D, 'the first double embossing process is used to form the patterned metal layer 801 and the metal plug 898. Then, as shown in FIGS. 16E to 16F In the step, after forming a polymer layer 98, the polymer layer 98 is planarized until the metal plug 898 is exposed. Continue to see the process steps before forming the patterned metal layer 802 as shown in FIG. Figure 16F is the same as the process of forming the patterned metal layer 801, the metal plug 898 and the polymer layer 98 by a double embossing process. However, in order to accommodate an additional metal layer, the patterned metal layer 8A of Figure 17A Slightly ground with the design of the metal pick 898 The design of the patterned metal layer 801 of the i6F is different from that of the metal plug 898. In addition, please refer to FIGS. 17A to 17G, and repeat the 15D to 15G and 16A to 16D. The process steps illustrated to form a patterned metal layer 8〇2, a metal plug 897, and a polymer 108 8

MEGA 06-015TWB layer 97, and metal plug 897. In the mth figure, it is formed in the following manner: (1) deposition--resistance_sub-layer; (2) deposition of a photoresist layer; (3) electroplating of a thick metal layer 8 〇 22 in the photoresist layer The first resist layer is removed to form a structure as shown in FIG. 17A. Then, as shown in FIG. 17B, the photoresist layer 74 is deposited and patterned to form a photoresist barrier on the thick metal layer 8〇22, or directly forms the photoresist layer opening 740, in the adhesion/barrier. / Seed layer on the seed layer. Referring to the first sinking diagram, the opening of the photoresist layer 74 〇 and the photoresist layer are formed by means of a key, and a metal check layer and a metal layer are formed therein, and the metal layer 897 can be used as a domain metal layer 898. Referring to FIGS. 17D to 17th, the photoresist layer 74 is removed, and the adhesion/barrier/seed layer 8021 which is not under the thick metal layer 8〇22 and the metal layer 897 is removed. Please read the pattern of the 17F to the i7G at the same time, and then deposit the polymer layer % and planarize the polymer layer 97 until the metal plug 897 is exposed. Next, please refer to the 17th to 171th drawings, which reveals the steps of using a single embossing to lift/form the patterned metal layer, as described below. (1) Deposit adhesion/resistance chapter / seed layer (four); (2) deposited and patterned - level layer; (3) enamel into a thick metal layer 8032; and (4) remove the photoresist layer, and remove it by self-aligned etch (sdf life & e (four) Adhesion of the thick metal layer 8〇32/(! and the barrier/seed layer 8〇31. Finally, as shown in the mth figure, it is revealed by depositing a top polymer layer 99' and bribing the top polymerization. 99 alkali polymer layer opening exposed as 1344686

MEGA 06-015TWB is a complete structure for one of the external circuits connected to the external circuit 8000 for the connection. Referring to FIGS. 18A to 181, another process step of forming a patterned metal layer 80 and a patterned metal layer 802 and a patterned metal layer 803 is disclosed. 8〇1 and patterned metal layer 803 are formed by a single embossing process, while the second metal layer is utilized by a pair

The embossing process is formed. First, referring to Fig. 18A, the patterned metal layer 8〇1 is formed by a single embossing process as described in Figs. 15D to 15H. Next, in the process step described in FIG. 151, a polymer layer 98 is deposited and the polymer layer 98 is subjected to a chemical composition, and then the polymer layer opening 98 () exposes the patterned metal layer 80. In order to accommodate an additional metal layer, the patterned metal layer of the i8A pattern is slightly different from the design layer of the polymer layer σ _ and the patterned metal I 801 and the polymer layer opening 98 第 of the (5) figure. Different. Referring again to FIGS. 18 to 18G, the process steps of forming a patterned metal layer and a metal plug 897 using a double embossing process are disclosed and described as follows: (1) Please refer to FIG. 18B As shown, the deposition forms an adhesion/resist layer 8021; (2) see the 丨% photoresist layer 72, and patterned the photoresist layer lamp, followed by a thick metal layer 8022 in the contact layer 7; (3) Removal of light - two structures as shown in Fig. 18D.傅 傅 来 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明 明

The MEGA 06-015TWB is on the layer 8022 and/or forms the photoresist layer opening 73A on the seed layer of the adhesion/barrier/seed layer φ 8021. Continuing with the manner of electroplating, a metal plug 897 and a metal layer 897' are formed in the photoresist layer openings 730, 730, and the metal layer 897' can be used as the metal layer 898 as described in FIG. 16D. , the same use. Referring to Figs. 18F to 18G, the photoresist layer 73 is removed, and the adhesion/barrier/seed layer 8〇21 which is not under the thick metal layer 8022 and the metal layer 897' is removed. Referring to Figure 18H, a polymer layer 97 is deposited and the polymer layer 97 is planarized until the metal plug 897 is exposed. Finally, referring to FIG. 181, it is revealed that the patterned metal layer 803 is formed by the single embossing process described in FIGS. 17H to 171, and a top polymer layer 99 is deposited and patterned. The top polymer layer 99 forms a polymer opening 990 exposing a complete structure that is connected as a connection line to one of the contact pads 8 of the external circuit. . Referring also to FIGS. 19A to 19G, the process of forming a protective layer upper structure 8 on the wafer 10 as shown in FIG. 51 or FIG. 15B is revealed, wherein the patterned metal layer 8 is patterned. 1 is formed by a double embossing process, and the patterned metal layer 8 〇 2 is formed by a single embossing process. First, in the first embodiment, the double embossing process steps described in the 15D to 15G and the 16A to 16F are used to form the patterned metal layer 8 and the metal layer 8 and the metal layer, and Polymer layer 98. Next, please refer to the same figure as shown in the figure, which uses the same single embossing process as described in Figures 15C to 15K to form a pattern 111 (s) 1344686 ^ΕΟΑΟδ-Ο^χψΒ

The metal layer 8〇2, the polymer layer 97, the top polymerization and the polymer layer opening 990 expose the contact pads 8〇〇〇, and will not be described in detail herein. Finally, as shown in Figure 19, the wafer is sawed (diced) into a plurality of individual a-chips and connected to external circuits through contact pads 8000 on separate wafers, such as wire bonding wires using wire bonding processes (eg Gold wire, wire or copper wire) is connected to an external circuit. Next, please refer to FIG. 21A to FIG. 21M, which are detailed in the dynamic randomness of the present invention in combination with the above-mentioned various implementations of the structure above the ore layer.

access. The example of the memory (DRAM) s on the film. First, as shown in FIG. 21A, in the wafer 1 () shown in FIG. 15A or FIG. 5A, there are # complex dynamic random access memory cells (not shown), and the plurality of chip external circuits 40 The alpha and complex internal circuits 20, and at least one electronic fuse 25 and at least one laser fuse (laser 26) are formed in the fine line structure 6 of the wafer ω, and the fine circuit structure 6 includes There are four contacts, which are the first contact, the second contact,

The third contact and the thin contact (not shown), the sub-protection _ 25 includes a first end point and a second end point (not shown) and the first end point of the electronic fuse 25 The second end point is respectively connected to the first contact and the second contact of the thin circuit structure 6 (for example, a first contact and a second contact of one of the first thin circuit metal layers in the fine circuit structure 6), In addition, the laser fuse 26 also includes a first end point and a second end point (the first end point and the second end point of the laser wire 26 are connected to the third line of the fine line structure 6 respectively. The contact point and the fourth contact point (for example, a second thin line metal layer in the fine line structure 6 - the first contact point and the second contact point), as for the relevant wafer ι〇8 1344686

For the structure and formation method of MEGA 06-015TWB, please refer to the contents of the above figure, and the internal circuit 2 provided on the substrate 〇1, please refer to the part of the series of internal circuits 2〇's external circuit 4 For the part of the 〇, please refer to the relevant part of the third embodiment for the external circuit of the wafer. In the above, the electronic fuse 25 is a polysilicon layer 251 having a thickness of between 2 Å and 2 Å, and is located on the polysilicon layer 251 and has a thickness of 'I1. 000 angstroms to 3, a metal stone between the 〇〇〇 ( 五 五 五 五 五 五 丨丨 层 层 层 层 层 层 252 252 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中25 The sheet resistance before unburning is between ohm and 15 ohms, and further has an insulating layer on the electronic fuse, the wire 25 and/or the dielectric constant less than 3, φ the insulating layer comprises a Oxime compound. In addition, the material of the laser fuse 26 includes copper, aluminum or polysilicon, and an opening 526 of the protective layer 5 is formed on the laser fuse 26, and the opening 526 exposes the niobium oxide located on the laser fuse 20 ( siliC0n oxide) layer (not shown). The next wafer electrical test was performed 'before continuing the next step' to find the perfect grain, completely bad grain and repairable grain in the wafer 10, and the repairable crystal The laser is repaired by laser (laser repairp laser repair is in the form of a laser-based laser fuse 26, causing the first end of the laser fuse 26 to form an open circuit with the second end point) as shown in Fig. 21B. The repaired crystal grains become completely fine crystal grains. Next, please refer to FIG. 21C to form a metal layer 95 in the protective layer Φ 5, the protective layer opening 5 暴露 exposed metal pads _ and the opening 526 Exposed 113 8 1344686

The oxidized stone layer Jl' of MEGA 06-015TWB is then patterned to polymerize the polymer layer 95 to form a plurality of polymer layer openings 950. Continuing, see Figure 21D to form an adhesion/barrier/seed layer 8011 on the polymer layer 95 and the exposed portion of the polymer opening 95'. See also Figure 21E for the adhesion/barrier. A patterned photoresist layer 71 is formed on the seed layer 8011, and a thick metal layer 8〇12 is deposited in the photoresist layer opening 710 of the photoresist layer 7丨, as shown in FIG. 21F. Please also refer to the 'removal of the photoresist layer, and then remove the adhesion/barrier/seed layer 8011 which is not under the thick metal layer 8〇' to form the patterned metal layer 801 as shown in FIG. 21G to the first drawing. The patterned metal layer 801 includes a patterned metal layer 8〇ia (including a thick metal layer 8〇12& and an adhesion/barrier/seed layer 8011a) and a patterned metal layer 8〇b (including a thick metal layer 8012b and adhesion/resistance). Barrier/seed layer 8〇Ub). Wherein, the patterned metal layer is used to interconnect the internal circuit 20' and allow the internal circuit 20 to transmit signals or data through the patterned metal layer, or to supply the power required by the internal circuit 20 by the patterned metal layer 801a. The patterned metal layer 8 lb is used as a reconfiguration line to reposition the metal pads 600 connecting the wafer external circuitry 40 to a different location of the contact pads using the reconfiguration circuitry. Referring to FIG. 211, a top polymer layer 99 is formed on the exposed polymer layer 95 and the patterned metal layer 8〇1 (including 8〇丨& and 801b), and then the top polymer is patterned. Layer 99' exposes a contact pad 8'' to expose the patterned metal layer 801b to an external circuit. Then, “Tk select the second wafer electrical test to find out the complete φ aa grain in the wafer, all the bad grains and the repairable grains, and the wafer is within 1 inch. Repairable 114 1344686

MEGA 06-015TWB die for electronic repair ^, the way is in the fresh to the brain micro-attack t time to add a current to the 〇. 〇 5 amp to 2 amps through the electronic fuse Gong to the woman to _ women When _, 丝松αι魏至〗 ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ The current between the first end point and the second end point of the electronic fuse 25 is transmitted through the polycrystalline layer (5), and the metal slab layer 252 forms an open circuit, as shown in Fig. 21J, allowing repairable _ The grains become completely fine grains. At this time, the sheet resistance of the electronic wire entangled is between K) 〇 ohm to 1G, _ ohm. Then, after the scratching (four) ore cutting (cutting step 3 ' can also be performed on the wafer sawing (the selective third wafer selection to find out the complete fine grain in the wafer, completely Bad grains and repairable grains. Mouth month> No. 21K does not 'complete the wafers (10) J of the structure above the protective layer into a plurality of wafers 10, and the wafers are 1 〇, The contact pads _ 〇 can be connected to the external circuit by using the wire of the rug line process (gold wire, Ming wire or steel wire), and at this time, the third wafer electrical test can be selectively found completely. The bad grain in the crystal_cut (_) is the next step in the province to save the cost of sealing on the completely bad grain. Please refer to the melon figure, using an adhesive layer (four) wafer 1 〇 疋On a package substrate, such as the organic substrate 13, followed by a wire bonding step of "connecting the contact pads and the pads" with a dozen wires, and continuing the bonding step (eg, ball-to-array package, BGA) to - Encapsulation layer 17 package is fixed at 115 1344686

MEGA 06-015TWB Wafer i on the organic substrate 13. Further, the wafer (1) fixed on the organic substrate 13 may be a stacked wafer of two wafers 1' or a plurality of wafers 1'. Please refer to the same figure as the two wafers 1G'---------------------------------------- The top surface and the same-pad 15 are provided, but the wire bonding wires 89 of the two wafers may be connected to different interfaces 15 instead of the same interface 15. In addition, the above package substrate may also be a lead frame, and the material of the pad is 矽, such as 矽 or copper.凊Refer to Figure 21N, which is a schematic top view of the application of the 21st L picture in a dynamic random access memory. As shown in the figure, a dynamic random access memory has an input/output interface. In the case of the memory access device of the memory access device, however, using the chip 1' shown in Fig. 21L, the dynamic random access memory can be transmitted through the patterning of the reconfigured line as the secret cell _man/transmission (four)塾Reconfigure the sniffing/transmission doping, so that the dynamic random access counter can be used in the wire bonding in the stencil (such as stacked package). - Performing the first wafer electrical test after completing the packaging step, and screening out the two good wafers 10', the completely bad wafers 10' and the repairable wafers 10', and then prepending the good 4 10' After baking (bum_in), and after the wire is pre-fired, the Japanese wafer 1 is again tested and the type 5 is selected to select a wafer of good quality. As for the first wafer electrical test - the repairable wafer 1G, the above-described electronic repairing step is performed again to make the repairable wafer 1G' into a good wafer 1G, and then optional 116 1344686

MEGA 06-015TWB Secondary wafer electrical test to select a wafer that has indeed become a good one, continue to turn this into a good wafer 10' for pre-burning' and after the pre-burning is completed, the wafer is re-fired. Test to pick out a good quality wafer 10,. The above method and the detailed description can be applied to the random access memory, which can also be considered on other _ (4), such as fast memory, static random access memory, or application in a logic. (丨ogic) on the wafer. [Simple diagram of the diagram] • Figure 1A is a schematic diagram of a circuit with a regulator or transformer. FIG. 1B is a schematic diagram of a circuit having a voltage regulator or a transformer according to the present invention. The first ic diagram is a circuit diagram of the structure of the present invention using the metal line or plane above the protective layer to transport the NMOS and the ground reference voltage Vss. φ Figure 2A is a top plan view of a conventional voltage regulator or transformer. 2B is a top plan view of the present invention having a voltage regulator or transformer. 2C is a top plan view showing the structure of the metal line or the plane above the protective layer and the ground reference voltage Vss. Figure 3A is a schematic cross-sectional view of a conventional voltage regulator or transformer. Figure 3B is a schematic cross-sectional view of a voltage regulator or transformer of the present invention. Figure 3C is a schematic cross-sectional view showing the structure of the metal line or plane transport voltage and the ground reference voltage Vss over the protective layer of the present invention. Figure 3D is a schematic cross-sectional view of a voltage regulator or transformer of the present invention. • Figure 4 is a transformer of the present invention. Figure 5A is a circuit diagram of a conventional internal circuit. 117 5 1344686

MEGA 06-015TWB Figure 5B is a circuit diagram showing a second embodiment of the present invention. ^ Figure 5C is an inverter of the present invention. Figure 5D is an internal drive of the present invention. Figure 5E is an internal tristate buffer of the present invention. Figure 5F is a circuit diagram showing a memory cell of the present invention connected to an internal circuit through an internal tristate buffer, a metal line or plane on the protective screen, and a thin line metal structure under the protective layer. The Luthe 5G diagram is a circuit diagram of a memory cell of the present invention connected to an internal circuit through a circuit, a metal line or plane on the protective layer, and a thin line metal structure under the protective layer. Figure φ is a circuit diagram showing a memory cell of the present invention connected to an internal circuit through a latch circuit, a metal line or plane on the protective layer, and a thin line metal structure under the protective layer. Figure 51 is a circuit diagram showing a memory cell of the present invention connected to an internal circuit through a circuit, an internal driver, a metal line or plane on a spring layer, and a thin line metal structure under the protective layer. Figure 5J is a circuit diagram showing a memory cell of the present invention connected to an internal circuit through a latch circuit, an internal driver, a metal line or plane on the protective layer, and a thin-line metal structure under the protective layer. Section 5K: Figure is a circuit diagram of a second embodiment of the present invention. Figure 5L is an internal receiver of the present invention. (Dj 118 1344686

MEGA 06-015TWB Figure 5M is an internal tristate buffer of the present invention. The fifth 5N is a circuit diagram showing the internal circuit of the present invention connected to a memory cell through a fine-line metal structure under the protective layer, a metal line or plane on the protective layer, and an internal tri-state buffer. Figure 50 is a circuit diagram showing an internal circuit of the present invention through a thin-line metal structure under a protective layer, a metal line or plane on a protective layer, and a circuit connected to a memory cell. Lu 5th is a schematic diagram of a circuit in which an internal circuit of the present invention is connected to a memory cell through a thin-line metal structure under the protective layer, a metal line or plane on the protective layer, and a latch circuit. $5Q is a schematic diagram of a circuit in which an internal circuit of the present invention is protected by a thin circuit metal structure under a protective layer, a metal line or plane on the germanium layer, an internal receiver, and a circuit connected to a memory cell. The figure is a schematic diagram of a circuit in which an internal circuit of the present invention is connected to a memory cell through a thin circuit metal junction under a protective layer, a metal line or plane on a layer, an internal receiver, and a flash lock circuit. Fig. 5S is a circuit diagram showing the use of a metal circuit or a planar connection analog circuit above the protective layer in the present invention. Figure 5T is an operational amplifier of the present invention. Figure 6A is a top plan view of a conventional internal circuit. ♦ Figure 6B is a top plan view of a second embodiment of the present invention. 119 1344686 MEGA 06-015TWB Figure 7A is a schematic cross-sectional view of a conventional internal circuit.

Cross-sectional view of the cased metal layer Fig. 7B is a view showing a single layer of the second embodiment of the present invention. Figure 7C. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 7D is a cross-sectional view showing a cross-sectional schematic layer and a bottommost patterned metal layer having two patterned metal layers according to a second embodiment of the present invention, which is a cross-sectional view showing a polymer layer between guards according to a second embodiment of the present invention. Figure 8A is a circuit diagram of a conventional wafer.

Figure 8B is a circuit diagram showing a third embodiment of the present invention. Figure 8C is a circuit diagram of a third embodiment of the present invention. Figure 8D is a circuit diagram showing a third embodiment of the present invention. Figure 8E is a circuit diagram showing a third embodiment of the present invention. Figure 8F is a circuit diagram showing a third embodiment of the present invention. Figure 9A is a top plan view of a conventional wafer. Figure 9B is a top plan view of a third embodiment of the present invention. Figure 9C is a top plan view of a third embodiment of the present invention. Figure 9D is a top plan view of a third embodiment of the present invention. Figure 10A is a schematic cross-sectional view of a conventional wafer. Figure 10B. A cross-sectional representation of a single layer patterned metal layer in accordance with a third embodiment of the present invention

120 1344686

MEGA 06-015TWB FIG. 10C is a schematic cross-sectional view showing a two-layer patterned metal layer according to a third embodiment of the present invention. FIG. 10D is a third embodiment of the present invention in the bottom layer of the protective layer and the single-layer patterned metal layer. A schematic cross-sectional view of a polymer layer. Figure 10E is a schematic cross-sectional view showing a polymer layer between a protective layer and a bottom layer of two patterned metal layers in accordance with a second embodiment of the present invention. Figure 10F is a schematic cross-sectional view of a conventional wafer having a wire bond. • Fig. 10G is a schematic cross-sectional view showing a third embodiment of the present invention having a wire bonding. Fig. 10H is a schematic cross-sectional view showing a wire bonding according to a third embodiment of the present invention. Figure 101 is a cross-sectional view showing a third embodiment of the present invention having a wire bonding. Φ Figure 11 is a wafer external drive of the present invention. Figure 11 is a wafer external receiver of the present invention. The UC diagram is a wafer tristate buffer of the present invention. Figure 11D is a wafer external drive of the present invention. Figure 11E is a wafer tristate buffer of the present invention. Figure 11F is an electrostatic discharge protection circuit of the present invention. Figure 11G is a series drive of the present invention. The 12A _f knows that the external power supply directly inputs the voltage to the internal circuit and has a circuit diagram of the voltage or current surge generated by the external supply of the electrostatic discharge protection circuit. Figure 12B is a circuit diagram showing a fourth embodiment of the present invention. 121 1344686

MEGA 06-015TWB The first to the first is the structure of the upper layer of the protective layer of the present invention.

The figures to the first embodiment form the structure above the protective layer of the present invention. Fig. 20 is a cross-sectional view of the present invention. Spears Steps 21A to 21M are diagrams showing the flow of the present invention in consideration of dynamic random access memory. Figure 21N is a top plan view of the present invention applied to a dynamic random access memory. [Main component symbol description] 1 substrate 2' gold oxide semi-transistor 6 fine circuit structure 1 〇 wafer u adhesive layer 15 connection high pad 21 internal circuit 23 internal circuit 25 electronic fuse 30 fine line dielectric view 4〇 Wafer Outer Circuit 42 Wafer Outer Circuit 44 Electrostatic Discharge Protection Circuit 2 Component Layer 5 Protective Layer 8 Protective Layer Above Structure 10' Wafer 13 Organic Substrate 17 Package Layer 20 Internal Circuit 22 Internal Circuit 24 Internal Circuit 26 Laser Fuse 30' Opening 41 voltage regulator or transformer 43 chip external circuit 45 electrostatic discharge protection circuit 123 (S)

1344686

MEGA 06-015TWB 50 protective layer opening 60' conductive plug 61' fine line metal structure 63 fine line metal structure 69 fine line metal structure 72 photoresist layer 74 photoresist layer φ 81 metal line or plane 83 metal line or plane 83t reconfiguration Metal line 89' wire conductor Lu 90 polymer layer 97 polymer layer 99 top polymer layer • 201 source 203 gate 212 internal driver 213 internal tristate buffer 214 sense amplifier 216 through circuit • 217 latch circuit 60 Fine line metal layer 61 fine line metal structure 62 fine line metal structure 66 metal top layer 71 photoresist layer 73 photoresist layer 80 patterned metal layer 82 metal line or plane 83r • metal line or plane 89 contact structure 89t tin boat bump 95 Polymer layer 98 polymer layer 200 internal structure 202 drain 211 inverter 212' internal receiver 213' internal tristate buffer 215 static random access memory unit 216' through circuit 217' latch circuit 124 1344686

MEGA 06-015TWB 218 Operational Amplifier 251 Polysilicon Layer 252' Notch 410 Reference Voltage Generator 421 Wafer Outer Driver 421" Second Stage 422' First Stage 511 Protective Layer Opening 514 Protective Layer Opening 519' Protective Layer Opening 522 Protective Layer Opening 526 opening 531 protective layer opening 532 protective layer opening 534 protective layer opening 539 protective layer opening 549 protective layer opening 559 protective layer opening 600 metal pad 602 fine line metal layer 602y fine line metal layer 219 differential circuit 252 metal germanium layer 400 wafer External structure 410' current mirror circuit 421' first stage 422 wafer external receiver 422" second stage 512 protective layer opening 519 protective layer opening 521 protective layer opening 524 protective layer opening 529 protective layer opening 531 'protective layer opening 532 'Protective layer opening 534' protective layer opening 539' protective layer opening 549' protective layer opening 559' protective layer opening 601w fine line metal layer 602x fine line metal layer 602z fine line metal layer 125 1344686

MEGA 06-015TWB 611 fine line metal structure 612a fine line metal structure 612c fine line metal structure 618 fine line metal structure 619' fine line metal structure 622 fine line metal structure 622b fine line metal structure 624 fine line metal structure 631 fine line metal structure 632 fine line metal structure 632b fine line metal structure 632a' fine line metal structure 632c' fine line metal structure 634' fine line metal structure 639 fine line metal structure 649 fine line metal structure 659 fine line metal structure 661 metal top 664 metal top 669 'Metal top layer 720 photoresist layer opening 612 fine line metal structure 612b fine line metal structure 614 fine line metal structure 619 fine line metal structure 621 fine line metal structure 622a fine line metal structure 622c fine line metal structure 629 fine line metal structure 631' Fine line metal structure 632a fine line metal structure 632c fine line metal structure 632b, fine line metal structure 634 fine line metal structure 638 fine line metal structure 639' fine line metal structure 649' fine line metal structure 659' fine line metal structure 662 metal Top 669 metal Layer 710 photoresist layer openings 720 'wide photoresist layer openings S) 126 1344686

MEGA 06-015TWB 730 photoresist layer opening 740 photoresist layer opening 8〇1 patterned metal layer 801b patterned metal layer 802 patterned metal layer 802y patterned metal layer 803 patterned metal layer 812 patterned metal layer 831 patterned metal Layer 831b patterned metal layer 832a patterned metal layer 891 bump bottom metal layer 897' metal layer 898' metal layer 980 polymer layer opening 2101 N-type gold oxide semi-transistor 2103 N-type gold oxide semi-transistor 2104P type gold oxygen Semi-transistor 2107N type gold oxide semi-transistor 2109'N-type gold oxide semi-transistor 2111 N-type gold oxide semi-transistor 730' photoresist layer opening 740' photoresist layer opening 801a patterned metal layer 801w patterned metal layer 802x Patterned metal layer 802z patterned metal layer 811 patterned metal layer 821 patterned metal layer 831a patterned metal layer 832 patterned metal layer 832b patterned metal layer 897 metal plug 898 metal plug 950 polymer layer opening 990 polymer layer opening 2102P type gold oxide semi-transistor 2103'N type gold oxide semi-transistor 2104'P type gold oxide semi-transistor 2108 P type gold oxide semi-transistor 2110'P type gold oxide semi-transistor 2112P type gold oxide semi-transistor 127 8 1344686

MEGA 06-015TWB 2113N gold oxide semi-transistor 2115N type gold oxide semi-transistor 2117N type gold oxide semi-transistor 2119N type gold oxide semi-transistor 2121 N-type gold oxide semi-transistor 2123 line selection transistor 2124'N-type gold Oxygen semi-transistor 2126 P-type gold oxide semi-transistor 2128 P-type gold oxide semi-transistor 2129'N-type gold oxide semi-transistor 2130'N-type gold oxide semi-transistor 2132 P-type gold oxide semi-transistor 2134 resistor 2136P Type MOS semi-transistor 4102 P-type gold oxide semi-transistor 4104P type gold oxide semi-transistor 4106P type gold oxide semi-transistor 4108N type gold oxygen semi-transistor 4110P type gold oxide semi-transistor 4112 electric conductive crystal 4201 N-type gold Oxygen semi-transistor 2114P type gold oxide semi-transistor 2116P type gold oxide semi-transistor 2118P type gold oxide semi-transistor 2120N type gold oxide semi-transistor 2122 row selection transistor 2124N type gold oxygen semi-transistor 2125 N-type gold oxygen half Transistor 2127N type gold oxide semi-transistor 2129N type gold oxide semi-transistor 2130N type gold oxide semi-transistor 2131 P-type gold oxide semi-transistor 2133 capacitor 2135N type gold oxide semi-transistor 4101 P-type gold oxide semi-transistor 4103 P Type MOS semi-transistor 4105 P-type MOS semi-transistor 4107N 4109P metal oxide semiconductor transistor-type metal-oxide-semiconductor transistor 4111 electrically conducting crystalline node 4199 4202 P-type metal-oxide-semiconductor transistor 128

1344686 MEGA 06-015TWB 4203 N-type gold oxide semi-electric crystal ^ 4205 N-type gold oxide semi-transistor 4207 N-type gold-bismuth semi-transistor 4204 P-type gold oxide semi-transistor 4206 P-type gold oxide semi-transistor 4208 P-type gold Oxygen semi-transistor 4209N type gold oxide semi-transistor 4331 inverse bias diode 4210P type gold oxide semi-transistor 4332 reverse bias diode 4333 reverse bias diode 6111 fine line metal structure 6121 fine line metal structure _ 612lb fine line metal structure 6141 fine line metal structure 6121a fine line metal structure 6121c fine line metal structure 6190 metal joint 6190' metal joint 6290 metal joint 6191 fine line metal structure 6311 fine line metal structure Lu 6321 fine line metal structure 6321a Fine line metal structure 6321b fine line metal structure 6321c fine line metal structure 6341 fine line metal structure 6390 metal joints • 6391 fine line metal structure 6391' fine line metal structure 6490 metal pad 6490' metal pad 8000 contact pad 8011 adhesive / barrier / seed layer 8011 'recess 8011a adhesion / barrier / seed layer 8011b adhesion / barrier / seed layer 8012 thick metal layer 8012a thick metal layer 8012b thick metal layer Lu 8〇2丨 adhesion/barrier/seed layer 8022 thick metal layer 129 129 1344686

MEGA 06-015TWB 8031 Adhesive / Barrier / Seed Layer 8110 Contact Pad 8112 Thick Metal Layer 8121 Adhesive / Barrier / Seed Layer 8211 Adhesive / Barrier / Seed Layer 8310 Contact Pad 8311a Adhesive / Barrier / Seed Layer 8312 Thick Metal layer 8312b thick metal layer 8321 adhesion/barrier/seed layer 8321b adhesion/barrier/seed layer 8322a thick metal layer 9511 polymer layer opening 9514 polymer layer opening 9519' polymer layer opening 9532 polymer layer opening 9539 polymer Layer opening 9549 polymer layer opening 9831 polymer layer opening 9839 polymer layer opening 9919 polymer layer opening 8032 thick metal layer 8111 adhesion/barrier/seed layer 8120 contact pad 8122 thick metal layer 8212 thick metal layer 8311 adhesion/resistance Barrier/Seed Layer 8311b Adhesive/Barrier/Seed Layer 8312a Thick Metal Layer 8320 Contact Pad 8321a Adhesive/Barrier/Seed Layer 8322 Thick Metal Layer 8322b Thick Metal Layer 9512 Polymer Layer Opening 9519 Polymer Layer Opening 9531 Polymer Layer Opening 9534 polymer layer opening 9539' polymer layer opening 9829 polymer layer opening 9834 polymer layer opening 9849' polymer layer opening 9929 polymer layer opening 130 1344686

MEGA 06-015TWB 9939 polymer layer opening 9939' polymer layer opening _ 9949 polymer layer opening 9949' polymer layer opening

131

Claims (1)

1344686 f ibX- jjr/J. Patent application A wafer comprising: a voltage stabilizing element; an internal circuit comprising: a transistor. a broken substrate carrying the rolling element and the internal circuit; a first metal line connecting the voltage stabilizing element And the first metal line comprises a first copper layer having a thickness between 0.2 μm and 丨 micron; a second metal line connecting the internal circuit; an insulating layer on the germanium substrate, the voltage stabilizing element The internal circuit, the first metal line and the second metal line; a plurality of dielectric layers between the stone substrate and the insulating layer; a polymer layer positioned above the insulating layer And the thickness of the polymer layer is between 2 microns and 150 microns, the thickness of the polymer layer is greater than the thickness of each of the dielectric layers; and the second metal line is located above the insulating layer, and the A third metal line connects the first metal line and connects the second metal line, the second metal line including a second copper layer having a thickness between 3 microns and 20 microns. 2. The wafer according to claim 1, wherein when the voltage regulator outputs a voltage value, a difference between the voltage value and a set target voltage value is divided by a percentage of the set target voltage value. Less than 10 〇 / 〇. 3. The wafer of claim 2, wherein the set target voltage value is between 0.5 volts and 1 volt. 132 The internal circuit as described in item 1 of the patent application is -NOR gate. J. As described in the first item of the patent scope - or gate (OR gate).丨 If you apply for the patent scope, the first item is an AND gate. The wafer of claim 1, wherein the internal NAND gate. a chip, wherein the internal circuit is a day-to-day film, wherein the internal circuit is a circuit, such as the wafer of the first item of the patent application, seven + a μ, and the internal circuit is one Static Random Access Memory Unit (SRAM eeU). 9. The wafer of claim 1, wherein the internal circuit is a dynamic random access memory cell (DRAM ce). 1) The wafer of claim i, wherein the internal circuit is a non-volatile memory cell. U. The wafer of claim 1, wherein the internal circuit is a flash mem 〇 cell. 12. The wafer of claim 1, wherein the internal circuit is an erasable programmable read only memory unit (epr〇M ceU). 13. The wafer of claim i, wherein the internal circuit is a ROM cell. The wafer of claim 1, wherein the internal circuit is a magnetic random access memory (MRAM) unit. The wafer of claim 1, wherein the internal circuit is a sense amplifier. 133 15 • The wafer of claim 1, wherein the internal circuit i 7 is an Operational Amplifier. The wafer of claim 1, wherein the internal circuit is an adder. 18. The wafer of claim 1, wherein the internal circuit is a multiplexer. 19. The wafer of claim 1, wherein the internal circuit is a duplexer. 2〇 As described in item 1 of the patent application, wherein the internal circuit is a multiplier. 21. The wafer of claim i, wherein the internal circuit is an analog/digital converter (A/D c〇nverter). 22. The wafer of claim i, wherein the internal circuit is a digital/analog converter (D/A C (10) verterp 23 ‘the wafer of claim i, wherein the internal circuit The CMOS sens〇r cell is a wafer as described in claim 1, wherein the internal circuit is a photo-sensitive diode. 25. The wafer of claim i, wherein the internal circuit is a bi-carrier complementary metal oxide semiconductor (BiCM〇s circuh). 26. The wafer of claim i, wherein the internal circuit is a bipolar circuit unit. 27. The wafer of claim i, wherein the first metal 134 1344686 circuit further comprises a titanium-containing metal layer. 28. The wafer of claim 1, wherein the first metal line further comprises a titanium nitride layer. 29. The wafer of claim i, wherein the first metal line further comprises a button metal layer. The wafer of claim i, wherein the first metal line further comprises a tantalum nitride layer. 31. The wafer of claim 1, wherein the wafer further comprises a fourth metal line above the insulating layer, and the fourth metal line is connected to a ground node of the internal circuit, the second metal line A power supply node is connected to the internal circuit, and the third metal line is connected to the power supply node via the second metal line. 32. The wafer of claim 2, further comprising a fourth metal line above the insulating layer, wherein the fourth metal line is connected to a power node of the internal circuit, the second metal line connection The ground circuit of the internal circuit is connected to the ground node via the second metal line. 33. The wafer of claim 2, further comprising a third copper layer over the third metal line, and the third copper layer has a thickness between 2 microns and 150 microns. 34. The wafer of claim 33, further comprising a titanium-containing metal layer between the third copper layer and the third metal line. 35. The wafer of claim 33, further comprising a titanium nitride layer between the third copper layer and the third metal line. 135 1344686 36. The wafer of claim 33, further comprising a homing alloy layer between the second copper layer and the third metal line. 37. The wafer of claim 33, further comprising a metal-containing layer between the third copper layer and the third metal line. 38. The wafer of claim i, wherein the material of the dielectric layer comprises silica 〇x 〇xide. 39. If you apply for a patent scope! The wafer of the above, wherein the materials of the dielectric layers comprise siHccm nitride. 40. The wafer of claim i, wherein the dielectric layers comprise a silicon oxynitride. For example, in the wafer of claim i, the material of the dielectric layer (4) includes a dielectric material having a dielectric constant value of between 15 and 35. 42. The wafer of claim 1, wherein the insulating layer has a first opening and a second opening, and the third metal line connects the first metal line via the first opening and via the second opening Connecting the second metal line. 43. If you apply for a patent scope! The wafer of item, wherein the third metal line further comprises an m alloy layer ' and the second _ position is above the titanium alloy layer. The wafer of claim 1, wherein the third metal line further comprises a titanium-containing metal layer, and the second copper layer is above the titanium-containing metal layer. The wafer of claim 1, wherein the third metal line further comprises a titanium nitride layer, and the second copper layer is above the titanium nitride layer 136 by 46 lines = profit range The wafer of l3S, wherein the third metal 2 further comprises gold and the second copper layer is above the metal containing group. 47. The first line of the patent application scope also includes a layer of tantalum nitride. 48. The wafer of claim 1, wherein the third metal line further comprises a -containing metal layer and the second copper layer is over the metal-containing layer. 49. The wafer of claim 1, wherein the material of the insulating layer comprises a nitrogen arsenide compound. 50. The wafer of claim i wherein the material of the insulating layer comprises an oxonium compound. The wafer of claim 3, wherein the third metal layer is located on the nitride button layer A, such as the wafer of claim i, wherein the material of the insulating layer comprises a oxynitride compound. . For example, the scope of patent application! The wafer of claim 7, wherein the polymer layer is further positioned between the insulating layer and the third metal line. 53. The wafer of claim i, wherein the transistor is an N-type 〇s transistor, and a channel width of the n-type MOS transistor The channel length ratio is between ο" and 5. 54. The wafer of claim i, wherein the transistor is a P-type PMOS transistor, and a channel width of the p-type gold oxide 137 1344686 semi-transistor. / channel length ratio is between 〇2 to! Between 〇. The team is applying for the patent scope! The wafer of the item wherein the current flowing through the third metal line is between 1 〇〇 microamperes to 丨 milliamperes. 56. The crystal of claim 2, wherein the second metal line is connected to a power supply node of the internal circuit. 57. The wafer of claim 1, wherein the second metal line is connected to a ground node of the internal circuit. 58. If you apply for a patent scope! The wafer of the item wherein the third metal line is not electrically connected to the outside. 59. The wafer of claim i wherein the polymer layer is further on the third metal line. 60. A wafer comprising: a transformer element; - an internal circuit comprising a transistor; - an imaginary substrate carrying the transformer element and the internal circuit; a first metal line connecting the change a pressing member, and the first metal line includes a first copper layer having a thickness between 0.2 μm and 1 μm; a second metal line connecting the internal circuit; an insulating layer positioned on the substrate, the change a voltage element, the internal circuit, the first metal line and the second metal line; a plurality of dielectric layers 'between the substrate> and the insulating layer; a polymer layer' is located in the insulating layer Above the layer, and the thickness of the polymer layer is between 2 microns and 150 microns, the thickness of the polymer layer is greater than the thickness of each of the 138 dielectric layers; and - the third metal line is located Above the insulating layer, the third metal line connects the first metal line and connects the second metal line, the second metal line includes a second copper layer having a thickness between 3 microns and 20 microns. The wafer of the sixth aspect of the invention, wherein the transformer element ♦ the input voltage is converted into an output voltage and the output voltage is different from the input voltage. The wafer of claim 61, wherein the input voltage "the difference between the output voltages divided by the output voltage is greater than 10 〇 / 〇〇 〇〇 专利 专利 专利 专利 专利 , , , , , , , , Wherein the output voltage is between 1 volt and volt volt. 64' The wafer of claim 60, wherein the internal circuit is a NOR gate. The wafer of claim 60, wherein the internal circuit is an OR gate. 66. The wafer of claim 6, wherein the (four) (four) is an AND gate. For example, the wafer described in the scope of claim 6G, wherein the internal circuit is a NAND gate. For example, the term "When the hometown (4) (10) is used, the internal circuit is a static random access memory. Body unit (SRAMcell). [9] The wafer of the above-mentioned patent scope (9), wherein the internal circuit 139 1344686 is a dynamic random access memory cell (DRAM cell). 70. The wafer of claim 60, wherein the internal circuit is a non-volatile memory cell. 71. The wafer of claim 60, wherein the internal circuit is a flash memory cell. 72. The wafer of claim 60, wherein the internal circuit is an erasable read only memory cell (EPROM cell). 73. The wafer of claim 60, wherein the internal circuit is a ROM cell. 74. The wafer of claim 60, wherein the internal circuit is a magnetic RAM (MR AM) unit. 75. The wafer of claim 60, wherein the internal circuit is a sense amplifier. 76. The wafer of claim 60, wherein the internal circuit is an Operational Amplifier. 77. The wafer of claim 60, wherein the internal circuit is an adder. 78. The wafer of claim 60, wherein the internal circuit is a multiplexer. 79. The wafer of claim 60, wherein the internal circuit is a duplexer. 80. The wafer of claim 60, wherein the internal circuit is a multiplier. 81. The wafer of claim 60, wherein the internal circuit 140 1344686 is an analog/digital converter (A/D converter). 82. The wafer of claim 60, wherein the internal circuit is a digital/analog converter (D/A Converter). The wafer of claim 60, wherein the internal circuit is a CMOS sensor cell. The wafer of claim 60, wherein the wafer of claim 60, wherein The internal circuit is a photo-sensitive diode. 85. The wafer of claim 60, wherein the internal circuit is a bi-substrate complementary biCMOS circuit. 86. The wafer of claim 60, wherein the internal circuit is a bipolar circuit unit. 87. The wafer of claim 60, wherein the first metal line further comprises a titanium-containing metal layer. 88. The wafer of claim 60, wherein the first metal line further comprises a titanium nitride layer. 89. The wafer of claim 60, wherein the first metal line further comprises a button metal layer. 90. The wafer of claim 60, wherein the first metal line further comprises a nitride button layer. 91. The wafer of claim 60, further comprising a fourth metal line above the insulating layer, and the fourth metal line is connected to a ground node of the internal circuit, the second metal line connection A power supply node of the internal circuit, the third metal line is connected to the power supply node via the second metal circuit connection 141 1344686. 92. The wafer of claim 9, wherein the fourth metal line is above the insulating layer, and the fourth metal line is connected to a power node of the internal circuit. a ground node of the internal circuit, the third metal line connecting the ground node via the second metal line. 93. The wafer of claim 6 further comprising a third copper layer above the third metal line, and the third copper layer has a thickness between 2 microns and 150 microns. 94. The wafer of claim 93, further comprising a titanium-containing metal layer between the third copper layer and the third metal line. 95. The wafer of claim 93, further comprising a titanium nitride layer between the third copper layer and the third metal line. 96. The wafer of claim 93, further comprising a titanium-tungsten alloy layer between the third copper layer and the third metal line. 97. The wafer of claim 93, further comprising a button metal layer between the third copper layer and the third metal line. 98. The wafer of claim 6, wherein the material of the dielectric layer comprises oxidized stone. The wafer of claim 60, wherein the dielectric layers are made of tantalum nitride. The wafer of claim 60, wherein the material of the dielectric layer comprises nitrous oxide. 101. The wafer of claim 60, wherein the dielectric 142 1344686 layer material comprises a dielectric material having a dielectric constant between 1.5 and 3.5. The wafer of claim 6 , wherein the insulating layer has a first opening and a second opening, and the third metal line connects the first metal line via the first opening and via the The second opening is connected to the second metal line. The wafer of claim 6, wherein the third metal line further comprises a titanium-tungsten alloy layer, and the second copper layer is above the titanium-tungsten alloy layer. 104. The wafer of claim 6 wherein the third metal line further comprises a titanium-containing metal layer and the second copper layer is over the titanium-containing metal layer. 105. The wafer of claim 6 wherein the third metal line further comprises a titanium nitride layer and the second copper layer is over the titanium nitride layer. 106. The wafer of claim 6 wherein the third metal line further comprises a button metal layer and the second copper layer is over the button metal layer. 107. The wafer of claim 6 wherein the third metal line further comprises a nitride layer and the second copper layer is above the nitride layer. 108. The wafer of claim 6 wherein the third metal line further comprises a chromium-containing metal layer and the second copper layer is over the chromium-containing metal layer. The wafer of claim 6, wherein the material of the insulating layer comprises a nitrogen ruthenium compound. 110. The wafer of claim 6 wherein the material of the insulating layer comprises an oxonium compound. 111. The wafer of claim 6 wherein the material of the insulating layer comprises a oxynitride compound. 112. The wafer of claim 6 wherein the polymer layer is further positioned between the insulating layer and the third metal line. 113. The wafer of claim 6, wherein the transistor is an N-type NMOS transistor, and a channel width of the N-type oxy-oxygen semiconductor body. The channel length ratio is between 〇丨 and 5. 114. The wafer of claim 6, wherein the transistor is a P-type PMOS transistor, and a channel width of the P-type MOS solar cell. The channel length ratio is between 〇.2 and 1〇. 115. The wafer of claim 6 wherein the current flowing through the second metal line is between 100 microamperes and milliamperes. 116. The wafer of claim 6 wherein the second gold line is connected to a power node of the internal circuit. 117. The wafer of claim 6, wherein the second gold line is connected to a ground node of the internal circuit (gr.un.), as described in claim 6 The wafer, wherein the third metal line is not electrically connected to the outside. 144 1344686 119. The wafer of claim 6 wherein the polymer layer is further positioned on the third metal line. The wafer of claim 6 wherein the transformer element is a step-down transformer element. 121. The wafer of claim 6 wherein the transformer element is a booster transformer element. 122. A wafer comprising: - a first circuit comprising a first transistor; - a second circuit 'comprising a second transistor; a stone substrate carrying the first circuit and the second circuit; a metal line connecting the first circuit, and the first metal line includes a first steel layer having a thickness between 0.2 μm and μm; a first metal line connecting the second circuit; and an insulating layer Located in the stone eve base, the a circuit, the second circuit, the first metal line and the second metal line, and the insulating layer has a first opening and a second opening; a plurality of dielectric layers on the substrate and the insulating layer Between the layers; a third metal line positioned above the insulating layer, and the third metal line connecting the first metal line via the first opening and the second metal line via the second opening, the The trimetal circuit includes a second copper layer having a thickness between 3 microns and 20 microns, the first circuit connecting the second circuit via the third metal line; and a transformer element connected via the third metal line The first circuit and the second circuit. The chip of claim 122, wherein the transformer element converts an input voltage into an output voltage, and the output voltage is different from the input voltage. The wafer of claim 122, wherein the difference between the input voltage and the output voltage is divided by the percentage of the wheel-out voltage greater than 10%, and the wafer described in claim 122 of the patent scope, The output voltage is between 1 volt and 10 volts. 126. The wafer of claim 122, wherein the first circuit is a static random access memory unit (SRAM ceU). The wafer of claim 122, wherein the first circuit is a dynamic random access memory cell (DRAM ceU). The wafer of claim 122, wherein the first circuit The non-volatile memory cell is the non-volatile memory cell. The wafer of claim 122, wherein the first circuit is a flash memory cell. 130. The wafer of claim 11, wherein the first circuit is an erasable programmable read only memory unit (EpR〇N1 ceU). 131. The wafer of claim 122, wherein the first circuit is a ROM cell. 132. The wafer of claim 11, wherein the first circuit is a magnetic random access memory (MRAM) unit. 133. The wafer of claim 122, wherein the first electrical circuit 146 1344686 is a sense amplifier. 134. The wafer of claim 122, wherein the first circuit is an analog/digital converter (A/D converter). 135. The wafer of claim 122, wherein the first circuit is a digital/analog converter (D/A Converter). 136. The wafer of claim 122, wherein the first circuit is a CMOS sensor cell. 137. The wafer of claim 122, Wherein the first transistor is an N-type NMOS transistor, and the channel width/channel length ratio of the N-type MOS transistor is between 0.1 and Between 5 138. The wafer of claim 122, wherein the first transistor is a P-type MOS transistor, and a channel width of the P-type MOS transistor The channel length ratio is between 0.2 and 10. 139. The wafer of claim 122, wherein the second metal line is connected to one of the power nodes of the second circuit. 140. The wafer of claim 122, wherein the first metal circuit further comprises a titanium-containing metal layer. 141. The wafer of claim 122, wherein the first metal circuit further comprises a titanium nitride layer. 142. The wafer of claim 122, wherein the first metal circuit further comprises a ruthenium containing metal layer. 147. The wafer of claim 122, wherein the first metal line further comprises a tantalum nitride layer. 144. The wafer of claim 122, further comprising a fourth metal line on the insulating layer, wherein the fourth metal line is connected to a first ground node of the first circuit and connected to the The second circuit - the second ground node. 145. The wafer of claim 122, further comprising a fourth metal line on the insulating layer, wherein the fourth metal line is connected to a first ground node of the first circuit and connected to the first A second ground node of the second circuit, the fourth metal line comprising a third copper layer having a thickness between 3 microns and 20 microns. 146. The wafer of claim 11, wherein the dielectric layers comprise a oxidized stone. 147. The wafer of claim 11, wherein the dielectric layers comprise a gasification fossil. 148. The wafer of claim 11, wherein the dielectric layers comprise a material of bismuth oxynitride. 149. The wafer of claim 1, wherein the dielectric material comprises a dielectric material having a dielectric constant between 1.5 and 3.5. 150. The wafer of claim 122, wherein the third metal line further comprises a titanium-tungsten alloy layer, and the second copper layer is over the titanium-tungsten alloy layer. 151. The wafer of claim 122, wherein the third gold 148 1344686 genus further comprises a titanium-containing metal layer over the metal layer. And the second copper layer is in the wafer of claim 122, wherein the third gold line m titanium nitride layer '(10) the second copper layer is located in the atmosphere layer 153. The wafer of claim 122, wherein the third gold The genus line further includes a metal layer containing the group, and the second copper layer is above the metal layer of the stack. 154. The wafer of claim 122, wherein the third metal line further comprises a tantalum nitride layer, and the second copper layer is over the nitride button layer. 155. The wafer of claim 122, wherein the material of the insulating layer comprises a nitrogen arsenide compound. 156. The wafer of claim 11, wherein the material of the insulating layer comprises an oxygen compound. 157. The wafer of claim 1, wherein the material of the insulating layer comprises a nitrogen oxide compound. 158. The wafer of claim 1, wherein the wafer further comprises a polymer layer having a thickness between 2 microns and 150 microns, and the polymer layer is between the insulating layer and the third metal line. . 159. The wafer of claim 5, further comprising a polymer layer having a thickness between 2 microns and 15 microns and wherein the polymer layer is above the insulating layer. 160. The wafer of claim 122, wherein the transformer 149 1344686 is a step-down transformer element. 161. The wafer of claim 122, wherein the transformer element is a booster transformer element. 162. The wafer of claim 11, wherein the first circuit and the second circuit are connected to a ground reference voltage. 163. A wafer comprising: - a first circuit 'comprising a first transistor; - a second circuit comprising a second transistor; a stone substrate carrying the first circuit and the second circuit; a metal circuit connected to the first circuit, and the first metal line includes a first copper layer having a thickness between 2 μm and 1 μm; a second metal line connecting the second circuit; an insulating layer Positioning on the substrate, the first circuit, the second circuit, the first metal line and the second metal line, and the insulating layer has a first opening and a second opening; the plurality of dielectric layers Positioning between the germanium substrate and the insulating layer; a third metal line 'being the insulating layer, and the third metal line connecting the first metal line via the first opening and via the second opening Connecting the second metal line, the third metal line includes a second copper layer having a thickness between 3 micrometers and 20 micrometers, the first circuit connecting the second circuit via the third metal line; and a voltage regulator Component via Three metal lines connected to the first circuit and the second circuit. 164. The wafer of claim 1, wherein the voltage regulator 150 150344 outputs a voltage value, and the difference between the voltage value and a set target voltage value is divided by the set target voltage value. The percentage is less than 10%. 165. The wafer of claim 164, wherein the set target voltage value is between 〇.5 volts to 1 volt. 166. The wafer of claim 163, wherein the first circuit is a static random access memory cell (SrAM cell). 167. The wafer of claim 163, wherein the first circuit is a dynamic random access memory unit (DrAM cell). 168. The wafer of claim 163, wherein the first circuit is a non-volatile memory cell (non_v〇latile mem〇ry ceU). 169. The wafer of claim 163, wherein the first circuit is a flash memory ceU. 170. The wafer of claim 163, wherein the first circuit is an erasable programmable read only memory unit (EPr〇M ceU). 171. The wafer of claim 163, wherein the first circuit is a read only memory unit (R〇M ce丨1). The wafer of claim 163, wherein the first circuit is a magnetic random access memory (MRAM) unit. 173. The wafer of claim 163, wherein the first circuit is a sense amplifier. 4. The wafer of claim 163, wherein the first circuit is an analog/digital converter.晶片 5. The wafer of claim 163, wherein the first electrical circuit 151 1344686 is a digital/analog converter (D/A Converter). 176. The wafer of claim 163, wherein the first circuit is a CMOS sensor cell. 177. The wafer of claim 163, The first transistor is an N-type NMOS transistor, and the channel width/channel length ratio of the N-type MOS transistor is between 0.1 and 5. between. 178. The wafer of claim 163, wherein the first transistor is a P-type MOS transistor, and the channel width of the P-type MOS transistor is ) / Channel length ratio is between 0.2 and 10. 179. The wafer of claim 163, wherein the second metal line is connected to a power node of the second circuit. 180. The wafer of claim 163, wherein the first metal circuit further comprises a titanium-containing metal layer. 181. The wafer of claim 163, wherein the first metal circuit further comprises a titanium nitride layer. 182. The wafer of claim 163, wherein the first metal circuit further comprises a ruthenium containing metal layer. 183. The wafer of claim 163, wherein the first metal line further comprises a tantalum nitride layer. 184. The wafer of claim 163, further comprising a fourth metal line above the insulating layer, and the fourth metal line connecting the first ground node of the first circuit of the 152 1344686 and the connection a second ground node of the second circuit. 185. The wafer of claim 163, further comprising a fourth metal line on the insulating layer, wherein the fourth metal line is connected to a first ground node of the first circuit and connected to the first A first ground node of the second circuit, the fourth metal line comprising a third copper layer having a thickness between 3 microns and 20 microns. 186. The wafer of claim 163, wherein the material of the dielectric layer comprises yttrium oxide. 187. The wafer of claim 163, wherein the material of the dielectric layer comprises tantalum nitride. 188. The wafer of claim 163, wherein the material of the dielectric layer comprises bismuth oxynitride. 189. The wafer of claim 163, wherein the dielectric material comprises a dielectric material having a dielectric constant between 15 and 35. 190. The wafer of claim 163, wherein the third metal line further comprises a titanium-titanium alloy layer and the second copper layer is over the titanium-bismuth alloy layer. The wafer of claim 163, wherein the third metal line further comprises a titanium-containing metal layer, and the second copper layer is above the metal-containing layer. 192. The wafer of claim 163, wherein the third metal line further comprises a layer of titanium nitride, and the second layer of copper is above the layer 153 of the gasification layer 193 j. The wafer of claim 163, wherein the third metal line further comprises a gold-containing metal layer, and the second copper layer is above the metallization layer. 194. The wafer of claim 163, wherein the third metal line further comprises a tantalum nitride layer, and the second copper layer is above the gasification layer. 195. The wafer of claim 163, wherein the material of the insulating layer comprises a nitrogen arsenide compound. The wafer of claim 163, wherein the material of the insulating layer comprises an oxonium compound. 197. The wafer of claim 163, wherein the material of the insulating layer comprises a oxynitride compound. 198. The wafer of claim 163, further comprising a polymer layer having a thickness between 2 microns and 15 microns, and the polymer layer is located between the insulating layer and the third metal line between. 199. The wafer of claim 163, further comprising a polymer layer having a thickness between 2 microns and 15 microns and wherein the polymer layer is above the insulating layer. 200. The wafer of claim 163, wherein the first circuit and the second circuit are connected to a same ground reference voltage. 154