CN101231997B - Circuit component - Google Patents

Circuit component Download PDF

Info

Publication number
CN101231997B
CN101231997B CN200710003679XA CN200710003679A CN101231997B CN 101231997 B CN101231997 B CN 101231997B CN 200710003679X A CN200710003679X A CN 200710003679XA CN 200710003679 A CN200710003679 A CN 200710003679A CN 101231997 B CN101231997 B CN 101231997B
Authority
CN
China
Prior art keywords
circuit
layer
metal
metallic
protective layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200710003679XA
Other languages
Chinese (zh)
Other versions
CN101231997A (en
Inventor
林茂雄
周健康
李进源
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Megica Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megica Corp filed Critical Megica Corp
Priority to CN200710003679XA priority Critical patent/CN101231997B/en
Publication of CN101231997A publication Critical patent/CN101231997A/en
Application granted granted Critical
Publication of CN101231997B publication Critical patent/CN101231997B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

The invention provides a circuit component structure, which enables an inner circuit below a protection layer to transmit signals to a plurality of components or circuit units on the same chip or distributes a power voltage or a grounding reference voltage to the plurality of components or circuit units on the same chip through a metal circuit or a plane above the protection layer.

Description

A kind of circuit pack
Technical field
What the present invention relates to is a kind of circuit pack; what be particularly related to is a kind of at an integrated circuit (integratedcircuit; IC) on the chip; the metallic circuit or the plane that utilize protective layer (passivation layer) top to form are sent to other circuit unit with signal by a chip built-in circuit (on-chip circuit) unit, or supply voltage or ground connection reference voltage are sent to the structure and the method thereof of other circuit unit.
Background technology
Many electronic building bricks now all need move under the situation of a high speed and/or low power consumption.In addition, present electronic system, module or circuit board (circuit board) include many dissimilar chips, central processing unit (Central Processing Units for example, CPUs), Digital System Processor (Digita SignalProcessors, DSPs), analog chip (analog chip), DRAM (Dynamic Random Access Memory) (DRAMs), static random access memory (SRAMs) or flash memory (Flashs) etc.Each chip use dissimilar with and/or the integrated circuit process technology of different generations make.For example, in notes type personal computer (notebook personalcomputer) now, central processing unit may use an advanced person 65 nanometers (nm) technology to make, its power supply supply voltage is 1.2 volts (V), analog chip uses one 0.25 microns (μ m) integrated circuit process technologies to make, its power supply supply voltage is 3.3 volts, the DRAM (Dynamic Random Access Memory) chip uses one 90 nanometer integrated circuit process technologies to make, its power supply supply voltage is 1.5 volts, flash chip then uses one 0.18 micron technologies to make, and its power supply supply voltage is 2.5 volts.Owing in a triangular web, have multiple supply voltage, so that need pressurizer (voltage regulator), the transformer (voltageconverter) of chip built-in (on-chip) or include voltage stabilizing and the circuit design of transformation, for example the DRAM (Dynamic Random Access Memory) chip needs a chip built-in transformer that 3.3 volts of voltages are transformed into 1.5 volts, and flash chip then needs a chip built-in transformer that 3.3 volts of voltages are transformed into 2.5 volts.Wherein, chip built-in pressurizer, transformer or contain voltage stabilizing and the circuit design of transformation provides the semiconductor subassembly of a burning voltage to diverse location on same chip by chip built-in power supply/ground connection reference voltage bus (power/ground bus).In addition, if at a chip built-in pressurizer, transformer or contain voltage stabilizing and the circuit design of transformation adds low-resistance power supply/ground connection reference voltage circuit, except energy resource consumption can being minimized, also can reduce because the electric capacity of load and the noise that resistance fluctuation is caused.
At United States Patent (USP) the 6th, 495, in No. 442, it openly goes out back sheath (post-passivation) structure on a kind of wafer top.Back sheath structure on this protection using integrated circuit layer is used as comprehensive (global), power supply, ground connection reference voltage or signal distribution network.Wherein, power supply/ground connection reference voltage is from an outside (chip exterior) power supply unit.
At United States Patent (USP) the 6th; 649; openly go out a kind of relief processing (embossing process) that forms back sheath connection line (post-passivation interconnection) structure on the protection using integrated circuit floor in No. 509, it can be used as the comprehensive distribution network of power supply, ground connection reference voltage, frequency (clock) or signal.
Summary of the invention
A purpose of the present invention is by metallic circuit or plane on the protective layer (passivation), and the chip built-in circuit unit that makes protective layer below is sent to several assemblies or circuit unit on the same chip (IC chip) with signal.
A purpose of the present invention is by metallic circuit on the protective layer or plane, and the chip built-in pressurizer that makes protective layer below is sent to several assemblies or circuit unit on the same chip with power supply.
A purpose of the present invention is by metallic circuit on the protective layer or plane, and the chip built-in transformer that makes protective layer below is sent to several assemblies or circuit unit on the same chip with power supply.
A purpose of the present invention is to reduce because the signal loss that is sent to several assemblies or circuit unit that ghost effect (parasitic effect) is caused.
A purpose of the present invention is to reduce because the power loss that is sent to several assemblies or circuit unit that ghost effect caused.
A purpose of the present invention is by the protective layer opening and be formed on metallic circuit or plane on the protective layer, and power supply is sent to several assemblies or circuit unit.
A purpose of the present invention is by metallic circuit on the protective layer or plane, will be assigned at least one another internal circuit or intraware from signal, power supply or the output of ground connection reference voltage of at least one internal circuit or intraware.
A purpose of the present invention; be by metallic circuit on the protective layer or plane; to be assigned at least one another internal circuit or intraware from signal, power supply or the output of ground connection reference voltage of at least one internal circuit or intraware, and need not be connected to Electrostatic Discharge protection circuit, drive circuit or acceptor circuit.
A purpose of the present invention; be by metallic circuit on the protective layer or plane; to be assigned at least one another internal circuit or intraware from signal, power supply or the output of ground connection reference voltage of at least one internal circuit or intraware, and need not be connected to outside (chip exterior) circuit.
A purpose of the present invention is by fine rule road metal structure (fine-line metal) structure under the protective layer and metallic circuit or the plane on the protective layer, and the signal that internal circuit or intraware produced is sent to external circuit.
A purpose of the present invention; be by metallic circuit on the protective layer or plane; to be assigned at least one another internal circuit or intraware from signal, power supply or the output of ground connection reference voltage of at least one internal circuit or intraware, and the contact structures on the protective layer connect outer (off-chip) circuit with a chip respectively and external circuit is connected.
A purpose of the present invention is to distribute an external power source supply to internal circuit and the contact structures so far power supply and the ground connection reference voltage of external power source supply by metallic circuit on the protective layer or plane.
According to purpose of the present invention, a circuit pack comprises metallic circuit or the plane on the protective layer, and can utilize this metallic circuit or plane to distribute a pressurizer to transport to the voltage and/or the electric current of internal circuit.
According to purpose of the present invention; one circuit pack comprises metallic circuit or the plane on the protective layer, and can utilize this metallic circuit or plane to be assigned at least one another internal circuit or intraware from signal, power supply or the output of ground connection reference voltage of at least one internal circuit or intraware.
According to purpose of the present invention; one circuit pack comprises metallic circuit or the plane on the protective layer; this metallic circuit or plane can will be assigned at least one another internal circuit or intraware from the signal of at least one internal circuit or intraware, power supply or the output of ground connection reference voltage, and utilize contact structures on the protective layer to connect a chip to connect external circuit to external circuitry.
According to purpose of the present invention; one circuit pack comprises metallic circuit or the plane on the protective layer, and utilizes this metallic circuit or plane to distribute an external power source supply to arrive the power supply and the ground connection reference voltage of external power source supply to internal circuit and contact structures.
For achieving the above object, the technical solution used in the present invention is that scheme one provides a kind of circuit pack, a kind of circuit pack, and wherein, it comprises:
One first internal circuit, it has an output node;
One second internal circuit, it has an input node;
One first metallic circuit connects the described output node of described first internal circuit;
One second metallic circuit connects the described input node of described second internal circuit;
One protective layer is positioned on described first internal circuit, described second internal circuit, described first metallic circuit and described second metallic circuit; And
One the 3rd metallic circuit is positioned on the described protective layer, and connects described first metallic circuit and described second metallic circuit.
Scheme two provides a kind of circuit pack, a kind of circuit pack, and wherein, it comprises:
One chip connects external circuit, comprises an input node and an output node;
One internal circuit comprises an input node and an output node;
One first metallic circuit connects described chip and connects external circuit;
One second metallic circuit connects described internal circuit;
One protective layer is positioned at described chip and connects on external circuit, described internal circuit, described first metallic circuit and described second metallic circuit;
One the 3rd metallic circuit connects described first metallic circuit and described second metallic circuit;
One the 4th metallic circuit is positioned under the described protective layer and connects described chip and connects external circuit, and described the 4th metallic circuit comprises that at least one first metallic pad is exposed in the opening of described protective layer;
One five metals belongs to circuit, being positioned at described protective layer top and described five metals belongs to circuit and comprises one second metallic pad, described second metallic pad is electrically connected described first metallic pad, the described second metallic pad position is different from the described first metallic pad position, and described second metallic pad comprises that thickness is greater than a first metal layer of 1.5 microns; And
One lead is positioned on described second metallic pad.
Scheme three provides a kind of circuit pack, a kind of circuit pack, and wherein, it comprises: an internal storage location;
One first internal circuit;
One first metallic circuit connects described internal storage location;
One second metallic circuit connects described first internal circuit;
One protective layer is positioned on described internal storage location, described first internal circuit, described first metallic circuit and described second metallic circuit; And
One the 3rd metallic circuit is positioned on the described protective layer, and connects described first metallic circuit and described second metallic circuit.
Description of drawings
Figure 1A is existing circuit diagram with a pressurizer or transformer;
Figure 1B has the circuit diagram of a pressurizer or transformer for the present invention;
Fig. 1 C carries the circuit diagram of voltage vcc and ground connection reference voltage Vss structure for the present invention utilizes protective layer upper metal circuit or plane;
Fig. 2 A has the schematic top plan view of a pressurizer or transformer for having now;
Fig. 2 B has the schematic top plan view of a pressurizer or transformer for the present invention;
Fig. 2 C carries the schematic top plan view of voltage vcc and ground connection reference voltage Vss structure for the present invention utilizes protective layer upper metal circuit or plane;
Fig. 3 A has the generalized section of a pressurizer or transformer for having now;
Fig. 3 B has the generalized section of a pressurizer or transformer for the present invention;
Fig. 3 C carries the generalized section of voltage vcc and ground connection reference voltage Vss structure for the present invention utilizes protective layer upper metal circuit or plane;
Fig. 3 D has the generalized section of a pressurizer or transformer for the present invention;
Fig. 4 is a transformer of the present invention;
Fig. 5 A is the circuit diagram of existing internal circuit;
Fig. 5 B is a circuit diagram of second embodiment of the invention;
Fig. 5 C is an inverter of the present invention;
Fig. 5 D is the present invention's inner drive;
Fig. 5 E is tristate buffer within the present invention;
Fig. 5 F is an internal storage location of the present invention is connected to an internal circuit by the fine rule road metal structure under the metallic circuit on inner tristate buffer, the protective layer or plane and the protective layer a circuit diagram;
Fig. 5 G is that an internal storage location of the present invention is by being connected to the circuit diagram of an internal circuit by the fine rule road metal structure under the metallic circuit on circuit, the protective layer or plane and the protective layer;
Fig. 5 H is an internal storage location of the present invention is connected to an internal circuit by the fine rule road metal structure under the metallic circuit on latch circuit, the protective layer or plane and the protective layer a circuit diagram;
Fig. 5 I is that an internal storage location of the present invention is by being connected to the circuit diagram of an internal circuit by the fine rule road metal structure under the metallic circuit on circuit, inner drive, the protective layer or plane and the protective layer;
Fig. 5 J is an internal storage location of the present invention is connected to an internal circuit by the fine rule road metal structure under the metallic circuit on latch circuit, inner drive, the protective layer or plane and the protective layer a circuit diagram;
Fig. 5 K is a circuit diagram of second embodiment of the invention;
Fig. 5 L is receiver within the present invention;
Fig. 5 M is tristate buffer within the present invention;
To be an internal circuit of the present invention be connected to the circuit diagram of an internal storage location by the fine rule road metal structure under the protective layer, metallic circuit on the protective layer or plane and inner tristate buffer to Fig. 5 N;
Fig. 5 O is an internal circuit of the present invention by the fine rule road metal structure under the protective layer, metallic circuit on the protective layer or plane and the circuit diagram that is connected to an internal storage location by circuit;
To be an internal circuit of the present invention be connected to the circuit diagram of an internal storage location by the fine rule road metal structure under the protective layer, metallic circuit on the protective layer or plane and latch circuit to Fig. 5 P;
Fig. 5 Q is an internal circuit of the present invention by the fine rule road metal structure under the protective layer, metallic circuit on the protective layer or plane, inner receiver and the circuit diagram that is connected to an internal storage location by circuit;
Fig. 5 R circuit diagram that to be an internal circuit of the present invention be connected to an internal storage location by the fine rule road metal structure under the protective layer, metallic circuit on the protective layer or plane, inner receiver and latch circuit;
Fig. 5 S utilizes the metallic circuit of protective layer top or the circuit diagram that the plane connects analog circuit for the present invention;
Fig. 5 T is an operational amplifier of the present invention;
Fig. 6 A is the schematic top plan view of existing internal circuit;
Fig. 6 B is the schematic top plan view of second embodiment of the invention;
Fig. 7 A is the generalized section of existing internal circuit;
Fig. 7 B is the generalized section that second embodiment of the invention has the single layer pattern metal level;
Fig. 7 C is the generalized section that second embodiment of the invention has two-layer patterned metal layer;
Fig. 7 D is second embodiment of the invention has a polymeric layer between protective layer and bottom patterned metal layer a generalized section;
Fig. 8 A is the circuit diagram of existing wafer;
Fig. 8 B is a circuit diagram of third embodiment of the invention;
Fig. 8 C is a circuit diagram of third embodiment of the invention;
Fig. 8 D is a circuit diagram of third embodiment of the invention;
Fig. 8 E is a circuit diagram of third embodiment of the invention;
Fig. 8 F is a circuit diagram of third embodiment of the invention;
Fig. 9 A is the schematic top plan view of existing wafer;
Fig. 9 B is a schematic top plan view of third embodiment of the invention;
Fig. 9 C is a schematic top plan view of third embodiment of the invention;
Fig. 9 D is a schematic top plan view of third embodiment of the invention;
Figure 10 A is the generalized section of existing wafer;
Figure 10 B is the generalized section that third embodiment of the invention has the single layer pattern metal level;
Figure 10 C is the generalized section that third embodiment of the invention has two-layer patterned metal layer;
Figure 10 D is third embodiment of the invention has a polymeric layer between the protective layer and the single layer pattern metal level bottom a generalized section;
Figure 10 E is third embodiment of the invention has a polymeric layer between the protective layer and the two-layer patterned metal layer bottom a generalized section;
Figure 10 F has the generalized section that a routing engages for existing wafer;
Figure 10 G is that third embodiment of the invention has the generalized section that a routing engages;
Figure 10 H is that third embodiment of the invention has the generalized section that a routing engages;
Figure 10 I is that third embodiment of the invention has the generalized section that a routing engages;
Figure 11 A is that chip of the present invention connects outer driver;
Figure 11 B is that chip of the present invention connects outer receiver;
Figure 11 C is a chip tristate buffer of the present invention;
Figure 11 D is that chip of the present invention connects outer driver;
Figure 11 E is a chip tristate buffer of the present invention;
Figure 11 F is an electrostatic storage deflection (ESD) protection circuit of the present invention;
Figure 11 G is a series driver of the present invention;
Figure 12 A for the existing direct input voltage of external power supply to internal circuit and have an electrostatic storage deflection (ESD) protection circuit and prevent the voltage that external power supply produced or the circuit diagram of electric current surging;
Figure 12 B is a circuit diagram of fourth embodiment of the invention;
Figure 12 C is a circuit diagram of fourth embodiment of the invention;
Figure 12 D is the circuit diagram that fourth embodiment of the invention has two electrostatic storage deflection (ESD) protection circuit;
Figure 12 E is an electrostatic storage deflection (ESD) protection circuit of the present invention;
Figure 13 A for the existing direct input voltage of external power supply to internal circuit and have an electrostatic storage deflection (ESD) protection circuit and prevent the voltage that external power supply produced or the schematic top plan view of electric current surging;
Figure 13 B is a schematic top plan view of fourth embodiment of the invention;
Figure 13 C is a schematic top plan view of fourth embodiment of the invention;
Figure 14 A for the existing direct input voltage of external power supply to internal circuit and have an electrostatic storage deflection (ESD) protection circuit and prevent the voltage that external power supply produced or the generalized section of electric current surging;
Figure 14 B is a generalized section of fourth embodiment of the invention;
Figure 14 C is a generalized section of fourth embodiment of the invention;
Figure 14 D is a generalized section of fourth embodiment of the invention;
Figure 15 A is the generalized section of a wafer;
Figure 15 B is the generalized section of a wafer;
Figure 15 C to Figure 15 K forms a procedure of processing of square structure on the protective layer for the present invention;
Figure 16 A to Figure 16 L forms a procedure of processing of square structure on the protective layer for the present invention;
Figure 17 A to Figure 17 J forms a procedure of processing of square structure on the protective layer for the present invention;
Figure 18 A to Figure 18 I forms a procedure of processing of square structure on the protective layer for the present invention;
Figure 19 A to Figure 19 I forms a procedure of processing of square structure on the protective layer for the present invention;
Figure 20 is a generalized section of the present invention.
Description of reference numerals: 1-substrate; The 2-component layer; 2 '-MOS (metal-oxide-semiconductor) transistor; The 5-protective layer; 6-fine rule line structure; Square structure on the 8-protective layer; The 10-wafer; 10 '-chip; 19-bed hedgehopping pad; 20 internal circuits; The 21-internal circuit; 22 internal circuits; The 23-internal circuit; 24 internal circuits; 30-fine rule road dielectric layer; 30 ' opening; The 40-chip connects external circuit; 41 pressurizers or transformer; The 42-chip connects external circuit; 43 chips connect external circuit; The 44-electrostatic storage deflection (ESD) protection circuit; 45 electrostatic storage deflection (ESD) protection circuit; 50-protective layer opening; 60 fine rule road metal levels; 60 '-conductive plug; 61 fine rule road metal structures; 61 '-fine rule road metal structure; 62 fine rule road metal structures; 63-fine rule road metal structure; 66 metal top layers; 69-fine rule road metal structure; 71 photoresist layers; The 72-photoresist layer; 73 photoresist layers; The 74-photoresist layer; 80 patterned metal layers; 81-metallic circuit or plane; 82 metallic circuits or plane; 83-metallic circuit or plane; 83r metallic circuit or plane; 83t-reshuffles metallic circuit; 89 contact structures; The 89t-Solder Bumps; 90 polymeric layers; The 97-polymeric layer; 98 polymeric layers; The 200-internal structure; 201 source electrodes; The 202-drain electrode; 203 grids; The 211-inverter; 212 inner drives; 212 '-inner receiver; 213 inner tristate buffers; 213 '-inner tristate buffer; 214 sensing amplifiers; The 215-sram cell; 216 pass through circuit; 216 '-pass through circuit; 217 latch circuits; 217 '-latch circuit; 218 operational amplifiers; The 219-differential circuit; 400 chips connect external structure; The 410-reference voltage generator; 410 ' current mirroring circuit; The 421-chip connects outer driver; 421 ' the first order; 421 "-second level; 422 chips connect outer receiver; 422 '-first order; 422 " second level; 511-protective layer opening; 512 protective layer openings; 514-protective layer opening; 519 protective layer openings; 519 '-protective layer opening; 521 protective layer openings; 522-protective layer opening; 524 protective layer openings; 529-protective layer opening; 531 protective layer openings; 531 '-protective layer opening; 532 protective layer openings; 532 '-protective layer opening; 534 protective layer openings; 534 '-protective layer opening; 539 protective layer openings; 539 '-protective layer opening; 549 protective layer openings; 549 '-protective layer opening; 559 protective layer openings; 559 '-protective layer opening; 600 metallic pad; 601w-fine rule road metal level; 602 fine rule road metal levels; 602x-fine rule road metal level; 602y fine rule road metal level; 602z-fine rule road metal level; 611 fine rule road metal structures; 612-fine rule road metal structure; 612a fine rule road metal structure; 612b-fine rule road metal structure; 612c fine rule road metal structure; 614-fine rule road metal structure; 618 fine rule road metal structures; 619-fine rule road metal structure; 619 ' fine rule road metal structure; 621-fine rule road metal structure; 622 fine rule road metal structures; 622a-fine rule road metal structure; 622b fine rule road metal structure; 622c-fine rule road metal structure; 624 fine rule road metal structures; 629-fine rule road metal structure; 631 fine rule road metal structures; 631 '-fine rule road metal structure; 632 fine rule road metal structures; 632a-fine rule road metal structure; 632b fine rule road metal structure; 632c-fine rule road metal structure; 632a ' fine rule road metal structure; 632b '-fine rule road metal structure; 632c ' fine rule road metal structure; 634-fine rule road metal structure; 634 ' fine rule road metal structure; 638-fine rule road metal structure; 639 fine rule road metal structures; 639 '-fine rule road metal structure; 649 fine rule road metal structures; 649 '-fine rule road metal structure; 659 fine rule road metal structures; 659 '-fine rule road metal structure; 661 metal top layers; 662-metal top layer 664 metal top layers; 669-metal top layer 669 ' metal top layer; 710-photoresist layer opening; 720 photoresist layer openings; 720 '-photoresist layer opening; 730 photoresist layer openings; 730 '-photoresist layer opening; 740 photoresist layer openings; 740 '-photoresist layer opening; 801 patterned metal layers; The 801a-patterned metal layer; The 801b patterned metal layer; The 801w-patterned metal layer; 802 patterned metal layers; The 802x-patterned metal layer; The 802y patterned metal layer; The 802z-patterned metal layer; 803 patterned metal layers; The 811-patterned metal layer; 812 patterned metal layers; The 821-patterned metal layer; 831 patterned metal layers; The 831a-patterned metal layer; The 831b patterned metal layer; The 832-patterned metal layer; The 832a patterned metal layer; The 832b-patterned metal layer; The 891 protruding bottom metal layers of determining; The 897-metal plug; 897 ' metal level; The 898-metal plug; 898 ' metal level; 950-polymeric layer opening; 980 polymeric layer openings; 990-polymeric layer opening; 2101-N type MOS (metal-oxide-semiconductor) transistor; 2102-P type MOS (metal-oxide-semiconductor) transistor; 2103-N type MOS (metal-oxide-semiconductor) transistor; 2103 '-N type MOS (metal-oxide-semiconductor) transistor; 2104-P type MOS (metal-oxide-semiconductor) transistor; 2104 '-P type MOS (metal-oxide-semiconductor) transistor; 2107-N type MOS (metal-oxide-semiconductor) transistor; 2108-P type MOS (metal-oxide-semiconductor) transistor; 2109 '-N type MOS (metal-oxide-semiconductor) transistor; 2110 '-P type MOS (metal-oxide-semiconductor) transistor; 2111-N type MOS (metal-oxide-semiconductor) transistor; 2112P type MOS (metal-oxide-semiconductor) transistor; 2113-N type MOS (metal-oxide-semiconductor) transistor; 2114-P type MOS (metal-oxide-semiconductor) transistor; 2115-N type MOS (metal-oxide-semiconductor) transistor; 2116-P type MOS (metal-oxide-semiconductor) transistor; 2117-N type MOS (metal-oxide-semiconductor) transistor; 2118-P type MOS (metal-oxide-semiconductor) transistor; 2119-N type MOS (metal-oxide-semiconductor) transistor; 2120-N type MOS (metal-oxide-semiconductor) transistor; 2121-N type MOS (metal-oxide-semiconductor) transistor; The 2122-row selecting transistor; The 2123-row selecting transistor; 2124-N type MOS (metal-oxide-semiconductor) transistor; 2124 '-N type MOS (metal-oxide-semiconductor) transistor; 2125-N type MOS (metal-oxide-semiconductor) transistor; 2126-P type MOS (metal-oxide-semiconductor) transistor; 2127-N type MOS (metal-oxide-semiconductor) transistor; 2128-P type MOS (metal-oxide-semiconductor) transistor; 2129-N type MOS (metal-oxide-semiconductor) transistor; 2129 '-N type MOS (metal-oxide-semiconductor) transistor; 2130-N type MOS (metal-oxide-semiconductor) transistor; 2130 '-N type MOS (metal-oxide-semiconductor) transistor; 2131-P type MOS (metal-oxide-semiconductor) transistor; 2132-P type MOS (metal-oxide-semiconductor) transistor; The 2133-capacitor; The 2134-resistor; 2135-N type MOS (metal-oxide-semiconductor) transistor; 2136-P type MOS (metal-oxide-semiconductor) transistor; 4101-P type MOS (metal-oxide-semiconductor) transistor; 4102-P type MOS (metal-oxide-semiconductor) transistor; 4103-P type MOS (metal-oxide-semiconductor) transistor; 4104-P type MOS (metal-oxide-semiconductor) transistor; 4105-P type MOS (metal-oxide-semiconductor) transistor; 4106-P type MOS (metal-oxide-semiconductor) transistor; 4107-N type MOS (metal-oxide-semiconductor) transistor; 4108-N type MOS (metal-oxide-semiconductor) transistor; 4109-P type MOS (metal-oxide-semiconductor) transistor; 4110-P type MOS (metal-oxide-semiconductor) transistor; The 4111-electricity is led transistor; The 4112-electricity is led transistor; The 4199-node; 4201-N type MOS (metal-oxide-semiconductor) transistor; 4202-P type MOS (metal-oxide-semiconductor) transistor; 4203-N type MOS (metal-oxide-semiconductor) transistor; 4204-P type MOS (metal-oxide-semiconductor) transistor; 4205-N type MOS (metal-oxide-semiconductor) transistor; 4206-P type MOS (metal-oxide-semiconductor) transistor; 4207-N type MOS (metal-oxide-semiconductor) transistor; 4208-P type MOS (metal-oxide-semiconductor) transistor; 4209-N type MOS (metal-oxide-semiconductor) transistor; 4210-P type MOS (metal-oxide-semiconductor) transistor; 4331-reverse blas diode; 4332-reverse blas diode; 4333-reverse blas diode; 6111-fine rule road metal structure; 6121-fine rule road metal structure; 6121a-fine rule road metal structure; 6121b-fine rule road metal structure; 6121c-fine rule road metal structure; 6141-fine rule road metal structure; The 6190-metallic pad; 6190 '-metallic pad; The 6290-metallic pad; 6191-fine rule road metal structure; 6311-fine rule road metal structure; 6321-fine rule road metal structure; 6321a-fine rule road metal structure; 6321b-fine rule road metal structure; 6321c-fine rule road metal structure; 6341-fine rule road metal structure; The 6390-metallic pad; 6391-fine rule road metal structure; 6391 '-fine rule road metal structure; The 6490-metallic pad; 6490 '-metallic pad; 8011 '-depressed part; 8011a-sticks together/hinders barrier/Seed Layer; 8011b-sticks together/hinders barrier/Seed Layer; The 8012a-thick metal layers; The 8012b-thick metal layers; 8021-sticks together/hinders barrier/Seed Layer; The 8022-thick metal layers; 8031-sticks together/hinders barrier/Seed Layer; The 8032-thick metal layers; 8110-contacts connection pad; 8111-sticks together/hinders barrier/Seed Layer; The 8112-thick metal layers; 8120-contacts connection pad; 8121-sticks together/hinders barrier/Seed Layer; The 8122-thick metal layers; 8211-sticks together/hinders barrier/Seed Layer; The 8212-thick metal layers; 8310-contacts connection pad; 8311-sticks together/hinders barrier/Seed Layer; 8311a-sticks together/hinders barrier/Seed Layer; 8311b-sticks together/hinders barrier/Seed Layer; The 8312-thick metal layers; The 8312a-thick metal layers; The 8312b-thick metal layers; 8320-contacts connection pad; 8321-sticks together/hinders barrier/Seed Layer; 8321a-sticks together/hinders barrier/Seed Layer; 8321b-sticks together/hinders barrier/Seed Layer; The 8322-thick metal layers; The 8322a-thick metal layers; The 8322b-thick metal layers; 9511-polymeric layer opening; 9512-polymeric layer opening; 9514-polymeric layer opening; 9519-polymeric layer opening; 9519 '-polymeric layer opening; 9531-polymeric layer opening; 9532-polymeric layer opening; 9534-polymeric layer opening; 9539-polymeric layer opening; 9539 '-polymeric layer opening; 9549-polymeric layer opening; 9829-polymeric layer opening; 9831-polymeric layer opening; 9834-polymeric layer opening; 9839-polymeric layer opening; 9849 '-polymeric layer opening; 9919-polymeric layer opening; 9929-polymeric layer opening; 9939-polymeric layer opening; 9939 '-polymeric layer opening; 9949-polymeric layer opening; 9949 '-polymeric layer opening.
Embodiment
Below in conjunction with accompanying drawing, be described in more detail with other technical characterictic and advantage the present invention is above-mentioned.
Circuit pack of the present invention comprises wafer (monolithic wafer), chip (chip) or encapsulation monomer etc.
First embodiment: protective layer top (over-paeeivation) power supply/ground connection reference voltage bus that connects a pressurizer or transformer.
Please consult simultaneously earlier shown in Figure 1B to Fig. 1 C, Fig. 2 B to Fig. 2 C and Fig. 3 B to Fig. 3 D, it openly goes out the first embodiment of the present invention.Wherein, Figure 1B and Fig. 1 C present a circuit diagram of simplifying; its utilize metallic circuit on the protective layer 5 or plane 81 with and/or metallic circuit or plane 82 connect pressurizers (voltageregulator) or transformer (voltage converter) 41 and internal circuit 20 (comprising 21,22,23,24), and utilize this metallic circuit or plane 81 with and/or metallic circuit or plane 82 voltage that distributes pressurizers or transformer 41 outputs with and/or a ground connection reference voltage.Fig. 2 B and Fig. 2 C present the schematic top plan view of the circuit shown in Figure 1B and Fig. 1 C respectively.Fig. 3 B and Fig. 3 C then present the generalized section of the circuit shown in Figure 1B and Fig. 1 C respectively.In addition; in Fig. 1 series and Fig. 2 series, protective layer 5 is represented by dotted lines, and the circuit or the plane that are formed on the protective layer 5 are represented with " thick line "; the circuit that is formed under the protective layer 5 is then represented with " fine rule ", and this kind representation also is useful among all embodiment of the present invention.
In the present embodiment, power supply is to rely on the metallic circuit of protective layer top or plane to be sent to by the pressurizer of a chip built-in or transformer 41 to be positioned at same integrated circuit (IC) chip (integrated circuit, IC) several assemblies (circuit) on.By being deposited on metallic circuit or the plane on the protective layer, power supply can be sent in several assemblies or the circuit unit under the low-loss situation.This kind adds regulation and control voltage and utilizes protective layer upper metal circuit or the design of planar transmission voltage can be controlled at the voltage quasi position of transporting to internal circuit on one voltage quasi position very accurately.In addition, the target setting voltage of the output voltage of pressurizer in this pressurizer positive and negative 10% between (be that pressurizer is when exporting a magnitude of voltage, difference between this magnitude of voltage and the target setting magnitude of voltage divided by the percentage of target setting magnitude of voltage less than 10%), and with between this target setting voltage positive and negative 5% between be the preferably, wherein the target setting magnitude of voltage of this pressurizer is such as between between 0.5 volt to 10 volts or between 0.5 volt to 5 volts.So, rely on this kind mode can prevent to import node (input node) and be subjected to abrupt voltage wave that external power supply produces or bigger voltage fluctuation, therefore can improve circuit performance by this kind design.Yet, in some applications,,, also need utilize a transformer that the voltage transitions that external power supply provided is become voltage required in the chip so chip is interior except pressurizer because chip need be different from the voltage that external power supply provides.This transformer can convert an input voltage to an output voltage, and output voltage is different with input voltage value, and greater than 10%, wherein this output voltage is such as being between between 1 volt to 10 volts or between 1 volt to 5 volts divided by the percentage of output voltage for the difference of input voltage and output voltage.In addition, the pattern of this transformer can be a step-down transformer or a booster transformer.
Figure 1A, Fig. 2 A and Fig. 3 A openly have a pressurizer or how transformer 41 is connected to internal circuit 20 circuit diagram, schematic top plan view and the generalized section of (comprising 21,22,23 and 24).This prior art is utilized the fine rule road metal structure 619,6191 and 61 ( comprise 618,6111,6121 and 6141, wherein 6121 comprise 6121a, 6121b and 6121c again) under the protective layer 5 to make pressurizer or transformer 41 accept the voltage Vdd of external power supply input, output one voltage vcc and is transmitted voltage vcc to internal circuit 20 (comprising 21,22,23 and 24).Yet, be positioned at protective layer 5 times and use the fine rule road metal structure 61 of wafer processing and material manufacturing and can't provide thick metal level (for example thickness 5 microns metal level) easily or thick dielectric layer (for example thickness 5 microns dielectric layer).In addition, the high resistance per unit length of fine rule road metal level and high capacitance per unit length can cause supply voltage to fall (IR voltage drop), noise (noises), signal distortion (signaldistortion), passing time delay (propagation time delay), high power consumption (high powerconsumption) and produce high heat (high heat generation).
See also shown in Figure 1B, it is the circuit diagram of first embodiment of the invention.In this embodiment, a pressurizer or transformer 41 are accepted the voltage Vdd of external power supply input via protective layer opening 519 and fine rule road metal structure 619, and export a voltage vcc to internal circuit 20 (comprising 21,22,23 and 24).Pressurizer or transformer 41 are distributed to internal circuit 21 at the voltage vcc of node P output by following mode, 22,23,24 voltage node Tp, Up, Vp, Wp, this mode is at first up passed through the protective layer opening 519 ' that is positioned at protective layer 5 by fine rule road metal structure 619 ', then through a metallic circuit or plane 81 on the protective layer 5, come again down by protective layer opening 511,512,514, after meticulous circuit metal structure 61 ' (comprises 611,612,614, wherein 612 comprise 612a again, 612b, 612c), wherein pass through fine rule road metal structure 611 to internal circuit 21 to internal circuit 20; Process fine rule road metal structure 612a and fine rule road metal structure 612b are to internal circuit 22; Pass through fine rule road metal structure 612a and fine rule road metal structure 612c to internal circuit 23, and; Process fine rule road metal structure 614 is to internal circuit 24.
In addition, internal circuit 20 (comprises 21,22,23,24) constituted by a MOS (metal-oxide-semiconductor) transistor (MOS transistor) at least, and above-mentioned fine rule road metal structure is connected to internal circuit 20 and (comprises 21,22,23,24) MOS (metal-oxide-semiconductor) transistor, such as the source electrode that is connected to MOS (metal-oxide-semiconductor) transistor (source), and this MOS (metal-oxide-semiconductor) transistor can be " channel width (Channel width)/passage length (Channel length) " ratio between the N type MOS (metal-oxide-semiconductor) transistor (NMOS transistor) between 0.1 to 5 or between 0.2 to 2, or " channel width/passage length " ratio is between the P type MOS (metal-oxide-semiconductor) transistor (PMOStransistor) between 0.2 to 10 or between 0.4 to 4.In addition, the flow through electric current on metallic circuit or plane 81 is between between 50 micromicroamperes to 2 milliampere or between between 100 micromicroamperes to 1 milliampere.
Therefore; structure shown in Figure 1B is to use a metallic circuit or plane 81 as a power circuit or plane; in addition because metallic circuit or plane 81 on the protective layer 5 are a thick metallic conductor; and thick metallic conductor has low-resistance advantage; so can significantly reduce the pressure drop (voltage drop) that metallic circuit or plane 81 are produced, but and supply voltage of providing of stable metal circuit or plane 81.
At Figure 1B to Fig. 1 C, among Fig. 2 B to Fig. 2 C and Fig. 3 B to Fig. 3 D, internal circuit 20 comprises internal circuit 21, internal circuit 22, internal circuit 23 and internal circuit 24, wherein internal circuit 22,24 is NOR gate (NOR gate), and internal circuit 23 is NAND gate (NAND gate), each NOR gate and NAND gate all have three input node Ui in addition, Wi, Vi, an output node Uo, Wo, Vo, a voltage vcc power supply node Up, Wp, Vp and a ground connection reference voltage Vss ground connection node Us, Ws, Vs, internal circuit 21 then have an input nodes X i, an output node Xo, a voltage vcc power supply node Tp and a ground connection reference voltage Vss ground connection node Ts.Therefore, internal circuit 20 (comprising 21,22,23 and 24) has signal node (signal node), power supply node (power node) and ground connection node (groundnode) usually.Yet internal circuit 20 (comprising 21,22,23 and 24) also can be the integrated circuit of any pattern, this hold within partly will be in the lump in follow-up Figure 15 series explanation internal circuit 20 narrate when (comprising 21,22,23 and 24); Some exemplary applications of in addition relevant internal circuit 21 then will illustrate among Fig. 5 C to Fig. 5 J and Fig. 5 M to Fig. 5 R subsequently.
Please consult simultaneously shown in Fig. 2 B and Fig. 3 B, it is respectively schematic top plan view shown in Figure 1B of the present invention and generalized section.In Fig. 3 B, fine rule road metal structure 611,612,614,619,619 ' can be formed by the conductive plug 60 ' that fills up in fine rule road metal level 60 and the opening 30 ', the mode that forms forms such as the storehouse mode with rough aligning, that is to say to be rough alignment between two openings 30 ' up and down, be rough alignment between the two fine rule road metal levels 60 up and down, and also up and down rough alignment between two conductive plugs 60 ', be separately in addition between the fine rule road metal level 60, and the explanation of relevant above-mentioned fine rule road metal structure also is useful in all embodiment of the present invention by fine rule road dielectric layer 30 (for example silica).In Fig. 2 B; metallic circuit on the protective layer 5 or plane 81 can be single layer pattern metal level (for example patterned metal layer 811 of Fig. 3 B) or multi-layered patterned metal level (not shown); and when metallic circuit or plane 81 are multi-layered patterned metal level; be separately between the patterned metal layer by a polymeric layer; and this polymeric layer can be polyimides (polyimide; PI); benzyl ring butylene (benzo cyclo butene; BCB); Parylene (pary lene); epoxy-based material (epoxy-based material); epoxy resin or for example by the photoepoxy SU-8 that SotecMicrosystems provided of the Renens that is positioned at Switzerland; elastomeric material (elastomer), for example silicone (silicone).In addition, metallic circuit or plane 81 are to comprise that one sticks together/hinder a barrier/Seed Layer (adhesion/barrier/seed layer) and a thick metal layers, for example in Fig. 3 B, patterned metal layer 811 includes one and sticks together/hinder a barrier/Seed Layer 8111 and a thick metal layers 8112.As for will in follow-up Figure 15 series, Figure 16 series, Figure 17 series, Figure 18 series and Figure 19 series, illustrating about method and being described in detail then of metallic circuit or plane 81 that forms metallic circuit or plane 81.In addition, fine rule road metal structure 612 includes fine rule road metal structure 612a, fine rule road metal structure 612b and fine rule road metal structure 612c, it is intended for the distribution of regional power (localpower), metallic circuit or plane 81 then are used as the distribution of comprehensive power (global power), and are connected with fine rule road metal structure 619 ' with fine rule road metal structure 61 ' (comprising 611,612,614).Please consult simultaneously shown in Figure 1B, Fig. 2 B and Fig. 3 B; external power supply provides a voltage Vdd at contact connection pad 8110; and after passing through a protective layer opening 519 and a fine rule road metal structure 619; be input to pressurizer or transformer 41; wherein this fine rule road metal structure 619 comprises a metallic pad (metal pad) 6190 of the top layer of fine rule road metal level 60, and exposes metallic pad 6190 by protective layer opening 519 and be connected to contact connection pad 8110.
The present invention utilizes a top polymeric layer 99 to cover metallic circuit or plane 81, this top polymeric layer 99 can be polyimides, benzyl ring butylene, Parylene, epoxy-based material (for example epoxy resin or photoepoxy SU-8), elastomeric material (for example silicone), for example shown in Fig. 3 B, patterned metal layer 811 covers a top polymeric layer 99.In addition; the also alternative polymeric layer 95 that increases between protective layer 5 and metallic circuit or plane 81; this polymeric layer 95 can be polyimides, benzyl ring butylene, Parylene, epoxy-based material (for example epoxy resin or photoepoxy SU-8), elastomeric material (for example silicone); for example shown in Fig. 3 D; increase by a polymeric layer 95 between protective layer 5 and patterned metal layer 811, wherein the polymeric layer opening the 9519, the 9519 ', 9511,9512, the 9514th, is aligned in the protective layer opening 519,519 ', 511,512,514 in the protective layer 5 respectively.In the present invention, the size of polymeric layer open bottom can be the size less than below protective layer opening, and polymeric layer covers the connection pad that part protective layer opening is exposed, for example in Fig. 3 D, polymeric layer opening 9519, the size of 9519 ' bottom promptly is respectively less than below protective layer opening 519,519 ' size, and polymeric layer 95 covers partly protective layer opening 519,519 ' the metallic pad that is exposed 6190,6190 ', the protective layer opening 519 in addition, 519 ' size is between 20 microns to 100 microns, and polymeric layer opening 9519,9519 ' size then is between 20 microns to 100 microns; Yet in some design; the size of polymeric layer opening also can be the size greater than below protective layer opening; and expose that the protective layer opening exposed by the polymeric layer opening all partly; for example the polymeric layer opening 9511; 9512; 9514 size promptly is respectively greater than below protective layer opening 511; 512; 514 size; and polymeric layer opening 9511; 9512; 9514 expose protective layer opening 511 respectively; 512; 514 all that are exposed partly; this external protection opening 511; 512; 514 size is between 10 microns to 50 microns, and polymeric layer opening 9511; 9512; 9514 size then is between 20 microns to 100 microns.Relevant above-mentioned explanation also is useful in all embodiment of the present invention.
In addition, be used for distributing the metallic circuit of stable or changing voltage Vcc or plane 81 except can be single layer pattern metal level (patterned metal layer 811 shown in Fig. 3 B), also can be to have polymeric layer to be deposited on multi-layered patterned metal level between each metal level, and multi-layered patterned metal level can link together the patterned metal layer of different layers by the opening between the polymeric layer.
Come again; please consult simultaneously shown in Figure 1A, Fig. 2 A and Fig. 3 A; it is existing correlation technique; as shown in the figure; external power supply is to provide pressurizer or transformer 41 required input voltage in following described mode; it is: the voltage Vdd that the metallic pad 6190 of utilizing protective layer opening 519 to be exposed receives from the external power supply input, then down pass through fine rule road metal structure 619, and at last voltage Vdd is input to pressurizer or transformer 41.Continue, (comprising 618,6111,6121,6141) the output voltage V cc of voltage regulator or transformer 41 is distributed to the voltage vcc node of internal circuit 21,22,23,24 via fine rule road metal structure 61.Only, this prior art has and shows the slow down shortcoming of (speedreduction) of land energy loss (energy loss) and speed.
In Figure 1B, Fig. 2 B, Fig. 3 B and Fig. 3 D, the ground connection reference voltage is expressed as Vss, but its circuit, layout and structure is not described in detail.Now please consult simultaneously shown in Fig. 1 C, Fig. 2 C and Fig. 3 C, it is to be respectively the present invention to utilize protective layer upper metal circuit or plane to distribute circuit diagram, schematic top plan view and the generalized section of voltage vcc and ground connection reference voltage Vss structure.Wherein, except pressurizer or transformer 41 and the shared ground connection reference voltage of internal circuit 20 (comprising 21,22,23,24), just except ground connection node Ts, Us, Vs, Ws, the Rs of internal circuit 20 and pressurizer or transformer 41 all be connected to same ground connection reference voltage node Es, the structure of ground connection reference voltage Vss and connected mode be to above-mentioned carry to voltage vcc similar.In Fig. 1 C, Fig. 2 C and Fig. 3 C; the ground connection node Es that receives ground connection reference voltage Vss is the ground connection node R s that is connected to pressurizer or transformer 41 via the protective layer opening 529 of protective layer 5 and the fine rule road metal structure 629 under the protective layer 5, and the ground connection node Ts, Us, Vs, the Ws that are connected to internal circuit 21,22,23,24 via metallic circuit or plane 82 (patterned metal layer 821 among Fig. 3 C), protective layer opening 521,522,524 and fine rule road metal structure 621,622 (comprising 622a, 622b, 622c), 624.
Now see also shown in Fig. 3 C; it is openly to go out the two-layer patterned metal layer 812 and 821 that the protective layer top is used as power supply/ground connection reference voltage structure; wherein the patterned metal layer 821 of bottom is metallic circuit or plane 82; as route, bus or the plane of distributing a ground connection reference voltage Vss; the patterned metal layer 812 of top layer then is metallic circuit or plane 81, is used as circuit, bus or the plane of distributing a voltage vcc.In addition in Fig. 3 C; number 821 is in order to the patterned metal layer of representative as the ground connection reference voltage; wherein the numeral 1 on number 821 the right is expression the first metal layers; numeral 2 expression ground connection (ground) in the middle of the number 821, number 821 left-hand digits 8 are then represented protective layer upper metal (over-passivation metal).Similarly; in Fig. 3 C, number 812 is in order to the patterned metal layer of representative as power supply, and wherein the numeral 2 on number 812 the right is expression second metal levels; numeral 1 expression power supply (power) in the middle of the number 812, number 812 left-hand digits 8 are then represented the protective layer upper metal.Continue, one polymeric layer 98 separates two patterned metal layers 821 and 812, and one top polymeric layer 99 cover on the patterned metal layer 812 on top, wherein polymeric layer 98 can be polyimides, benzyl ring butylene, Parylene, epoxy-based material (for example epoxy resin or photoepoxy SU-8), elastomeric material (for example silicone).In addition; the alternative polymeric layer 97 (not showing among Fig. 3 C) that forms is between protective layer 5 and patterned metal layer 821 lowermost ends, and this polymeric layer 97 can be polyimides, benzyl ring butylene, Parylene, epoxy-based material (for example epoxy resin or photoepoxySU-8), elastomeric material (for example silicone).Material about the polymeric layer among Fig. 3 C 97,98,99 is then identical with Fig. 3 D with Fig. 3 B with processing, and relevant narration then will illustrate in follow-up Figure 15 series.In addition; being used among Fig. 3 C distributing the patterned metal layer 821 of ground connection reference voltage Vss is by protective layer opening 521; 522; 524; 529 and fine rule road metal structure 621; 622; 624; 629 are connected to the internal circuit 21 of protective layer below; 22; 23; 24 ground connection node Ts; Us; Vs; the ground connection node R s of Ws and pressurizer or transformer 41, being used for distributing the patterned metal layer 812 of voltage vcc then is by polymeric layer opening (not shown); protective layer opening (not shown) and fine rule road metal structure (not shown) are connected to the internal circuit 21 of protective layer below; 22; 23; 24 power supply node Tp; Up; Vp; the power supply node (not shown) of Wp and pressurizer or transformer 41.In addition, the electric current on flow through metallic circuit or plane 81,82 is between between 50 micromicroamperes to 2 milliampere or between between 100 micromicroamperes to 1 milliampere.
In some applications, metallic circuit or plane 81 except be used in power supply design, circuit or planes in metallic circuit or the plane 81 also can be used for transmitting data or signal (for example digital signal or analog signal).Similarly, metallic circuit or plane 82 except be used in ground connection design, circuit or planes in metallic circuit or the plane 82 also can be used to transmit data or signal (for example digital signal or analog signal).
Square structure still has more other patterns on the protective layer, it is described below: (1) is in the application of high-performance (highperformance) circuit or high-accuracy (high percision) analog circuit, can increase between patterned metal layer 812 and the patterned metal layer 821 and be used for a patterned metal layer (not shown) of transmission signal (for example digital signal or analog signal), and below this patterned metal layer and above be formed with a polymeric layer (not shown) respectively, this patterned metal layer and patterned metal layer 812 and patterned metal layer 821 are separated; (2) in the application of high electric current (high current) or high-accuracy (high percision) circuit, the top of patterned metal layer 812 can increase a patterned metal layer (not shown) that is used for distributing a ground connection reference voltage, and between this patterned metal layer and patterned metal layer 812, form a polymeric layer, and utilize a top polymeric layer to cover this patterned metal layer.In other words, patterned metal layer 812 is in patterned metal layer 821 centre of patterned metal layer therewith, thereby forms a kind of Vss/Vcc/Vss structure above protective layer 5; (3) if necessary, the patterned metal layer top that can further in above-mentioned (2), increase, formation is used for distributing another patterned metal layer (not shown) of a power supply, and form a polymeric layer between patterned metal layer that in above-mentioned (2), increases and the patterned metal layer 812, form another polymeric layer between the patterned metal layer that in above-mentioned (2), increases and another patterned metal layer, and one the top polymeric layer cover on another patterned metal layer, thereby produce the power supply/ground connection reference voltage structure of a kind of Vss/Vcc/Vss/Vcc (storehouse pattern from down to up).For high-current circuit, high-accuracy analog circuit, at a high speed for (high speed) circuit, low-power (lowpower) circuit, power management (power management) circuit and the high performance circuit, above-mentioned structure can provide a kind of stable power supply.
See also shown in Figure 4ly, it is open to go out at a pressurizer shown in Figure 1B to Fig. 1 D, Fig. 2 B to Fig. 2 C and Fig. 3 B to Fig. 3 D or an example of transformer 41.This example circuit is a transformer that has voltage stabilizing and transformation function simultaneously, and usually use as by B.Prince in 1991 and by John Wiley﹠amp; (Dynamic Random AccessMemory is in design DRAM) for the described modern DRAM (Dynamic Random Access Memory) of one book for " the Semiconductor Memories:Ahand book of Design; Manufacture andApplication " of Sons distribution.As shown in Figure 4, voltage stabilizing and transformation function by transformer, the voltage Vdd of external power supply input can be converted into an output voltage V cc, and the difference between this an output voltage V cc and the target setting voltage vcc 0 divided by the percentage of target setting voltage vcc 0 less than 10%, and being the preferably less than 5%.Described as " background technology " content, the voltage transitions that the integrated circuit (IC) chip in more modern times need rely on the mode of chip built-in transformer that outside (system, circuit board, module or circuit card) power supply is supplied becomes the required voltage of chip.In addition, some chip is as a DRAM (Dynamic Random Access Memory) chip, on same chip even need the voltage of twice or three times, for example peripheral control circuit uses 3.3 volts (V), and the internal storage location in the memory cell array zone (memory cell) uses 1.5 volts.
In Fig. 4, transformer includes two circuit blocks (circuit block), and it is reference voltage generator (voltage reference generator) 410 and current mirroring circuit (current mirror circuit) 410 '.Reference voltage generator 410 can produce a reference voltage VR in node R, with voltage fluctuation (voltage fluctuation) influence of the external power source supply voltage Vdd that avoids being subjected to node 4199.In addition, external power source supply voltage Vdd also is the input supply voltage (input supply voltage) of reference voltage generator 410.Reference voltage generator 410 includes two voltage dividers (voltage divider) path, the one, comprise three P type MOS (metal-oxide-semiconductor) transistor 4101,4103,4105 that link together, another then is to draw together two P type MOS (metal-oxide-semiconductor) transistor 4102,4104 that link together.Continue, the drain electrode (drain) by P type MOS (metal-oxide-semiconductor) transistor 4103 links to each other with the grid (gate) of P type MOS (metal-oxide-semiconductor) transistor 4104, and reference voltage VR can be regulated and control.Therefore, when external power source supply voltage Vdd fluctuation was risen, the voltage of node G rose, and causes the opening degree of P type MOS (metal-oxide-semiconductor) transistor 4104 lower, and then reference voltage VR is descended.Similarly, when external power source supply voltage Vdd descended, reference voltage VR then can rise.So far, above-mentioned content interpret the adjustment characteristic of reference voltage generator 410.The output of reference voltage generator 410 is intended for a reference voltage of current mirroring circuit 410 '.For an integrated circuit (IC) chip, current mirroring circuit 410 ' can be exported stable voltage and have the ability of big electric current, rely in addition and avoid the direct high current path of external power source supply voltage Vdd to ground connection reference voltage Vss, current mirroring circuit 410 ' also can be eliminated great power consumption or waste.In addition, drain electrode by P type MOS (metal-oxide-semiconductor) transistor 4109 links to each other with the grid of P type MOS (metal-oxide-semiconductor) transistor 4106, and output voltage node P is connected to the grid of reference voltage mirror (reference-voltage-mirror) P type MOS (metal-oxide-semiconductor) transistor 4110, current mirroring circuit 410 ' can be regulated and control the voltage vcc of output, allows the voltage vcc of output be controlled in the voltage of an appointment.In addition, it is a little P type MOS (metal-oxide-semiconductor) transistor that electricity is led transistor (conductance transistor) 4112, and its grid links to each other with ground connection reference voltage Vss, so electricity is led transistor 4112 and is in opening forever; And electricity to lead transistor 4111 be a big P type MOS (metal-oxide-semiconductor) transistor, and its grid is subjected to the control of a signal Φ, when internal circuit during in the active cycle (active cycle), electricity is led transistor 4111 and is in opening, allows P type MOS (metal-oxide-semiconductor) transistor 4109 and N type MOS (metal-oxide-semiconductor) transistor 4107 formed current paths (curren path) and P type MOS (metal-oxide-semiconductor) transistor 4110 have quick response (fast response) with N type MOS (metal-oxide-semiconductor) transistor 4108 formed current paths.In addition, electricity is led the unlatching of transistor 4111, big transient current (transient current) the unsettled situation of output voltage V cc moment that demand caused of internal circuit (for example internal circuit 21,22,23,24 among Figure 1B to Fig. 1 C, Fig. 2 B to Fig. 2 C, Fig. 3 B to Fig. 3 D) can be reduced to minimum.When internal circuit when idle period (idle cycle), 4111 in transistor is in closed condition, to avoid power consumption (power consumption).
Second embodiment: the protective layer top connection line (over-passivation interconnection) that connects internal circuit (internal circuit).
Formerly hold within disclosed in the patent as patentee of the present invention; for example United States Patent (USP) the 6th; 657; No. 310 and United States Patent (USP) the 6th; 495; No. 442, thick metallic conductor of the present invention (or metallic circuit or plane of protective layer top) can be used for distributing signal, voltage or ground connection reference voltage.In addition; " protective layer top (over-passivation) " used in the present invention words is that patentee of the present invention is formerly in the patent; for example United States Patent (USP) the 6th; 495; No. 442; " back sheath (post-passivation) " words of selected use, and the metallic circuit of " protective layer top " or plane are such as the connection line that can be used as lsi internal circuit (interconnection).In this embodiment, thick metallic conductor (or protective layer top metallic circuit or plane) can be sent to data or signal one input node (input node) of one second internal circuit from an output node (output node) of one first internal circuit.Design is used for connecting a branch of metallic circuit of two one group of similar nodes (for example data, position or signal address) at a distance of between the internal circuit of growing (for example above 1 millimeter), for example be used for connecting processor unit on the same chip and 8,16,32,64,128,256,512 or 1024 data (or address) metallic circuit between an internal storage location, usually these metallic circuits are called bus (bus), and this bus is such as character (word) bus or position (bit) bus of being to use in an internal memory.In addition; because the present invention provides a thick metallic conductor (or metallic circuit or plane of protective layer top) to connect a plurality of internal circuits above protective layer; and this thick metallic conductor can be away from semiconductor subassembly; so when signal when blocked up metallic conductor (or protective layer top metallic circuit or plane); can reduce this signal and upset the situation of lower semiconductor assembly; or can reduce the situation of this signal of lower semiconductor component interference, allow this signal have preferable integrality (signal integrity).Only; in this embodiment; the thick metallic conductor of protective layer top (or metallic circuit or plane of protective layer top) only connects the node of internal circuit; do not connect outer input/output circuitry (off-chip input/output circuit), be not connected to an external circuit yet through any chip.In addition, the thick metallic conductor above the protective layer of the present invention (or metallic circuit or plane of protective layer top) design is to be different from the design that existing connection pad reconfigures (pad redistribution).In addition; because thick metallic conductor (or metallic circuit or plane of protective layer top) has low-resistance advantage and caused parasitism (parasitic) electric capacity is very low; so signal will can not decayed tempestuously, make the present invention be suitable for use in very much in the application of high speed, low-power, high electric current or low-voltage.The present invention is under most of situation, do not need extra amplifier, driver or signal relay (repeater) help keep the integrality of signal, yet in some cases, then need an inner drive (internal driver), inner receiver (internal receiver), signal relay or inner tristate buffer (internal tri-state buffer), grow distance and transmit signal, and inner drive, inner receiver, inner tristate buffer or signal relay include size connects the MOS (metal-oxide-semiconductor) transistor (MOS transistor) of external circuit less than chip MOS (metal-oxide-semiconductor) transistor, as for relevant internal circuit, inner drive, inner receiver, inner tristate buffer and chip connect the size of the MOS (metal-oxide-semiconductor) transistor of external circuit, narrate in detail in will holding within follow-up and compare.
Now please consult simultaneously shown in Fig. 5 B, Fig. 6 B and Fig. 7 B, it is openly to go out the second embodiment of the present invention.Fig. 5 B presents a circuit diagram of simplifying, and it is to utilize metallic circuit on the protective layer 5 or the fine rule road metal structure 631 under plane 83 and the protective layer 5,632a, 632b, 632c, 634 to connect internal circuits 20 (comprising 21,22,23,24).In Fig. 5 B, internal circuit 21 has an input nodes X i and an output node Xo, and send a signal by output node Xo, and this signal can rely on metallic circuit or plane 83 and fine rule road metal structure 631,632a, 632b, 632c, 634 are sent to internal circuit 22,23,24 input node Ui, Vi, Wi, internal circuit 21 can be a gate (logic gate) in addition, for example anti-or (NOR) door, anti-and (NAND) door, or (OR) door, with (AND) door, or an internal buffer is (as Fig. 5 C, inverter shown in Fig. 5 D and Fig. 5 E, inner drive or inner tristate buffer).Fig. 6 B presents the schematic top plan view of the circuit shown in Fig. 5 B.Fig. 7 B then presents the generalized section of the circuit shown in Fig. 5 B.In addition, in Fig. 5 B and Fig. 6 B, the circuit or the plane that are formed on the protective layer 5 represent that with " thick line " line construction that is formed under the protective layer 5 is then represented with " fine rule ".
In the present invention, the inner drive that is used for driving protective layer upper metal circuit is identical with the U.S. No. 20040089951 (patentee's of the present invention previous patent) described chip inner driver (intra-chipdriver) of publication.By protective layer opening 532,534 in the metallic circuit on the protective layer 5 or plane 83, the protective layer 5 and fine rule road metal structure 631,632a, 632b, the 632c, 634 under the protective layer 5; three internal logic circuits (internal circuit 22,24 is a NOR gate, and internal circuit 23 is and door) can receive data or signal that internal circuit 21 is transmitted.Because the characteristic that the metallic circuit of protective layer top or plane 83 have low resistance and can produce low parasitic capacitance, so input node Ui, Vi, Wi have very little decay and noise between the voltage amplitude between the Vdd to Vss (voltage swing).In addition, in the present embodiment, metallic circuit or plane do not need to be connected to any chip that will be used for being connected to an external circuit in follow-up the 11st figure series and connect external circuit, for example Electrostatic Discharge protection circuit, chip connect outer driver, chip connects outer receiver or chip connects outer buffer circuits (for example chip three-state buffer circuit), so present embodiment can improve speed and reduce power consumption.
Please consult simultaneously shown in Fig. 5 A, Fig. 6 A and Fig. 7 A; it is the related art for present embodiment; as shown in the figure, the internal circuit 21 that is positioned at protective layer 5 belows is to be connected to an internal circuit 22 (a for example NOR gate), to be connected to an internal circuit 23 (a for example NAND gate) and to be connected to other internal circuit 24 (a for example NOR gate) by fine rule road metal structure 6311,638,6341 by fine rule road metal structure 6311,638,6321a, 6321c by fine rule road metal structure 6311,638,6321a, 6321b.Therefore, existing is to rely on the fine rule road metal structure 638,6311,6321,6341 that is positioned at protective layer 5 belows the data of internal circuit 21 outputs are sent to other internal circuit 22,23,24.Only, existing design can cause signal attenuation, performance reduction, high power consumption and produce high heat.
Then, please consult simultaneously shown in Fig. 5 B and Fig. 6 B, it is to set up a metallic circuit or plane 83 on protective layer 5, and by being arranged in metallic circuit or plane 83 replacement Fig. 5 A and Fig. 6 A fine rule road metal structures 638 on the protective layer 5, make internal circuit 21,22,23,24 rely on metallic circuit or plane 83 to link together, as shown in the figure, one signal is by an output node (the normally drain electrode of a MOS (metal-oxide-semiconductor) transistor of the internal circuit 21) output of internal circuit 21, transmit fine rule road metal structure 631 then through protective layer 5 belows, the protective layer opening 531 of protective layer 5 and metallic circuit on the protective layer 5 or plane 83, then (1) is through the protective layer opening 534 of protective layer 5 and the fine rule road metal structure 634 under the protective layer 5, hand down at last and deliver to an input node (the normally grid of a MOS (metal-oxide-semiconductor) transistor of internal circuit 24, for example grid of a MOS (metal-oxide-semiconductor) transistor of NOR gate) of internal circuit 24 (a for example NOR gate); (2) through the protective layer opening 532 of protective layer 5 and the fine rule road metal structure 632 (comprising 632a, 632b, 632c) under the protective layer 5; be sent to internal circuit 22 (a for example NOR gate) at last and import node (being respectively the grid of a MOS (metal-oxide-semiconductor) transistor of internal circuit 22 and internal circuit 23 usually, for example is respectively the grid of a MOS (metal-oxide-semiconductor) transistor of NOR gate and NAND gate) with one of internal circuit 23 (a for example NAND gate).
Therefore; in sum; one output node of internal circuit 21 (the normally drain electrode of a MOS (metal-oxide-semiconductor) transistor of internal circuit 21) is to be connected with fine rule road metal structure 631 under the protective layer 5; then through metallic circuit or plane 83 on the protective layer opening 531 connection protective layers 5 of protective layer 5; be connected at last through the fine rule road metal structure 632,634 under protective layer opening 532, the 534 connection protective layers 5 of protective layer 5, and then with an input node (the normally grid of a MOS (metal-oxide-semiconductor) transistor of internal circuit 22,23,24) of internal circuit 22,23,24.Wherein, internal circuit 21,22,23,24 comprise a NOR gate, one or the door, one with the door or a NAND gate, and internal circuit 21,22,23, the 24th, constituted institute by a MOS (metal-oxide-semiconductor) transistor at least and constituted, that is to say NOR gate, or door, at least constituted by a MOS (metal-oxide-semiconductor) transistor with door inclusive NAND door, and this MOS (metal-oxide-semiconductor) transistor is such as being that size (channel width is divided by the ratio of passage length) is between the N type MOS (metal-oxide-semiconductor) transistor between 0.1 to 5 or between 0.2 to 2, or size (channel width is divided by the ratio of passage length) is between the P type MOS (metal-oxide-semiconductor) transistor between 0.2 to 10 or between 0.4 to 4, other flow through current ratio scope between 50 micromicroamperes (μ A) are to 2 milliamperes in this way on metallic circuit or plane 83, or between between 100 micromicroamperes to 1 milliampere.
Continue; please consult simultaneously shown in Fig. 7 B and Fig. 7 C; it is two kinds of enforcement aspects of the circuit structure shown in Fig. 5 B; shown in two figure; the metallic circuit of protective layer 5 tops or plane 83 can be single layer pattern metal level (the single layer pattern metal levels 831 shown in Fig. 7 B); or multi-layered patterned metal level; and between each adjacent patterns metal level, has a polymeric layer; the two-layer patterned metal layer 831 shown in Fig. 7 C (comprising 831a and 831b) and 832 for example, and between two patterned metal layers 831 and 832, have a polymeric layer 98.In addition, the metallic circuit of protective layer 5 tops or plane 83 can cover a top polymeric layer 99 (shown in Fig. 7 B, a top polymeric layer 99 covers on the metal level 831; Shown in Fig. 7 C; one top polymeric layer 99 covers on the patterned metal layer 832); and top polymeric layer 99 not opening expose metallic circuit or plane 83, so the metallic circuit of protective layer 5 tops or plane 83 (for example patterned metal layer 831 or patterned metal layer 832) can't be connected to external circuit.In other words, in this embodiment, metallic circuit or plane 83 (for example patterned metal layer 831 or patterned metal layer 832) is not used for connecting the contact connection pad (contact pad) of external circuit.
In Fig. 7 B, the number of patterned metal layer 831 respectively is representative: " 8 " are to represent the protective layer upper metal, and " 3 " are to represent a signal circuit, and " 1 " then is the first metal layer of representing the protective layer top.In like manner know by inference, in Fig. 7 C, the number of patterned metal layer 832 respectively is representative: " 8 " are to represent the protective layer upper metal, and " 3 " are to represent a signal circuit, and " 2 " then are second metal levels of representing the protective layer top.In addition; patterned metal layer 831 on the protective layer 5 comprises that one sticks together/hinder barrier/Seed Layer (adhesion/barrier/seed layer) 8311 and one thick metal layers 8312; alternative in addition formation one polymeric layer 95 is between the protective layer 5 and patterned metal layer 831 bottoms, shown in Fig. 7 D.In like manner; in Fig. 7 C; patterned metal layer 831a, 831b, 832 on the protective layer 5 comprises that one sticks together/hinder barrier/Seed Layer 8311a, 8311b, 8321 and one thick metal layers 8312a, 8312b, 8322, and the alternative polymeric layer 95 that forms is between the protective layer 5 and patterned metal layer 831 (comprising 831a, the 831b) bottom.
Fig. 7 C square structure on protective layer include two patterned metal layers 831 and 832, all the other are all similar to Fig. 7 B.In Fig. 7 C, it is to replace single pattern metal level 831 among Fig. 7 B with two patterned metal layers 831 (comprising 831a, 831b) and patterned metal layer 832, and utilizes a polymeric layer 98 to separate patterned metal layer 831 and patterned metal layer 832.In addition aspect the signal transmission, the output node of circuit 21 (the normally drain electrode of a MOS (metal-oxide-semiconductor) transistor of the internal circuit 21) output internally of one signal, transmit fine rule road metal structure 631 then through protective layer 5 belows, protective layer opening 531 in the protective layer 5 and the patterned metal layer 831b of protective layer 5 tops, then (1) is in first path: up pass through the opening polymeric layer 9831 in the polymeric layer 98, through patterned metal layer 832, down through a polymeric layer opening 9834, through patterned metal layer 831a, protective layer opening 534 through protective layer 5, fine rule road metal structure 634 through protective layer 5 belows, hand down at last and deliver to an input node (the normally grid of a MOS (metal-oxide-semiconductor) transistor of internal circuit 24, for example grid of a MOS (metal-oxide-semiconductor) transistor of NOR gate) of internal circuit 24 (for example NOR gate); (2) in second path: down through a protective layer opening 532 of protective layer 5 and through the fine rule road metal structure 632 under the protective layer 5; be sent to internal circuit 22 (for example NOR gate) at last and import node (being respectively the grid of a MOS (metal-oxide-semiconductor) transistor of internal circuit 22 and internal circuit 23 usually, for example is respectively the grid of a MOS (metal-oxide-semiconductor) transistor of NOR gate and NAND gate) with one of internal circuit 23 (for example NAND gate).
In addition, the part of protective layer upper metal circuit or plane, polymeric layer and the internal circuit of relevant second embodiment of the invention will be narrated in follow-up Figure 15 series, Figure 16 series, Figure 17 series, Figure 18 series and Figure 19 series in detail.
In addition, in Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C and Fig. 7 D, metallic circuit or plane 83 (comprise 831 and/or 832) do not have and connect external circuit with the chip that is used for being connected an external circuit and connect, so can not produce apparent voltage drop (voltage drop) or signal attenuation on metallic circuit or the plane 83.
In addition, it is the ratio of channel width (channel width) divided by passage length (channel length) that the size of the present invention's one MOS (metal-oxide-semiconductor) transistor may be defined as, or to speak by the book be the ratio of effective channel width divided by effective channel length, and this definition is useful among all embodiment of the present invention.
Please consult shown in Fig. 5 C to Fig. 5 E now simultaneously, it is openly to go out the example of internal circuit 21 as an internal buffer (internal buffer), wherein this internal buffer is made of a MOS (metal-oxide-semiconductor) transistor (MOStransistor) at least, and this MOS (metal-oxide-semiconductor) transistor is such as comprising that channel width/passage length ratio is between the P type MOS (metal-oxide-semiconductor) transistor (PMOS transistor) between 3 to 60 or between 5 to 20, or channel width/passage length ratio is between the N type MOS (metal-oxide-semiconductor) transistor (NMOS transistor) between 1.5 to 30 or between 2.5 to 10, and the electric current on flow through this moment metallic circuit or plane 83 is between between 500 micromicroamperes to 10 milliampere or between between 700 micromicroamperes to 2 milliampere.Fig. 5 C discloses an inverter 211, in order to the internal circuit 21 as Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C and Fig. 7 D.In first is used, N type MOS (metal-oxide-semiconductor) transistor 2101 and the size of P type MOS (metal-oxide-semiconductor) transistor 2102 can and be used measure-alike in the MOS (metal-oxide-semiconductor) transistor of internal circuit, so in inverter 211, the size of N type MOS (metal-oxide-semiconductor) transistor 2101 is between 0.1 to 5, and being the preferably between 0.2 to 2, the size of P type MOS (metal-oxide-semiconductor) transistor 2102 then is between 0.2 to 10, and being the preferably between 0.4 to 4.In addition, are scopes between 50 micromicroamperes (μ A) are to 2 milliamperes by inverter 211 output and through the electric current on the metallic circuit of protective layer 5 tops or plane 83, and being the preferably between the scope between 100 micromicroamperes to 1 milliampere.In second application, inverter 211 needs to export a bigger drive current (drive current), for example when internal circuit 22,23,24 needs high capacity (heavy load), or when internal circuit 22,23,24 and internal circuit 21 at a distance of need greater than 1 millimeter or 3 millimeters a long distance be connected metallic circuit the time, inverter 211 needs the bigger drive current of output one.In addition, electric current from inverter 211 output is to be higher than general internal circuit, and electric current, for example 1 milliampere (mA) or 5 milliamperes, be the scope between 500 micromicroamperes (μ A) are to 10 milliamperes, and being the preferably between the scope between 700 micromicroamperes to 2 milliampere.Therefore, in second application, the size of the N type MOS (metal-oxide-semiconductor) transistor 2101 of inverter 211 is the scopes between 1.5 to 30, and be the preferably with the scope between 2.5 to 10, the size of P type MOS (metal-oxide-semiconductor) transistor 2102 is the scope between 3 to 60 then, and is the preferably with the scope between 5 to 20.As for the size of the MOS (metal-oxide-semiconductor) transistor of more relevant (general) internal circuits or be used for driving within the internal circuit of other high capacity internal circuit and hold, will in follow-up Figure 15 series, be described in detail.
In addition; in Fig. 5 C; the drain electrode of N type MOS (metal-oxide-semiconductor) transistor 2101 is to be connected with the metallic circuit of protective layer 5 tops or plane 83 (as Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C with shown in Fig. 7 D), and the drain electrode of P type MOS (metal-oxide-semiconductor) transistor 2102 then is to be connected with the metallic circuit of protective layer 5 tops or plane 83 (as Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C with shown in Fig. 7 D).
In most application; because the metallic circuit or the plane of protective layer top have less impedance; so a plurality of internal circuits that formed by less MOS (metal-oxide-semiconductor) transistor can interconnect by metallic circuit on the protective layer or plane; more wherein said internal circuit comprises size (channel width is divided by the ratio of passage length) between the N type MOS (metal-oxide-semiconductor) transistor between 0.1 to 5 or between 0.2 to 2, or size (channel width is divided by the ratio of passage length) is between the P type MOS (metal-oxide-semiconductor) transistor between 0.2 to 10 or between 0.4 to 4.In addition, on some is used, when internal circuit 22,23,24 needs high capacity, or when internal circuit 22,23,24 and internal circuit 21 at a distance of need greater than 1 millimeter or 3 millimeters a long distance be connected metallic circuit the time, then need a bigger drive current.Therefore, in the situation of high capacity, need an inner drive (internal drive) or an internal buffer (internal buffer).
Fig. 5 D and Fig. 5 E open go out with inner drive 212 or inner tristate buffer 213 as internal circuit 21, and utilize the metallic circuit on the protective layer 5 that inner drive 212 or inner tristate buffer 213 drive shown in Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C and Fig. 7 D or the example of plane 83 and other internal circuit 22,23,24.Fig. 5 D and the circuit shown in Fig. 5 E are not connected with an external circuit except (1) inner drive 212 or inner tristate buffer 213; And the MOS (metal-oxide-semiconductor) transistor size of (2) inner drive 212 or inner tristate buffer 213 connect less than chip outer driver or chip tristate buffer the MOS (metal-oxide-semiconductor) transistor size outside, to connect external circuit (off-chip circuit) similar to subsequent figure 11A and the chip described in Figure 11 C respectively for all the other.Inner drive 212 among Fig. 5 D is to be the example of patentee of the present invention at the chip inner driver (intra-chip driver) described in No. the 20040089951st, U.S.'s publication.Inner tristate buffer 213 provides and has amplified the ability (drive capability) of signal and the ability (switch capability) that opens or closes, and inner tristate buffer 213 helps especially as a data signals or an address signal in metallic circuit above the protective layer of data or address bus or planar transmission one memory chip.
In Fig. 5 D; the size of N type MOS (metal-oxide-semiconductor) transistor 2103 is between 1.5 to 30; and being the preferably between 2.5 to 10; the size of P type MOS (metal-oxide-semiconductor) transistor 2104 then is between 3 to 60; and being the preferably between 5 to 20; the electric current that passes through the electric current on metallic circuit on the protective layer 5 or plane 83 and inner drive 212 output node Xo (being generally the drain electrode of a metal semiconductor assembly) output in addition is between the scope between 500 micromicroamperes to 10 milliampere, and being the preferably between the scope between 700 micromicroamperes to 2 milliampere.In addition; in Fig. 5 D, inner drive 212 can drive a signal of output node Xo output, and behind the metallic circuit or plane 83 above the process protective layer 5; be sent to input node Ui, Vi, the Wi of internal circuit 22,23,24, but be not sent to an external circuit.
In Fig. 5 E; the size of N type MOS (metal-oxide-semiconductor) transistor 2107 is between 1.5 to 30; and being the preferably between 2.5 to 10; the size of P type MOS (metal-oxide-semiconductor) transistor 2108 then is between 3 to 60; and being the preferably between 5 to 20; be between the scope between 500 micromicroamperes to 10 milliampere through the electric current of the output node Xo output of the metallic circuit of protective layer 5 tops or plane 83 and inner tristate buffer 213 in addition, and being the preferably between the scope between 700 micromicroamperes to 2 milliampere.In addition; in Fig. 5 E, inner tristate buffer 213 can drive the signal from output node Xo output, and behind the metallic circuit or plane 83 above the process protective layer 5; be sent to input node Ui, Vi, the Wi of internal circuit 22,23,24, but be not sent to an external circuit.
When internal circuit 22,23,24 needs high capacity, or when internal circuit 22,23,24 and internal circuit 21 at a distance of need greater than 1 millimeter or 3 millimeters a long distance be connected metallic circuit the time, the output node Xo of inner drive 212 and inner tristate buffer 213 need export a bigger drive current.
One of the important application on protective layer upper metal circuit or plane is the internal storage location (memory cell) and internal circuit (for example logical circuit) that a segment distance is arranged connecting on the memory chip apart.See also shown in Fig. 5 F, it is openly to go out an internal storage location how to utilize metallic circuit on the protective layer 5 or the fine rule road metal structure under plane 83 and the protective layer 5 to be connected to internal circuit 22,23,24 (Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C and Fig. 7 D) as logical circuit.Wherein, this logical circuit is such as comprising a NOR gate, one or the door, one with the door or a NAND gate, internal circuit 22 in addition, 23,24 are made of a MOS (metal-oxide-semiconductor) transistor at least, and above-mentioned fine rule road metal structure is to be connected to internal circuit 22,23, a MOS (metal-oxide-semiconductor) transistor of 24, for example be connected to the source electrode (source) of a MOS (metal-oxide-semiconductor) transistor, drain electrode (drain) or gate pole (gate), and this MOS (metal-oxide-semiconductor) transistor can be that channel width/passage length ratio is between the N type MOS (metal-oxide-semiconductor) transistor between 0.1 to 5 or between 0.2 to 2, or channel width/passage length ratio is between the P type MOS (metal-oxide-semiconductor) transistor between 0.2 to 10 or between 0.4 to 4, and the current ratio on flow through in addition metallic circuit or plane 83 is in this way between between 50 micromicroamperes to 2 milliampere or between between 100 micromicroamperes to 1 milliampere.
In this used, metallic circuit on the protective layer 5 or plane 83 were as a data/address bus (data bus), for example a bit line (bit line) bus or reverse bit line (bit line) bus.In the design that connects a memory array (memory array) and logical circuit; can on protective layer 5, form 4,8,16,32,64,128,256,512,1024,2048 or 4096 metallic circuit or the plane 83 that is arranged in parallel; as the data/address bus of a memory chip, and the data signals of utilizing these metallic circuits or plane 83 to transmit between internal storage locations and the logical circuit.The metallic circuit of protective layer 5 tops or plane 83 particularly suitables for example transmit the data of 64,128,256,512,1024 bit widths (bit width) in the transmission of wide position (wide-bit) data.In addition; when the signal between transmission internal storage location and the logical circuit (logic circuit); the metallic circuit of protective layer 5 tops or plane 83 except as above-mentioned carry and data/address bus, also can be used as address bus (address bus), in order to the transport address signal.In addition, the signal of metallic circuit on the protective layer 5 or plane 83 transmission also comprises frequency (clock) signal.Fig. 5 F is with the example of a sram cell 215 as internal storage location, only this internal storage location also can be other internal storage location in the present embodiment, for example DRAM (Dynamic Random Access Memory) (DRAM) unit, Erasable ﹠Programmable ROM (EPROM) but unit, electronics cancelling read-only memory (EEPROM) unit, flash memory (Flash) unit, read-only memory (ROM) unit and magnetic RAM (magnetic RAM, MRAM) unit.This sram cell 215 includes six MOS (metal-oxide-semiconductor) transistor, it is two driving N type MOS (metal-oxide-semiconductor) transistor 2115,2117, two load P type MOS (metal-oxide-semiconductor) transistor 2116,2118, and two character code-line-controls (word-line-control) N type MOS (metal-oxide-semiconductor) transistor 2119,2120.In addition, in a memory chip, rely on repetition sram cell 215 can form a memory array.When sram cell 215 during at reading state, sram cell 215 output complementary datas, for example position (bit) data and oppositely position (bit) data, and respectively by N type MOS (metal-oxide-semiconductor) transistor 2119 and N type MOS (metal-oxide-semiconductor) transistor 2120 complementary data transmission is put in place (bit) line and reverse position (bit) line, (column selection CS) inputs to a sensing amplifier (sense amplifier) 214 behind the transistor 2122,2123 through the space selection to follow (bit) data and (bit) data transmission of reverse position.Come again, the bit line of internal storage location connects the grid of the N type MOS (metal-oxide-semiconductor) transistor 2113 in the sensing amplifier 214, the the opening or closing of N type MOS (metal-oxide-semiconductor) transistor 2113 with control sensing amplifier 214, when the N of sensing amplifier 214 type MOS (metal-oxide-semiconductor) transistor 2113 is opened, sensing amplifier 214 can just make the reverse position of amplification (bit) data make it have preferable waveform or preferable voltage quasi position, and exports this through just making reverse position (bit) data of amplification to inner tristate buffer 213.In Fig. 5 F, it is to use a differential amplifier (differential amplifier) to be used as an example of sensing amplifier 214, this differential amplifier contains four transistors, comprise 2111,2113 and two P type MOS (metal-oxide-semiconductor) transistor 2112,2114 of two N type MOS (metal-oxide-semiconductor) transistor, wherein this differential amplifier is to utilize N type MOS (metal-oxide-semiconductor) transistor 2121 to isolate differential amplifier and ground connection reference voltage Vss, and rely on delegation to select signal to control differential amplifier, to avoid power consumption.When sram cell 215 during not at reading state, also promptly when the character line that connects sram cell 215 and bit line are not selected, 2121 of N type MOS (metal-oxide-semiconductor) transistor are closed.From reverse position (bit) data that N type MOS (metal-oxide-semiconductor) transistor 2113 grids of sensing amplifier 214 are exported are the input nodes X i that are sent to an inner drive, internal buffer or inner tristate buffer 213 (shown in Fig. 5 F).In addition, to be output read (read enable) circuit (not shown) from one for controlling signal En, En, and utilize this controlling signal En, En to control the unlatching of inner tristate buffer 213 or close.In Fig. 5 F, the output node Xo of inner tristate buffer 213 exports the bit data of amplification more to internal circuit 22,23,24 (shown in Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C and Fig. 7 D) by metallic circuit on the protective layer 5 or plane 83.Therefore; comprehensive the above; one sram cell 215 is to be connected to internal circuit 22,23,24 on the same chip by the fine rule road metal structure 631 under sensing amplifier 214, inner tristate buffer 213, the protective layer 5, protective layer opening 531, metallic circuit on the protective layer 5 or plane 83, protective layer opening 532,534 in the protective layer 5 and fine rule road metal structure 632,634 in the protective layer 5, shown in Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C and Fig. 7 D.Wherein, internal circuit 21 is an inner tristate buffer 213 at this, only this internal circuit 21 also can be inner drive 212 (shown in Fig. 5 D) or other internal circuit, NOR gate (NOR gate) for example, NAND gate (NAND gate), with door (AND gate), or door (OR gate), adder (adder), multiplexer (multiplexer), duplexer (diplexer), multiplier (multiplier), CMOS (Complementary Metal Oxide Semiconductor), two-carrier CMOS (Complementary Metal Oxide Semiconductor) or two-carrier circuit (bipolar circuit), and when internal circuit 21 is inner drive 212, inner the tunnel 21 is made of a MOS (metal-oxide-semiconductor) transistor at least, and this MOS (metal-oxide-semiconductor) transistor comprises that channel width/passage length ratio is between the P type MOS (metal-oxide-semiconductor) transistor between 3 to 60 or between 5 to 20, or channel width/passage length ratio is between the N type MOS (metal-oxide-semiconductor) transistor between 1.5 to 30 or between 2.5 to 10, and the electric current on flow through this moment metallic circuit or plane 83 is between between 500 micromicroamperes to 10 milliampere or between between 700 micromicroamperes to 2 milliampere; In addition, when internal circuit 21 is above-mentioned other internal circuit, this inner the tunnel 21 comprises that at least channel width/passage length ratio is between the N type MOS (metal-oxide-semiconductor) transistor between 0.1 to 5 or between 0.2 to 2, or channel width/passage length ratio is between the P type MOS (metal-oxide-semiconductor) transistor between 0.2 to 10 or between 0.4 to 4, and the electric current on flow through this moment metallic circuit or plane 83 is between between 50 micromicroamperes to 2 milliampere or between between 100 micromicroamperes to 1 milliampere.
See also shown in Fig. 5 G, reverse position (bit) data of sensing amplifier 214 outputs will be passed through circuit (pass circuit) 216 through one earlier before the output node Xo that arrives internal circuit 21, be by circuit 216 at this internal circuit 21.This can be a simple MOS (metal-oxide-semiconductor) transistor by circuit 216, N type MOS (metal-oxide-semiconductor) transistor 2124 for example, and controlled by a reading signal.In this design; one sram cell 215 is by sensing amplifier 214, is connected to internal circuit 22,23,24 by the fine rule road metal structure 631 under circuit 216, the protective layer 5, protective layer opening 531, metallic circuit on the protective layer 5 or plane 83, protective layer opening 532,534 in the protective layer 5 and the fine rule road metal structure 632,634 under the protective layer 5 in the protective layer 5, shown in Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C and Fig. 7 D.
See also shown in Fig. 5 H, reverse position (bit) data of sensing amplifier 214 outputs will be latch circuit 217 at this internal circuit 21 earlier through a latch circuit (latch circuit) 217 before the output node Xo that arrives internal circuit 21.Latch circuit 217 can be a sram cell, in order to send in the data of sensing amplifier 214 output logical circuit (as internal circuit 22,23,24) before, temporarily store the data (also being that data are lived by breech lock) of sensing amplifier 214 outputs.In addition, N type MOS (metal-oxide-semiconductor) transistor 2129,2130 can be controlled by a reading signal.In this design; one sram cell 215 is to be connected to internal circuit 22,23,24 by the fine rule road metal structure 631 under sensing amplifier 214, latch circuit 217, the protective layer 5, protective layer opening 531, metallic circuit on the protective layer 5 or the plane 83 in the protective layer 5, protective layer opening 532,534 and the fine rule road metal structure 632,634 in the protective layer 5, shown in Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C and Fig. 7 D.
Yet the latch circuit 217 that passes through circuit 216 or Fig. 5 H of Fig. 5 G does not provide big driving force.In order to drive the internal circuit 22,23,24 that needs high capacity, or the length Distance Transmission arrives internal circuit 22,23,24 by reverse position (bit) data of circuit 216 outputs or position (bit) data of latch circuit 217 outputs, can increase that foregoing is carried at the output node (shown in Fig. 5 J) of output node (shown in Fig. 5 I) by circuit or latch circuit and an inner drive 212, amplify by reverse position (bit) data of circuit 216 outputs or (bit) data of latch circuit 217 outputs to utilize this inner drive 212.
See also shown in the 5K figure, except internal circuit 21 is the signals that receive from internal circuit 24 (is a NOR gate at this), rather than drive internal circuit 24 outside, the remaining circuit design is all similar to Fig. 5 B.This internal circuit 24 (is a NOR gate at this) is by the fine rule road metal structure 634 ' under the protective layer 5; protective layer opening 534 ' in the protective layer 5; metallic circuit on the protective layer 5 or plane 83; protective layer opening 531 ' in the protective layer 5 and the fine rule road metal structure 631 ' under the protective layer 5; the input nodes X i ' (the normally grid of a MOS (metal-oxide-semiconductor) transistor of internal circuit 21) that signal that its output node Wo is sent or data are sent to internal circuit 21; internal circuit 24 (is a NOR gate at this) is also by the fine rule road metal structure 634 ' under the protective layer 5 simultaneously; protective layer opening 534 ' in the protective layer 5; metallic circuit on the protective layer 5 or plane 83; protective layer opening 532 ' in the protective layer 5 and the fine rule road metal structure 632a ' under the protective layer 5; 632b ', the input node Ui that signal that its output node Wo is sent or data are sent to internal circuit 22 (is a NOR gate at this).Moreover; simultaneously internal circuit 24 (is a NOR gate at this) is also by fine rule road metal structure 634 ', the protective layer opening 534 ' in the protective layer 5, the metallic circuit on the protective layer 5 or plane 83, the protective layer opening 532 ' in the protective layer 5 and fine rule road metal structure 632a ', the 632c ' under the protective layer 5 under the protective layer 5, the input node vi that signal that its output node Wo is sent or data are sent to internal circuit 23 (is a NAND gate at this).Wherein, fine rule road metal structure 634 ', 631 ' can be formed by metallic circuit and plane, and in this example, fine rule road metal structure 634 ', 631 ' is to be formed by the conductive plug in the dielectric layer and metallic pad and fine rule road metal level, and for example the storehouse mode with rough aligning forms.In some integrated circuit technique, conductive plug is to be tungsten plug (tungsten plug) or damascene copper (damascene copper).Internal circuit the 21,22, the 23rd receives signal with input nodes X i ', Ui, Vi, and at output node Xo ', Uo, Vo signal is outputed to other internal circuit.In addition, internal circuit 21 can be an internal interface receiver 212 ' (shown in Fig. 5 L) at this, one inner tristate buffer 213 ' (shown in Fig. 5 M) or other internal circuit, such as being NOR gate (NORgate), NAND gate (NAND gate), with door (AND gate), or door (OR gate), operational amplifier (operational amplifier), adder (adder), multiplexer (multiplexer), duplexer (diplexer), multiplier (multiplier), analog/digital converter (A/D converter), digital/analog converter (D/AConverter), CMOS (Complementary Metal Oxide Semiconductor), two-carrier CMOS (Complementary Metal Oxide Semiconductor) or two-carrier circuit (bipolar circuit), and when internal circuit 21 is internal interface receiver 212 ', internal circuit 21 is made of a MOS (metal-oxide-semiconductor) transistor at least, and this MOS (metal-oxide-semiconductor) transistor comprise channel width/passage length ratio between between 3 to 60 or between the P type MOS (metal-oxide-semiconductor) transistor between 5 to 20 or channel width/passage length ratio between the N type MOS (metal-oxide-semiconductor) transistor between 1.5 to 30 or between 2.5 to 10, and the electric current on flow through this moment metallic circuit or plane 83 is between between 500 micromicroamperes to 10 milliampere or between between 700 micromicroamperes to 2 milliampere; In addition, when internal circuit 21 is above-mentioned other internal circuit, this inner the tunnel 21 comprise at least channel width/passage length ratio between between 0.1 to 5 or between the N type MOS (metal-oxide-semiconductor) transistor between 0.2 to 2 or channel width/passage length ratio between the P type MOS (metal-oxide-semiconductor) transistor between 0.2 to 10 or between 0.4 to 4, and the electric current on flow through this moment metallic circuit or plane 83 is between between 50 micromicroamperes to 2 milliampere or between between 100 micromicroamperes to 1 milliampere.Except that this, internal circuit 21 still comprises a sram cell (SRAM cell), DRAM (Dynamic Random Access Memory) unit (DRAM cell), non-volatile memory cell (non-volatile memory cell), flash cell (flash memory cell), Erasable ﹠Programmable ROM unit (EPROM cell) ROM unit (ROM cell), magnetic RAM (magnetic RAM, MRAM) unit or sensing amplifier (sense amplifier).In addition, the input node of internal circuit 21 is the grid of a MOS (metal-oxide-semiconductor) transistor normally.See also shown in Fig. 5 L, inner receiver 212 ' can be accepted a signal via metallic circuit on the protective layer 5 or plane 83, and exports a signal to other internal circuit from output node Xo ', but does not export this signal to an external circuit.See also shown in Fig. 5 M, inner tristate buffer 213 ' can be accepted a signal via metallic circuit on the protective layer 5 or plane 83, and exports a signal to other internal circuit from output node Xo ', but does not export this signal to an external circuit.
In Fig. 5 L; the size of N type MOS (metal-oxide-semiconductor) transistor 2103 ' is between 1.5 to 30; and being the preferably between 2.5 to 10; the size of P type MOS (metal-oxide-semiconductor) transistor 2104 ' then is between 3 to 60; and being the preferably between 5 to 20; be between the scope between 500 micromicroamperes to 10 milliampere through the metallic circuit or the plane 83 of protective layer 5 tops and the electric current of importing the input nodes X i of inner receiver 212 ' in addition, and being the preferably between the scope between 700 micromicroamperes to 2 milliampere.In addition; the input nodes X i ' of inner receiver 212 ' can accept a signal of the output node Wo output of internal circuit 24 via metallic circuit on the protective layer 5 or plane 83; but do not receive the signal of external circuit output, shown in Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 7 C and Fig. 7 D.
In Fig. 5 N to Fig. 5 R, it is openly to go out the design that the data of internal circuit 24 (gate) output is written to an internal storage location of a memory array.Please consult simultaneously shown in Fig. 5 K and Fig. 5 N, internal circuit 21 can be an inner tristate buffer 213 '.This inner tristate buffer 213 ' has the function of amplification data and switch, and in addition to be output read the circuit (not shown) from one for controlling signal En, En, and utilizes this controlling signal En, En to control the unlatching of inner tristate buffer 213 or close.In addition; by metallic circuit on the protective layer 5 or plane 83; (bit) data can be sent to the input nodes X i ' of inner tristate buffer 213 '; and when reverse position (bit) data of amplifying are a supply voltage; reverse position (bit) data of amplifying are to export reverse position (bit) line to by P type MOS (metal-oxide-semiconductor) transistor 2110 '; and when reverse position (bit) data of amplifying were a ground connection reference voltage, reverse position (bit) data of amplification were to export reverse position (bit) line to by N type MOS (metal-oxide-semiconductor) transistor 2109 '.The amplification of output node Xo ' output oppositely position (bit) data can be through being sent to sram cell 215 by the row selecting transistor 2122 of delegation's selection (CS) signal control and through N type MOS (metal-oxide-semiconductor) transistor 2119.Please consult simultaneously shown in Fig. 5 K and Fig. 5 N, internal circuit 24 (is a NOR gate at this) is to transmit data by the metallic circuit of a fine rule road metal structure 634 ', a protective layer opening 534 ', protective layer 5 tops or plane 83, a protective layer opening 531 ', a fine rule road metal structure 631 ' and one inner tristate buffer 213 ' to remove to write a sram cell 215 in the memory array.
See also shown in Fig. 5 O, the bit data of internal circuit 24 (is a NOR gate at this) output is after passing through circuit 216 ' through one, be connected to the bit line of sram cell array, come again to write sram cell 215 by row selecting transistor.Wherein, the internal circuit 21 among Fig. 5 K is one by circuit 216 ', and this can be a simple MOS (metal-oxide-semiconductor) transistor by circuit 216 ', N type MOS (metal-oxide-semiconductor) transistor 2124 ' for example, and write signal (write enable signal) by one and controlled.In this design (please also refer to Fig. 5 K and Fig. 5 O); data by the output node Wo of internal circuit 24 (is a NOR gate at this) output are to be written in the sram cell 215 by following approach: since a fine rule road metal structure 634 '; up through a protective layer opening 534 '; through a metallic circuit or the plane 83 on the protective layer 5; down through a protective layer opening 531 '; one fine rule road metal structure 631 '; one by circuit 216 '; be connected to the bit line of sram cell array then, come again to be written to sram cell 215 by row selecting transistor.
See also shown in Fig. 5 P, it is similar to Fig. 5 H, the input bit line data write sram cell 215 before, can temporarily be stored or be latched in the latch circuit 217 '.In addition, N type MOS (metal-oxide-semiconductor) transistor 2129 ', 2130 ' is intended for the control that writes.In this design (please also refer to Fig. 5 K and Fig. 5 P); data by the output node Wo of internal circuit 24 (is a NOR gate at this) output are to be written in the sram cell 215 by following approach: since a fine rule road metal structure 634 '; up through a protective layer opening 534 '; through a metallic circuit or the plane 83 on the protective layer 5; down through a protective layer opening 531 '; one fine rule road metal structure 631 '; one latch circuit 217 '; be connected to the bit line of sram cell array then, come again to be written to sram cell 215 by row selecting transistor.
Yet the latch circuit that passes through circuit 216 ' or Fig. 5 P 217 ' of Fig. 5 O possibly can't provide enough sensitivity to detect at the weak signals of importing node.In order to rebuild (restore) weak data signals (weak datasignal), can increase by an inner receiver 212 ' at the input (shown in Fig. 5 Q) by circuit 216 ' or at the input (shown in Fig. 5 R) of latch circuit 217 '.
Another important application of protective layer top connection line is to transmit accurate analog signal (analogsignal).The low resistance per unit length on protective layer upper metal circuit or plane and electric capacity (resistance andcapacitance per unit length) characteristic provides the Digital Simulation analog signal of a low signal distortion (signal distortion).See also shown in Fig. 5 S, it is an open board design that goes out to utilize metallic circuit on the protective layer 5 or plane 83 to connect analog circuits.Except internal circuit 21,22,23,24 for the signal of analog circuit or hybrid circuit (mixed-mode circuit), metallic circuit or plane 83 transmission be the signal of Digital Simulation analog signal and internal circuit 21,22,23,24 output/receptions be a Digital Simulation analog signal, the design of Fig. 5 S is similar to Fig. 5 B.In Fig. 5 S; one output node Yo of internal circuit 21 connects fine rule road metal structure 631; then up through metallic circuit or plane 83 on the protective layer opening 531 connection protective layers 5 of protective layer 5; come again through protective layer opening 532; 534 connect fine rule road metal structure 632 (comprises 632a; 632b; 632c); 634; utilize fine rule road metal structure 632 (to comprise 632a at last again; 632b; 632c); 634 are connected to internal circuit 22; 23; an input node Ui ' of 24; Vi '; Wi '; wherein as the internal circuit 21 of analog circuit; 22; 23; the 24th, comprise a P type MOS (metal-oxide-semiconductor) transistor; one N type MOS (metal-oxide-semiconductor) transistor; one NOR gate (NOR gate); one NAND gate (NAND gate); one with the door (an AND gate); one or the door (OR gate); one sensing amplifier (sense amplifier); one amplifier is calculated big device (Operational Amplifier); one analog/digital converter (A/D converter); one digital/analog converter (D/A Converter); one pulse wave reshapes circuit (pulsere shaping circuit); one suitching type capacitive filter (switched-capacitor filter); one resistor ﹠ capacitor filter (RC filter) or the analog circuit of other type etc.; narrate as for other relevant Fig. 5 B that partly sees also, narrate no longer in detail at this.
See also shown in Fig. 5 T; it is that the internal circuit 21 of openly publishing picture among the 5S is operational amplifier 218; and its output node Yo is connected to the metallic circuit on the protective layer 5 or an example on plane 83; it is to design according to a CMOS (Complementary Metal Oxide Semiconductor) (CMOS) technology that this amplifier is calculated big device, " the CMOS Digital Circuit Technology " that please refer to that M.Shoji in 1987 and issued by Prentice-Hall company.Differential analog signal is among the input node Yi+ and Yi-that inputs to by 2125,2127 and two P type MOS (metal-oxide-semiconductor) transistor of two N type MOS (metal-oxide-semiconductor) transistor, 2126,2128 formed differential circuits (differential circuit) 219, and wherein this input node Yi+ and Yi-are the grids that is connected respectively to P type MOS (metal-oxide-semiconductor) transistor 2126 and P type MOS (metal-oxide-semiconductor) transistor 2128.Differential circuit 219 is to be connected on first electrode of the grid of N type MOS (metal-oxide-semiconductor) transistor 2135 and capacitor (capacitor) 2133 in the output of the drain electrode of the drain electrode of N type MOS (metal-oxide-semiconductor) transistor 2127 and P type MOS (metal-oxide-semiconductor) transistor 2128.One output node Yo is second electrode that is connected to capacitor 2133, the drain electrode of N type MOS (metal-oxide-semiconductor) transistor 2135 and the drain electrode of P type MOS (metal-oxide-semiconductor) transistor 2136.Therefore, can control by the opening degree of N type MOS (metal-oxide-semiconductor) transistor 2135 at the signal of output node Yo, wherein N type MOS (metal-oxide-semiconductor) transistor 2135 also is subjected to the control of differential circuit 219 outputs.The power supply node P of differential circuit 219 is connected with the drain electrode of P type MOS (metal-oxide-semiconductor) transistor 2132, wherein is that the source electrode with P type MOS (metal-oxide-semiconductor) transistor 2126 is connected with power supply node P with the source electrode of P type MOS (metal-oxide-semiconductor) transistor 2128 in the differential circuit 219.In addition, the voltage quasi position of P type MOS (metal-oxide-semiconductor) transistor 2132 grids can be subjected to the control of resistor 2134.In addition, by capacitor 2133, can amplify the signal of differential circuit 219 outputs.Capacitor 2133 often is used in the Design of Simulating Circuits, and normally polysilicon capacitor (poly-to-poly capacitor) is formed with a gold medal oxygen half capacitor (MOS capacitor) or a polysilicon, wherein this golden oxygen half capacitor is to use polysilicon gate (poly gate) and two electrodes of silicon base (silicon substrate) as capacitor 2133, and polysilicon then is to use one first polysilicon (poly silicon) and two electrodes of one second polysilicon as capacitor 2133 to polysilicon capacitor.Resistor also often is used on the analog circuit, and normally with the doping impurity diffusion region in the silicon base (impurity-doped diffusion area), for example n well, p well, N+ diffusion, P+ diffusion, and/or impurity doped polysilicon (impurity-doped poly silicon) forms.
The 3rd embodiment: complete structure of the present invention.
The technology that forms the thick metallic conductor in protective layer top (or metallic circuit or plane of protective layer top) can provide chip extra benefit.The material of the thick metallic conductor in protective layer top (or metallic circuit or plane of protective layer top) is to comprise gold, copper, silver, palladium, rhodium, platinum, ruthenium or nickel, and it not only can form conductor body, also can form other contact structures.Utilize various different types of contact structures, for example solder projection (solderbump), scolder connection pad (solder pad), solder ball (solder ball), golden projection (Au bomp), golden connection pad (goldpad), palladium connection pad (Pd pad), aluminium connection pad (Al pad) or routing connection pad (wire bonding pad), chip can utilize diverse ways to engage with external circuit easily.In Fig. 5 B, Fig. 5 K, Fig. 5 S, Fig. 7 B, Fig. 7 C and Fig. 7 D, the metallic circuit or the plane of protective layer top are to be used for transmitting the signal that internal circuit is exported or imported, and internal circuit is not connected to external circuit.Only, a chip must be connected to external circuit, and transmits with external circuit.Then, please consult simultaneously shown in Fig. 8 B to Fig. 8 F, Fig. 9 B to Fig. 9 D and Figure 10 B to Figure 10 I, it is openly to go out a complete structure of the present invention, and with this as the third embodiment of the present invention.Fig. 8 B to Fig. 8 F, Fig. 9 B to Fig. 9 D and Figure 10 B to Figure 10 I have narrated the signal that internal circuit produced and how to be sent to external circuit by the metallic circuit of protective layer top or the fine rule road metal structure of plane and protective layer below, or how the signal that external circuit produced is sent to internal circuit by the metallic circuit of protective layer top or the fine rule road metal structure of plane and protective layer below.Fig. 8 B to Fig. 8 F, Fig. 9 B to Fig. 9 D and Figure 10 B to Figure 10 I are circuit structure, schematic top plan view and the generalized sections that is respectively present embodiment, and it is openly to go out the complete structure that the present invention uses fine rule road metal structure and protective layer upper metal with the whole chip design that internal circuit connects external circuit.In addition, the also suitable internal circuit 20 (comprising 21,22,23,24) in the present embodiment of internal circuit 20 (comprising 21,22,23,24) narrated of relevant Fig. 5 B to Fig. 5 T, Fig. 6 B and Fig. 7 B to Fig. 7 D.
In the present embodiment, the signal of internal structure 200 is to connect outer (off-chip) structure 400 by a chip to be sent to the external circuit (not shown), shown in Fig. 8 B, or the signal of external circuit (not shown) is to connect outer (off-chip) structure 400 by chip to be sent to internal structure 200, shown in Fig. 8 C.The metallic circuit of protective layer 5 tops or plane 83r can be used as fine rule road metal structure (I/O) connection pad (for example metallic pad 6390 among Figure 10 B) reconfigure circuit; in other words; (I/O) connection pad utilization with fine rule road metal structure reconfigures the connection pad (for example contact connection pad 8310 among Figure 10 B) that circuit is repositioned onto a diverse location exactly; utilize the lead or the projection that are positioned on this connection pad to be connected to external circuit then; so see by birds-eye perspective; the position of this connection pad is (I/O) connection pad position that is different from fine rule road metal structure; for example in Figure 10 B; see by birds-eye perspective; the position of contact connection pad 8310 is the positions that are different from metallic pad 6390; in addition, being used in the thickness that reconfigures circuit that forms contact connection pad 8310 is greater than 1.5 microns.In addition, metallic circuit on the protective layer 5 or plane 83r can form simultaneously with metallic circuit or the plane 83 on the protective layer 5.The electric current on metallic circuit or plane 83 of flowing through this moment is between between 50 micromicroamperes to 10 milliampere.
The contact connection pad 8310 that is exposed by a polymer opening 9939 that is positioned at top polymeric layer 99 can use routing or other joint method described in follow-up Figure 15 series to be connected to external circuit.In addition, for cover brilliant assembling (flip-chip assembly), winding engages (Tape Automated Bonding automatically, TAB) or other joint method described in follow-up Figure 15 series, alternative on contact connection pad 8310 and in the polymeric layer opening 9939, form contact structures 89, as for the method that forms contact structures 89 and be described in detail also and will in follow-up Figure 15 series, illustrate.Contact connection pad 8310 can connect external circuit 40 with chip and be connected.Therefore, comprehensive above-mentioned explanation, what chip connect that external structure 400 includes that a chip connects external circuit 40, a metallic pad 6390, contact structures 89 (selectivity) and protective layer top reconfigures circuit 83r (selectivity).
Chip connects external circuit 40 and includes a chip that connects external circuit 42 as chip and connect outer I/O (I/O) circuit, and at least one static discharge (the Electrostatic Discharge that connects external circuit 43 as chip, ESD) protection circuit, for example shown in Fig. 8 D, chip connects external circuit 43 and includes two electrostatic storage deflection (ESD) protection circuit.In foregoing, it can be that a chip connects outer driver, a chip connects outer receiver or a chip connects outer buffer (for example chip tristate buffer) that chip connects outer input/output circuitry, and related content is then narrated in Figure 11 A, Figure 11 B, Figure 11 C and Figure 11 E respectively; In addition, electrostatic storage deflection (ESD) protection circuit can be by two reverse blas diodes (reverse-biased diode), 4331,4332 structures of being formed, shown in Figure 11 F.The MOS (metal-oxide-semiconductor) transistor size that chip connects in the outer input/output circuitry will illustrate in follow-up Figure 15 series the MOS (metal-oxide-semiconductor) transistor size in the internal circuit.
Fig. 8 A; Fig. 9 A and Figure 10 A are the project organizations for existing wafer; as shown in the figure; all circuit (comprise internal circuit 21; 22; 23; 24 and chip connect external circuit 40) be by fine rule road metal structure 638; 6311; 6321 (comprise 6321a; 6321b; 6321c); 6341; 6391 ' is connected to each other together; yet existing do not have the metallic circuit or the plane of use protective layer top to connect all circuit; existing only when contact structures are Solder Bumps 89t, use one of protective layer top to reshuffle the position that metallic circuit 83t reconfigures external connection connection pad.
Please consult simultaneously shown in Fig. 9 B and Figure 10 B, it is schematic top plan view and the generalized section that is respectively the circuit design shown in Fig. 8 B.One internal circuit 21 is that the path by what follows is connected to contact connection pad 8310 or contact structures 89; the signal that allows internal circuit 21 produce is sent to an external circuit: internal circuit 21 is at first through a fine rule road metal structure 631; up through a protective layer opening 531; continue metallic circuit or plane 83 through individual layer (as the patterned metal layer among Figure 10 B 831) or multilayer; down be connected to the input node that chip connects external circuit 42 then through a protective layer opening 539 ' and a fine rule road metal structure 639 '; the chip that the output node that other allows chip connect external circuit 42 by fine rule road metal structure 69 is connected to as electrostatic storage deflection (ESD) protection circuit connects on the signal contact of external circuit 43; then, be connected to contact connection pad 8310 or contact structures 89 through a metallic circuit or the plane 83r that reshuffles circuit as the protective layer top at last up through a fine rule road metal structure 639 and a protective layer opening 539.In addition; it also can be to utilize the metallic circuit or the plane of protective layer top to reach with the mode that chip connects external circuit 43 that the connection chip connects external circuit 42, also promptly utilizes the metallic circuit or the plane of fine rule road metal structure and protective layer top to replace fine rule road metal structure 69.
See also shown in Figure 10 C, it is to disclose metallic circuit or plane 83 to have and similarly advise two patterned metal layers 831,832 at Fig. 7 C.In addition, Figure 10 D and Figure 10 E are except increase by one polymeric layer 95 between protective layer 5 and patterned metal layer 831 lowermost ends, and all the other are similar with Figure 10 C to Figure 10 B respectively.See also shown in Figure 10 D, utilize as the metallic circuit or the plane 83r that reconfigure circuit, metallic pad 6390 originally can be relocated to the contact connection pad 8310 on the protective layer 5.Use reconfigures circuit, and to reconfigure the I/O connection pad useful on storehouse encapsulation flash memory, DRAM (Dynamic Random Access Memory) or static random access memory chip especially.In addition, the I/O connection pad of a DRAM (Dynamic Random Access Memory) chip designs at the center along chip online normally roughly, so can't use in the storehouse encapsulation.Yet, utilize as the metallic circuit that reconfigures circuit or plane 83r with central connection pad reconfigure to chip around, can allow chip use the routing in encapsulation (for example storehouse encapsulation) to engage.
Please consult simultaneously shown in Figure 10 F and Figure 10 G, it is to be respectively contact connection pad 8310 to have the concrete example that a routing engages.In Figure 10 F and Figure 10 G, one sram cell, a flash cell or a DRAM (Dynamic Random Access Memory) unit are the input nodes X i that is connected in the internal circuit 21, and the method that relevant internal circuit 21 and internal storage location are connected to internal circuit 21 then illustrates in Fig. 5 F to Fig. 5 J respectively.At first see also shown in Figure 10 F, it is via (1) sensing amplifier that a sram cell, a flash cell or a DRAM (Dynamic Random Access Memory) unit are connected to external circuit; (2) internal buffer, by circuit, latch circuit, by circuit and inner drive or latch circuit and inner drive; (3) fine rule road metal structure 6311; (4) fine rule road metal structure 638; (5) be connected to the input node that a chip connects external circuit 42 via fine rule road metal structure 6391 '; (6) output node that connects external circuit 42 via chip connects fine rule road metal structure 6391, and a chip that is connected to as electrostatic storage deflection (ESD) protection circuit by fine rule road metal structure 69 connects external circuit 43; (7) one protective layer openings 539; (8) process is as the metallic circuit or the plane 83r that reconfigure circuit; (9) the contact connection pad 8310 through being exposed by a polymeric layer opening 9939; And (10) are connected to external circuit through the routing lead 89 ' on the contact connection pad 8310.Come, see also shown in Figure 10 G, it is via (1) sensing amplifier that a sram cell, a flash cell or a DRAM (Dynamic Random Access Memory) unit are connected to external circuit; (2) inner tristate buffer, by circuit, latch circuit, by circuit and inner drive or latch circuit and inner drive; (3) fine rule road metal structure 631; (4) up pass through protective layer opening 531; (5) the polymeric layer opening 9531; (6) patterned metal layer 831; (7) down pass through polymeric layer opening 9539 '; (8) the protective layer opening 539 '; (9) be connected to the input node that a chip connects external circuit 42 through fine rule road metal structure 639 '; (10) output node that connects external circuit 42 via chip connects fine rule road metal structure 639, and a chip that is connected to as electrostatic storage deflection (ESD) protection circuit by fine rule road metal structure 69 connects external circuit 43; (11) the protective layer opening 539; (12) the polymeric layer opening 9539; (13) process is as the metallic circuit or the plane 83r that reconfigure circuit; (14) the contact connection pad 8310 through being exposed by a polymeric layer opening 9939; And (15) are connected to external circuit through the routing lead 89 ' on the contact connection pad 8310.
In addition, as reconfigure the metallic circuit of circuit or plane 83r below or on can form a polymeric layer, for example in Figure 10 G, be formed with a polymeric layer 95 under metallic circuit or the plane 83r, and be formed with a top layer polymeric layer 99 on metallic circuit or the plane 83r.In addition, as the metallic circuit that reconfigures circuit or plane 83r can be to form (to electroplate or electroless-plating forms) between a gold medal layer of scope between 1.5 microns to 30 microns (to be the preferably) by thickness between 2 microns to 10 microns, or by being that thickness forms (forming with plating) between a bronze medal layer of scope between 2 microns to 100 microns (to be the preferably) between 3 microns to 20 microns.Wherein, there is assembling (assembly) metal level (its thickness is between 0.05 micron to 5 microns) of a nickel dam (its thickness is between between 0.5 micron to 5 microns) and gold, palladium or ruthenium on copper layer top.One routing is bonded on gold, palladium or the ruthenium laminar surface that contacts on the connection pad 8310 and carries out.
When signal was sent to external circuit or assembly, some chip connects external circuit need remove external circuit or the assembly that (1) drives needs large current load; (2) detection is from the signal that contains noise (noisysignal) of external circuit or assembly; And (3) protection internal circuit is exempted from surging (surge) infringement that signal produced that is subjected to from external circuit or assembly.See also shown in Figure 11 A, Figure 11 B and Figure 11 E and Figure 11 G, it is to disclose out respectively to connect outer driver 421, chip with chip and connect outer driver 422 and inner tristate buffer connect external circuit 42 as chip example.In Figure 11 A, it is that a chip of two-stage series connection (two-stage cascade) connects outer driver 421.In order to drive the external circuit (encapsulation, other chip or assembly or the like) that needs high capacity (heavy load), chip connects outer driver 421 and is designed to produce big electric current.In addition, it is to use a CMOS (Complementary Metal Oxide Semiconductor) series driver to form that chip connects outer driver.This series driver may include several grades inverter.The output current that one chip connects outer driver is with progression and uses at each grade chip and meet transistor size (W/L in the outer driver, the MOS (metal-oxide-semiconductor) transistor channel width is meant the ratio of the effective channel width of MOS (metal-oxide-semiconductor) transistor to effective channel length more accurately to the ratio of passage length) proportional.
In Figure 11 A, the first order 421 ' that chip connects outer driver 421 is to be an inverter, it is to be formed by N type MOS (metal-oxide-semiconductor) transistor 4201 and P type MOS (metal-oxide-semiconductor) transistor 4202, and the size of N type MOS (metal-oxide-semiconductor) transistor 4201 and P type MOS (metal-oxide-semiconductor) transistor 4202 is the sizes (as the size of the internal circuit 21,22,23,24 of first embodiment, second embodiment, the 3rd embodiment and follow-up the 4th embodiment) greater than internal circuit.In addition, to connect the first order 421 ' of outer driver 421 be to receive a signal from internal circuit 21,22,23,24 at input node F to chip.In addition, chip connects the second level 421 of outer driver 421 " also be an inverter, it is to be formed with P type MOS (metal-oxide-semiconductor) transistor 4204 by a larger sized N type MOS (metal-oxide-semiconductor) transistor 4203.Chip connects outer driver 421 drive current is provided, and this drive current is that (milia amperes is mA) to 5 amperes of (amperes, the A) scopes between, and be the preferably with the scope between 10 milliamperes to 100 milliamperes between 5 milliamperes.In order to reach these target output driving currents, the second level 421 " size of N type MOS (metal-oxide-semiconductor) transistor 4203 of (in other words; just chip connects the output stage of outer driver 421) is the scope between 20 to 20,000, and be the preferably with the scope between 30 to 300.In addition, because the drive current of a P type MOS (metal-oxide-semiconductor) transistor approximately is half of drive current of a N type MOS (metal-oxide-semiconductor) transistor.So, the second level 421 " and the size of P type MOS (metal-oxide-semiconductor) transistor 4204 of (in other words, just chip connects the output stage of outer driver 421) is the scope between 40 to 40,000, and be the preferably with the scope between 60 to 600.Yet, for a power supply chip (power chip) or a power management chip (power management chip), drive current must be bigger, for example 10 amperes or 20 amperes, and its drive current is the scope between 500 milliamperes to 50 amperes, and is the preferably with the scope between 500 milliamperes to 5 amperes.Therefore, to connect the size of the N type MOS (metal-oxide-semiconductor) transistor of outer driver be between 2,000 to 200 to a chip of a power supply chip or power management chip, scope between 000, and be the preferably with the scope between 2,000 to 20,000, the size of P type MOS (metal-oxide-semiconductor) transistor then is between 4, scope between 000 to 400,000, and with between 4, scope between 000 to 40,000 is the preferably.In addition, see also shown in Figure 11 D, chip connects outer driver 421 can be in the second level 421 " in a plurality of inverters in parallel; make the second level 421 " driver bigger N type MOS (metal-oxide-semiconductor) transistor of size (channel width is divided by the ratio of passage length) and P type MOS (metal-oxide-semiconductor) transistor can be provided, therefore chip connects outer driver 421 can provide a bigger drive current, wherein in the second level 421 " driver in; be that the N type MOS (metal-oxide-semiconductor) transistor of a plurality of reversers and the grid of P type MOS (metal-oxide-semiconductor) transistor are linked, link with the N type MOS (metal-oxide-semiconductor) transistor of a plurality of reversers and the drain electrode of P type MOS (metal-oxide-semiconductor) transistor.Fig. 8 E, Fig. 9 C and Figure 10 H are circuit diagram, schematic top plan view and the generalized sections that is respectively the circuit design of present embodiment application drawing 11D in addition.See also shown in Figure 11 G, chip connects outer driver 421 and also can rely in the mode of a plurality of inverters of back series connection of the first order 421 ', form a series connection driver (cascade driver), and make chip connect outer driver 421 by the inverter of amplifying step by step to amplify signal step by step, wherein the size (channel width is divided by the ratio of passage length) of the N type MOS (metal-oxide-semiconductor) transistor of the inverter of back level and P type MOS (metal-oxide-semiconductor) transistor be respectively greater than the N type MOS (metal-oxide-semiconductor) transistor of inverter of previous stage and the size (channel width is divided by the ratio of passage length) of P type MOS (metal-oxide-semiconductor) transistor, its preferable multiplying power is nature index (e, natural exponent) multiplying power, its connected mode is that the N type MOS (metal-oxide-semiconductor) transistor of inverter of previous stage and the drain electrode of P type MOS (metal-oxide-semiconductor) transistor are to be connected to the N type MOS (metal-oxide-semiconductor) transistor of the inverter of back one-level and the grid of P type MOS (metal-oxide-semiconductor) transistor in addition.Fig. 8 F, Fig. 9 D and Figure 10 I are circuit diagram, schematic top plan view and the generalized sections that is respectively the circuit design of present embodiment application drawing 11G in addition.
See also shown in Figure 11 B, it connects outer receiver 422 for a chip of two-stage series connection, and this chip connects outer receiver 422 can receive signal from the external circuit (not shown), and output signal is to the input node of internal circuit.The first order 422 ' (near external circuit) that chip connects outer receiver 422 is an inverter, it is to be formed by N type MOS (metal-oxide-semiconductor) transistor 4205 and P type MOS (metal-oxide-semiconductor) transistor 4206, and this N type MOS (metal-oxide-semiconductor) transistor 4205 and P type MOS (metal-oxide-semiconductor) transistor 4206 have the size that design is used for detecting the outside signal that contains noise.The first order 422 ' that chip connects outer receiver 422 is to receive the signal (can be the signal from other chip) that contains noise from one of external circuit or assembly at the E point.Chip connects the second level 422 of outer receiver 422 " also be an inverter, it is to be formed by the N type MOS (metal-oxide-semiconductor) transistor 4207 of a large-size and P type MOS (metal-oxide-semiconductor) transistor 4208.Chip connects the second level 422 of outer receiver 422 " be to be used for restoring (restore) integrality toward the outside signal that contains noise of internal circuit.
See also shown in Figure 11 C, to be a chip tristate buffer connect an example of outer driver as a chip for it, and exportable signal to a bus of this chip tristate buffer (bus), and then be transferred to a plurality of gates.Chip tristate buffer among Figure 11 C can be considered to be a gated inverter (gate inverter).When facilitating signal (enabling signal) En to be high levle (En is a low level), the chip tristate buffer allows the signal from internal circuit be sent to external circuit, and when signal En was in low level, internal circuit then cut off with external circuit.In this kind situation, the chip tristate buffer is to be used for driving external data bus (external data bus).Other connects N type MOS (metal-oxide-semiconductor) transistor 4209 sizes of outer driver about the chip tristate buffer as chip and the scope of P type MOS (metal-oxide-semiconductor) transistor 4210 sizes then is described among Figure 11 A, and will further specify in Figure 15 series.
See also shown in Figure 11 E, it is a chip tristate buffer connects outer receiver as a chip a example.When facilitating signal En to be high levle (En is a low level), the chip tristate buffer allows the signal from external circuit be sent to internal circuit, and when signal En was in low level, internal circuit then cut off with external circuit.In this kind situation, the chip tristate buffer is at the signal of node E reception from external data bus.Other connects N type MOS (metal-oxide-semiconductor) transistor 4209 sizes of outer receiver about the chip tristate buffer as chip and the scope of P type MOS (metal-oxide-semiconductor) transistor 4210 sizes is to be described among Figure 11 B, and will further specify in Figure 15 series.
Above-mentioned example is to be used in the accurate position of CMOS (Complementary Metal Oxide Semiconductor) signal (CMOS level signal).If this outside signal is transistor-transistor logic (transistor-transistor logic, TTL) accurate position, then need a CMOS/TTL buffer, if and this outside signal is emitter-coupled logic (emitter coupled logic, ECL) accurate position then needs a CMOS/ECL interface buffer.Between internal circuit and chip tristate buffer, can increase one pole or more multipole inverter.
See also shown in Figure 11 F, it is further to disclose a chip to connect outer recipient 422 and have an example that connects outer recipient 43 as the chip of electrostatic storage deflection (ESD) protection circuit.In this example, connect external circuit 43 as the chip of electrostatic storage deflection (ESD) protection circuit and comprise two reverse blas diodes (reverse-biased diode) 4331,4332.The reverse blas diode 4331 of bottom externally carries out reverse bias between input voltage (voltage that E is ordered) and the ground connection reference voltage Vss, and the reverse blas diode 4332 on top then externally carries out reverse bias between input voltage and the supply voltage Vdd.When the external input voltage from an external circuit is enhanced to beyond supply voltage Vdd suddenly, electric current will be by the reverse blas diode 4332 of discharge through the top, and when external input voltage was hanged down at ground connection reference voltage Vss, electric current then can be by the reverse blas diode 4331 of discharge through the bottom.Therefore, will be maintained between supply voltage Vdd and the ground connection reference voltage Vss toward the input voltage of internal circuit, and the semiconductor subassembly that chip connects in outer receiver 422 or the internal circuit 20 will be protected and exempt from be subjected to electrostatic breakdown.
The 4th embodiment: power supply/ground connection reference voltage bus project organization.
In first embodiment of the invention, one external power supply is to internal circuit 20 (comprising 21,22,23,24) via a pressurizer or transformer 41 input voltages, and in the present embodiment, one external power supply is that direct input voltage is to internal circuit 20 (comprising 21,22,23,24), but in this kind situation, then need the voltage or the electric current surging (surge) that utilize an electrostatic storage deflection (ESD) protection circuit 44 to prevent external power supply to produce.
At first, ask shown in Figure 12 A, it is the related art of present embodiment.In Figure 12 A; one external voltage Vdd is via a protective layer opening 549 inputs, then passes through a power supply node Tp, Up, Vp, the Wp that the fine rule road metal structure 618,6111,6121 (comprising 6121a, 6121b, 6121c), 6141 that is positioned under the protective layer 5 is dispensed to internal circuit 21,22,23,24.The power supply node Dp of one electrostatic storage deflection (ESD) protection circuit 44 is connected to fine rule road metal structure 618 via a fine rule road metal structure 6491.Figure 13 A and Figure 14 A are corresponding schematic top plan view of Figure 12 A and generalized section.
Then; relevant Figure 12 B to 12C schemes; shown in Figure 13 B to Figure 13 C and Figure 14 B to the 14D figure; it is the electrical block diagram that is respectively fourth embodiment of the invention; schematic top plan view and generalized section; as shown in the figure; one electrostatic storage deflection (ESD) protection circuit 44 is by the metallic circuit on the protective layer 5 or plane 81 and/or metallic circuit or plane 82 and internal circuit 21; 22; 23; 24 parallel connections; wherein internal circuit 21; 22; 23; 24 such as being NOR gate (NOR gate); NAND gate (NAND gate); with door (AND gate); or door (ORgate); operational amplifier (operational amplifier); adder (adder); multiplexer (multiplexer); duplexer (diplexer); multiplier (multiplier); analog/digital converter (A/D converter); digital/analog converter (D/A Converter); CMOS (Complementary Metal Oxide Semiconductor); the two-carrier CMOS (Complementary Metal Oxide Semiconductor); two-carrier circuit (bipolar circuit); sram cell (SRAM cell); DRAM (Dynamic Random Access Memory) unit (DRAM cell); non-volatile memory cell (non-volatile memory cell); flash cell (flash memory cell); Erasable ﹠Programmable ROM unit (EPROM cell); ROM unit (ROM cell); magnetic RAM (magnetic RAM, MRAM) unit or sensing amplifier (sense amplifier).This internal circuit 21,22,23,24 at least by one channel width/passage length ratio between the N type MOS (metal-oxide-semiconductor) transistor (NMOStransistor) between 0.1 to 5 or between 0.2 to 2, or channel width/passage length ratio constitutes between the P type MOS (metal-oxide-semiconductor) transistor (PMOS transistor) between 0.2 to 10 or between 0.4 to 4, and flow through this moment metallic circuit or plane 81,82 current ratio is in this way between between 50 micromicroamperes to 2 milliampere or between between 100 micromicroamperes to 1 milliampere, and metallic circuit or plane 81,82 such as being to utilize a lead to be formed on metallic circuit or plane 81, on 82, and then be electrically connected to an extraneous power supply; In addition, electrostatic storage deflection (ESD) protection circuit 44 is such as being a reverse blas diode (reverse-biased diode) 4333, and shown in Figure 12 E, it has a power supply contact and a ground contact.In addition, in first embodiment shown in Fig. 1 series, Fig. 2 series and Fig. 3 series, also can increase electrostatic storage deflection (ESD) protection circuit, and parallel connection pressurizer or transformer 41 and internal circuit 21,22,23,24.
In Figure 12 B and Figure 13 B; electrostatic storage deflection (ESD) protection circuit 44 (comprises 21 with internal circuit 20; 22; 23; 24) include a power supply node (power node) and a ground connection node (ground node); wherein the node Ep of external voltage Vdd input is via metallic circuit on the protective layer 5 or plane 81; the protective layer opening 511 of protective layer 5; 512; 514 and protective layer 5 under fine rule road metal structure 611; 612 (comprise 612a; 612b; 612c); 614; be connected to internal circuit 21; 22; 23; a power supply node of 24 (power node) Tp; Up; Vp; Wp, and then external voltage Vdd is dispensed to internal circuit 21; 22; 23; 24 power supply node Tp; Up; Vp; Wp.In addition, node Ep is also via the metallic circuit on the protective layer 5 or plane 81, the protective layer opening 549 of protective layer 5 and the power supply node Dp that the fine rule road metal structure 649 under the protective layer 5 is connected to an electrostatic storage deflection (ESD) protection circuit 44.
Figure 14 B is the corresponding generalized section of Figure 12 B.In Figure 14 B, include one as the patterned metal layer 811 on metallic circuit or plane 81 and stick together/hinder barrier/Seed Layer (adhesion/barrier/seed layer) 8111 and one thick metal layers 8112.Figure 12 C also discloses out the connection of a ground connection reference voltage Vss except the open connection that goes out as the external voltage Vdd of Figure 12 B.
In Figure 12 C and Figure 13 C, the node Eg of ground connection reference voltage Vss input is via the metallic circuit on the protective layer 5 or plane 82, the protective layer opening 521,522,524 of protective layer 5 and a ground connection node Ts, Us, Vs, the Ws that the fine rule road metal structure 621,622 (comprising 622a, 622b, 622c), 624 under the protective layer 5 is connected to internal circuit 21,22,23,24.In addition, the node Eg ground connection node Dg that also is connected to electrostatic storage deflection (ESD) protection circuit 44 via the protective layer opening 549 ' and the fine rule road metal structure 649 ' under the protective layer 5 of the metal on the protective layer 5 82, protective layer 5.
Figure 14 C is the corresponding generalized section of Figure 12 C.Figure 14 C openly goes out to have two patterned metal layers above protective layer, and wherein patterned metal layer 821 is to be used in the ground connection reference voltage Vss connection, and patterned metal layer 812 then is to be used in the power supply Vdd connection.Patterned metal layer 821 includes one and sticks together/hinder a barrier/Seed Layer 8211 and a thick metal layers 8212, and patterned metal layer 812 then includes one and sticks together/hinder a barrier/Seed Layer 8121 and a thick metal layers 8122.Figure 14 D except between protective layer 5 and patterned metal layer 811 lowermost ends, be formed with as metallic circuit or plane 81 polymeric layer 95, all the other are all similar to Figure 14 B.
See also shown in Figure 12 D, it is similar to Figure 12 C, and difference is that Figure 12 C only has an electrostatic storage deflection (ESD) protection circuit 44, and Figure 12 D then has two electrostatic storage deflection (ESD) protection circuit 44,45, and wherein this electrostatic storage deflection (ESD) protection circuit 45 is such as being a reverse blas diode.In Figure 12 D; electrostatic storage deflection (ESD) protection circuit 44; 45 with internal circuit 20 (comprise 21; 22; 23; 24) include a power supply node and a ground connection node; one external voltage Vdd is via metallic circuit on the protective layer 5 or plane 81; the protective layer opening 511 of protective layer 5; 512; 514 and protective layer 5 under fine rule road metal structure 611; 612a; 612b; 612c; 614; be input to internal circuit 21; 22; 23; a power supply node Tp of 24; Up; Vp; Wp, and then external voltage Vdd is dispensed to internal circuit 21; 22; 23; 24 power supply node Tp; Up; Vp; Wp.In addition, external voltage Vdd is also via the metallic circuit on the protective layer 5 or plane 81, the protective layer opening 549,559 of protective layer 5 and a power supply node Dp, the Dp ' that the fine rule road metal structure 649,659 under the protective layer 5 is input to electrostatic storage deflection (ESD) protection circuit 44,45.In addition, a ground connection reference voltage Vss is via the metallic circuit on the protective layer 5 or plane 82, the protective layer opening 521,522,524 of protective layer 5 and a ground connection node Ts, Us, Vs, the Ws that fine rule road metal structure 621,622a, 622b, 622c, 624 under the protective layer 5 are input to internal circuit 21,22,23,24.In addition, ground connection reference voltage Vss also via the protective layer opening 549 ' of the metal on the protective layer 5 82, protective layer 5,559 ' and protective layer 5 under fine rule road metal structure 649 ', 659 ' be connected to a ground connection node Dg, the Dg ' of electrostatic storage deflection (ESD) protection circuit 44,45.
Other related content of present embodiment is identical with first embodiment, second embodiment and the 3rd embodiment in addition, all will further describe in follow-up Figure 15 series, Figure 16 series, Figure 17 series, Figure 18 series and Figure 19 series.
In addition, in the 3rd embodiment, narrate to reconfigure circuit also applicable on the first embodiment of the present invention and the 4th embodiment, just in first embodiment and the 4th embodiment, be used for accepting contact connection pad (the contact connection pad 8110 among Fig. 3 B to Fig. 3 D for example of external voltage Vdd or ground connection reference voltage Vss, 8120, contact connection pad 8110 among Figure 14 B to Figure 14 D, 8120) also can utilize and reshuffle the contact connection pad that circuit is repositioned onto a diverse location, make the contact connection pad position of this diverse location and the metallic pad of the fine rule road metal structure (metallic pad 6190 among Fig. 3 B to Fig. 3 D for example, 6290, metallic pad 6490 among Figure 14 B to Figure 14 D, 6490 ') position difference utilizes a lead or projection on the contact connection pad that is positioned at this diverse location to be connected to external circuit then.
The formation method and the related description thereof of protective layer top (over-paeeivation) structure
In all embodiment of the present invention (first embodiment, second embodiment, the 3rd embodiment and the 4th embodiment), the principal character of protective layer top (over-passivation) structure is: thick patterned metal layer (thickness is between 2 microns to 200 microns) and thick dielectric layer (thickness is between 2 microns to 300 microns).Figure 15 series discloses a kind of relief (embossing) processing and a kind of pair of relief (doubleembossing) processing respectively with Figure 16 series, and it can be used to make the patterned metal layer and the dielectric layer of protective layer top among all embodiment of the present invention.In these two kinds processing (Figure 15 series and Figure 16 series), it is to utilize polymeric material (polymermaterial) as dielectric layer, and be formed on each patterned metal layer, between each patterned metal layer and/or under each patterned metal layer.In addition, Figure 15 series is based on Figure 10 E among the 3rd embodiment with Figure 16 series, and forms the method for square structure on the protective layer as all embodiment of example explanation the present invention with this.In other words, the method for being narrated below is applicable at all embodiment of the present invention with its related description.
The processing that forms square structure on the protective layer is to begin later in IC wafers (IC wafer) process finishing.See also shown in Figure 15 A; it is openly to go out a kind of parent material (startingmaterial) as square structure on the formation protective layer; as shown in the figure; the processing that forms square structure on the protective layer is that beginning is made on the IC wafers 10 of finishing in a traditional semiconductor fabrication factory (ICfab), and this wafer 10 comprises:
(1) substrate (substrate) 1
Substrate 1 is generally a silicon base (silicon substrate), and this silicon base can be an essence (ihtrinsic) silicon base, a p type silicon base or a n type silicon base.For high performance chip, then be to use SiGe (SiGe) or silicon-on-insulator (Silicon-On-Insulator, SOI) substrate.Wherein, silicon-Germanium base comprises that a SiGe grows nonparasitically upon another plant layer (epitaxial layer) on the surface of silicon base, and in addition the silicon-on-insulator substrate then comprises an insulating barrier (being preferably silica) on a silicon base, and a silicon or the SiGe layer of growing nonparasitically upon another plant is formed on the insulating barrier.
(2) component layer (device layer) 2
Component layer 2 generally includes at least one semiconductor subassembly (semiconductor device), and this component layer 2 is in the surface of substrate 1 and/or on the surface.Wherein, semiconductor subassembly can be a MOS (metal-oxide-semiconductor) transistor (MOS transistor) 2 ', N type MOS (metal-oxide-semiconductor) transistor (NMOS transistor for example, n-channel MOStransistor) or P type MOS (metal-oxide-semiconductor) transistor (PMOS transistor, p-channel MOS transistor), and this MOS (metal-oxide-semiconductor) transistor 2 ' comprises one source pole 201, one drain electrode, 202 and one grid 203, and grid 203 is generally a polysilicon (poly silicon), one compound crystal metal silication tungsten (tungsten polycide), one tungsten silicide (tungstensilicide), one titanium silicide (titanium silicide), an one cobalt silicon (cobalt silicide) or a silicide grids (salicide gate).In addition, semiconductor subassembly also can be two-carrier transistor (bipolar transistor), diffused metal oxide emiconductor (Diffused MOS, DMOS), Laterally Diffused Metal Oxide Semiconductor (LateralDiffused MOS, LDMOS), Charged Coupled Device (Charged-Coupled Device, CCD), CMOS (Complementary Metal Oxide Semiconductor) (CMOS) sensing component, photodiode (photo-sensitive diode), resistor assembly (because polysilicon layer or diffusion region in the silicon base form).Utilize these semiconductor subassemblies can form various circuit, for example CMOS (Complementary Metal Oxide Semiconductor) (CMOS) circuit, N type metal oxide semiconductor circuit, P-type mos circuit, two-carrier CMOS (Complementary Metal Oxide Semiconductor) (BiCMOS) circuit, CMOS semiconductor sensor circuit, diffused metal oxide emiconductor power circuit, Laterally Diffused Metal Oxide Semiconductor circuit etc.In addition, component layer 2 also comprises internal circuit 20 (comprising 21,22,23,24) in all embodiments, pressurizer or transformer 41 are in first embodiment, and chip connects external circuit 40 (comprising 42,43) in the 3rd embodiment, and electrostatic storage deflection (ESD) protection circuit 44 is in the 4th embodiment.
(3) fine rule line structure (fine-line scheme) 6
This fine rule line structure 6 comprises a plurality of fine rules road metal level (fine-line metal layer) 60, a plurality of fine rules road dielectric layer (fine-line dielectric layer) 30 and a plurality of conductive plug (fine-line viaplug) 60 ' in the opening 30 ' of fine rule road dielectric layer 30.In addition, fine rule road metal structure 63 comprises fine rule road metal level 60 and conductive plug 60 ', and this fine rule road metal structure 63 comprises in the present invention: (1) fine rule road metal structure 611,612 (comprising 612a, 612b and 612c), 614,619,619 ', 621,622 (comprising 622a, 622b and 622c), 624,629 are at first embodiment; (2) fine rule road metal structure 631,632 (comprising 632a, 632b and 632c), 634 is at second embodiment; (3) fine rule road metal structure 631,632 (comprising 632a, 632b and 632c), 634,639,639 ' is at the 3rd embodiment; (4) fine rule road metal structure 611,612 (comprising 612a, 612b and 612c), 614,649,659,621,622 (comprising 622a, 622b and 622c), 624,649 ' and 659 ' are at the 4th embodiment.
Fine rule road metal level 60 can be aluminium lamination or copper floor, or more particularly, can be with the aluminium lamination of sputtering way formation or the copper layer that forms with mosaic mode.So fine rule road metal level 60 can be: (1) all fine rule road metal levels 60 are aluminium lamination; (2) all fine rule road metal levels 60 are the copper floor; (3) the fine rule road metal level 60 of bottom is an aluminium lamination, and the fine rule road metal level 60 of top layer is the copper floor; Or the fine rule road metal level 60 of (4) bottom is the copper floor, and the fine rule road metal level 60 of top layer is an aluminium lamination.In addition, the thickness of each fine rule road metal level 60 is between 0.05 micron (μ m) is to 2 microns, and be the preferably with the thickness between 0.2 micron to 1 micron, if fine rule road metal level 60 circuits in addition, then its transverse design standard (width) is between 20 nanometers (nano-meter) are to 15 microns, and with between being the preferably between 20 nanometers to 2 micron.
In foregoing, aluminium lamination normally utilizes physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) mode forms, for example utilize the mode of sputter (sputtering) to form, then between a photoresist layer that (is preferably between 0.3 micron to 2 microns) between 0.1 micron to 4 microns this aluminium lamination is carried out patterning by deposit thickness, come this aluminium lamination is carried out a wet etching (wet etching) or a dry ecthing (dry etching), preferable mode is to be dry type electricity slurry (dry plasma) etching (comprising fluorine electricity slurry usually) again.In addition, alternatively under aluminium lamination form one and stick together/barrier layer (adhesion/barrier layer), wherein this stick together/barrier layer can be the formed composite bed of titanium, titanium-tungsten, titanium nitride or above-mentioned material; And on aluminium lamination the also alternative anti-reflecting layer (for example titanium nitride) that forms.In addition, opening 30 ' alternative with chemical vapour deposition (CVD) (chemical vapordeposition, CVD) mode of tungsten metal is filled up, then again with cmp (chemical mechanicalpolish, CMP) mode is ground the tungsten metal level, to form metal plug 60 '.
In addition in foregoing, the copper layer normally utilizes the mode of electroplating with damascene process (damascene process) to form, and it is described below: (1) deposition one bronze medal diffused barrier layer (for example layer of oxynitride or the nitride layer of thickness between 0.05 micron to 0.25 micron); (2) utilize plasma enhanced chemical vapor deposition (plasmaenhanced CVD, PECVD), rotary coating (spin-on coating) or high density plasma enhanced chemical vapor deposition (High Density Plasma CVD, HDPCVD) the fine rule road dielectric layer 30 of mode deposit thickness between 0.1 micron to 2.5 microns, wherein this fine rule road dielectric layer 30 is to be the preferably with the thickness between 0.3 micron to 1.5 microns; (3) utilize the photoresist layer of deposit thickness between 0.1 micron to 4 microns to come patterning fine rule road dielectric layer 30, wherein the thickness of photoresist layer is again being the preferably between 0.3 micron to 2 microns, then this photoresist layer is exposed and development, make photoresist layer form a plurality of openings and/or a plurality of irrigation canals and ditches, remove this photoresist layer again; (4) utilize the mode of sputter or chemical vapour deposition (CVD), deposition one is sticked together/barrier layer and a Seed Layer (seed layer).Wherein, this sticks together/and barrier layer comprises tantalum, tantalum nitride, titanium nitride, titanium or titanium-tungsten, or by the formed composite bed of above-mentioned material.In addition, this Seed Layer is a bronze medal layer normally, and this copper layer can be to utilize sputter copper metal, chemical vapour deposition (CVD) copper metal, or earlier with chemical vapour deposition (CVD) one bronze medal metal, and then the mode of sputter one bronze medal metal forms; (5) the bronze medal layer of electroplating thickness between 0.05 micron to 2 microns is the preferably with the bronze medal layer of copper electroplating layer thickness between 0.2 micron to 1 micron again wherein on this Seed Layer; (6) remove not in the opening of fine rule road dielectric layer 30 or copper floor, Seed Layer in the irrigation canals and ditches in the mode of grinding (preferable mode is a cmp) wafer and stick together/barrier layer, until expose be positioned at stick together/fine rule road dielectric layer 30 under the barrier layer till.After through cmp, the only remaining metal that is positioned at opening or irrigation canals and ditches, remaining metal then is used as metallic conductor (circuit or plane) or conductive plug 60 ' (connecting two adjacent fine rule road metal levels 60).In addition, also can utilize a dual damascene (double-damascene) processing, once form conductive plug 60 ' and metallic circuit or metal flat simultaneously in plating processing and a cmp.Twi-lithography (photolithography) processing is to be useful in the dual damascene processing with twice plating processing.Between the step (3) of patterning one dielectric layer of dual damascene processing in above-mentioned single damascene process and the step (4) of depositing metal layers, increase the procedure of processing of more depositions and another dielectric layer of patterning.
Fine rule road dielectric layer 30 is to utilize the mode of chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition, high density plasma enhanced chemical vapor deposition or spin coating (spin-on) to form.The material of fine rule road dielectric layer 30 comprises silica (silicon oxide), silicon nitride (silicon nitride), silicon oxynitride (silicon oxynitride), tetraethoxysilane (PECVD TEOS) with plasma enhanced chemical vapor deposition formation, spin-coating glass (SOG, Si oxide or siloxy group), fluorine silex glass (Fluorinated Silicate Glass, FSG) or a low-k (low-K) material, black diamond film (Black Diamond for example, it is the product of Applied Materials, and company's translated name is an Applied Materials), the dielectric material of the low-k of ULK CORAL (being the product of Novellus company) or SiLK (IBM Corporation).The silica that forms with plasma enhanced chemical vapor deposition, the tetraethoxysilane that forms with plasma enhanced chemical vapor deposition or have dielectric constant K between 3.5 to 4.5 with the oxide that high-density electric slurry forms; The fluorine silex glass that forms with plasma enhanced chemical vapor deposition or have dielectric constant values between 3.0 to 3.5 with the fluorine silex glass that high-density electric slurry forms, low dielectric constant dielectric materials then has the dielectric constant values between 1.5 to 3.5.Low dielectric constant dielectric materials, black diamond film for example, it is a porousness, and includes hydrogen, carbon, silicon and oxygen, its molecular formula is HwCxSiyOz.This fine rule road dielectric layer 30 generally includes inorganic material (inorganic material), in order to reach thickness greater than 2 microns.The thickness of each fine rule road dielectric layer 30 is between 0.05 micron to 2 microns.In addition, the opening 30 ' in the fine rule road dielectric layer 30 is to utilize the mode etched pattern photoresist layer of wet etching or dry ecthing to form, and wherein preferable etching mode is dry ecthing.The dry ecthing kind comprises fluorine electricity slurry (fluorine plasma).
(4) protective layer (passivation layer) 5
Protective layer 5 is being played the part of very important role in the present invention.Protective layer 5 is to be an important part in IC industry; by S.Wolf as nineteen ninety; and " the Silicon Processing in the VLSI era " the 2nd that issued by Lattice Press is described; protective layer 5 is to be defined as final layer in integrated circuit processing, and is deposited on the surface on the whole of wafer.Protective layer 5 is to be an insulation, protective layer, can prevent the machinery and chemistry injury that are caused during assembling and encapsulation.Except prevent mechanical scratch, protective layer 5 also can prevent moving iron (mobileion), such as being sodium (sodium) ion, and transition metal (transition metal), such as being gold, copper, penetrates into the integrated circuit package to the below.In addition, protective layer 5 also can protect the assembly and the connection line (fine rule road metal structure and fine rule road dielectric layer) of below to exempt from the intrusion that is subjected to aqueous vapor (moisture).
Protective layer 5 generally includes a silicon nitride (silicon nitride) layer and/or a silicon oxynitride (siliconoxynitride) layer; and its thickness is between 0.2 micron to 1.5 microns, and is the preferably with the thickness between 0.3 micron to 1.0 microns.Other uses the material at protective layer 5 that silica, reinforced titanium dioxide tetraethyl orthosilicate salt (the plasma-enhanced tetraethylorthosilicate of electricity slurry that forms with plasma enhanced chemical vapor deposition then arranged; PETEOS) oxide, phosphorosilicate glass (phosphosilicate glass; PSG), boron-phosphorosilicate glass (borophospho silicate glass, BPSG), the oxide that forms with high-density electric slurry (HDP).Then, some examples that narration protective layer 5 is made up of composite bed, its bottom to order at top is: (1) thickness is between the oxide/thickness of (preferred thickness is then between between 0.3 micron to 0.7 micron) between 0.1 micron to the 1.0 microns silicon nitride between (preferred thickness is then between 0.35 micron to 1.0 microns) between 0.25 micron to 1.2 microns, the protective layer 5 of this pattern normally covers on the metal connection line that forms with aluminium, and wherein the metal connection line that forms with aluminium generally includes the processing of sputtering aluminum and etching aluminium; (2) thickness between the oxynitrides/thickness of 0.05 micron to 0.35 micron (preferred thickness is then between between 0.1 micron to 0.2 micron) between the oxide/thickness of 0.2 micron to 1.2 microns (preferred thickness is then between between 0.1 micron to 0.2 micron) between the nitride/thickness of 0.2 micron to 1.2 microns (preferred thickness is then between between 0.3 micron to 0.5 micron) oxide between 0.2 micron to 1.2 microns (preferred thickness is then between 0.3 micron to 0.6 micron); the protective layer 5 of this pattern normally covers on the metal connection line that forms with copper, and wherein the metal connection line that forms with copper generally includes plating; cmp and damascene process.In addition, oxide skin(coating) in above-mentioned two examples can be silica, the reinforced titanium dioxide tetraethyl orthosilicate salt of electricity slurry (plasma-enhanced tetraethyl orthosilicate, oxide PETEOS), the oxide that utilizes high-density electric slurry to form that utilizes plasma enhanced chemical vapor deposition to form.More than within to hold be to be useful among all embodiment of the present invention (first embodiment, second embodiment, the 3rd embodiment and the 4th embodiment).
Protective layer opening 50 is to utilize the mode of wet etching or dry ecthing to form, and wherein is again preferred mode with the dry ecthing.In the present invention, protective layer opening 50 comprises: (1) protective layer opening 511,512,514,519,519 ', 521,522,524 and 529 is in first embodiment; (2) protective layer opening 531,532 and 534 in a second embodiment; (3) protective layer opening 531,532,534,539 and 539 ' is in the 3rd embodiment; (4) protective layer opening 511,512,514,549,521,522,524,549 ', 559 and 559 ' is in the 4th embodiment.In addition; the size of protective layer opening 50 is between 0.1 micron to 200 microns; and between 1 micron to 100 microns or between 5 microns to 30 microns, being the preferably; the shape of protective layer opening 50 can be circle, square, rectangle or polygon in addition; so the size of above-mentioned protective layer opening 50 is meant circular diameter dimension, foursquare size dimension, polygonal long-diagonal size or rectangular width dimensions; wherein rectangular length dimension then is between 1 micron to 1 centimetre, and being the preferably between 5 microns to 200 microns.For internal circuit; its protective layer opening 531; 532; 534 size is between 0.1 micron to 100 microns; and between 0.3 micron to 30 microns, being the preferably; protective layer opening 519 for pressurizer or transformer 41; 519 '; 529 or connect external circuit 42 for chip; 43 protective layer opening 539; 539 ' or for the protective layer opening 549 of electrostatic storage deflection (ESD) protection circuit 44; 549 '; 559; 559 '; the size of opening is bigger; its scope is between 1 micron to 150 microns, and between 5 microns to 100 microns, being the preferably.In addition, protective layer opening 50 exposes the metallic pad (metal pad) of fine rule road metal level 60 the superiors, in order to electrically connect the metallic circuit or the plane of protective layer top (over-passivation).
One chip 10, Silicon Wafer (silicon wafer) for example, be to use the integrated circuit process technology of different generations to make, for example 1 micron, 0.8 micron, 0.6 micron, 0.5 micron, 0.35 micron, 0.25 micron, 0.18 micron, 0.25 micron, 0.13 micron, 90 nanometers (nm), 65 nanometers, 45 nanometers, 35 nanometers, 25 nanometer technologies define and the generation of these integrated circuit process technologies is grid length (gatelength) or effective channel lengths (channel length) with MOS (metal-oxide-semiconductor) transistor 2 '.In addition, the size of wafer 10 is such as being or etc. at 5 o'clock, 6 o'clock, 8 o'clock, 12 o'clock at 18 o'clock.Wafer 10 is to use lithography process to make, and this lithography process comprises coating (coating), exposure (exposing) and (developing) photoresistance that develops.Be used in the photoresistance of making wafer 10, its thickness is between 0.1 micron to 0.4 micron, and with five times of (5X) stepping exposure machines (stepper) or scanning machine (scanner) this photoresistance that exposes.Wherein, the multiple of stepping exposure machine be meant when light beam from a light shield (normally with quartz constitute) when being projected on the wafer, figure on the light shield dwindles the ratio on wafer, and five times (5X) is meant that promptly pattern proportion on the light shield is five times of pattern proportion on the wafer.Priority of use is advanced the scanning machine on the integrated circuit process technology from generation to generation, normally dwindles with four times of (4X) dimension scales and improves resolution.The employed light beam wavelength of stepping exposure machine or scanning machine be 436 nanometers (g-lihe), 365 nanometers (i-line), 248 nanometers (deep UV (ultraviolet light), DUV), 193 nanometers (DUV), 157 nanometers (DUV) or 13.5 nanometers (extremely short ultraviolet light, EUV).In addition, profit formula (high-index immersion) photoetching technique invaded in high index also can be in order to finish the fine rule road feature of wafer 10.
In addition, wafer 10 is to make in the dust free room (cleanroom) with grade 10 (class 10) or better (for example grade 1).The dust free room of grade 10 allows the maximum dust particle number of every cubic feet per Foot to be: the dust particle that contains more than or equal to 1 micron is no more than 1, the dust particle that contains more than or equal to 0.5 micron is no more than 10, the dust particle that contains more than or equal to 0.3 micron is no more than 30, the dust particle that contains more than or equal to 0.2 micron is no more than 75, the dust particle that contains more than or equal to 0.1 micron is no more than 350, and the dust free room of grade 1 then allows the maximum dust particle number of every cubic feet per Foot to be: the dust particle that contains more than or equal to 0.5 micron is no more than 1, the dust particle that contains more than or equal to 0.3 micron is no more than 3, the dust particle that contains more than or equal to 0.2 micron is no more than 7, the dust particle that contains more than or equal to 0.1 micron is no more than 35.
See also shown in Figure 15 B; when using copper as fine rule road metal level 60; then need the copper connection pad (copper pad) that uses a metal top layer (metal cap) 66 (comprising 661,662,664,669 and 669 ') to protect protective layer opening 50 to be exposed; make this copper connection pad exempt from erosion damage, and can be used as the routing joint of follow-up chip being subjected to oxidation.This metal top layer 66 comprises an aluminium (aluminum) layer, a gold medal (gold) layer, a titanium (Ti) layer, a titanium-tungsten layer, a tantalum (Ta) layer, tantalum nitride (TaN) layer or a nickel (Ni) layer.Wherein, when metal top layer 66 is an aluminium lamination, then between copper connection pad and metal top layer 66, be formed with a barrier layer (barrierlayer), and this barrier layer comprises titanium, titanium-tungsten, titanium nitride, tantalum, tantalum nitride, chromium (Cr) or nickel.In all embodiment of the present invention, the wafer 10 alternative metal top layers 66 that form.
See also shown in Figure 15 C to Figure 15 K; it is the procedure of processing that openly goes out making square structure (over-passivation scheme) 8 on the protective layer on the wafer 10 shown in Figure 15 A or Figure 15 B; wherein this procedure of processing forms two-layer patterned metal layer above protective layer, and utilizes this two patterned metal layer to connect internal circuit and be connected chip and connect external circuit.Only; though only disclosing out the protective layer top, this example has two-layer patterned metal layer; but also can use the same or analogous mode of being chatted with Figure 15 C to Figure 15 K, above protective layer, form one deck patterned metal layer, three layer pattern metal levels, four layer pattern metal levels or more multi-layered patterned metal layer.In addition, holding within narrating below is to be useful among all embodiment of the present invention.
At first see also shown in Figure 15 K, square structure 8 is formed together on the beginning material (startingmaterial) on the protective layer, and this parent material is a wafer 10 (shown in Figure 15 A or Figure 15 B) of semiconductor manufactory made.In addition; square structure 8 includes patterned metal layer 80 and 90 liang of parts of polymeric layer (or insulating barrier) on the protective layer; wherein patterned metal layer 80 comprises one deck, two-layer, three layers, four layers or more multi-layered metal level; and this patterned metal layer 80 can such as be patterned metal layer except top layer for the gold layer, all the other all are the copper layer and stick together/barrier layer (for example chromium or titanium-tungsten).
All embodiment of the present invention comprise one deck or two-layer patterned metal layer as example with patterned metal layer 80, and it is to comprise:
(1) patterned metal layer 801, comprise (1) 811 and 821 in first embodiment; (2) 831 (comprising 831a, 831b) in a second embodiment; (3) 83r, 831 (comprising 831a, 831b) is in the 3rd embodiment; And (4) 811 and 821 in the 4th embodiment.
(2) patterned metal layer 802, comprise (1) 812 in first embodiment; (2) 832 in a second embodiment; (3) 832 (comprising 832a, 832b) are in the 3rd embodiment; And (4) 812 in the 4th embodiment.
In addition, the material of patterned metal layer 80 comprises gold, silver, copper, palladium, platinum, rhodium, ruthenium, nickel, and the composite bed that the patterned metal layer 80 on formation metallic circuit or plane is normally formed by metal stack.In Figure 15 K, patterned metal layer 801 all is composite beds with patterned metal layer 802, wherein the bottom of composite bed is one to stick together/hinder barrier/Seed Layer (adhesion/barrier/seedlayer) 8011,8021, and it is to comprise: (1) 8111,8121 and 8211 in first embodiment; (2) 8311,8311a, 8311b and 8321 are in a second embodiment; (3) 8311,8311a, 8311b, 8321a and 8321b are in the 3rd embodiment; And (4) 8111,8211 and 8121 in the 4th embodiment; In addition, the top layer of composite bed is a thick metal layers 8012,8022, and it is to comprise: (1) 8112,8122 and 8212 in first embodiment; (2) 8312,8312a, 8312b and 8322 are in a second embodiment; (3) 8312,8312a, 8312b, 8322a and 8322b are in the 3rd embodiment; And (4) 8112,8212 and 8122 in the 4th embodiment.
In foregoing, stick together/hinder barrier/ Seed Layer 8011,8021 comprise one stick together/barrier layer (not shown) and being positioned at sticks together/a seed (seed) layer (not shown) on the barrier layer, wherein this stick together/material of barrier layer can be titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten, vanadium, chromium, copper, chrome copper, tantalum, tantalum nitride, the formed alloy of above-mentioned material or the composite bed of being made up of above-mentioned material.In addition, stick together/barrier layer can utilize the mode of plating (electroplating), electroless-plating (electroless plating), chemical vapour deposition (CVD) or physical vapour deposition (PVD) (for example sputter) to form, be preferable generation type with physical vapour deposition (PVD) again wherein, for example metal sputtering processing.In addition, this sticks together/thickness of barrier layer is between 0.02 micron to 0.8 micron, and is the preferably with the thickness between 0.05 micron to 0.2 micron.
The Seed Layer of sticking together/hindering barrier/ Seed Layer 8011,8021 top layers can help follow-up plating processing, and Seed Layer normally utilizes the mode of physical vapour deposition (PVD) or sputter processing to form.In addition, the material that is used in Seed Layer can be gold, copper, silver, nickel, palladium, rhodium, platinum or ruthenium, and normally identical with thick metal layers material in the follow-up plating processing.In addition, Seed Layer can utilize the mode of plating, electroless-plating, chemical vapour deposition (CVD) or physical vapour deposition (PVD) (for example sputter) to form, and is preferable generation type with physical vapour deposition (PVD) again wherein, for example metal sputtering processing.The thickness of Seed Layer is between 0.05 micron to 1.2 microns, and is the preferably with the thickness between 0.05 micron to 0.8 micron.
Thick metal layers 8012, the 8022nd, form with low resistance conductor, and normally utilize plating mode to form, in addition, thick metal layers 8012,8022 thickness is normally between 0.5 micron to 100 microns, and be the preferably with the thickness between 3 microns to 20 microns, and thick metal layers 8012,8022 material can be a gold, copper, silver, nickel, palladium, rhodium, platinum or ruthenium, wherein golden, silver, palladium, rhodium, the preferred thickness of platinum or ruthenium is between 1.5 microns to 15 microns, the preferred thickness of copper is between 1.5 microns to 50 microns, and the preferred thickness of nickel then is between 0.5 micron to 6 microns.In addition, also alternative protection/resistance barrier (cap/barrier) the layer (not shown) that form is on thick metal layers 8012,8022, as the usefulness of protection or diffusion barrier.This protection/barrier layer can utilize the mode of plating, electroless-plating, chemical vapour deposition (CVD) or physical vapour deposition (PVD) (for example sputter) to form, and forms the preferably with the plating mode deposition.In addition, the thickness of protection/barrier layer is the scope between 0.05 micron to 5 microns, is the preferably with the thickness between 0.5 micron to 3 microns again wherein.This protection/barrier layer can be a nickel dam, cobalt layer or vanadium layer.In addition, in assembling (assembly) or encapsulation, alternative assembling contact (assembly-contact) the layer (not shown) that form particularly is formed on the thick metal layers or protection/barrier layer (not shown) of the top layer of patterned metal layer 80 on thick metal layers 8012,8022 or protection/barrier layer (not shown).This assembling contact layer can be used as that routing engages or help humectant (solder wettable) as scolder, and then is used for routing (wirebonding), gold and connects (goldconnection), solder ball welding (solder ball mounting) or welding (solder connection).In addition, the assembling contact layer can be gold, silver, platinum, palladium, rhodium or ruthenium.Polymeric layer opening 990 in the top polymeric layer (polymer layer) 99 (comprises 9919 and 9929 in first embodiment; 9939 and 9939 ' in the 3rd embodiment; And 9949 with 9949 ' in the 4th embodiment) connection pad (contac tpad) 8000 that contacts that exposes the patterned metal layer 80 that is arranged in top (comprises 8110 and 8120 at first embodiment; 8310 and 8320 in the 3rd embodiment; And 8110 and 8120 in the 4th embodiment) surface.Being connected to the assembling contact layer that polymeric layer opening 990 exposed can be a routing lead (bonding wire), one solder ball (connecting a solder ball) with the solder ball of plating formation or with welding manner, one Metal Ball (such as being to connect a sn-ag alloy) with the sn-ag alloy of plating formation or with welding manner, metal coupling on other substrate or chip (metal bump), gold medal projection (gold bump) on other substrate or chip, at metal column on other substrate or the chip (metal post) or the bronze medal post (copper post) on other substrate or chip.For the aluminium that forms with sputter or to electroplate the made integrated circuit contact connection pad (contact pad) of copper (utilizing the cmp damascene process to form) that forms, the metallic circuit of protective layer top or plane can be wherein a kind of patterns what follows, are respectively from down to up: the Seed Layer of the golden material of (1) titanium-tungsten/form with sputter/to electroplate the gold that forms; (2) Seed Layer of the golden material of titanium/form with sputter/to electroplate the gold that forms; (3) Seed Layer of the golden material of tantalum/form with sputter/to electroplate the gold that forms; (4) Seed Layer of the copper material of chromium/form with sputter/to electroplate the copper that forms; (5) Seed Layer of the copper material of titanium-tungsten/form with sputter/to electroplate the copper that forms; (6) Seed Layer of the copper material of tantalum/form with sputter/to electroplate the copper that forms; (7) Seed Layer of the copper material of titanium/form with sputter/to electroplate the copper that forms; (8) Seed Layer of the copper material of chromium, titanium-tungsten, titanium or tantalum/form with sputter/to electroplate the copper that forms/to electroplate the nickel that forms; (9) Seed Layer of the copper material of chromium, titanium-tungsten, titanium or tantalum/form with sputter/to electroplate the copper that forms/to electroplate the nickel that forms/to electroplate gold, silver, platinum, palladium, rhodium or the ruthenium that forms; And the Seed Layer of the copper material of (10) chromium, titanium-tungsten, titanium or tantalum/form with sputter/to electroplate the copper that forms/to electroplate gold, silver, platinum, palladium, rhodium or the ruthenium of the nickel that forms/form with electroless-plating.The thickness of each patterned metal layer 80 is between 2 microns to 50 microns, and be preferred thickness with the thickness between 3 microns to 20 microns, if patterned metal layer 80 metallic circuits in addition, then its transverse design standard (width) is between 1 micron to 200 microns, and between 2 microns to 50 microns, being the preferably, if and patterned metal layer 80 metal flats, particularly as power supply or ground connection reference voltage plane, its transverse design standard (width) then is being the preferably greater than 200 microns.In addition, the two adjacent metallic circuits or the minimum range on plane are between 1 micron to 500 microns, and between 2 microns to 150 microns, being the preferably.
Of the present invention during some uses, metallic circuit or plane can only comprise with the formed thickness of sputtering way sticks together/barrier layer (comprising titanium, titanium-tungsten, titanium nitride, tantalum or tantalum nitride layer) between aluminium that (is preferably between 3 microns to 5 microns) between 2 microns to 6 microns and the selectivity that is positioned under this aluminium lamination.
Continue, contact structures (contact structure) 89 alternatives are formed on the connection pad 8000 of patterned metal layer 80.These contact structures 89 can be a metal coupling (metal bump), a solder projection (solderbump), a solder ball (solder ball), a gold medal projection (gold bump), a copper bump (copper bump), a metallic pad (metal pad), a scolder connection pad (solder pad), a gold medal connection pad (gold pad), a metal column (metalpost), a solder post (solder post), a principal column (gold post) or a bronze medal post (copper post).One projection underlying metal (under bump metal, UBM) layer is positioned at these contact structures 89 times, this projection bottom metal layer comprises titanium, titanium-tungsten, titanium nitride, chromium, copper, chrome copper, tantalum, tantalum nitride, nickel, nickel-vanadium alloy, vanadium or cobalt layer, or the composite bed of being made up of above-mentioned material.These contact structures 89 (comprising the projection bottom metal layer) can be wherein a kind of patterns what follows, are respectively from down to up: (1) titanium/golden connection pad (thickness of gold layer is between 1 micron to 15 microns); (2) titanium-tungsten/golden connection pad (thickness of gold layer is between 1 micron to 15 microns); (3) nickel/golden connection pad (thickness of nickel dam is between 0.5 micron to 10 microns, and the thickness of gold layer is then between 0.2 micron to 15 microns); (4) titanium/golden projection (thickness of gold layer is between 7 microns to 40 microns); (5) titanium-tungsten/golden projection (thickness of gold layer is between 7 microns to 40 microns); (6) nickel/golden projection (thickness of nickel dam is between 0.5 micron to 10 microns, and the thickness of gold layer is then between 7 microns to 40 microns); (7) titanium, titanium-tungsten or chromium/copper/nickel/golden connection pad (thickness of copper layer is between 0.1 micron to 10 microns, and the thickness of gold layer is then between 0.2 micron to 15 microns); (8) titanium, titanium-tungsten, chromium, chrome copper or nickel-vanadium alloy/copper/nickel/golden projection (thickness of copper layer is between 0.1 micron to 10 microns, and the thickness of gold layer is then between 7 microns to 40 microns); (9) titanium, titanium-tungsten, chromium, chrome copper or nickel-vanadium alloy/copper/nickel/scolder connection pad (thickness of copper layer is between 0.1 micron to 10 microns, and the thickness of solder layer is then between 0.2 micron to 30 microns); (10) titanium, titanium-tungsten, chromium, chrome copper or nickel-vanadium alloy/copper/nickel/solder projection or solder ball (thickness of copper layer is between 0.1 micron to 10 microns, and the thickness of solder layer is then between 10 microns to 500 microns); (11) titanium, titanium-tungsten, chromium, chrome copper or nickel-vanadium alloy/copper post (thickness of copper layer is between 10 microns to 300 microns); (12) titanium, titanium-tungsten, chromium, chrome copper or nickel-vanadium alloy/copper post/nickel (thickness of copper layer is between 10 microns to 300 microns); (13) titanium, titanium-tungsten, chromium, chrome copper or nickel-vanadium alloy/copper post/nickel/scolder (thickness of copper layer is between 10 microns to 300 microns, and the thickness of solder layer is then between 1 micron to 20 microns); (14) titanium, titanium-tungsten, chromium, chrome copper or nickel-vanadium alloy/same post/nickel/scolder (thickness of copper layer is between 10 microns to 300 microns, and the thickness of solder layer is then between 20 microns to 100 microns).In addition, the mode of assembling can be a routing, winding engages (Tape Automated Bonding automatically, TAB), glass flip chip encapsulation (chip-on-glass, COG), chip directly encapsulates (chip-on-board, COB), ball grid array substrate chip package (flip chip on BGAsubstrate), the membrane of flip chip joint (chip-on-film, COF), storehouse type multichip packaging structure (chip-on-chipstack interconnection), storehouse cake core encapsulating structure (chip-on-Si-substrate stackinterconnection) or the like on the silicon base.
Another important feature of square structure 8 is on the protective layer: at patterned metal layer 80 upper and lower or between be to use polymeric material as dielectric layer or insulating barrier.The use of polymeric material can be made thickness greater than 2 microns dielectric layer.By the polymeric layer that polymeric material forms, its thickness can be between 2 microns to 100 microns, and are the preferably with the thickness between 3 microns to 30 microns.The polymeric layer 90 (comprise 95,98,99) of use on protective layer 5 can be polyimides (polyimide; PI), benzyl ring butylene (benzocyclobutene; BCB), Parylene (parylene), epoxy-based material (epoxy-basedmaterial); epoxy resin or for example by the photoepoxy SU-8 that SotecMicrosystems provided, the elastomeric material (elastomer) of the Renens that is positioned at Switzerland, for example silicone (silicone).In addition, use weldering cover (solder mask) material in the printed circuit board (PCB) industry can be used as top polymeric layer 99 (being positioned at the polymeric layer of the top on all patterned metal layers 80).Polyimides can be that optical activity material (photosensitive material) is revolved in a sense.In addition, polyimides can be a nonionic polyimides (non-ionic polymide), the ether polyimides (ether-based polyimide) that is provided by the Asahi Chemical of Japan for example, PIMEL TMIn addition; because copper can't spread or be penetrated in the nonionic polyimides; so allow directly to contact between copper and the polyimides; and because the relation of nonionic polyimides; copper wire on the protective layer in the square structure 8 or interplanar distance can be close to 1 micron; such as being between 1 micron to 5 microns, in other words, two metallic circuits or interplanar distance are can be greater than 1 micron.In addition, when being the nonionic polyimides for the polymeric layer that with copper is the metallic circuit of material or plane and described metallic circuit of covering or plane, can selectivity not need overcoat (protectioncap) on metallic circuit or the plane, for example a nickel overcoat (Ni cap layer).Certainly, when forming metallic circuit or plane, also can form such as be the overcoat of nickel on the copper layer, can prevent that more copper ion is diffused in the polymeric layer.
Shown in Figure 15 K, the purpose that in polymeric layer, forms opening be for be used for interconnecting different patterned metal layer 80, fine rule road metal level 60 below being used for connecting or be used for connecting external circuit (external circuit).This polymeric layer opening comprises (1) 9919,9929,9829,9519,9519 ', 9511,9512 and 9514 in first embodiment; (2) 9831,9834,9531,9532 and 9534 in a second embodiment; (3) 9939,9939 ', 9831,9834,9839,9539,9539 ', 9531,9532 and 9534 in the 3rd embodiment; And (4) 9949,9949 ', 9849 ', 9549,9511,9512 and 9514 in the 4th embodiment.Polymeric material can be that optical activity (photo-sensitive) is revolved in sense or moral sense revolves optical activity (non-photo-sensitive).Revolve optically active polymer for sense, it is to utilize exposure and the mode of developing to define and patterned polymer layer opening, and revolve optically active polymer for non-sense, it is by being coated with for the first time photoresist layer definition opening on polymeric layer the time, then this photoresistance is exposed and develop to form opening in photoresistance, come again the polymeric layer that this photoresistance opening is exposed is carried out wet etching or dry ecthing to form opening in polymeric layer, rely at last and remove the formation that photoresistance is finished the polymeric layer opening.The size of polymeric layer opening is between 2 microns to 1000 microns, and between 5 microns to 200 microns, being the preferably.Yet in some design, the polymeric layer opening also might surpass 1,000 micron size.In addition, the polymeric layer opening can be designed to circle, have the square of fillet (corner-rounded square), rectangle or polygon.
Polymeric layer 95 is between protective layer 5 and patterned metal layer 801 lowermost ends.By the polymeric layer opening 950 in the polymeric layer 95, signal, power supply (Vdd or Vcc) and/or ground connection reference voltage (Vss) can transmit between fine rule road metal level 60 and patterned metal layer 80.For internal circuit 20 (comprising 21,22,23,24); polymeric layer opening the 9531,9532, the 9534th is aimed at protective layer opening 531,532,534 respectively; and the size of its polymeric layer opening 9531,9532,9534 is between 1 micron to 300 microns, and between 3 microns to 100 microns, being the preferably.For pressurizer or transformer 41, polymeric layer opening the 9519, the 9519 ', 9511,9512, the 9514th is aimed at protective layer opening 519,519 ', 511,512,514 respectively; Connect external circuit 40 (comprising 42,43) for chip, polymeric layer opening the 9539, the 9539 ', 9531,9532, the 9534th is aimed at protective layer opening 539,539 ', 531,532,534 respectively; For electrostatic storage deflection (ESD) protection circuit 44; polymeric layer opening the 9549,9511,9512, the 9514th is aimed at protective layer opening 549,511,512,514 respectively; polymeric layer opening 9519,9519 ', 9511,9512,9514 in addition; or polymeric layer opening 9539,9539 ', 9531,9532,9534 or the size of polymeric layer opening 9549,9511,9512,9514 can be bigger; its scope is between 5 microns to 1000 microns, and between 10 microns to 200 microns, being the preferably.Polymeric layer opening 950 on protective layer opening 50 has two kinds of opening patterns; in first kind of opening pattern, the polymeric layer opening, for example the polymeric layer opening 9531; be protective layer opening 531, and the polymer side walls of polymeric layer opening 9531 is to be positioned on the protective layer 5 greater than the below.In this kind pattern, can form a less protective layer opening 531, and then at less contact connection pad of metal level top, fine rule road formation, so this kind opening pattern allows the fine rule road of the fine rule road metal level of top to have higher coiling density (routing density); In second kind of opening pattern; the bottom of polymeric layer opening; for example the bottom of polymeric layer opening 9539 is the protective layer openings 539 less than the below, and the polymer side walls of polymeric layer opening (for example the polymeric layer opening 9539) is to be positioned on the metallic pad on metal level top, fine rule road.And in this kind pattern; polymeric layer 95 covers the sidewall of protective layer opening; and the slope of polymeric layer opening (for example the polymeric layer opening 9539) sidewall is less than the slope of protective layer opening sidewalls, and the barrier/Seed Layer 8011 of sticking together/hinder that follow-up metal sputtering is formed has ladder covering (step coverage) preferably.Sticking together/hinder barrier/seed metal ladder covering preferably is very important for the reliability of chip, this is because stick together/hinder metal diffusing that the covering of barrier/seed metal ladder can prevent thick metal layers preferably in the circuit or polymeric layer of below, to prevent metallic compound (the Inter-metallic compound that is situated between; IMC) the generation or the phenomenon of metal diffusing take place.
Polymeric layer opening 980 in the polymeric layer 98 is between patterned metal layer 801 and patterned metal layer 802.For internal circuit 21,22,23,24, the size of polymeric layer opening 9831,9834 is between 1 micron to 300 microns, and between 3 microns to 100 microns, being the preferably.Polymeric layer opening 9829 for pressurizer or transformer 41, or chip connect the size of the polymeric layer opening 9849 ' of the polymeric layer opening 9831,9834,9839 of external circuit 40 (comprising 42,43) or electrostatic storage deflection (ESD) protection circuit 44 can be bigger, its scope between 5 microns to 1, between 000 micron, and between 10 microns to 200 microns, being the preferably.
The connection pad of patterned metal layer 802 tops that exposed by the polymeric layer openings 990 in the top polymeric layer 99 can be used to connect external circuit, or in chip testing (chip testing) as the contact point of probe.For internal circuit 21,22,23,24, top polymeric layer 99 is not provided with the polymeric layer opening; In addition, the polymeric layer opening 9919,9929 of pressurizer or transformer 41, or chip connect polymeric layer opening 9949,9949 ' the size of the polymeric layer opening 9939 of external circuit 40 (comprising 42,43) or electrostatic storage deflection (ESD) protection circuit 44 can be bigger, its scope between 5 microns to 1, between 000 micron, and between 10 microns to 200 microns, being the preferably.
Signal on the input protection layer in the square structure 8, power supply or ground connection reference voltage be by fine rule line structure 6 be sent to internal circuit 20, pressurizer or transformer 41, chip connects in external circuit 40 or the electrostatic storage deflection (ESD) protection circuit 44.In addition, fine rule road metal structure 63 can be with the shortest path mode storehouse mode of rough aligning (for example with) formed fine rule road metal level 60 and conductive plug 60 ', shown in Figure 15 A 631,632,634,639 and 639 '.
The photoetching technique of making square structure 8 on the protective layer is to show to be different from the photoetching technique of making protective layer below integrated circuit.The lithography process of protective layer top equally also includes coating, exposure and development photoresistance.The photoresistance that is used for forming square structure 8 on the protective layer has two kinds of patterns, and it is: (1) wet film photoresistance (liquid photoresist), it is to utilize single or multiple rotary coating mode or printing (printing) mode to form.The thickness of this wet film photoresistance is between 3 microns to 60 microns, and between 5 microns to 40 microns, being the preferably; And (2) dry film photoresistance (dry film Photoresist), it is to utilize laminating type (laminating method) to form.The thickness of this dry film photoresistance is between 30 microns to 300 microns, and between 50 microns to 150 microns, being the preferably.In addition, photoresistance can be eurymeric (positive-type) or minus (negative-type), and is obtaining on the better resolution, is the preferably with the thick photoresistance of eurymeric (positive-type thick photoresist) then.When polymeric layer is when revolving the optical activity material for sense, can only utilize lithography process (need not etching and processing) to come on the patterned polymer layer.Utilize an alignment machine (aligner) or one times of (1X) stepping exposure machine this photoresistance that exposes.This one times (1X) is meant that when being projected on the wafer, the figure on the light shield dwindles the ratio on wafer from a light shield (normally constituting with quartz or glass) when light beam, and is identical with pattern proportion on wafer at the pattern proportion on the light shield.Alignment machine or one times of employed light beam wavelength of stepping exposure machine are 436 nanometers (g-line), 397 nanometers (h-line), 365 nanometers (i-line), g/h line (in conjunction with g-line and h-line) or g/h/i line (combining g-line, h-line and i-line).Use light beam wavelength can revolve in the exposure of optically active polymer at thick photoresistance or thick sense, bigger luminous intensity (light intensity) is provided as one times of stepping exposure machine (or one times of alignment machine) of g/h line or g/h/i line.
Because protective layer 5 can protect the MOS (metal-oxide-semiconductor) transistor of below and fine rule line structure 6 to exempt from the penetrating of the intrusion that is subjected to aqueous vapor and sodium or other moving iron and gold, copper or other transition metal, so square structure 8 can be under a grade 10 or more imprecise (less stringent) environment be handled in the dust free room of (for example grade 100) on the protective layer on the IC wafers.The dust free room of one grade 100 allows the maximum dust particle number of every cubic feet per Foot to be: the dust particle that contains more than or equal to 5 microns is no more than 1, the dust particle that contains more than or equal to 1 micron is no more than 10, the dust particle that contains more than or equal to 0.5 micron is no more than 100, the dust particle that contains more than or equal to 0.3 micron is no more than 300, the dust particle that contains more than or equal to 0.2 micron is no more than 750, the dust particle that contains more than or equal to 0.1 micron is no more than 3500.
Component layer 2 includes internal circuit 20 (comprising 21,22,23 and 24) in all embodiments, and (1) pressurizer or transformer 41 are in first embodiment; (2) chip connects external circuit 40 (comprising 42,43) in the 3rd embodiment; (3) electrostatic storage deflection (ESD) protection circuit 44 is in the 4th embodiment.In all embodiment of the present invention, internal circuit 20 (comprising 21,22,23,24) comprises a signal node (signal node), and this signal node (signalnode) is not to be connected with outside (chip exterior) circuit.And when the signal of internal circuit 20 need be connected to external circuit, be connected to external circuit before, signal must connect external circuit through a chip earlier, and for example chip tristate buffer, chip connect outer driver, chip connects outer receiver or other chip connects outer I/O (I/O) circuit.Therefore, internal circuit does not comprise that chip connects external circuit.
In the present invention, internal circuit 20 (comprises 21,22,23,24) except can a NOR gate (NOR gate) or a NAND gate (NAND gate), it also can be an inverter (inverter), one with the door (an AND gate), one or the door (OR gate), one sram cell (SRAM cell), one DRAM (Dynamic Random Access Memory) unit (DRAM cell), one non-volatile memory cell (non-volatile memoryc ell), one flash cell (flashmemory cell), one Erasable ﹠Programmable ROM unit (EPROM cell), one ROM unit (ROM cell), one magnetic RAM (magnetic RAM, MRAM) unit, one sensing amplifier (sense amplifier), one amplifier is calculated big device (operational amplifier, OpAmp, OPA), one adder (adder), one multiplexer (multiplexer), one duplexer (diplexer), one multiplier (multiplier), one analog/digital converter (A/D converter), one digital/analog converter (D/A converter), one CMOS (Complementary Metal Oxide Semiconductor) sensing component unit (CMOS sensor cell), one photodiode (photo-sensitivediode), one CMOS (Complementary Metal Oxide Semiconductor), a pair of BiCMOS thing semiconductor, one two-carrier circuit (bipolar circuit) or analog circuit (analog circuit).
In addition, internal circuit 20 (comprises 21,22,23,24) constituted by a MOS (metal-oxide-semiconductor) transistor (MOStransistor) at least, NOR gate for example, or door, at least constituted by a MOS (metal-oxide-semiconductor) transistor with door inclusive NAND door, in addition MOS (metal-oxide-semiconductor) transistor can be " channel width (Channel width)/passage length (Channel length) " ratio between the N type MOS (metal-oxide-semiconductor) transistor between 0.1 to 5 or between 0.2 to 2, or " channel width/passage length " ratio is between the P type MOS (metal-oxide-semiconductor) transistor between 0.2 to 10 or between 0.4 to 4.In first embodiment, internal circuit 20 (comprises 21,22,23,24) can be a power management chip (powe rmanagement chip) or power supply supply chip (power supply chip), this power management chip and power supply supply chip are made of a MOS (metal-oxide-semiconductor) transistor at least, and MOS (metal-oxide-semiconductor) transistor can be that " channel width/passage length " ratio is between 4,000 to 400, between 000 or between 4,000 to 40, P type MOS (metal-oxide-semiconductor) transistor between 000, or " channel width/passage length " ratio is between 2,000 to 200, between 000 or between 2, N type MOS (metal-oxide-semiconductor) transistor between 000 to 20,000, and flow through metallic circuit or plane 81,82 electric current then is between between 500 milliamperes to 50 amperes or between 500 milliamperes to 5 milliamperes.
In addition, internal circuit 20 can utilize its peak value the input or output current (electric current on promptly flow through metallic circuit or plane) to define, or defines with its MOS (metal-oxide-semiconductor) transistor size (channel width is divided by the ratio of passage length).One chip connects external circuit 40 (comprising 42,43), also can utilize its peak value the input or output current (electric current on promptly flow through metallic circuit or plane) to define, or define with its MOS (metal-oxide-semiconductor) transistor size (channel width is divided by the ratio of passage length).And this internal circuit 20 and chip connect the definition of external circuit 40 (comprising 42,43) is to be useful among all embodiment of the present invention.
Therefore, the fine rule road metal structure that the present invention can be by protective layer below and the metallic circuit or the plane of protective layer top be connected at least two MOS (metal-oxide-semiconductor) transistor in the same circuit pack respectively grid with grid, grid and source electrode, grid and drain electrode, source electrode and source electrode, source electrode and drain electrode or drain and drain.
Below will narrate with all embodiment of the present invention relatively in, the patterned metal layer 80 and fine rule road metal level 60 size characteristic and electric characteristics (electrical characteristic) between the two of square structure 8 on the protective layer.
(1) thickness of metallic circuit
The thickness of each patterned metal layer 80 is between 2 microns to 150 microns, and between 3 microns to 20 microns, being the preferably, the thickness of each fine rule road metal level 60 is then between 0.05 micron to 2 microns, and being the preferably between 0.2 micron to 1 micron.
For according to the designed wafer of embodiments of the invention; the thickness of one protective layer top patterned metal layer is greater than arbitrary fine rule road metal layer thickness; and both thickness is than being scope between 2 to 250, and is the preferably with the scope between 4 to 20.
(2) thickness of dielectric layer
Each protective layer top dielectric layer (is generally organic material; polymer for example) thickness; thickness as polymeric layer 90; be between 2 microns to 150 microns; and between 3 microns to 30 microns, being the preferably; and the thickness of each fine rule road dielectric layer 30 (being generally inorganic material, for example oxide or nitride) is then between 0.05 micron to 2 microns, and between 0.2 micron to 1 micron, being the preferably.
For according to the designed wafer of embodiments of the invention, the thickness of protective layer top dielectric layer is the thickness greater than arbitrary fine rule road dielectric layer, and both thickness is than being scope between 2 to 250, and is the preferably with the scope between 4 to 20.
(3) sheet resistor of metal level (sheet resistance) and resistance
The sheet resistor of one metal level is to rely on calculating metallic resistance rate (metal resistivity) to get divided by metal thickness.The sheet resistor of the protective layer of one bronze medal (thickness is 5 microns) material top patterned metal layer is approximately every square (per square) 4 millioersted nurses (mili-ohm), then is approximately every square 5.5 millioersted nurse for the sheet resistor of the protective layer top patterned metal layer of a gold medal (thickness is 4 microns) material.The sheet resistor of one protective layer top patterned metal layer is to the scope between every square 10 millioersted nurse, and being the preferably between every square 1 millioersted nurse to the scope between every square 7 millioersted nurse between every square 0.1 millioersted nurse.The fine rule road metal level of aluminium (thickness the is 0.8 micron) material that forms with sputter, its sheet resistor is approximately every square 35 millioersted nurse, and for the fine rule road metal level that forms a bronze medal (thickness is 0.9 micron) material with damascene process, its sheet resistor then is approximately 20 millioersted nurses.The sheet resistor of one fine rule road metal level is to the scope between every square 400 millioersted nurse, and being the preferably between every square 15 millioersted nurse to the scope between every square 100 millioersted nurse between every square 10 millioersted nurse.
The resistance per unit length of one metallic circuit (resistance per unit length) is to rely on the calculating sheet resistor to get divided by its width.The transverse design standard (width) of protective layer top patterned metal layer is between 1 micron to 200 microns; and between 2 microns to 50 microns, being the preferably; the transverse design standard (width) of fine rule road metal level then is between between 20 nanometers to 15 micron, and with between being the preferably between 20 nanometers to 2 micron.Every millimeter resistance (resistance per mm) of one protective layer top patterned metal layer is between every millimeters long 5 nurses difficult to understand between every millimeters long (resistance per mm length) 2 millioersted nurses; and being the preferably between every millimeters long 2.5 nurses difficult to understand between every millimeters long 50 millioersted nurses; every millimeter resistance of one fine rule road metal level then is to every millimeters long 3 between every millimeters long 500 millioersted nurses; between 000 nurse difficult to understand, and being the preferably between every millimeters long 500 millioersted nurses between every millimeters long 500 nurses difficult to understand.
For according to the designed wafer of embodiments of the invention; the resistance per unit length of one protective layer top patterned metal layer is the resistance per unit length less than arbitrary fine rule road metal level; and both resistance per unit lengths are the scopes between 3 to 250 than (fine rule road metal level than protective layer top patterned metal layer), and are the preferably with the scope between 10 to 30.
(4) capacitance per unit length of metallic circuit (capacitance per unit length)
Capacitance per unit length be with width, distance and the thickness of the type of dielectric medium and thickness, metallic circuit and horizontal direction and vertical direction on around metal relevant.The dielectric constant of polyimides is approximately 3.3, and the dielectric constant of benzyl ring butylene then is approximately 2.5.Then, please consult earlier to shown in the 20th figure, it is openly to go out on same patterned metal layer 802, one patterned metal layer 802x has two adjacent patterned metal layer 802y and patterned metal layer 802z, and have a patterned metal layer 801w for 802 times at patterned metal layer, and this patterned metal layer 801w utilizes a polymeric layer 98 and patterned metal layer 802 to separate.Similarly, the 20th figure also discloses out on same fine rule road metal level 602, one fine rule road metal level 602x has two adjacent fine rule road metal level 602y and fine rule road metal level 602z, and have a fine rule road metal level 601w for 602 times at fine rule road metal level, and this fine rule road metal level 601w utilizes a fine rule road dielectric layer 30 and fine rule road metal level 602 to separate.
The capacitance per unit length of patterned metal layer 802x and fine rule road metal level 602x includes three elements: (1) plate capacitance (plate capacitance), Cxw (pF/mm), it is metallic circuit or the plane width function divided by the ratio of dielectric medium thickness; (2) coupling capacitance (coupling capacitance), Ccx (=Cxy+Cxz), its be metallic circuit or planar thickness divided by between between adjacent metal circuit or the plane apart from a function of the ratio of (line spacing); And (3) edge capacitance (fringing capacitance), Cfx (=Cfl+Cfr), its be between between the thickness on metallic circuit or plane, adjacent metal circuit or the plane apart from a function of dielectric medium thickness.Every millimeter electric capacity of one patterned metal layer is to every millimeters long 2pF between every millimeters long 0.1pF (picoFarads), and being the preferably between every millimeters long 1.5pF between every millimeters long 0.3pF, every millimeter electric capacity of one fine rule road metal level then be between every millimeters long 0.2pF to every millimeters long 4pF, and with between every millimeters long 0.4pF to being the preferably between every millimeters long 2pF.
For according to the designed wafer of embodiments of the invention, the capacitance per unit length of one patterned metal layer is the capacitance per unit length less than arbitrary fine rule road metal level, and both capacitance per unit lengths are the scopes between 1.5 to 20 than (fine rule road metal level is than patterned metal layer), and are the preferably with the scope between 2 to 10.
(5) the resistance capacitance constant of metallic circuit (RC constant)
Signal passing time on one metallic circuit is to utilize capacitance-resistance to postpone (RC delay) to calculate.Based on holding within above-mentioned (3) and (4), it is between the scope of every millimeters long 0.003 to 10ps (picosecond) that the capacitance-resistance of one patterned metal layer postpones, and between the scope of every millimeters long 0.25 to 2ps (pico second), being the preferably, it then is between the scope of every millimeters long 10 to 2000ps (pico second) that the capacitance-resistance of one fine rule road metal level postpones, and between the scope of every millimeters long 40 to 500ps (pico second), being the preferably.
For according to the designed wafer of embodiments of the invention, the unit length capacitance-resistance passing time of one patterned metal layer (RC propagation time) is the unit length capacitance-resistance passing time less than arbitrary fine rule road metal level, and both unit length capacitance-resistance transmission delay time, (RC propagation delay time) was the scope between 5 to 500 than (fine rule road metal level is than patterned metal layer), and being the preferably between 10 to 30.
Come, see also back shown in Figure 15 C to Figure 15 L, it is openly to go out on completed wafer 10 (shown in Figure 15 A or Figure 15 B), forms the making step of square structure 8 on the protective layer.Each patterned metal layer 80 is to utilize relief processing (processing as a comparison with the damascene copper under the protective layer 5) to form.See also shown in Figure 15 C, a polymeric layer 95 is deposited on the protective layer 5, and exposes the metallic pad 600 that protective layer opening 50 is exposed by polymeric layer opening 950.If this polymer is to be liquid form (liquid form), it is to utilize the mode of rotary coating or printing to deposit formation, and if this polymer is a dry film (dryfilm), then this dry film can utilize a laminating type to form.Revolve optically active polymer for sense, polymeric layer 95 is to utilize alignment machine or one times of (1X) stepping exposure machine to expose by the light of light shield, and forms polymeric layer opening 950 by developing in polymeric layer 95; When polymer is non-sense when revolving optical activity, then must use photoresistance, and come pattern to dissolve polymeric layer opening 950 by traditional lithography process.The mode of patterned polymer layer, can be following mode: before the coating photoresistance, alternative deposition one is shielding (hardmask firmly, one silica layer for example, not shown in the figures) on polymeric layer 95, and during etching polymer layer opening, this hard shielding has an etch-rate (etch rate) slowly.In addition, the mode of patterned polymer layer 95 (being that polymeric layer 95 has polymeric layer opening 950) also can be utilized the mode (screen printingmethod) of screen printing, rely on and use a metal otter board (metal screen) to form, and the mode of screen printing does not need to expose and develop with patterning hole (hole).In addition, if polymeric layer is a dry film, on conforming to wafer before, can in a dry film, form hole earlier, so do not need to expose and develop in this mode.In addition; owing to can form polymeric layer 95 on protective layer 5; therefore the patterned metal layer 80 that is positioned at the below on the protective layer 5 can be formed on the comparatively smooth plane that upper surface provided by polymeric layer 95; so can prevent to produce between the adjacent lines of patterned metal layer 80 phenomenon of leakage current; and the situation that prevents to produce between the fine rule road metal structure under patterned metal layer 80 and the protective layer coupling, electrically (electrical performance) therefore can be provided preferably.Yet on some is used, also can omit polymeric layer 95 and cost saving.Polymeric layer opening 950 is to be aligned in protective layer opening 50, and polymeric layer opening 950 can be to be greater than or less than protective layer opening 50.In addition; protective layer opening 50 also can be that first deposited polymer layer 95 is on protective layer 5 with the generation type of polymeric layer opening 950; then form polymeric layer opening 950; form protective layer opening 50 at last again; and in this mode, the size of polymeric layer opening 950 pact is measure-alike with protective layer opening 50.
Please consult simultaneously shown in Figure 15 D to Figure 15 H, it is the open relief processing that goes out to form patterned metal layer 801.In Figure 15 D, barrier/Seed Layer 8011 is sticked together/hindered to deposition one on the polymeric layer 95, in polymeric layer opening 950 and in protective layer opening 50, wherein is that deposition forms the preferred mode of sticking together/hindering barrier/Seed Layer 8011 with the sputter.When be gold for the material that forms thick metal layers, the formation of sticking together/hindering barrier/Seed Layer 8011 be utilize earlier sputtering way formation thickness 3,000 dusts (
Figure GA20169723200710003679X01D00621
) a titanium-tungsten or the sticking together/barrier layer of titanium, then sputter forms a gold seeds layer of thickness 1,000 dust again.When being copper for the material that forms thick metal layers, the formation of sticking together/hindering barrier/Seed Layer 8011 be utilize earlier sputtering way form thickness 500 dusts the sticking together of a chromium metal/barrier layer, form thickness 1, sticking together/barrier layer or formation thickness 3 of one titanium of 000 dust, sticking together/barrier layer of one titanium-tungsten of 000 dust, follow again the copper seed layer that sputter forms thickness 5,000 dusts.Figure 15 E openly goes out a photoresist layer 71 to deposit and be patterned on the Seed Layer of sticking together/hindering barrier/Seed Layer 8011.Photoresist layer 71 is that the mode with rotary coating is coated with formation, then utilizes an alignment machine or one times of (1X) stepping exposure machine to expose, and after developing, forms photoresist layer opening 710 in photoresist layer 71 again.Photoresist layer opening 710 is to be used for defining the metallic circuit that contacts with protective layer opening 50 with polymeric layer opening 950 in the following process or the formation on plane, and this contact is on the metallic pad 600 that exposes, and connects this metallic pad that exposes 600.Among Figure 15 F, form a thick metal layers 8012 on the Seed Layer that photoresist layer opening 710 is exposed in the mode of electroplating.This thick metal layers 8012 can be the gold medal layer of thickness between 1.5 microns to 50 microns, or the bronze medal layer of thickness between 2 microns to 200 microns.One protection/barrier layer (cap/barrier layer, not shown in the figures) can utilize the mode selectivity of plating or electroless-plating to be formed on the thick metal layers 8012.One assembling/contact layer (assembly/contact layer, not shown in the figures) also can utilize electroplate or the mode of electroless-plating further selectivity be formed on thick metal layers 8012 and the protection/barrier layer.This assembling/contact layer can be a gold medal layer, a palladium layer or the ruthenium layer of thickness between 0.01 micron to 5 microns.Then, shown in Figure 15 G, remove photoresist layer 71.Continue, in Figure 15 H, utilize the mode of self-aligned (self-aligned) wet etching or dry ecthing, remove not by what thick metal layers 8012 covered and stick together/hinder barrier/Seed Layer 8011.When utilizing the wet etching mode to remove, can form depressed part (under cut) 8011 ' in the bottom of patterned metal layer 801 sidewalls, wherein this depressed part 8011 ' is to be positioned at thick metal layers 8012 belows, and when using anisotropy dry ecthing (anisotropiesdry etch), then do not have the generation of above-mentioned depressed part 8011 '.
Please consult simultaneously shown in Figure 15 I and Figure 15 J, it is openly to go out the step that forms a polymeric layer 98 and patterned metal layer 802 with the described processing of Figure 15 C to Figure 15 H.In addition, the processing shown in Figure 15 I and Figure 15 J can repeat to be used in and form on the 3rd metal level, the 4th metal level or the more metal level.If square structure 8 only comprises two metal levels (patterned metal layer 801 and patterned metal layer 802) on the protective layer; one protective polymers layer (cap polymer layer) 99 is deposited on patterned metal layer 802 (present top) and is not patterned on the polymeric layer 98 that metal level 802 covered, shown in Figure 15 K.Polymeric layer opening 990 is formed in the top polymeric layer 99, and exposes as the contact connection pad 8000 that connects external circuit.On some was used, for example when thick metal layers 8012 was gold, alternative was omitted top polymeric layer 99.Figure 15 K is the open wafer that goes out to have simultaneously square structure 8 on fine rule line structure 6 and the protective layer, and it is that polymeric layer opening 990 with top polymeric layer 99 exposes contact connection pad 8000.
Wafer sawing (cutting) is become a plurality of independent chips, and the contact connection pad 8000 of this independent chip can utilize mode what follows to connect external circuit, and it is: the routing lead (gold thread, aluminum steel or copper cash) of (1) one routing processing; (2) other suprabasil projection (golden projection, copper bump, solder projection or other metal coupling), at the bottom of this substrate can be silicon, silicon base, ceramic bases, organic group, ball-type palisade array (BGA) substrate, pliability (flexible) substrate, pliability winding (flexible tape) or substrate of glass, and in this suprabasil bump height is between 1 micron to 30 microns, and between 5 microns to 20 microns, being the preferably; (3) other suprabasil cylinder (principal column, copper post, solder post or other metal column), at the bottom of this substrate can be silicon, silicon base, ceramic bases, organic group, ball-type palisade array (BGA) substrate, pliability (flexible) substrate, pliability winding (flexible tape) or substrate of glass, and at this suprabasil height of column is between 10 microns to 200 microns, and between 30 microns to 120 microns, being the preferably; Projection on the plain conductor end of (4) one lead frames (lead frame) or a pliability winding (flexible tape) (golden projection, copper bump, solder projection or other metal coupling), this suprabasil bump height is between 1 micron to 30 microns, and between 5 microns to 20 microns, being the preferably.
In some applications, the contact structures 89 that are formed on the contact connection pad 8000 can be used on the connection external circuit, shown in Figure 15 L.One projection bottom metal layer (UBM) 891 is formed on contact structures 89 times, in order to as the usefulness of sticking together with diffusion barrier.These contact structures 89 can be: (thickness is between 0.1 micron to 30 microns for the scolder connection pad that (1) utilization is electroplated or stencil printing forms, and between 1 micron to 10 microns, being the preferably), or solder projection (height between 10 microns to 200 microns, and between 30 microns to 120 microns, being the preferably).Then, utilize a reflow (solder reflow) processing that it is formed the solder ball (ball-shaped solder ball) of a sphere again.Scolder connection pad or solder projection can be: 1. the scolder that lead tolerance is high (high lead solder), for example contain the leypewter (PbSn) that percentage by weight surpasses 85% plumbous composition; 2. eutectic solder (eutectic) for example contains the leypewter of the solder component of the plumbous composition of percentage by weight about 37% and percentage by weight about 63%; 3. lead-free solder (lead-free solder), for example sn-ag alloy (SnAg) or tin Kufil (SnCuAg).In addition, projection bottom metal layer 891 can be a composite bed (arrangement from down to up) what follows, comprising: titanium/nickel, titanium/same/nickel, titanium-tungsten/nickel, titanium-tungsten/copper/nickel, titanium/nickel/gold, titanium/copper/nickel/gold, titanium-tungsten/nickel/gold, titanium-tungsten/copper/nickel/gold, titanium/copper/nickel/palladium, titanium-tungsten/copper/nickel/palladium, chromium/chrome copper, nickel-vanadium alloy/copper, nickel/copper, nickel-vanadium alloy/gold, nickel/gold or nickel/palladium; (2) (thickness is between 0.1 micron to 10 microns to utilize the golden connection pad that plating mode forms, and between 1 micron to 5 microns, being the preferably), or golden projection (height between 5 microns to 40 microns, and between 10 microns to 20 microns, being the preferably).In addition, projection bottom metal layer 891 can be: the composite bed (arrangement from down to up) of composite bed of titanium, titanium-tungsten, tantalum, tantalum nitride, titanium/copper/nickel (arrangement from down to up) or titanium-tungsten/same/nickel; (3) utilize the Metal Ball (metal ball) of planting ball processing (ball mounting) formation.This Metal Ball can be the copper ball of a copper ball (copper ball), surface coated one nickel dam and a solder layer of a solder ball, surface coated one nickel dam or a copper ball of surface coated one nickel dam and a gold medal layer.In addition, the diameter of Metal Ball is between 10 microns to 500 microns, and between 50 microns to 300 microns, being the preferably.In addition, Metal Ball can directly be welded on the surface of the contact connection pad 8000 that is exposed by polymeric layer opening 990 or on the projection bottom metal layer 891, and the projection bottom metal layer 891 that forms the weld metal ball can be a composite bed (arrangement from down to up) what follows, and it is to comprise: titanium/nickel, titanium/copper/nickel, titanium-tungsten/nickel, titanium-tungsten/copper/nickel, titanium/nickel/gold, titanium/copper/nickel/gold, titanium-tungsten/nickel/gold, titanium-tungsten/copper/nickel/gold, titanium/copper/nickel/palladium, titanium-tungsten/copper/nickel/palladium, chromium/chrome copper, nickel-vanadium alloy/copper, nickel/copper, nickel-vanadium alloy/gold, nickel/gold or nickel/palladium.In addition, stick together Metal Ball after, can need to carry out a reflow (solder reflow) processing usually.
After formation contact structures 89, utilize the mode of sawing or cutting to cut apart chip on the wafer, be connected to external circuit to encapsulate or to assemble, wherein Zu Zhuan method can be that routing (is connected to outside organic, pottery, connection pad on glass or the silicon base, or be connected to the lead of a lead frame or a pliability winding), winding engages (TAB) automatically, coil type chip carrier (tape-chip-carrier, TCP) encapsulation, glass flip chip encapsulation (COG), chip directly encapsulates (COB), ball grid array substrate chip package (flip chip on BGA substrate), membrane of flip chip engages (COF), membrane of flip chip encapsulation (chip on flex), storehouse type multichip packaging structure (chip-on-chip stack interconnection), storehouse cake core encapsulating structure on the silicon base (chip-on-Si-substrate stack interconnection) or the like.
In the processing of the relief shown in Figure 15 C to Figure 15 K, it is that the open step that goes out to form a patterned metal layer is: form and stick together/hinder barrier/Seed Layer once, forming a photoresist layer subsequently and electroplating this patterned metal layer also is for once, remove photoresist layer at last again, and will not be patterned that metal level covers stick together/hinder barrier/Seed Layer removal.The processing of this kind pattern is called single relief processing (single-emboss process), also be this processing remove be not patterned that metal level covers stick together/hinder barrier/Seed Layer before, only comprise that once lithography process and plating once process.
A pair of relief processing (double-embossing process) can be by same sticking together/hinder barrier/Seed Layer to form a patterned metal layer and a metal plug (via plug), and remove be not patterned that metal level covers stick together/hinder barrier/Seed Layer before, finish twice lithography process and electroplate processing, wherein primary lithography process is to be used for forming patterned metal layer with electroplating processing, and secondary lithography process then is to be used for forming metal plug with electroplating processing.
Please consult simultaneously shown in Figure 16 A to Figure 16 D, it is the two reliefs processing that openly go out forming square structure 8 on the protective layer on the wafer 10 shown in Figure 15 A or Figure 15 B.Two reliefs are processed with and the identical making step of single processing shown in Figure 15 C to Figure 15 G.In Figure 15 G, it is that photoresistance is removed, and stays not sticking together under thick metal layers 8012/hinder barrier/Seed Layer 8011.So far two relief processing steps begin with the processing of single relief different; please consult simultaneously shown in Figure 16 A to the 16L figure; it is openly to go out to rely on to use a pair of relief to be processed to form patterned metal layer 801 and metal plug 898; and use a single relief to be processed to form the mode of the metal level 802 of top, form an example of the patterned metal layer structure of protective layer top among all embodiment of the present invention.Utilize primary lithography process and plating to be processed to form patterned metal layer 801, shown in Figure 15 D to Figure 15 G.Then, please consult simultaneously shown in Figure 16 A and Figure 16 B, the Seed Layer and the utilization of sticking together/hindering barrier/Seed Layer 8011 are electroplated on the thick metal layers 8012 that forms, deposit a photoresist layer 72, and this photoresist layer 72 carried out patterning, make photoresist layer 72:(1) on thick metal layers 8012, form photoresist layer opening 720, and utilize photoresist layer opening 720 to expose thick metal layers 8012; And/or (2) sticking together/hindering and forming photoresist layer opening 720 ' on the Seed Layer of barrier/Seed Layer 8011, and utilize this photoresist layer opening 720 ' to expose the Seed Layer of sticking together/hindering barrier/Seed Layer 8011.Continue, photoresist layer 72 remove before, implement to electroplate for the second time processing with formation metal plug 898 photoresist layer opening 720 in.In addition, sticking together/hindering on the Seed Layer of barrier/Seed Layer 8011 also a metal level 898 ' that can the accurate position of formation level hangs down in metal plug 898, this metal level 898 ' can be used on the encapsulation purposes.This metal level 898 ' can be thinner than thick metal layers 8012, also can be thicker than thick metal layers 8012, when the thickness of metal level 898 ' during less than the thickness of thick metal layers 8012, for example less than 5 microns (are between 1 micron to 3 microns in preferable situation), metal level 898 ' can be used for making than the high connection line (interconnection) of thick metal layers 8012 coiling density, yet when the thickness of metal level 898 ' during greater than the thickness of thick metal layers 8012, for example greater than 5 microns (are between 5 microns to 10 microns in preferable situation), metal level 898 ' can be used for making than the lower connection line of thick metal layers 8012 resistance.Come again, see also shown in Figure 16 C, remove photoresist layer 72, to expose thick metal layers 8012, metal plug 898, metal level 898 ' and under thick metal layers 8012 and metal level 898 ', not stick together/hinder barrier/seed 8011.See also shown in Figure 16 D, utilize wet etching (wet etch) and/or dry ecthing (dry etch) to remove not and under thick metal layers 8012 and metal level 898 ', stick together/hinder barrier/Seed Layer 8011.Therefore, patterned metal layer 801, metal plug 898 are formed in this stage shown in Figure 16 D with metal level 898 '.Continue to see also shown in Figure 16 E, a polymeric layer 98 be formed on metal plug 898, metal level 898 ', patterned metal layer 801 and first polymeric layer 95 that exposes on.See also shown in Figure 16 F, utilize grinding, mechanical lapping or cmp processing, the surface of planarization polymeric layer 98 is till exposing metal plug 898.Come, please consult simultaneously shown in Figure 16 G to the 16K figure, it is the open making step that is processed to form a patterned metal layer 802 as the described identical single relief of Figure 15 C to Figure 15 K that goes out to utilize.Continue, see also shown in the 16L figure, deposition and patterning one top polymeric layer 99 have square structure 8 on the protective layer of two patterned metal layers 801,802 to finish one at last.In addition, in assembling (assembly) and/or encapsulation, also can shown in Figure 15 L, form contact structures 89 on the contact connection pad 8000 that polymeric layer opening 990 exposes.In addition, Figure 15 D to Figure 15 G and Figure 16 A to Figure 16 D be described to be used for forming the making step of two reliefs processing of patterned metal layer 801 and metal plug 898, also reusable formation on second patterned metal layer (metal level of top) and the second metal plug (not shown), and this second metal plug can be used as the contact structures that are connected to external circuit.At last, narration and the explanation about Figure 16 A to the 16L figure is to be useful among all embodiment of the present invention.
See also shown in Figure 17 A to Figure 17 J; it is the procedure of processing that openly goes out square structure 8 formation patterned metal layer 801, patterned metal layer 802 and patterned metal layers 803 on the protective layer; wherein patterned metal layer 801 is to utilize a pair of relief to process to form with patterned metal layer 802, and patterned metal layer 803 then is to utilize a single relief to process to form.At first, as described in Figure 15 D to Figure 15 G and Figure 16 A to Figure 16 D, utilize primary pair of relief to process and form patterned metal layer 801 and metal plug 898.Then, the procedure of processing shown in Figure 16 E to Figure 16 F, behind formation one polymeric layer 98, this polymeric layer 98 of planarization is till exposing metal plug 898.Continue to see also shown in Figure 17 A, the procedure of processing before forming patterned metal layer 802 is identical with the procedure of processing that two reliefs are processed to form patterned metal layer 801, metal plug 898 and polymeric layer 98 with Figure 16 F.Yet in order to hold an extra metal level, the patterned metal layer 801 of Figure 17 A is slightly different with the design of metal plug 898 with the patterned metal layer 801 of Figure 16 F with the design of metal plug 898.Come again, please consult simultaneously shown in Figure 17 A to Figure 17 G, repeat Figure 15 D to Figure 15 G and the described procedure of processing of Figure 16 A to Figure 16 D forming a patterned metal layer 802, a metal plug 897 and a polymeric layer 97, and expose metal plug 897.In Figure 17 A, it is to form in the following manner: barrier/Seed Layer 8021 is sticked together/hindered to (1) deposition one; (2) deposition and patterning one photoresist layer; (3) opening in this photoresist layer is electroplated a thick metal layers 8022; And (4) remove this photoresist layer, to form the structure shown in Figure 17 A.Come, see also shown in Figure 17 B, deposition and patterning one photoresist layer 74 forming photoresist layer opening 740 on thick metal layers 8022, or directly form on the Seed Layer that photoresist layer opening 740 ' sticking together/hindering barrier/Seed Layer 8021.See also Figure 17 C, the mode of utilize electroplating forms metal plug 897 and metal level 897 ' in photoresist layer opening 740 and photoresist layer opening 740 ', and this metal level 897 ' can be used as the purposes identical with metal level 898 '.Please consult simultaneously shown in Figure 17 D to Figure 17 E, remove photoresist layer 74, and will not remove in thick metal layers 8022 and the barrier/Seed Layer 8021 of sticking together/hinder under the metal level 897 '.Please consult simultaneously shown in Figure 17 F to Figure 17 G, deposit a polymeric layer 97 again, and this polymeric layer 97 of planarization, till exposing metal embolism 897.Then, please consult simultaneously shown in Figure 17 H to Figure 17 I, it is openly to go out to use a single relief to process the step that forms a patterned metal layer 803, and be described below: barrier/Seed Layer 8031 is sticked together/hindered to (1) deposition; (2) deposition and patterning one photoresist layer; (3) electroplate formation one thick metal layers 8032; And (4) remove photoresist layer, and remove not sticking together under thick metal layers 8032/hinder barrier/Seed Layer 8031 in the mode of self-aligned etching (self-aligned etch).At last, see also shown in Figure 17 J, it is openly to go out to rely on deposition one top polymeric layer 99, and patterned top polymeric layer 99 formation polymeric layer openings 990 expose a complete structure that is connected to a contact connection pad 8000 of external circuit as connection line (interconnection).
See also shown in Figure 18 A to Figure 18 I; it is the another kind of procedure of processing that openly goes out square structure formation patterned metal layer 801, patterned metal layer 802 and patterned metal layer 803 on the protective layer; wherein patterned metal layer 801 is to utilize a single relief to process to form with patterned metal layer 803, and the second layer metal layer then is to utilize a pair of relief to process to form.At first see also shown in Figure 18 A, it is to utilize to process as the described single relief of Figure 15 D to Figure 15 H to form patterned metal layer 801.Then, with the described procedure of processing of Figure 15 I, deposition forms a polymeric layer 98, and polymeric layer 98 is carried out patterning, exposes patterned metal layer 801 to form polymeric layer opening 980.Yet in order to hold an extra metal level, the patterned metal layer 801 of Figure 18 A is slightly different with the design of polymeric layer opening 980 with the patterned metal layer 801 of Figure 15 I with the design of polymeric layer opening 980.Come again, see also shown in Figure 18 B to Figure 18 G, it is openly to go out to use a pair of relief to process to form the procedure of processing of a patterned metal layer 802 and a metal plug 897, and is described below: (1) sees also shown in Figure 18 B, and deposition forms one and sticks together/hinder barrier/Seed Layer 8021; (2) see also shown in Figure 18 C, deposit a photoresist layer 72, and photoresist layer 72 is carried out patterning to form photoresist layer opening 720, then in the photoresist layer opening 720 of photoresist layer 72, electroplate a thick metal layers 8022; And (3) removal photoresist layer 72, to form the structure shown in Figure 18 D.Come, see also shown in Figure 18 E, deposition forms a photoresist layer 73, and this photoresist layer 73 of patterning to be forming photoresist layer opening 730 on thick metal layers 8022, and/or form photoresist layer opening 730 ' and sticking together/hindering on the Seed Layer of barrier/Seed Layer 8021.Continue, utilize the mode of electroplating, in photoresist layer opening 730,730 ', form metal plug 897 and metal level (metal piece) 897 ', and this metal level 897 ' can be used as the same use as the described metal level 898 ' of Figure 16 D.See also shown in Figure 18 F to Figure 18 G, remove photoresist layer 73, and will not remove in thick metal layers 8022 and the barrier/Seed Layer 8021 of sticking together/hinder under the metal level 897 '.See also shown in Figure 18 H, deposit a polymeric layer 97 again, and this polymeric layer 97 of planarization is till exposing metal embolism 897.At last, see also shown in Figure 18 I, it is openly to go out to utilize the described single relief of Figure 17 H to Figure 17 I to be processed to form patterned metal layer 803, and relies on deposition one top polymeric layer 99 and these top polymeric layer 99 formation polymer openings 990 of patterning to expose a complete structure that is connected to a contact connection pad 8000 of external circuit as connection line (interconnection).
Please consult simultaneously shown in Figure 19 A to Figure 19 G; it is the processing that openly goes out forming square structure 8 on the protective layer on the wafer 10 shown in Figure 15 A or Figure 15 B; wherein patterned metal layer 801 is to utilize a pair of relief to process to form, and patterned metal layer 802 then is to utilize a single relief to process to form.At first, in Figure 19 A, utilize described pair of relief procedure of processing of Figure 15 D to Figure 15 G and Figure 16 A to Figure 16 F to form patterned metal layer 801, metal plug 898, metal level 898 ' and polymeric layer 98.Then, please consult simultaneously shown in Figure 19 A to the 19G figure, it is to utilize to form a patterned metal layer 802, a polymeric layer 97, top, top polymeric layer 99 as the described identical single relief procedure of processing of Figure 15 C to Figure 15 K and expose with a polymeric layer opening 990 and contact connection pad 8000, narrates no longer in detail at this.
At last, see also shown in Figure 19 H, wafer sawing (cutting) is become a plurality of independent chips, and connect external circuit, for example utilize the routing lead 89 ' (as gold thread, aluminum steel or copper cash) of routing processing to connect external circuit by the contact connection pad on the independent chip 8000.
The above only is preferred embodiment of the present invention, only is illustrative for the purpose of the present invention, and nonrestrictive.Those skilled in the art is understood, and can carry out many changes to it in the spirit and scope that claim of the present invention limited, revise, even equivalence, but all will fall within the scope of protection of the present invention.

Claims (36)

1. circuit pack, it is characterized in that: it comprises:
One first internal circuit has an output node;
One second internal circuit, has an input node, and described first internal circuit and described second internal circuit comprise a P-type mos assembly respectively at least, and the channel width of described P-type mos assembly and passage length ratio are between 0.2 to 10;
Described first internal circuit and described second internal circuit are carried in one siliceous substrate;
One first metallic circuit connects the described output node of described first internal circuit;
One second metallic circuit connects the described input node of described second internal circuit;
One protective layer, be positioned on described siliceous substrate, described first internal circuit, described second internal circuit, described first metallic circuit and described second metallic circuit, and the material of described protective layer be a nitrogen silicon compound and an oxygen silicon compound one of them or and combination;
A plurality of dielectric layers are between described siliceous substrate and described protective layer; And
One the 3rd metallic circuit; be positioned on the described protective layer; and described the 3rd metallic circuit connects described first metallic circuit and connects described second metallic circuit; described the 3rd metallic circuit comprises the bronze medal layer of thickness between 3 microns to 20 microns, and described the 3rd metallic circuit is not electrically connected with the external world.
2. circuit pack according to claim 1 is characterized in that: described first internal circuit comprises a NOR gate, one or the door, one with the door, one NAND gate, one sram cell, one DRAM (Dynamic Random Access Memory) unit, one non-volatile memory cell, one flash cell, one Erasable ﹠Programmable ROM unit, one ROM unit, one magnetic RAM unit, one sensing amplifier, one operational amplifier, one adder, one multiplexer, one duplexer, one multiplier, one analog/digital converter, one digital/analog converter, one complementary metal oxide semiconductor, one photodiode, a pair of BiCMOS thing semiconductor, one inverter, one inner drive, one inner receiver, an one inner tristate buffer and a two-carrier circuit unit one of them or and the combination.
3. circuit pack according to claim 1 is characterized in that: described first metallic circuit comprises the aluminium lamination of thickness between 0.05 micron to 2 microns.
4. circuit pack according to claim 1 is characterized in that: described first metallic circuit comprises the bronze medal layer of thickness between 0.05 micron to 2 microns.
5. circuit pack according to claim 1 is characterized in that: described the 3rd metallic circuit comprises that also one contains titanium coating, and described copper layer is positioned at described containing on the titanium coating.
6. circuit pack according to claim 1 is characterized in that: described circuit pack is a chip.
7. circuit pack according to claim 1 is characterized in that: also comprise one first polymeric layer of thickness between 2 microns to 100 microns, and described first polymeric layer is between described protective layer and described the 3rd metallic circuit.
8. circuit pack according to claim 1 is characterized in that: described second internal circuit comprises a NOR gate, one or the door, one with the door, one NAND gate, one sram cell, one DRAM (Dynamic Random Access Memory) unit, one non-volatile memory cell, one flash cell, one Erasable ﹠Programmable ROM unit, one ROM unit, one magnetic RAM unit, one sensing amplifier, one operational amplifier, one adder, one multiplexer, one duplexer, one multiplier, one analog/digital converter, one digital/analog converter, one complementary metal oxide semiconductor, one photodiode, a pair of BiCMOS thing semiconductor, one inverter, one inner drive, one inner receiver, an one inner tristate buffer and a two-carrier circuit unit one of them or and the combination.
9. circuit pack according to claim 1 is characterized in that: comprise that also a polymeric layer is positioned on described protective layer and described the 3rd metallic circuit.
10. circuit pack according to claim 1 is characterized in that: described siliceous substrate is a silicon base.
11. a circuit pack, it is characterized in that: it comprises:
One chip connects external circuit, comprises input node and an output node, and described chip connects external circuit and is made of a metal oxide semiconductor component at least;
One internal circuit comprises an input node and an output node;
One siliceous substrate is carried described chip and is connect external circuit and described internal circuit;
One first metallic circuit connects described chip and connects external circuit;
One second metallic circuit connects described internal circuit;
One protective layer is positioned at described chip and connects on external circuit, described internal circuit, described first metallic circuit and described second metallic circuit;
One the 3rd metallic circuit connects described first metallic circuit and described second metallic circuit;
One the 4th metallic circuit is positioned under the described protective layer and connects described chip and connects external circuit, and described the 4th metallic circuit comprises that at least one first metallic pad is exposed in the opening of described protective layer;
One five metals belongs to circuit, be positioned at described protective layer top, and described five metals belongs to circuit and comprises one second metallic pad, described second metallic pad is electrically connected described first metallic pad, the described second metallic pad position is different from the described first metallic pad position, and described second metallic pad comprises that thickness is greater than a first metal layer of 1.5 microns; And
One lead is positioned on described second metallic pad.
12. circuit pack according to claim 11 is characterized in that: described chip connects external circuit and comprises that a chip connects outer driver, and described first metallic circuit connects the output node that described chip connects outer driver.
13. circuit pack according to claim 11 is characterized in that: described chip connect external circuit comprise an electrostatic storage deflection (ESD) protection circuit, a reverse blas diode and a chip connect outer tristate buffer one of them or and the combination.
14. circuit pack according to claim 11 is characterized in that: described internal circuit comprises a NOR gate, one or the door, one with the door, one NAND gate, one sram cell, one DRAM (Dynamic Random Access Memory) unit, one non-volatile memory cell, one flash cell, one Erasable ﹠Programmable ROM unit, one ROM unit, one magnetic RAM unit, one sensing amplifier, one operational amplifier, one adder, one multiplexer, one duplexer, one multiplier, one analog/digital converter, one digital/analog converter, one complementary metal oxide semiconductor, one photodiode, a pair of BiCMOS thing semiconductor, one inverter, one inner drive, one inner receiver, an one inner tristate buffer and a two-carrier circuit unit one of them or and the combination.
15. circuit pack according to claim 11 is characterized in that: described first metallic circuit, described second belongs to circuit and described the 4th metallic circuit comprises an aluminium lamination or the bronze medal layer of thickness between 0.05 micron to 2 microns respectively.
16. circuit pack according to claim 11 is characterized in that: the material that described the 3rd metallic circuit and described five metals belong to circuit comprises gold, copper, silver, platinum, palladium or nickel one of them or and combination respectively.
17. circuit pack according to claim 11 is characterized in that: described the first metal layer comprise a gold medal layer, copper layer, silver layer, platinum layer, palladium layer or the nickel dam of thickness between 1.5 microns to 15 microns one of them or and the combination.
18. circuit pack according to claim 11 is characterized in that: the material of described protective layer comprises a nitrogen silicon compound and an oxygen silicon compound one of them or and combination.
19. circuit pack according to claim 11 is characterized in that: also comprise one first polymeric layer of thickness between 2 microns to 100 microns, and described first polymeric layer is between described protective layer and described the 3rd metallic circuit.
20. circuit pack according to claim 11 is characterized in that: also comprise the second polymer layer of thickness between 2 microns to 100 microns, and described the second polymer layer belongs between the circuit at described protective layer and described five metals.
21. circuit pack according to claim 11 is characterized in that: comprise that also a terpolymer layer is positioned on described the 3rd metallic circuit and described the 4th metallic circuit.
22. circuit pack according to claim 21 is characterized in that: described five metals belongs to circuit and is positioned on the described terpolymer layer.
23. circuit pack according to claim 11 is characterized in that: described siliceous substrate is a silicon base.
24. a circuit pack, it is characterized in that: it comprises:
One internal storage location;
One first internal circuit, and described first internal circuit is made of a metal oxide semiconductor component at least;
Described internal storage location and described first internal circuit are carried in one siliceous substrate;
One first metallic circuit connects described internal storage location;
One second metallic circuit connects described first internal circuit, and described first metallic circuit and described second metallic circuit comprise an aluminium lamination or the bronze medal layer of thickness between 0.05 micron to 2 microns respectively;
One protective layer is positioned on described siliceous substrate, described internal storage location, described first internal circuit, described first metallic circuit and described second metallic circuit;
A plurality of dielectric layers are between described siliceous substrate and described protective layer;
One first polymeric layer is positioned on the described protective layer, and the thickness of described first polymeric layer is between 2 microns to 100 microns; And
One the 3rd metallic circuit; be positioned on the described protective layer; and described the 3rd metallic circuit connects described first metallic circuit and connects described second metallic circuit, and described the 3rd metallic circuit comprises the bronze medal layer of thickness between 3 microns to 20 microns.
25. circuit pack according to claim 24 is characterized in that: but the pattern of described internal storage location comprise a sram cell, a DRAM (Dynamic Random Access Memory) unit, an Erasable ﹠Programmable ROM unit, an electronics cancelling ROM unit, a flash cell, a ROM unit and a magnetic RAM unit one of them or and the combination.
26. circuit pack according to claim 24 is characterized in that: comprise that also a sensing amplifier is between described internal storage location and described first metallic circuit.
27. circuit pack according to claim 26 is characterized in that: comprise that also one second internal circuit is between described sensing amplifier and described first metallic circuit.
28. circuit pack according to claim 27 is characterized in that: described second internal circuit comprises a NOR gate, one or the door, one with the door, one NAND gate, one sensing amplifier, one operational amplifier, one adder, one multiplexer, one duplexer, one multiplier, one analog/digital converter, one digital/analog converter, one complementary metal oxide semiconductor, one photodiode, a pair of BiCMOS thing semiconductor, one inverter, one inner drive, one inner receiver, an one inner tristate buffer and a two-carrier circuit unit one of them or and the combination.
29. circuit pack according to claim 26 is characterized in that: also comprise an inner drive, an inverter, an inner receiver, an internal buffer, an inner tristate buffer, one by circuit or a latch circuit between described sensing amplifier and described first metallic circuit.
30. circuit pack according to claim 24 is characterized in that: described first internal circuit comprises a NOR gate, one or the door, one with the door, one NAND gate, one sensing amplifier, one operational amplifier, one adder, one multiplexer, one duplexer, one multiplier, one analog/digital converter, one digital/analog converter, one complementary metal oxide semiconductor, one photodiode, a pair of BiCMOS thing semiconductor, one inverter, one inner drive, one inner receiver, an one inner tristate buffer and a two-carrier circuit unit one of them or and the combination.。
31. circuit pack according to claim 24 is characterized in that: described siliceous substrate is a silicon base.
32. circuit pack according to claim 24 is characterized in that: described circuit pack is a chip.
33. circuit pack according to claim 24 is characterized in that: the material of described protective layer is one of them or and combination of a nitrogen silicon compound and an oxygen silicon compound.
34. circuit pack according to claim 24 is characterized in that: described the 3rd metallic circuit is positioned on described first polymeric layer.
35. circuit pack according to claim 24 is characterized in that: described second metallic circuit is connected to an output node or an input node of described first internal circuit.
36. circuit pack according to claim 24 is characterized in that: described the 3rd metallic circuit is as a data/address bus or an address bus of described internal storage location, with transmission data signals or address signal.
CN200710003679XA 2007-01-23 2007-01-23 Circuit component Expired - Fee Related CN101231997B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200710003679XA CN101231997B (en) 2007-01-23 2007-01-23 Circuit component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN200710003679XA CN101231997B (en) 2007-01-23 2007-01-23 Circuit component

Publications (2)

Publication Number Publication Date
CN101231997A CN101231997A (en) 2008-07-30
CN101231997B true CN101231997B (en) 2011-02-09

Family

ID=39898330

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200710003679XA Expired - Fee Related CN101231997B (en) 2007-01-23 2007-01-23 Circuit component

Country Status (1)

Country Link
CN (1) CN101231997B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102456898B1 (en) * 2016-03-17 2022-10-19 삼성에스디에스 주식회사 Method and apparatus for generating norm pattern of data signal

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1783474A (en) * 2004-11-30 2006-06-07 联华电子股份有限公司 Integrated circuit structure with switching welding pad set on active circuit top
CN1855514A (en) * 2005-04-18 2006-11-01 海力士半导体有限公司 Non-volatile memory device capable of preventing damage by plasma charge

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1783474A (en) * 2004-11-30 2006-06-07 联华电子股份有限公司 Integrated circuit structure with switching welding pad set on active circuit top
CN1855514A (en) * 2005-04-18 2006-11-01 海力士半导体有限公司 Non-volatile memory device capable of preventing damage by plasma charge

Also Published As

Publication number Publication date
CN101231997A (en) 2008-07-30

Similar Documents

Publication Publication Date Title
CN101231993B (en) Circuit component
CN102379037B (en) Use the integrated circuit (IC) chip of top post-passivation technology and bottom structure technology
US8618580B2 (en) Integrated circuit chips with fine-line metal and over-passivation metal
US8013449B2 (en) Post passivation interconnection schemes on top of the IC chips
CN101231998B (en) Circuit component
US7880304B2 (en) Post passivation interconnection schemes on top of the IC chips
CN101231994B (en) Circuit component
CN101231997B (en) Circuit component
CN101231995B (en) Circuit component
CN101231996B (en) Circuit component
CN101312170B (en) Line component
TWI344686B (en) Circuit component and process for forming the same
CN101312174B (en) Line component
US20090032939A1 (en) Method of forming a stud bump over passivation, and related device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: MEIGETE ACQUIRING CORPORATION

Free format text: FORMER OWNER: MEGICA CORP.

Effective date: 20131202

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20131202

Address after: American California

Patentee after: MEGICA CORP

Address before: Taiwan, China

Patentee before: Megica Corp.

ASS Succession or assignment of patent right

Owner name: QUALCOMM INC.

Free format text: FORMER OWNER: MEIGETE ACQUIRING CORPORATION

Effective date: 20140820

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20140820

Address after: American California

Patentee after: Qualcomm Inc.

Address before: American California

Patentee before: MEGICA CORP

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110209

Termination date: 20160123

EXPY Termination of patent right or utility model