九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體製程領域，特別是有關於一種在半導 體晶圓上形成接_等開口之製程。本伽尤其適合應用在線寬 在65奈米或者45奈米以下之半導體製程。 【先前技術】 隨著積體電路的線寬不斷地縮小，半導體元件的微小化已進 入到深次微米以及奈料級’而單―晶#上的半導體元件的密度 越大表不7G件之間的間隔也就越小，這使得接觸洞的製作越來越 困難。尤其當半導體元件的線寬達到65奈米，甚至45奈米等級 時，要製作出如接觸洞、介層洞與溝渠等開口，特別是高深寬比 (aspectratio)的開口，難度曰益升高。 目前接觸洞餘刻製程多半是利用光阻遮罩法⑽伽—心純 approach)與硬遮罩法(hard mask approach)兩種方式進行。其中，光 阻遮罩法因黃光製程在193奈米光阻上的光學限制，在65奈米線 寬的接觸洞製程’間距(pitch)為180至200奈米之光學限制，只能 給予線上約120奈米的顯影後關鍵尺寸(after devei〇pment critical dimension，ADICD) ’ 並且為 了增加光阻聚焦景深(depth 〇f focus，DOF)的餘裕度，必須將i93奈米光阻的厚度進一步減少及 薄化，但也因此造成後續蝕刻時的難度。此外，習知的光阻遮罩 法仍然存有標準波(standard wave)以及碗形輪廓(bowling profile)等 1343091 缺點。 ，硬縣㈣騎使用金屬或金屬合金作為_硬遮 增加製程频雜。除了必财量硬鮮本身的材 貝疋否耐_以外’硬遮罩在沈積時是否影響前層，例如，對已 喊7化錄金屬層之元件而言，其後續硬遮罩在沈積時的溫度 H二^過_ C ’以及在_後剩下的硬遮罩層是否容易去除 荨等，都是必須額外考慮的因素。 由此可知，f知技藝職觸_方法財諸多缺點待 改善’該技術領域特別需要一種改良的接觸洞製作方法，其可以 避免使用到金屬硬遮罩，同時達到所要_刻後_尺寸(a細 etch mspect critical dimensi〇n，細即以及接觸洞輪廊。 .【發明内容】 以解決上 鲁 本發明之主要目的在提供一種改良之接觸洞製程， 述習知技藝之問題。 根據本發明之較佳實施例，本發明披露一種接觸洞製程。首 先，提供—轉體基底’其上具有至少-導電d域；於該半導體 基底以及該導電區域上沈積—介電層；接著，於該介電層上塗佈 一蝕刻抵擋層；於該蝕刻抵播層上塗佈一含矽硬遮罩及抗反射 (SHB)層；接著，於該SHB層上塗佈一光阻層；隨後，進行一微 8 1343091 影製程，於該光阻層t形成一第一開口，其具有一顯影後關鍵尺 寸(ADICD);再利用該光阻層作為一蝕刻遮罩，經由該第一開口蝕 刻該SHB層，以於該SHB層中形成一具有漸縮傾斜側壁之第二 開口’其底部具有一蝕刻後關鍵尺寸(A^CD)，且該约為 該ADICD的40%至80% ;然後，分別利用該SHB層以及該蝕刻 抵檔層做為綱鮮，經由該第二開口蝴絲龜騎以及該 介電層，以於該介電層中形成一接觸洞，暴露出部分的該導電區 域0 根據本發明之另-較佳實施例，本發明披露一種接觸洞製 程。首先’提供-半導體基底，其上具有至少一導電區域，接著， 於該料體基底以及該導電區域上沈積一介電層，接著，於該介 電層上塗佈-下層綠層；烘烤固化該下層光阻層，接著，於該 下詹光阻層上塗佈一含石夕硬遮罩及抗反射(shb)層，接著，於該 SHB層上塗佈—上層光阻層，該上層光阻層的厚度小於該下層光 阻料厚度’接著，進行—微影製程，於該上層光阻層f形成一 第一開口’接著’ _該上層光阻層作為—侧遮罩，經由該第 :=該SHB層’以於該SHB層恤一具有漸縮傾斜側 ^刻遮罩二由^ ^利用該層以及該下層光阻層做為 於該介電乂^ 侧該下層光阻層以及該介電層，以 、 g >成—接細’暴露出部分的該導電區域。 根據本發明之另—較佳實施例，本發明披露-種接觸洞製 i 1343091 -程’首先’提供一半導體基底，其上具有至少-導電區域，接著， 於該半導體基底以及該導電區域上沈積-侧停止層，接著，於 該侧停止層上沈積-介電層；於該介電層上塗饰一下層光阻 層，接著’烘烤固化該下層光阻層；於該下層光阻層上塗佈—含 微遮罩及抗反射(SHB)層；於該SHB層上塗佈—上層光阻層， 該上層光阻層的厚度小於該τ層光阻層的厚度，接著，進行—微 影製程’於該上層光阻層中形成一第一開口，接著，利 籲*阻層作為-餘刻遮罩，經由該第一開口敍刻該刪層，以於^ SHB層中形成—具有漸細斜罐之第二開口，接著，分別利用 該SHB層以及該下層光阻層做為_遮罩，經由該第二開口姓刻 該下層光阻層以及該介電層，以於該介電層令形成一接觸洞，暴 露出部分的該侧停止層，接著，經由該接觸纖除舰刻停止 層’暴露出部分的該導電區域。 —為了使胃審查委員月巨更進一步了解本發明之特徵及技術内 谷’請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考與輔麟日賴，並_鱗本_純限制者。 【實施方式】 曾μ參閱第1圖至第5圖，其繪示的是本發明較佳實施例在半 ¥體晶圓上形成接觸洞等開口之剖面示意圖。如第丨騎示，提 /、半‘體曰曰圓1 ’其上具有—底層(baselaye_，在底声1〇上 具有—導電區域12，其中底層10可以是-半導體基底^如，石夕 基底、石夕錯(SiGe)半導體基底、石夕覆絕緣(silicon-on-insulator, SOI) 基底等等，此時’導電區域12可以是一電性推·雜區域，例如，金 氧半導體(metal-oxide-semiconductor，MOS)電晶體元件的源極/沒 極摻雜區域(source/drain doping region)。 此外’底層10亦可以是一層間介電(inter-layer dielectric，ILD) 層’例如’摻雜石夕玻璃(doped silicate glass)、二氧化妙或者低介電 常數(low-dielectric constant)材料等等，此時，導電區域12可以是 一下層金屬内連線(lower metal interconnection)，例如，以镶後 (damascene)製程包覆形成在底層丨〇内的銅導線。若導電區域12 是以鑲嵌製程形成在介電層中的銅金屬，則通常在介電層與銅金 屬之間還會有一阻障層，用來避免銅的擴散，但此阻障層並未繪 示在圖中。 在底層10與導電區域12的表面上，覆蓋有一介電層14，其 可以是摻雜矽玻璃、二氧化矽或者低介電常數材料等等，形成方 式可以利用化學氣相沈積(chemical vap〇r d印〇siti〇n，C奶)法或者 旋轉塗佈(spin-〇n coating，SOC)法等等。 如第2圖所示，接著在介電層14上形成一钱刻抵撞層16，例 如n〇V〇laC型酚醛樹脂(novo丨acresin)或者類似i_line光阻等材料， 其厚度約為⑽埃(angstlOm)J_ 3_埃，較佳則為聊埃左右。 右以1 lme植為例，其形成方式仙—般光阻塗佈程序，塗佈在 1343091 介電層14上，然後再加以供烤固化β 接著，在蝕刻抵擋層16上形成一含矽硬遮罩及抗反射 (Silicon-containing Hard-mask Bottom anti-reflection coating, SHB) 層18 ’其成为為含石夕之有機南分子聚合物(〇rgan〇siiic〇np〇iymer) 或水珍物(polysilane) ’至少具有一發色基團gr0Up)以 及一交聯基團((^0381丨111^16运1*0叩），如第8圖所示，其具有的矽含 量(silicon content)約介於重量百分比5%至30%，較佳則介於15% 至25/ί>之間，此外，其成分中亦可以含有交聯劑(cr〇ssiinking agent)，使SHB層18在照光後可產生交聯反應。 根據本發明之較佳實施例’ SHB層18具有可藉由矽含量的調 整而獲得不同耐蝕刻能力之特性，並且在微影製程中能夠展現良 好的抗反射性。換言之，本發明將其用來作為形成在光阻層底下 的抗反射層，同時，藉由調整其矽含量，與下方的蝕刻抵擋層16 φ 之間產生較高的钮刻選擇比(etching selectivity)。 根據本發明之較佳實施例，SHB層18的矽含量介於15%至 25%之間，而其厚度則介於15〇埃至11〇〇埃之間較佳為8〇〇埃 左右。根據本發明之較佳實施例，SHB層18係以旋轉塗佈(spirW)n) 方式形成在敍刻抵擒層16上，因此不會影響到前層，例如，已形 成有矽化鎳金屬層之元件. 12 1343091 根據本發明之·實關，在完成前述之塗佈後，可以再進 行-供烤製程，將溶劑趕走。此外，前述之侧抵撞層16在塗佈 後.亦可以先不進行烘烤，而是待SHB们8塗佈完成後才 進行烘烤的動作。 在形成SHB層18之後，接著於舰層18上塗佈一光阻層 20。根據本發明之較佳實施例，光阻層2〇為—光阻或者^奈 米光阻，據本發明，光阻層2〇的厚度不需要太厚，因為光阻層 2〇其主要魏是在將其_以乾_方式娜至下方咖声^ 時，作為-乾_鮮。根縣㈣之齡實施例，光阻層％的 厚度僅而要600埃至2200埃之間，較佳約為15〇〇埃左右。她 於過去動軏需要3則埃以上的厚度因此本發明可以在黃光微影 製程中獲得較大賴程餘裕度，也能獲得較為鮮_案轉移結 =據本毛明之較佳實施例，光阻層2〇的厚度小於侧抵擒層 的尽度。根據本發明之較佳實_，㈣層Μ触刻抵擔層 之間具有高餘刻選擇比。 .圖所π接著進行一微影製程，利用曝光、顯影等步 ^ ^阻層20中形成—開口 22’定義出最終欲形成在下方介電 ^的接觸洞位置與形狀。開口 22暴露出部分的咖層18 、、面’且具有-尺寸(atodevelGpmentinspeetcriticai 13 1343091 dimension，ADICD)，例如，65 奈米。 接著，如第4圖所示，利用光阻層20作為一蝕刻遮罩，進行 一乾侧f程，綱σ 22所定義的接細圖案經由侧轉移至下 方的SHB層18中，形成開口 28，暴露出部分的侧抵播層16的 表面。根據本發明讀佳實酬，上職糊製針所使用的餘 刻氣體至少包含有全氟甲院(tetraflu〇r〇methane，CFj氣體以及一含 氫的氟烷氣體，例如，三氟甲離ifl_methanes eKp3)。 舉例來說’利用CF4/CHF3的钱刻條件如下：壓力約為8〇毫 托耳_如_ 150毫托耳，較佳為12〇毫托耳，功率約為5〇〇 瓦特至600瓦特之間，通入的Cf4氣體流量約為2〇〇至標準 立方毫米每分鐘(sccm)，較佳為2〇〇 sccm ’咖3氣體流量則約為 5至30標準立方絲每分鐘(_)，較佳為μ _，侧時間約 為30秒至1〇〇秒之間，較佳為35秒左右。 根據本發明之較佳實施例，上述含氫的氣烧氣體亦可以是 CHxFy ’ 其中，x=卜 2、3 ; 卜 2、3。 本毛月係刻思將含氫的氟烧氣體，例如，三氣甲烧(⑶⑸， 加入钱刻氣體成分中’其用意在使_下方的遞層·程中， 營造出能夠同時產生高分子沈積的_環境，如此-來，可以在 SHB層18中蝴出如第4圖中所示的具有漸縮傾斜㈣㈣側壁 1343091 - 的開口 28，其中開口 28的底部具有一小於開口 22的顯影後關鍵 尺寸之餘刻後關鍵尺寸(after etch inspect critical dimension, AEICD)，例如，45奈米。 根據本發明’開口 28的蝕刻後關鍵尺寸(AEICD)約為開口 22 的顯影後關鍵尺寸(ADICD)的40%至80%左右(亦即，縮小率可達 到20%至60%左右）。 此外，值得一提的是，若是使用不含氫的氟烧氣體，例如， C々F6氣體’混合全氟甲烷(CFO氣體，作為钮刻氣體成分，則吾人 發現在钮刻SHB層18過程中會有較嚴重的側蝕問題，而容易在 接觸洞較密集處導致相鄰接觸洞的橋接(bridging)現象，因此並不 適合。 如第5圖所示，接著利用SHB層18作為乾蝕刻遮罩，進行 • 一乾姓刻製程，經由開口 28非等向性乾餘刻蝕刻抵擋層16，且在 SHB層18消耗殆盡，將開口 28所定義的接觸洞圖案轉移至蝕刻 抵擋層16後，繼續以蝕刻抵擋層16作為乾蝕刻遮罩蝕刻介電層 Η，在介電層14中形成接觸洞34，其尺寸大小即約略等於開口 28的底部之姓刻後關鍵尺寸(AEICD)，例如，45奈米。接觸洞％ 暴露出部分的導電區域12的表面。 根據本發明之較佳實施例，接觸洞34的尺寸縮小率至少為開 15 1343091 口 22的顯影後關鍵尺寸的2〇%以上，甚至可達3〇%至仞％。 剞述乾餘刻钱刻抵擔層16的钱刻條件如下：屢力約為1〇毫 托耳㈣脇汀），功率約為7〇〇瓦特至3〇〇瓦特之間通入的氣= 為C0/02/N2，流量分別為薦〇/2〇〇 _，钱刻時間 左右。 請參閱第6圖及第7圖，歸補是本發明另—較佳實施例 的剖面不意圖。如第6圖所示’根據本發明另—較佳實施例，在 底層10與導電區域12的表面上，先覆財—接觸醜刻停止層 (contact etchmg stop layer, CESL)13 , M o ^ 同、浙止層13可以疋氮化石夕(SlN)所構成’但不限於此，其厚度 约為400埃至15〇〇埃之間。 此實施例㈣面步猶第1圖至第4_ 接觸洞侧停止層13的有I U做 刹田糧。 名…、根據本發明另一較佳實施例’同樣 利用SHB層18作為乾軸,】 〜w (早3^仃乾侧製程，經由開口 非柏錄__峨16，料 開口 28所定義的接觸洞 祕W將 翁婦μ ^ 轉移刻抵擋層16後，繼續以蝕 刻抵擒層I6料乾_縣 接觸洞34，她部分電 電層14中形成 平路刀的接觸洞餘刻停止I 13的表面。 如第7圖所示，隨後里q • 另一蝕刻製程，經由接觸洞34蝕刻 12 掉暴露出來的接觸_刻停止層13，暴露出下方的導電區域 請專利範 .範圍 _====犧細，財 ^寺I化與修傅，皆應屬本發明之涵蓋 【圖式簡單說明】 第1圖至第5 _示的是本發明較佳實施例在 .接觸洞等開口之剖面示意圖。 體曰曰®上形成 =圖及第7 ®料的是本發㈣—較佳實施例 第8圖繪示的是含奴有機高分子聚合物或聚飾之示意圖圖其 具有發色基團(chromophore group)以及—交聯基團 (crosslinkable group) 〇 【主要元件符號說明】IX. Description of the Invention: [Technical Field] The present invention relates to the field of semiconductor manufacturing, and more particularly to a process for forming an opening such as a via on a semiconductor wafer. Benga is especially suitable for semiconductor applications with a line width of 65 nm or less. [Prior Art] As the line width of the integrated circuit is continuously reduced, the miniaturization of the semiconductor element has entered the deep sub-micron and the nano-level] and the density of the semiconductor element on the single-crystal # is greater than that of the 7G piece. The smaller the interval between them, the more difficult it is to make contact holes. Especially when the line width of the semiconductor element reaches 65 nm or even 45 nm, openings such as contact holes, via holes and trenches, especially high aspect ratio openings, are made, and the difficulty is increased. . At present, the contact hole engraving process is mostly performed by the photoresist mask method (10) and the hard mask approach. Among them, the photoresist mask method is limited by the optical limitation of the yellow light process on the 193 nm photoresist, and the pitch of the 65 nm line width contact hole process is 180 to 200 nm, which can only be given to the line. After about 120 nm of the after devei〇pment critical dimension (ADICD)' and in order to increase the margin of depth 〇f focus (DOF), the thickness of the i93 nm photoresist must be further reduced. Thinning, but also causes difficulty in subsequent etching. In addition, the conventional photoresist mask method still has the disadvantages of standard wave and bowling profile 1343091. , Hard County (four) riding using metal or metal alloy as _ hard cover to increase the frequency of the process. In addition to the amount of hard food itself, whether it is resistant or not, does the hard mask affect the front layer when it is deposited, for example, for a component that has been called a metal layer, the subsequent hard mask is deposited. The temperature H 2 ^ _ C ' and whether the hard mask layer remaining after _ is easy to remove 荨, etc., are all factors that must be considered. It can be seen that there are many shortcomings to be improved in the technical skill of the art. The technical field particularly needs an improved contact hole manufacturing method, which can avoid the use of a metal hard mask while achieving the desired size. Fine etch mspect critical dimensi〇n, fine and contact hole porch. [SUMMARY OF THE INVENTION] The main purpose of the invention is to provide an improved contact hole process, and to solve the problems of the art. In a preferred embodiment, the present invention discloses a contact hole process. First, a turn-on substrate is provided having at least a conductive d-domain thereon; and a dielectric layer is deposited on the semiconductor substrate and the conductive region; Coating an etch resist layer on the electric layer; coating a ruthenium-containing hard mask and an anti-reflection (SHB) layer on the etch-receiving layer; and then coating a photoresist layer on the SHB layer; subsequently, performing a micro 8 1343091 shadow process, forming a first opening in the photoresist layer t, having a developed critical dimension (ADICD); and using the photoresist layer as an etch mask, etching the SHB through the first opening Floor Forming a second opening having a tapered inclined sidewall in the SHB layer, the bottom having an etched critical dimension (A^CD), and the amount is about 40% to 80% of the ADICD; and then utilizing the The SHB layer and the etching resist layer are as an outline, and the contact hole is formed in the dielectric layer via the second opening butterfly and the dielectric layer to expose a portion of the conductive region. In another preferred embodiment of the invention, the present invention discloses a contact hole process, which first provides a semiconductor substrate having at least one conductive region thereon, and then depositing a dielectric layer on the substrate substrate and the conductive region. Next, coating a lower green layer on the dielectric layer; baking and curing the lower photoresist layer, and then coating a lower surface of the lower resist layer with an anti-reflective (shb) layer, and then Applying an upper photoresist layer on the SHB layer, the upper photoresist layer having a thickness smaller than the thickness of the lower photoresist layer. Then, performing a lithography process to form a first opening in the upper photoresist layer f Then ' _ the upper photoresist layer acts as a side mask, via The:: the SHB layer is such that the SHB layer has a tapered tilted side mask, and the lower photoresist layer is used as the lower layer of the photoresist layer. And the dielectric layer, g > into a thin portion to expose a portion of the conductive region. According to another preferred embodiment of the present invention, the present invention discloses a contact hole system i 1343091 - "first" Providing a semiconductor substrate having at least a conductive region thereon, and then depositing a side stop layer on the semiconductor substrate and the conductive region, and then depositing a dielectric layer on the side stop layer; coating the dielectric layer Laminating a layer of photoresist layer, then 'baking and curing the underlying photoresist layer; coating the underlying photoresist layer with a micro-mask and anti-reflection (SHB) layer; coating the upper layer of light on the SHB layer a resist layer, the thickness of the upper photoresist layer being less than the thickness of the photoresist layer of the τ layer, and then performing a lithography process to form a first opening in the upper photoresist layer, and then, the resist layer is used as a mask that is engraved through the first opening to form a layer in the SHB layer a second opening of the oblique can, and then using the SHB layer and the lower photoresist layer as a mask, respectively, the lower photoresist layer and the dielectric layer are pasted through the second opening to serve the dielectric layer A contact hole is formed to expose a portion of the side stop layer, and then the portion of the conductive region is exposed through the contact fiber stop layer. - For a more detailed understanding of the features and technical aspects of the present invention, please refer to the following detailed description of the invention and the accompanying drawings. However, the drawings are for reference only and are supported by Fu Lin Ri Lai, and _ scales _ pure limit. [Embodiment] Referring to Figures 1 to 5, there is shown a schematic cross-sectional view showing an opening such as a contact hole formed on a half-wafer wafer in accordance with a preferred embodiment of the present invention. For example, the third 曰曰 示 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Substrate, SiGe semiconductor substrate, silicon-on-insulator (SOI) substrate, etc., at this time, the conductive region 12 may be an electrically conductive/doped region, for example, a metal oxide semiconductor ( Metal-oxide-semiconductor, MOS) source/drain doping region. In addition, 'underlayer 10 can also be an inter-layer dielectric (ILD) layer'. 'Doped silicate glass, low-dielectric constant or low-dielectric constant material, etc., at this time, the conductive region 12 may be a lower metal interconnection. For example, a copper wire formed in the underlying germanium is covered by a damascene process. If the conductive region 12 is a copper metal formed in a dielectric layer by a damascene process, usually between the dielectric layer and the copper metal. There will also be a barrier layer to avoid copper Diffusion, but the barrier layer is not shown in the figure. On the surface of the bottom layer 10 and the conductive region 12, a dielectric layer 14 is covered, which may be doped bismuth glass, germanium dioxide or a low dielectric constant material. Etc., the formation can be by chemical vapor deposition (chemical vap〇rd printing siti〇n, C milk) method or spin-coated coating (SOC) method, etc. As shown in Figure 2, Then, a dielectric layer 16 is formed on the dielectric layer 14, such as n〇V〇laC type phenolic resin (novo丨acresin) or a material similar to i_line photoresist, and has a thickness of about (10) angstroms (angstlOm) J_3_埃, preferably about 聊埃. Right 1 lme plant as an example, its formation method is a general-like photoresist coating process, coated on the 1341091 dielectric layer 14, and then baked for curing β, then, after etching A resistive layer 16 is formed with a layer of 18-'s hard-containing hard-mask Bottom anti-reflection coating (SHB), which is an organic south molecular polymer containing 石rgan〇siiic〇 Np〇iymer) or polysilane (at least one chromophore gr0Up) and one The joint group ((^0381丨111^16运1*0叩), as shown in Fig. 8, has a silicon content of about 5% to 30% by weight, preferably 15 Between % and 25/ί>, in addition, a crosslinking agent (cr〇ssiinking agent) may be contained in the composition to cause the SHB layer 18 to generate a crosslinking reaction after illumination. According to a preferred embodiment of the present invention, the SHB layer 18 has characteristics which can be obtained by adjusting the germanium content to obtain different etching resistance, and can exhibit good antireflection in the lithography process. In other words, the present invention is used as an anti-reflection layer formed under the photoresist layer, and at the same time, by adjusting the germanium content, a higher button selection ratio is generated between the underlying etching resist layer 16 φ (etching selectivity). ). In accordance with a preferred embodiment of the present invention, the SHB layer 18 has a germanium content of between 15% and 25%, and a thickness of between 15 and 11 angstroms, preferably about 8 angstroms. According to a preferred embodiment of the present invention, the SHB layer 18 is formed on the etched resist layer 16 in a spin coating manner, so that the front layer is not affected, for example, a nickel metallization layer has been formed. 12 1343091 According to the present invention, after the completion of the aforementioned coating, the baking process can be further carried out to drive off the solvent. Further, the side impact layer 16 may not be baked first after coating, but may be baked after the SHB 8 is applied. After forming the SHB layer 18, a photoresist layer 20 is then applied over the ship layer 18. According to a preferred embodiment of the present invention, the photoresist layer 2 is a photoresist or a photoresist. According to the present invention, the thickness of the photoresist layer 2〇 does not need to be too thick, because the photoresist layer 2 is mainly When it is _ dry _ way Na to the bottom of the coffee ^, as - dry _ fresh. In the embodiment of the age of the county (four), the thickness of the photoresist layer is only about 600 angstroms to 2,200 angstroms, preferably about 15 angstroms. In the past, she needed a thickness of more than 3 angstroms. Therefore, the present invention can obtain a larger margin in the yellow lithography process, and can also obtain a relatively small transfer junction. According to the preferred embodiment of the present invention, the photoresist The thickness of the layer 2 turns is less than the thickness of the side abutting layer. According to a preferred embodiment of the present invention, the (four) layer has a high residual selection ratio between the etched layers. The π is then subjected to a lithography process, and the formation/opening 22' in the resist layer 20 is defined by exposure, development, etc., to define the position and shape of the contact hole which is finally formed under the dielectric. The opening 22 exposes a portion of the coffee layer 18, face' and has a size (atodevelGpmentinspeetcriticai 13 1343091 dimension, ADICD), for example, 65 nm. Next, as shown in FIG. 4, the photoresist layer 20 is used as an etch mask to perform a dry side f path, and the fine pattern defined by the σ 22 is transferred to the lower SHB layer 18 via the side to form an opening 28, A portion of the surface of the side anchor layer 16 is exposed. According to the present invention, the residual gas used in the upper-level paste needle includes at least a tetrafluoromethane (CFj gas and a hydrogen-containing halothane gas, for example, trifluoromethane Ifl_methanes eKp3). For example, the cost of using CF4/CHF3 is as follows: the pressure is about 8 〇 mTorr _ such as _ 150 mTorr, preferably 12 〇 mTorr, and the power is about 5 watts to 600 watts. The flow rate of the Cf4 gas introduced is about 2 〇〇 to standard cubic millimeters per minute (sccm), preferably 2 〇〇 sccm 'the flow rate of the coffee 3 is about 5 to 30 standard cubic meters per minute (_), Preferably, μ _, the side time is between about 30 seconds and 1 second, preferably about 35 seconds. According to a preferred embodiment of the present invention, the hydrogen-containing gas-burning gas may also be CHxFy' wherein x = b 2, 3; This Maoyue is thinking about the hydrogen-containing fluoro-burning gas, for example, three-gas-fired ((3)(5), added to the gas-injected gas component'), which is intended to create a polymer that can simultaneously produce a polymer in the lower layer. The deposited environment can, as such, be exposed in the SHB layer 18 with an opening 28 having a tapered oblique (four) (four) sidewall 1343091 - as shown in FIG. 4, wherein the bottom of the opening 28 has a smaller opening than the opening 22 After etch inspect critical dimension (AEICD), for example, 45 nm. The post-etch critical dimension (AEICD) of opening 28 is approximately the post-development critical dimension of opening 22 (ADICD) in accordance with the present invention. 40% to 80% (that is, the reduction rate can reach 20% to 60%). In addition, it is worth mentioning that if you use a fluorine-free gas that does not contain hydrogen, for example, C々F6 gas 'mixed all Fluoromethane (CFO gas, as a gas component of the button engraving, we found that there is a serious side erosion problem in the process of buttoning the SHB layer 18, and it is easy to cause bridging of adjacent contact holes in denser contact holes. Phenomenon, so it is not suitable. As shown in FIG. 5, the SHB layer 18 is then used as a dry etching mask to perform an etching process, and the resist layer 16 is etched through the opening 28, and the SHB layer 18 is exhausted. After the contact hole pattern defined by 28 is transferred to the etch resist layer 16, the etch resist layer 16 is further used as a dry etch mask to etch the dielectric layer Η, and a contact hole 34 is formed in the dielectric layer 14, the size of which is approximately equal to the opening. The bottom of the 28 is the inscribed key dimension (AEICD), for example, 45 nm. The contact hole % exposes a portion of the surface of the conductive region 12. According to a preferred embodiment of the present invention, the contact hole 34 has a size reduction ratio of at least Open 15 1343091 Port 22 after development of the critical size of 2% or more, or even up to 3〇% to 仞%. The description of the dry engraved money engraved layer 16 of the money engraving conditions are as follows: repeated force is about 1 〇 Torre (four) vaso), the power between the power of about 7 watts to 3 watts = C0/02 / N2, the flow is recommended 〇 / 2 〇〇 _, the money is about time. Referring to Figures 6 and 7, the addition is a cross-sectional view of another preferred embodiment of the present invention. As shown in FIG. 6 'according to another preferred embodiment of the present invention, on the surface of the underlayer 10 and the conductive region 12, the contact etchmg stop layer (CESL) 13 , M o ^ The same, the Zhejiang stop layer 13 can be formed by 疋 夕 夕 (SlN) 'but not limited thereto, the thickness is between 400 angstroms and 15 angstroms. This embodiment (four) face step 1 to 4_ contact The IU side stop layer 13 has IU for the brake field. Name..., according to another preferred embodiment of the present invention, 'the SHB layer 18 is also used as the dry axis, 】~w (early 3^仃 dry side process, defined by the opening non-Bai recorded __峨16, material opening 28 The contact hole secret W is transferred to the barrier layer 16 and continues to etch the layer I6 to dry the _ county contact hole 34. The contact hole of the partial electric galvanic layer 14 forming a flat knives stops I 13 The surface is as shown in Fig. 7, and then another etching process is etched through the contact hole 34 to remove the exposed contact etch stop layer 13 to expose the conductive region below. Patent range. _=== = sacrifice fine, Cai ^ Temple I and repair, are all covered by the present invention [Simple description of the drawings] Figures 1 to 5 show the preferred embodiment of the present invention in the opening of the contact hole and other sections Schematic diagram of the formation of the body = 图 第 第 第 第 第 第 第 第 第 第 第 — — — — — — — — — — — — — — — — — — — — — 示意图 示意图 示意图 示意图 示意图 示意图 示意图 示意图Chromophore group and crosslinkable group 〇 [Main component symbol description]
1 半導體晶圓 10 12 導電區域 13 14 介電層 16 18 含梦硬遮罩層 20 22 開口 28 34 接觸洞 底層 接觸洞钱刻停止層 钱刻抵撞層 光阻層 開口1 Semiconductor wafer 10 12 Conductive area 13 14 Dielectric layer 16 18 Dream hard mask layer 20 22 Opening 28 34 Contact hole Bottom layer Contact hole money stop layer Money engraved layer Photoresist layer Opening