16〇l〇twf.doc/r 九、發明說明： 【發明所屬之技術領域】 且特別是有關於一種 本發明是有關於一種驅動裝置 掃描驅動的裝置。 、 【先前技術】 液晶顯示器由於具傷了輕 電磁干擾的優點，而大量應 二無輻射以及低 數位個人助理(PDA)、數位_仃筆記型電腦、 產品。加上#界積極投人研^， 痛等各式電子 提升。 X使液日日颂示器的品質不斷 A匈白天口欣曰日顯示器 ^ 了時序控制器〗〇2、掃描驅動哭=考圖1，其包括 門邛又包括多數條閘極線ΠΟ 線112用以傳輸影像訊號，以及 構去由，線110與源極線112所環繞之區域所 包括τ薄膜電晶體114用以根據掃 描戒5虎以及傳輸影像訊號來驅動液晶。 圖2為白知用於液晶螢幕掃描驅動器、1〇4部分之電 請參見圖2,其包括了五個反相邏輯閘分別為圖中的 〇 202、204、206以及208，還包括了兩個傳輸閘21〇 與212以及兩個反或邏輯閘214與216所組成，在圖中， 又才示上了郎點Α、Β、C、D、Ε、F，而掃描驅動器則是用 許多圖2的電路串接而成。 圖3為圖2電路之操作波形’請同時參照圖；2以及圖 首先^起始訊號STV拉南之後，即表示一張畫面要 1338272 16010twf.doc/r 開始了，由於起始訊號STV拉高，使得反或邏輯閘214輸 出節點A低電位，造成傳輸閘21〇導通，此時掃描訊號 ckv也會跟著開始送出高電位，通過傳輸閉21〇，節點= 電位也會跟著拉高，節點B電位經過反相邏輯閘挪以及 ^6造成了一一些延遲達到節點c，使的節點c也會高電位。 節點〒的高電位傳送到下一級的反或邏輯閘加，造成反 或邏輯閑216輸出節點D的低電位，使得傳 r傳輸通’節以接收到掃描訊號二 IΪ it由反相邏制雇，使得節點F持續維持低電位。 而第條閘極線的掃描線則由c節點送出。 _ Ϊ : ::: Γ及即點D跟著掃描訊號c κ ν變為低電位， 以及的傳二， 由於節= 閘極線的掃描線停止掃描。然而， 遲，'節财變^^^反相_問識的傳輸延 節點D持續使得反或邏輯聞2】6輸出 當使得傳輸㈣2持續導通。 持續導通，節點^著電位時’由於傳輸閘212 的wi二以^經過-個反相邏輯閘 二條閘極線的掃描气歸心耆’定為低電位，此時’第 于即點D南電位，使傳輸閘212截止。 1601 Otwf.doc/r d而’此義構必彡貞要兩·個移位暫存器成-對，且其 弟固移位暫存器具有偶數個反相器2〇4與2〇6，第二 固=暫存器具有奇數個反相器规，當只需要單數條掃 田、：吋’例⑹手機與個人數位助S PDA的螢幕設計 ，此時 元件’或是佔用到非顯示區域的空間。 g本毛明的目的就是在提供—種平面顯示器及其使用 ，掃描驅動u ’用以降低掃描驅動電路設計複雜度，節 省晶片或面板佈局空間。 本毛明的另-目的是在提供一種平面顯示器及其使用 的掃描驅練置，藉由__雛岐相n組合成的移 位暫存串接成電路的—部份，減少如習知技術般在 需要單數轉位暫存器時所產生的元件浪費。 本發明提出-種平面顯示器，其包括掃描驅練置盘 顯不面板，此掃描驅動裝置包含多個内部架構相同的移位 暫存器，且核㈣純暫存器職收的輸人時脈信號盘 偶數級的移位暫存器所接㈣輪人時脈信號互為反相。' 本發明提出-種掃描驅動裝置，其包括N個移位暫存 器'。其中，每一個移位暫存器包括輸入節點、輸出節點、 邏輯閉、《元件以及反麵制組。邏油包括第 入端、第二輸人端以及第-輪出端，其第—輸人端耗接二 巧入節點’其第二輸入端耦接該輪出節點。開關元件包括 弟-端以及第H1關it件接收邏輯間的第一輸出端 輸出訊號，決定是否導通其第—端與第ϋ的電路。 160 lOtwf.doc/r 160 lOtwf.doc/r ‘端，其輸出端耦接輸出節點，其中，N為自然 第N-1個移位 ==包?輸入端以及輪出端 ’其輸入端耦接開關 位暫存器之該輸入節點耦接 始訊號，第奇數個丄1暫存之輸入節點接收起 描訊號，第偶數彻#矛鳊筏收知 ㈣_移位暫存器之卩箱元件的第 描汛號之反相訊號。 ψ 一本發明因採用單—架構的移位暫存器，因此除了可以 二。十成驅動單數條掃描線的，動器而*造成 外，也:減低晶片或面板佈局複雜度。 為讓本發明之±述和其他目的、雜和優點能更明顯 2下下文特舉較佳實施例’並配合所附圖式’作詳細說 【實施方式】 在本發明一貫施例中所使用的掃描驅動裝置的内 電路方f關示如圖4Α。另外，在本發明-實施例中使^ 圖4Α掃描驅動裝置所驅動的平面顯示器績示如圖4Β。在 此實施例中，包括個移位暫存器SRJ〜SR—Ν，每— 個f位暫存器包括輸入節點node」、輸出節點⑽de〜〇、反 及邏輯閘NAND、開關元件sw以及反相邏輯閘糊、 INV2以^請3。其中，起始訊號STV輸人至移㈣存器 YR】，第奇數位的移位暫存器(例如SR1、SR3)接收掃描: 说CKV ’第偶數位的移位暫存器（例如SR2、SR4)接 描§fl號CKV的反相訊號。 16010twf.d〇c/r 16010twf.d〇c/rBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for scanning drive of a driving device. [Prior Art] Due to the advantages of light electromagnetic interference, LCD monitors have a large number of radiation-free and low-digit personal assistants (PDAs), digital _仃 notebook computers, and products. In addition, #界 actively invests in research, pain and other electronic upgrades. X makes the quality of the liquid daily display constantly A Hunghe daytime mouth Xinyi day display ^ Timing controller〗 〇 2, scan drive cry = test figure 1, which includes the threshold and includes a number of gate lines 112 112 For transmitting the image signal, and constituting the region surrounded by the line 110 and the source line 112, the τ thin film transistor 114 is used to drive the liquid crystal according to the scan ring and the image signal. 2 is a schematic diagram of the power for the liquid crystal screen scanning driver, and the power of the 〇4 portion is shown in FIG. 2, which includes five inverted logic gates, namely 〇202, 204, 206, and 208 in the figure, and two The transmission gates 21〇 and 212 and the two reverse or logic gates 214 and 216 are formed. In the figure, the points are 郎, Β, C, D, Ε, F, and the scan driver is used by many. The circuit of Figure 2 is connected in series. Figure 3 is the operation waveform of the circuit of Figure 2, please refer to the figure at the same time; 2 and the picture first, after the start signal STV is pulled south, it means that a picture should be 1338272 16010twf.doc/r, starting from the start signal STV Therefore, the reverse logic gate 214 outputs a low potential of the node A, causing the transmission gate 21 to be turned on. At this time, the scanning signal ckv will also start to send a high potential, and after the transmission is closed, the node = potential will also be pulled up, node B. The potential is inverted by the inverting logic gate and ^6 causes some delay to reach node c, so that node c will also be high. The high potential of the node 传送 is transferred to the next stage of the inverse or logic gate plus, causing the reverse or logic idle 216 to output the low potential of the node D, so that the transmission is transmitted to the section to receive the scan signal II. It is employed by the reverse logic. So that node F continues to maintain a low potential. The scan line of the first gate line is sent by the c node. _ Ϊ : ::: Γ and point D follows the scan signal c κ ν becomes low, and the second pass, because the scan line of the node = gate line stops scanning. However, late, 'savings change ^^^inverted_information of the transmission delay node D continues to make the inverse or logic smell 2] 6 output when the transmission (four) 2 is continuously turned on. Continuous conduction, when the node is at the potential 'Because the Wi 2 of the transmission gate 212 passes through the scanning gas of the two gates of the inverting logic gate, it is set to a low potential, and at this time, the first point is D. , the transfer gate 212 is turned off. 1601 Otwf.doc/rd and 'this structure must have two shift registers into pairs, and its younger shift register has an even number of inverters 2〇4 and 2〇6, The second solid = register has an odd number of inverter gauges. When only a single sweep is required, the screen design of the 吋 'example (6) mobile phone and the personal digital assistant S PDA, the component 'is occupied by the non-display area. Space. The purpose of g Maoming is to provide a flat panel display and its use. The scan driver u ’ is used to reduce the complexity of the scan driver circuit design and save space for wafer or panel layout. The other purpose of the present invention is to provide a flat-panel display and a scanning and squeezing device thereof, which is reduced in conventional parts by a combination of __ 岐 岐 n n n Technically, the component waste generated when a singular index register is required. The invention provides a flat panel display, which comprises a scanning and arranging disk display panel. The scan driving device comprises a plurality of shift registers with the same internal structure, and the input clock of the core (4) pure register register is received. The (4) round clock signals of the even-numbered shift register of the signal disc are inverted. The present invention proposes a scanning drive device comprising N shift registers. Each of the shift registers includes an input node, an output node, a logic close, a component, and a reverse group. The logic oil includes a first input end, a second input end, and a first-round output end, and the first input end is coupled to the second input end and the second input end is coupled to the round-out node. The switching element includes a first output signal outputted by the second terminal and the first H1 switch receiving logic to determine whether to turn on the circuits of the first end and the second end. 160 lOtwf.doc/r 160 lOtwf.doc/r 'end, its output is coupled to the output node, where N is the natural N-1th shift == packet? input and the wheel end 'its input coupling The input node of the switch bit register is coupled to the start signal, and the odd number of input nodes temporarily stored by the 丄1 receive the tracing number, and the even number of the spears are received (four) _ the buffer box of the shift register The reverse signal of the first nickname. ψ An invention uses a single-architecture shift register, so it can be used in addition to two. Ten percent drive a single number of scan lines, and the actuators are *, also: reduce the complexity of the wafer or panel layout. In order to make the present invention and other objects, advantages and advantages more obvious, the following is a detailed description of the preferred embodiment 'and in conjunction with the drawings'. [Embodiment] It is used in the consistent embodiment of the present invention. The internal circuit of the scan driver is shown in Figure 4A. Further, in the present invention-embodiment, the flat panel display driven by the scan driving device is shown in Fig. 4A. In this embodiment, a shift register SRJ~SR_Ν is included, and each of the f-bit registers includes an input node node, an output node (10) de 〇, an inverse logic gate NAND, a switching element sw, and a counter Phase logic brake, INV2 to ^ please 3. Wherein, the start signal STV is input to the shift (four) register YR], and the odd-numbered shift register (for example, SR1, SR3) receives the scan: said CKV 'the even-bit shift register (for example, SR2) SR4) The inverted signal of § CKV is taken. 16010twf.d〇c/r 16010twf.d〇c/r
案珑：94142024Case: 94142002
圖4B 98年5月25日修正-替換頁 的平面顯示器在此實施例中使用的是一液晶顯 不面板來做為一個例子。圖4B中，掃描驅動裝置4〇即為 圖4A的裝置，掃描驅動裝置40接收起始訊號STV以及 掃描訊號CKV，並將驅動液晶面板41訊號由每一級移位 暫存器輸出端輸出至液晶面板閘極線SL，作為掃描訊號。 另外，開關元件SW用傳輸閘，也就是N型電晶體與p型 電晶體所組成，任何熟習此技藝者，應當知道，開關元件 有許多不同實行方式，在此不多做贅述。 其中，反及邏輯閘NAND第一輸入端為輸入節點 node__i ’其第二輸入端耦接輸出節點n〇de_〇。開關元件sw 具有兩端點N1以及N2,接收反及邏輯閘NAND之輸出訊 號，決定N1與N2開路或短路。反相邏輯閘INV3接收反 及邏輯閉NAND之輸出訊號，並將其反相，以供應開關元 件SW的P型電晶體閘極決定開關的導通錢止。反相邏 輯閘INV2搞接開關元件N2端，將其訊號反相，並輸出至 輸出節點node一〇,另外反相邏輯閘INV1再將輸出節點 node_〇的訊號反相輸出。 為了說明的方便性’我們將圖4A實施例中SR1與SR2 拿出來繪示為圖5A ’分別討論，請參照圖5A。其包括了 6個反相邏輯閘分別為圖中的5〇〇、5〇2、5〇4、5〇6、5〇8 以及51〇 ’還包括了兩個傳輪閉512與514(也就是圖4上 面的開關7L件SW)以及兩個反及邏輯閘516肖518。在圖 中，又標上了 A ' B、c、d、je、F、G、Η等8個節點， 16010twf.doc/r 另外，我們將圖5A上面8個節點的時序波形圖、反相起 如afl说STV以及掃描訊號CKV分別繪示在圖π，請同時 參照圖5Α以及圖5Β。 首先，起始t峨STV在一張畫面開始的時候，將電壓 準位拉為低電位並輸入至反及邏輯問si6。此時，反及邏 輯，516接收到低電位訊號，節點A輸出變為高電位。由 於即點A為南電位使得傳輸閘512内部n型電晶體閑極接 電位’另外’卽點A的高電位透過反相邏輯閘50〇 $低雜施加於P型電晶體閘極，使得傳輪閘512導通。 丄於知描訊號CKV接著變成高電位，節點B跟著也 :電位。節點B的高電位經過反相邏輯閘5 遲 使節點C變為低電位。 f询、峰 =的，i點C的低電位經過反相邏輯間地傳 輪即點G，此B才第一條掃描線開始 低電位使反及邏輯閘518的輪入 卜即點C的 * 而為低電位，造成筋ϋ ΉFig. 4B Planar display of the correction-replacement page of May 25, 1998 In this embodiment, a liquid crystal display panel is used as an example. In FIG. 4B, the scan driving device 4 is the device of FIG. 4A. The scan driving device 40 receives the start signal STV and the scan signal CKV, and outputs the driving liquid crystal panel 41 signal from each stage of the shift register output to the liquid crystal. The panel gate line SL serves as a scanning signal. In addition, the switching element SW is composed of a transfer gate, that is, an N-type transistor and a p-type transistor. Anyone skilled in the art should know that the switching element has many different implementation modes, and will not be described here. The first input end of the logic gate NAND is the input node node__i ', and the second input end is coupled to the output node n〇de_〇. The switching element sw has terminals N1 and N2 at both ends, and receives an output signal opposite to the logic gate NAND, which determines that N1 and N2 are open or shorted. The inverting logic gate INV3 receives the output signal of the inverse logic NAND and inverts it to supply the P-type transistor gate of the switching element SW to determine the conduction of the switch. The inverting logic gate INV2 is connected to the N2 terminal of the switching element, inverts its signal, and outputs it to the output node node, and the inverted logic gate INV1 inverts the signal of the output node node_〇. For convenience of explanation, 'we take SR1 and SR2 in the embodiment of Fig. 4A as shown in Fig. 5A', respectively, please refer to Fig. 5A. It consists of 6 inverted logic gates, which are 5〇〇, 5〇2, 5〇4, 5〇6, 5〇8, and 51〇 in the figure. Also includes two transmissions closed 512 and 514 (also That is, the switch 7L member SW) and the two opposite logic gates 516 are shown in FIG. In the figure, 8 nodes including A 'B, c, d, je, F, G, and , are also marked, 16010twf.doc/r. In addition, we will take the timing waveforms of the 8 nodes above in Figure 5A and invert them. As afly said STV and scan signal CKV are shown in Figure π, please refer to Figure 5Α and Figure 5Β at the same time. First, the starting t峨STV pulls the voltage level to a low level at the beginning of a picture and inputs it to the logic and si6. At this time, in opposition to the logic, 516 receives the low potential signal and the node A output goes high. Since the point A is the south potential, the internal n-type transistor of the transmission gate 512 is connected to the potential of the 'other' point A, and the high potential of the anode is transmitted through the inverted logic gate 50 〇 $ low impurity applied to the P-type transistor gate, so that The wheel brake 512 is turned on. The CKV then becomes high and the node B follows: potential. The high potential of Node B is delayed by the inverted logic gate 5 to cause node C to go low. f inquiry, peak =, the low potential of i point C passes through the inversion logic between the two points, that is, the point G, the first scanning line starts to be low, so that the turn of the logic gate 518 is the point C. * It is low potential, causing tendons
為向電位，進一步使得傳輸開 1即點D 收到掃描訊號CKV的反相娜]°彳即點£接 輪延遲使節鮮高電位㈣，㈣反相邏輯間5】〇傳 當起始訊號由低電位轉為古 ，緊接著由高電位轉為描訊號 邏輯閘504傳輸延遲得到—古雷'、 P，，’ 、，工過反相 到兩個高電位輸入之後，輪 閘幻2截止。由於節點r -电位至郎點Λ，使傳輸 截止由於即占C為兩電位使得節點〇變為低電 ι·__—1 98年12月ι8 案號：^>4142024 -替換頁 位’此時第一條掃描結束。， 同樣的’由於掃描訊號CKV由高電位轉為低電位， 掃描訊號CKV的反相訊號便由低電位轉為高電位，施加 於節點Ε，透過反相邏輯閘510使得節點F變為低電位。 另外，節點F低電位透過反相邏輯閘508輸出至節點Η， 使得節點Η高電位，開始了第二條掃描。當掃描訊號CKV 由低電位轉為高電位時，掃描訊號CKV的反相訊號便由 高電位轉為低電位，此時節點F變為高電位使得反及邏輯 閘518輸入皆為高電位，節點D變成了低電位使傳輸閘514 不通。另外，由於節點F變為高電位，使得節點H變為低 電位，此時第二條掃描結束。以下便如同上述操作模式的 延續，故不予贅述。 然而，可以注意到的是，上面的所有移位暫存器SR1 二SRN皆為相同的架構，因此，在晶片或面板佈局上可 減低晶片或面板佈局複雜度。 本發明另一實施例中所使用的掃描驅動裝置的内部 電路方塊圖顯示如圖6A，另外，在本發明一實施例中使用 圖6A掃描驅動裝置所驅動的平面顯示器繪示如圖6b。在 此實施例中，包括了 N個移位暫存器SR—1〜SR—N，每一 個移位暫存器包括輸人節點nGde」、輪出節點nQde_〇、反 或邏輯閘NOR、P·元件SW以及反相邏輯問爾「贈2 以及INV3。 開始訊號stv輸人至移位暫存器SR1，第奇數位的移 16010twf.d〇c/i 16010twf.d〇c/i 位暫存為（例如SRI、SR3)接收掃描訊號CKV，第偶數位 的移位暫存器（例如SR2、SR4)接收掃描訊號CKV的反相 σ ϋ 口 6Β的平面顯示器在此實施例中使用的是一液晶 顯示面板來做為一個例子。圖6Β中，掃描驅動裝置60即 為圖6Α的掃描驅動裝置，掃描驅動裝置6〇接收起始訊號 stv以及掃描訊號CKV，並將驅動液晶面板61訊號由每 一級移位暫存器輸出端輸出至液晶面板閘極線S L，作為掃 描虎。另外，開關元件sw用傳輸閘，也就是n型電晶 體與P型電晶體所組成，任何熟習此技藝者，應當知道， 開關兀件有許多不同實行方式，在此不多做費述。 為了說明的方便性，我們將圖6A實施例中SR1與SR2 手出來繪不為圖7A，分別討論，請參照圖7A。其包括了 6個反相邏輯閘分別為圖中的700、702、704、706、708 以及=10，還包括了兩個傳輸閘7]2與714(也就是上面的 開關tl件SW)以及兩個反或邏輯閘716與718所組成，在 圖中’又標上了 A、B、c、D、E、F等6個節點，另外，In order to the potential, the transmission is further turned on, that is, the point D receives the inverted signal of the scanning signal CKV, and the point is delayed, so that the delay is high (4), and (4) the inverting logic is 5] when the starting signal is The low potential turns to ancient, and then the high-potential to analog signal gate 504 transmission delay is obtained - Gu Lei ', P,, ',, after the process is reversed to two high-potential inputs, the wheel brakes 2 cutoff. Since the node r-potential to the point Λ, the transmission is cut off because the C is the two potentials, so that the node becomes low. ι·__—1 December 98 ι8 Case number: ^>4142024 - Replace page position 'At this time The first scan ends. , the same 'Because the scan signal CKV turns from high to low, the inverted signal of the scan signal CKV turns from low to high, applied to the node Ε, and the node F becomes low through the inverted logic gate 510. . In addition, the low potential of the node F is output to the node 透过 through the inverted logic gate 508, causing the node to be at a high potential to start the second scan. When the scanning signal CKV changes from low potential to high potential, the inverted signal of the scanning signal CKV changes from high potential to low potential, and the node F becomes high potential, so that the input of the inverse logic gate 518 is high, the node D becomes low and the transfer gate 514 is disabled. In addition, since the node F becomes high, the node H becomes low, and the second scan ends. The following is a continuation of the above mode of operation, so it will not be described. However, it can be noted that all of the above shift registers SR1 and SRN are of the same architecture, thus reducing wafer or panel layout complexity on the wafer or panel layout. An internal circuit block diagram of a scan driving apparatus used in another embodiment of the present invention is shown in Fig. 6A, and in addition, a flat panel display driven by the scanning driving apparatus of Fig. 6A is shown in Fig. 6b in an embodiment of the present invention. In this embodiment, N shift registers SR-1 to SR_N are included, and each shift register includes an input node nGde", a round-out node nQde_〇, an inverse or a logic gate NOR, P·Component SW and inverting logic are “Gift 2 and INV3. Start signal stv input to shift register SR1, odd-number shift 16010twf.d〇c/i 16010twf.d〇c/i The storage (for example, SRI, SR3) receives the scan signal CKV, and the even-numbered shift register (for example, SR2, SR4) receives the inverted σ port of the scan signal CKV. The flat display is used in this embodiment. A liquid crystal display panel is taken as an example. In FIG. 6 , the scan driving device 60 is the scan driving device of FIG. 6 , and the scan driving device 6 receives the start signal stv and the scan signal CKV, and drives the liquid crystal panel 61 signal. Each stage of the shift register output is output to the liquid crystal panel gate line SL as a scanning tiger. In addition, the switching element sw is composed of a transfer gate, that is, an n-type transistor and a P-type transistor, and any skilled person is familiar with the art. It should be known that there are many different ways of implementing switch components. For the convenience of description, we will not draw the SR1 and SR2 in the embodiment of FIG. 6A as FIG. 7A, which will be discussed separately. Please refer to FIG. 7A, which includes 6 inverted logic gates respectively. For the 700, 702, 704, 706, 708 and = 10 in the figure, two transmission gates 7] 2 and 714 (that is, the above switch tl SW) and two reverse logic gates 716 and 718 are also included. The composition is marked with 6 nodes A, B, C, D, E, F, etc. in the figure.
我們1圖7A上面6個節點的時序波形圖、起始訊號STV 以及知描訊號CKV分別纟f示在圖7B，讀者請同時參昭圖 7A以及圖7B。 / 準位訊=Μ""在—張晝面開始的時候’將電壓 。’减人至反或邏輯閘716，使得節點A變 為電位’由於節點A為低電位使得傳輸閘712内部p型 電晶體閉極接收㊆丨柄+ & 賊到低电位，另外，節點A的低電位透過反 16010twf.d〇c/r 相邏輯閘700將低電位施加於P沒電晶體閘極，使得傳車介 閘712導通。緊接著掃描訊號CKV跟著變成高電位，通 過傳輸閘7】2，使得節點B變為高電位。節點B的高電位 經過反相邏輯閘704以及702的傳輸延遲，使節點c跟著 變為高電位，此時，第一條掃描線開始掃描。 同樣的’反或邏輯閘718接收到節點C的高電位，輪 出一低電位，使的傳輸閘714導通，而節點E便接收到^ 描訊號CKV的反相訊號，經過反相邏輯閘7]〇以及7卯 的傳輸延遲，節點F跟著變成低電位。 斤接考，富掃描訊號CKV開始轉變為低電位時，此時 即點B跟著變為低電位，經過反相邏輯閘704以及702的 節點〇也變成了低電位，此時，第—條掃描線 輸^^ °此時，由於716輪入接收到兩個低電位，使得 輸出為向電位，使傳輸閘712戴止。 則轉開始轉變為低電位’其反相訊號 閘710以刀位節點Ε亦轉變為高電位，經過反相邏輯 此時開M 7G8的傳輸延遲’節點F跟著轉變為高電位， 卷二弟一條掃描線的掃描。 便從高電位2 CKV接著從低電位轉為高電位時，節點Ε 傳輸延遲，低電位，經過反相邏輯閘710以及708的 結束掃栺。：：？跟著5變為低電位，此時第二條掃描線 反或邏輯閉私由於節點F與節點C皆為低電位，使得 私出高電位，使傳輸閘714截止。以下便 1338272 160 lOtwf.doc/r 如同上述操作模式的延續，故不予贅述。 此除本發明採用單-架:的移位暫存器，因 可減低晶片或面板佈局複雜f線的驅動器之外，並且 雖然本發明已以較佳實施例揭露如上，狄 限定本發明，任何熟習此蓺 ”、、…、’以 和範圍内，當可作此卞夕在不脫離本發明之精神 粑圍當視後附之申請專利· 之保叹 【圖式簡單說明】 疋者為準。 圖U會示為習知液晶顯示器之電路。 圖2綠示為習知用於液晶螢幕掃描驅動哭、 形。圖3緣示為圖2習知用於液晶螢幕掃描驅動器操作波 電路方圖::示為本發明-實施例之婦描_ 塊圖圖4B緣示為本發明一實施例之平面顯示器的電路方 内二=發明-實施， 操作繪示為本發明一實施例之掃•動裝置圖认的 部電為本發明另一實施例之婦描驅動裝置的内 圖6B綠示為本發明一實施例之平面顯示器的電路方 14 1338272 16010twf.doc/r 塊圖。 圖7A繪示為本發明一實施例之掃描驅動裝置圖6的 内部部份電路方塊圖。 圖7B繪示為本發明一實施例之掃描驅動裝置圖7A的 操作波形。 【主要元件符號說明】 102 :時序控制器 104 :掃描驅動器 106 :源極驅動器 10 8 .液晶面板 Π0 :閘極線 112 :源極線 210、212、512、514、712、714 :傳輸閘 40、 60 :掃描驅動裝置 41、 61 :液晶面板 A、B、C、D、E、F、G、Η :節點 STV :起始訊號、反相起始訊號 SL :閘極線 CKV :掃描訊號 INV；l、INV2、INV3、200、202、204、206、208、500、 502、504、506、508、510、700、702、704、706、708、 710 :反相邏輯閘 N卜N2 :端點 node i :輸入節點 1338272 16010twf.doc/r node_o :輸出節點 NAND、516、518 :反及邏輯閘 NOR、214、216、716、718 :反或邏輯閘 SR_1〜SR_N :移位暫存器 SW :開關元件The timing waveform diagram, the start signal STV and the known signal CKV of the six nodes above in FIG. 7A are respectively shown in FIG. 7B, and the reader is also referred to FIG. 7A and FIG. 7B. / Quasi-position = Μ "" At the beginning of Zhangye, the voltage will be. 'Decrement to the inverse or logic gate 716, causing node A to become potential'. Since node A is low, the internal p-type transistor of the transfer gate 712 is closed to receive the seven-handle handle + & thief to low potential, in addition, node A The low potential is applied to the P-free gate via the reverse 16010twf.d〇c/r phase logic gate 700, causing the pass-through 712 to conduct. Immediately after the scan signal CKV goes high, the transfer gate 7] 2 causes the node B to go high. The high potential of node B passes through the propagation delays of inverting logic gates 704 and 702, causing node c to go high, at which point the first scan line begins to scan. The same 'reverse OR logic gate 718 receives the high potential of the node C, rotates a low potential, so that the transmission gate 714 is turned on, and the node E receives the inverted signal of the analog signal CKV, and passes through the inverted logic gate 7 ]〇 and the transmission delay of 7卯, node F becomes low. After receiving the test, the rich scan signal CKV begins to change to a low potential, at which point point B follows a low potential, and the node 经过 through the inverted logic gates 704 and 702 also becomes a low potential. At this time, the first scan Line transmission ^^ ° At this time, since the 716 wheel receives two low potentials, the output is turned to the potential, so that the transmission gate 712 is worn. Then, the turn starts to change to a low potential', and the inverted signal gate 710 is also turned into a high potential by the tool position node ,, and the transmission delay of the M 7G8 is turned on by the inverting logic at this time, the node F is followed by the transition to the high potential. Scanning of the scan line. When the high potential 2 CKV is followed by the low potential to the high potential, the node 传输 transmission delays, low potential, and ends the sweep through the inverted logic gates 710 and 708. ::? Following 5 becomes a low potential, at which time the second scan line is reversed or logically closed because node F and node C are both low, causing a high potential to turn off, and the transfer gate 714 is turned off. The following 1338272 160 lOtwf.doc/r is like the continuation of the above operation mode, so it will not be described. In addition to the present invention, a single-station shift register is used, and since the driver of the f-line or panel layout is complicated to reduce the f-line, and although the present invention has been disclosed in the preferred embodiment as above, Di defines the present invention, I am familiar with this 蓺",,..., 'and the scope of the sigh, and can be used for the sigh of the invention without the spirit of the invention. Figure U will be shown as a circuit of a conventional liquid crystal display. Figure 2 is shown in the prior art for the liquid crystal screen scanning drive crying, shape. Figure 3 is shown in Figure 2 for the liquid crystal screen scanning driver operating wave circuit diagram Illustrated in the present invention is a circuit diagram of a flat panel display according to an embodiment of the present invention. Figure 6B is a block diagram of a circuit board 14 1338272 16010 twf.doc/r of a flat panel display according to an embodiment of the present invention. Figure 7A depicts a portion of the circuit diagram of the embodiment of the present invention. A scanning drive device according to an embodiment of the present invention is shown in FIG. Figure 7B is a diagram showing the operation waveform of the scanning drive device of Figure 7A according to an embodiment of the present invention. [Main component symbol description] 102: Timing controller 104: Scan driver 106: Source driver 10 8 . Liquid crystal panel Π0: gate line 112: source line 210, 212, 512, 514, 712, 714: transfer gates 40, 60: scan driving devices 41, 61: liquid crystal panels A, B, C, D, E, F , G, Η: node STV: start signal, inversion start signal SL: gate line CKV: scan signal INV; 1, INV2, INV3, 200, 202, 204, 206, 208, 500, 502, 504, 506, 508, 510, 700, 702, 704, 706, 708, 710: Inverted logic gate Nb N2: End point node i: Input node 1338272 16010twf.doc/r node_o: Output node NAND, 516, 518: Counter And logic gate NOR, 214, 216, 716, 718: inverse or logic gate SR_1 ~ SR_N: shift register SW: switching element
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