1337361 九、發明說明： v • 【發明所屬之技術領域】 本發明係關於一種半導體記愧體裝置；且更特定言之， 本發明係關於一種具有共用位元線感測放大器機制之半導 體記憶體裝置及其驅動方法。 【先前技術】 在包括DRAM之大多數半導體記憶體裝置中，位元線感 測放大器用於感測施加於位元線上之微弱資料訊號。半導 • 體記憶體裝置具有核心區域，其中排列有複數個記憶體單 凡。在該核心區域中，在行方向重複地排列記憶體單元陣 列及位元線感測放大器陣列。亦即，記憶體單元陣列係排 列於位元線感測放大器之上方及下方。提出一可最大化位 元線感測放大器之效率並減少晶片面積之共用位元線感測 放大器機制。在該共用位元線感測放大器機制中，由上部 及下部記憶體單元陣列共同使用一位元線感測放大器。 圖1為具有共用位元線感測放大器機制之DRAM核心之 Φ 電路圖。 參看圖1 ’位元線感測放大器包括連接於上拉電壓線RTQ 與位元線對BL及BLB之間的兩個PMOS電晶體，及連接於下 拉電壓線SB與位元線對BL及BLB之間的兩個NMOS電晶 體。 位元線感測放大器係由上部單元陣列CELL ARRAYO及 下部單元陣列CELL ARRAY1共用。位元線斷開單元、位元 線等化單元、位元線預充電單元及行選擇單元排列於位元 112594.doc 線感測放大器與記憶體單元陣列之間。 具體言之，NMOS電晶體M0至M4安置於位元線感測放大 器與單元陣列〇區塊之間。NMOS電晶體Μ1及M2回應於上 部位元線斷開訊號BISH而使上部位元線對BLU及BLBU與 位元線感測放大器連接/斷開。NMOS電晶體M3及Μ4回應於 位元線等化訊號BLEQ而將位元線對BL及BLB預充電至位 元線預充電電壓VBLP(—般為Vdd/2)。NMOS電晶體M0回應 於位元線等化訊號BLEQ而使上部位元線對BLU及BLBU等 化。 同樣地，NMOS電晶體M5至M7及兩個NMOS電晶體安置 於位元線感測放大器與單元陣列CELL ARRAY1之間。 NMOS電晶體M5及M6回應於下部位元線斷開訊號BISL而 使下部位元線對BLD及BLBD與位元線感測放大器連接/斷 開。NMOS電晶體M7回應於位元線等化訊號BLEQ而使下部 位元線對BLD及BLBD等化。兩個NMOS電晶體回應於行選 擇訊號C Y而將位元線對BL及BLB選擇性連接至區段資料 匯流排對SIO及SIOB。 圖2為用於產生位元線斷開訊號BISH及BISL以及位元線 等化訊號BLEQ之習知位元線控制電路之方塊圖。 參看圖2，習知位元線控制電路包括區塊控制器1 00、位 元線斷開訊號產生器11 0，及位元線等化訊號產生器120。 區塊控制器1 〇〇接收區塊位址訊號AX以產生對應於記憶體 單元陣列之區塊選擇訊號BS_0及BS_1。位元線斷開訊號產 生器110回應於區塊選擇訊號BS_0及BS_1而產生位元線斷 I12594.doc ^337361 開訊號BISH及BISL。位元線等化訊號產生器120回應於區 塊選擇訊號BS_0及BS_1而產生位元線等化訊號BLEQ。區 塊控制器丨00包括對應於記憶體單元陣列之複數個區塊選 擇訊號產生器。 再次參看圖1，在預充電狀態中開啟NMOS電晶體M0至 M7。當施加作用中命令（active command)並選擇單元陣列〇 區塊時，區塊選擇訊號BS—0及BS_1分別變為邏輯位準高 (HIGH)及邏輯位準低（LOW)。1337361 IX. Description of the Invention: v • Technical Field of the Invention The present invention relates to a semiconductor recording device; and more particularly, to a semiconductor memory having a shared bit line sense amplifier mechanism Device and its driving method. [Prior Art] In most semiconductor memory devices including DRAMs, bit line sense amplifiers are used to sense weak data signals applied to bit lines. The semi-conductive memory device has a core area in which a plurality of memory memories are arranged. In the core region, the memory cell array and the bit line sense amplifier array are repeatedly arranged in the row direction. That is, the memory cell array is arranged above and below the bit line sense amplifier. A common bit line sense amplifier mechanism is proposed which maximizes the efficiency of the bit line sense amplifier and reduces the wafer area. In the shared bit line sense amplifier mechanism, a single line sense amplifier is used in common by the upper and lower memory cell arrays. Figure 1 is a Φ circuit diagram of a DRAM core with a shared bit line sense amplifier mechanism. Referring to FIG. 1 'The bit line sense amplifier includes two PMOS transistors connected between the pull-up voltage line RTQ and the bit line pair BL and BLB, and is connected to the pull-down voltage line SB and the bit line pair BL and BLB. Between two NMOS transistors. The bit line sense amplifier is shared by the upper cell array CELL ARRAYO and the lower cell array CELL ARRAY1. The bit line disconnecting unit, the bit line equalizing unit, the bit line pre-charging unit, and the row selecting unit are arranged between the bit 112594.doc line sense amplifier and the memory cell array. Specifically, the NMOS transistors M0 to M4 are disposed between the bit line sense amplifier and the cell array block. The NMOS transistors Μ1 and M2 connect/disconnect the upper portion of the line pair BLU and the BLBU to the bit line sense amplifier in response to the upper portion of the line disconnection signal BISH. The NMOS transistors M3 and Μ4 precharge the bit line pair BL and BLB to the bit line precharge voltage VBLP (generally Vdd/2) in response to the bit line equalization signal BLEQ. The NMOS transistor M0 responds to the bit line equalization signal BLEQ to equalize the upper part line pair BLU and BLBU. Similarly, NMOS transistors M5 to M7 and two NMOS transistors are disposed between the bit line sense amplifier and the cell array CELL ARRAY1. The NMOS transistors M5 and M6 are connected/disconnected to the bit line sense amplifiers in response to the lower portion of the line line break signal BISL and the lower part line pair BLD and BLBD. The NMOS transistor M7 equalizes the lower bit line pair BLD and BLBD in response to the bit line equalization signal BLEQ. The two NMOS transistors selectively connect the bit line pair BL and BLB to the sector data bus pair SIO and SIOB in response to the row select signal C Y . 2 is a block diagram of a conventional bit line control circuit for generating bit line off signals BISH and BISL and bit line equalization signals BLEQ. Referring to Fig. 2, the conventional bit line control circuit includes a block controller 100, a bit line disconnection signal generator 110, and a bit line equalization signal generator 120. The block controller 1 receives the block address signal AX to generate block select signals BS_0 and BS_1 corresponding to the memory cell array. The bit line disconnection signal generator 110 generates a bit line break in response to the block selection signals BS_0 and BS_1. I12594.doc ^337361 The signal numbers BISH and BISL. The bit line equalization signal generator 120 generates a bit line equalization signal BLEQ in response to the block selection signals BS_0 and BS_1. The block controller 丨00 includes a plurality of block selection signal generators corresponding to the memory cell array. Referring again to Figure 1, the NMOS transistors M0 through M7 are turned on in the precharge state. When an active command is applied and the cell array block is selected, the block select signals BS-0 and BS_1 become logic level high (HIGH) and logic level low (LOW), respectively.
在區塊選擇訊號B S_0及B S_ 1之組合中，上部位元線斷開 訊號BISH維持邏輯位準HIGH，以使得NMOS電晶體Ml及 M2開啟，且下部位元線斷開訊號BISL撤銷為邏輯位準 LOW，以使得NMOS電晶體N5及M6關閉。 當區塊選擇訊號BS_0啟動為邏輯位準HIGH時，位元線等 化訊號BLEQ撤銷為邏輯位準low，以使得NMOS電晶體 MO、M3、M4及 M7 關閉。In the combination of the block selection signals B S_0 and B S_ 1 , the upper part of the element line disconnection signal BISH maintains the logic level HIGH, so that the NMOS transistors M1 and M2 are turned on, and the lower part of the element line disconnection signal BISL is deactivated. The logic level is LOW so that the NMOS transistors N5 and M6 are turned off. When the block select signal BS_0 is activated to the logic level HIGH, the bit line equalization signal BLEQ is deasserted to the logic level low, so that the NMOS transistors MO, M3, M4 and M7 are turned off.
如圖2中所說明，必須獨立提供位元線斷開訊號產生器 1 1 〇及位7L線等化訊號產生器120。因為必須提供獨立訊號 線所以於要許多金屬線。如上文所述，以陣列形式排列 位元線感測放大器，且提供許多位元線感測放大器陣列。 因此’晶Μ Φ積由於位元線控制f路及金屬線而增加。 【發明内容】 此本心明之-目的為提供一種具有共用位元線感測 放大器機制之半導體記憶體裝置及其驅動方法，從而能释 防止由位元線控制電路及金屬線引起的晶片面積增加。 M2594.doc 根據本發明之一態樣，提供一種半導體記憶體裝置，其 包括：一位元線感測放大器，其用於對施加於位元線對上 之資料進行放大；一上部位元線斷開單元，其用於回應於 上部位元線斷開訊號而使該位元線感測放大器自上部單 元陣列之位元線對選擇性斷開；一下部位元線斷開單元， 其用於回應於一下部位元線斷開訊號而使該位元線感測放 大器自下部單元陣列之位元線對選擇性斷開；一上部位元 線等化單元’其用於回應於該下部位元線斷開訊號而使該 上部單元陣列之該位元線對等化；及一下部位元線等化單 元’其用於回應於該上部位元線斷開訊號而使該下部單元 陣列之該位元線對等化。 根據本發明之另一態樣，提供一種驅動半導體記憶體裝 置之方法，其包括：對施加於位元線對上之資料進行放大； 回應於一上部位元線斷開訊號而使一位元線感測放大器自 上部單元陣列之位元線對選擇性斷開；回應於一下部位元 線斷開訊號而使該位元線感測放大器自下部單元陣列之位 元線對選擇性斷開；回應於該下部位元線斷開訊號而使該 上部單元陣列之該位元線對等化；及回應於該上部位元線 斷開訊號而使該下部單元陣列之該位元線對等化。 【實施方式】 下文中，將參看隨附圖式詳細描述根據本發明之例示性 實施例的具有共用位元線感測放大器機制之半導體記憶體 裝置及其驅動方法。 圖3為根據本發明之一實施例之dram核心的電路圖。 112594.doc 1337361 位元線感測放大器包括連接於上拉電壓線（RT〇線）與位 元線對BL及BLB之間的兩個PMOS電晶體，及連接於下拉電 壓線SB與位元線對BL及BLB之間的兩個NMOS電晶體《行 選擇單元44包括具有接收行選擇訊號cy之閘極的兩個 NMOS電晶體，並使位元線對BL及BLB與區段資料匯流排 對SIO及SIOB選擇性連接。 圖4為用於產生圖3中之上部位元線斷開訊號及下部位元 線斷開訊號之位元線控制電路的電路圖。 參看圖4，位元線控制電路包括區塊控制器2〇〇及位元線 斷開訊號產生器2 1 0。區塊控制器2〇〇接收區塊位址訊號Αχ 以產生對應於記憶體單元陣列之區塊選擇訊號Bs—〇及 BS_ 1。位元線斷開訊號產生器21 〇回應於區塊選擇訊號 BS一0及BS_1而產生位元線斷開訊號bisH及BISL。 與圖1中所示之先前技術相比，本發明之位元線控制電路 不包括位元線等化訊號產生器12〇。此之原因為位元線等化 單元40及48係由位元線斷開訊號BISh&BISL控制，而非由 位元線等化訊號BLEQ控制。 區塊控制器200包括對應於個別記憶體單元陣列之複數 個區塊選擇訊號產生器。 位元線斷開訊號產生器2丨〇包括：上部位元線斷開訊號產 生器，其用於回應於下部區塊選擇訊號BS一丨而產生上部位 元線斷開訊號BISH ;及下部位元線斷開訊號產生器，其用 於回應於上部區塊選擇訊號BS_〇而產生下部位元線斷開訊 號 BISL。 ° I I2594.doc 1337361 上部位元線斷開訊號產生器包括用於接收下部區塊選擇 訊號BS_1之反轉器INV卜及用於增加反轉器INV1之輸出訊 號之啟動位準的位準偏移器LS卜且下部位元線斷開訊號產 生器包括用於接收上部區塊選擇訊號BS_0之反轉器 INV3，及用於增加反轉器INV3之輸出訊號之啟動位準的位 準偏移器LS2。As illustrated in Fig. 2, the bit line disconnection signal generator 1 1 〇 and the bit 7L line equalization signal generator 120 must be independently provided. Because of the need to provide an independent signal line, many metal wires are required. As described above, the bit line sense amplifiers are arranged in an array and a plurality of bit line sense amplifier arrays are provided. Therefore, the crystal Φ product increases due to the bit line controlling the f path and the metal line. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device having a common bit line sense amplifier mechanism and a driving method thereof, thereby preventing an increase in wafer area caused by a bit line control circuit and a metal line. . M2594.doc According to an aspect of the present invention, a semiconductor memory device is provided, comprising: a one-bit line sense amplifier for amplifying data applied to a bit line pair; an upper part line a disconnecting unit for selectively disconnecting the bit line sense amplifier from a bit line pair of the upper cell array in response to the upper part cell line disconnection signal; a lower part element line disconnecting unit for Responding to the lower part of the element line disconnection signal to selectively disconnect the bit line sense amplifier from the bit line pair of the lower cell array; an upper part element line equalization unit 'for responding to the lower part element The line disconnects the signal to equalize the bit line of the upper cell array; and the lower part element line equalization unit 'uses the bit of the lower cell array in response to the upper part of the element line disconnection signal The yuan line is equalized. According to another aspect of the present invention, a method of driving a semiconductor memory device includes: amplifying data applied to a bit line pair; and responding to an upper portion of the line disconnecting signal to make a bit The line sense amplifier is selectively disconnected from the bit line pair of the upper cell array; the bit line sense amplifier is selectively disconnected from the bit line pair of the lower cell array in response to the lower part of the line line disconnection signal; Reciprocating the bit line of the upper cell array in response to the lower portion of the cell line disconnection signal; and equalizing the bit line of the lower cell array in response to the upper portion of the cell line disconnection signal . [Embodiment] Hereinafter, a semiconductor memory device having a shared bit line sense amplifier mechanism and a method of driving the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. 3 is a circuit diagram of a dram core in accordance with an embodiment of the present invention. 112594.doc 1337361 The bit line sense amplifier includes two PMOS transistors connected between the pull-up voltage line (RT〇 line) and the bit line pair BL and BLB, and is connected to the pull-down voltage line SB and the bit line The two NMOS transistors between the BL and the BLB "the row selection unit 44 includes two NMOS transistors having gates for receiving the row selection signal cy, and the pair of bit lines BL and BLB and the sector data bus pair SIO and SIOB are selectively connected. 4 is a circuit diagram of a bit line control circuit for generating a top line disconnection signal and a lower part line disconnection signal in the upper portion of FIG. Referring to Fig. 4, the bit line control circuit includes a block controller 2A and a bit line disconnection signal generator 2 1 0. The block controller 2 receives the block address signal Αχ to generate block select signals Bs_〇 and BS_1 corresponding to the memory cell array. The bit line disconnection signal generator 21 generates the bit line disconnection signals bisH and BISL in response to the block selection signals BS_0 and BS_1. The bit line control circuit of the present invention does not include the bit line equalization signal generator 12A as compared with the prior art shown in FIG. The reason for this is that the bit line equalization units 40 and 48 are controlled by the bit line disconnection signal BISh & BISL instead of the bit line equalization signal BLEQ. Block controller 200 includes a plurality of block selection signal generators corresponding to individual memory cell arrays. The bit line disconnection signal generator 2 includes: an upper part element line disconnection signal generator for generating an upper part element line disconnection signal BISH in response to the lower block selection signal BS; and a lower part The line disconnect signal generator is configured to generate a lower part line disconnection signal BISL in response to the upper block selection signal BS_〇. ° I I2594.doc 1337361 The upper part of the line disconnection signal generator comprises a reverser INV for receiving the lower block selection signal BS_1 and a level offset for increasing the activation level of the output signal of the inverter INV1 The shifter LS and the lower part of the element line disconnection signal generator include an inverter INV3 for receiving the upper block selection signal BS_0, and a level shifting for increasing the start level of the output signal of the inverter INV3 LS2.
在位準偏移器LSI中，兩個PMOS電晶體MP1及MP2具有 連接至高電壓端子VPP之源極，及交又連接在一起之閘極 與汲極。NMOS電晶體MN1具有連接至PMOS電晶體MP1之 汲極的汲極、連接至輸入端子N1之源極，及接收電源電壓 VDD之閘極。NMOS電晶體MN2具有連接至PMOS電晶體 MP2之汲極的汲極、連接至接地端子VSS之源極，及連接至 輸入端子N1之閘極。反轉器INV2連接至PMOS電晶體MP2 之及極。In the level shifter LSI, the two PMOS transistors MP1 and MP2 have a source connected to the high voltage terminal VPP, and a gate and a drain which are connected and connected together. The NMOS transistor MN1 has a drain connected to the drain of the PMOS transistor MP1, a source connected to the input terminal N1, and a gate receiving the power supply voltage VDD. The NMOS transistor MN2 has a drain connected to the drain of the PMOS transistor MP2, a source connected to the ground terminal VSS, and a gate connected to the input terminal N1. The inverter INV2 is connected to the sum of the PMOS transistors MP2.
使用熟知電路來建構位準偏移器LS 1及LS2 ^使用位準偏 移器LSI及LS2來產生位元線斷開訊號BISH及BISL之原因 在於：考慮到臨限電壓之損失，以高於電源電壓VDD之高 電壓VPP驅動位元線斷開電晶體。 圖5 A至5C分別展示圖3之位元線等化單元40及48之電路 圖。 參看圖5A，位元線等化單元40及48包括：NMOS電晶體， 其具有接收位元線斷開訊號BIS之閘極且連接於位元線對 BL與BLB之間；及兩個NMOS電晶體，其具有接收位元線 斷開訊號BIS之閘極且連接於位元線預充電電壓VBLP( — II2594.doc -12-Using well-known circuits to construct the level shifters LS 1 and LS2 ^ The use of the level shifters LSI and LS2 to generate the bit line disconnect signals BISH and BISL is due to the fact that the loss of the threshold voltage is exceeded. The high voltage of the power supply voltage VDD, VPP, drives the bit line to turn off the transistor. 5A through 5C are circuit diagrams showing the bit line equalization units 40 and 48 of Fig. 3, respectively. Referring to FIG. 5A, the bit line equalization units 40 and 48 include: an NMOS transistor having a gate receiving the bit line off signal BIS and connected between the bit line pair BL and BLB; and two NMOS transistors a crystal having a gate receiving the bit line disconnection signal BIS and connected to the bit line precharge voltage VBLP (- II2594.doc -12-
1337361 般VBPL = Vdd/2)與位元線對BL及BLB之間。 參看圖5B，位元線等化單元40及48包括兩個NMOS電晶 體，其具有接收位元線斷開訊號BIS之閘極，且連接於位元 線預充電電壓VBLP(—般為Vdd/2)與位元線對BL及BLB之 間。 參看圖5C，位元線等化單元40及48包括一 MOS電晶體， 其具有接收位元線斷開訊號BIS之閘極且連接於位元線對 BL與BLB之間。 在圖5A及5B中，位元線預充電電壓VBLP係施加至上部 位元線等化單元40與下部位元線等化單元48。相反地，在 圖5(C)中，位元線預充電電壓VBLP被施加至上部位元線等 化單元40及下部位元線等化單元48之一。 因為在預充電狀態中上部位元線斷開訊號BISH及下部 位元線斷開訊號BISL處於邏輯位準HIGH，所以NMOS電晶 體M8至Mil被開啟。位元線等化單元40及48之所有NMOS 電晶體亦被開啟。 當施加作用中命令且選擇單元陣列CELL ARRAY0B夺，區 塊選擇訊號BS_0及BS_1分別變為邏輯位準HIGH及邏輯位 準LOW。在區塊選擇訊號BS_0及BS_1之組合中，上部位元 線斷開訊號BISH維持邏輯位準HIGH。因此，上部位元線斷 開單元42之NMOS電晶體M8及M9以及下部位元線等化單 元48之所有NMOS電晶體亦被開啟。同時，下部位元線斷開 訊號BISL撤銷為邏輯位準LOW，以使得下部位元線斷開單 元46之NMOS電晶體Ml 0及Ml 1以及上部位元線等化單元 13 Il2594.doc V 5 > 40之所有NMOS電晶體被關閉。 相反地’當選擇單元陣列CELL ARRAY1時，區塊選擇訊 5虎及bs—I分別變為邏輯位準L〇w及邏輯位準HIGH。 因此’下部位元線斷開訊號bisl維持邏輯位準high。因 此下部位元線斷開單元46之NMOS電晶體ΜI 0及Μ11以及 上部位疋線等化單元4〇之所有NMOS電晶體亦開啟《同時， 上。卩位元線斷開訊號BISH撤銷為邏輯位準LOW，以使得上 4位元線斷開單元42之NMOS電晶體M8及M9以及下部位 凡線等化單元48之所有NMOS電晶體關閉。 如上文所述’即使在使用位元線斷開訊號來控制位元線 等化單元之情況下’亦可正常操作記憶體裝置。亦即，不 需要額外電路來產生位元線等化訊號β 根據本發明’可簡化位元線控制電路，從而減少記憶體 晶片面積。 本申請案含有與分別在2005年9月29曰及2005年12月29 曰於私國專利局申請之韓國專利申請案第2005-90956號及 第2005-133985號有關的主旨，該等專利申請案之全文以引 用的方式併入本文中。 雖然已關於某些較佳實施例描述了本發明，但熟習此項 技術者將易於瞭解’在不偏離如以下申請專利範圍中所界 定之本發明之範疇的情況下，可進行各種改變及修正。 【圖式簡單說明】 圖1為具有共用位元線感測放大器機制之dram核心之 電路圓；1337361 Like VBPL = Vdd/2) and bit line pair between BL and BLB. Referring to FIG. 5B, the bit line equalization units 40 and 48 include two NMOS transistors having a gate receiving the bit line off signal BIS and connected to the bit line precharge voltage VBLP (normally Vdd/ 2) Between the bit line pair BL and BLB. Referring to Fig. 5C, the bit line equalization units 40 and 48 include a MOS transistor having a gate receiving the bit line off signal BIS and connected between the bit line pair BL and BLB. In Figs. 5A and 5B, the bit line precharge voltage VBLP is applied to the upper bit line equalization unit 40 and the lower part element line equalization unit 48. In contrast, in Fig. 5(C), the bit line precharge voltage VBLP is applied to one of the upper portion element line equalization unit 40 and the lower portion element line equalization unit 48. Since the upper portion line disconnection signal BISH and the lower bit line disconnection signal BISL are at the logic level HIGH in the precharge state, the NMOS transistors M8 to Mil are turned on. All NMOS transistors of bit line equalization units 40 and 48 are also turned on. When the active command is applied and the cell array CELL ARRAY0B is selected, the block select signals BS_0 and BS_1 become the logic level HIGH and the logic level LOW, respectively. In the combination of the block selection signals BS_0 and BS_1, the upper part line disconnection signal BISH maintains the logic level HIGH. Therefore, all of the NMOS transistors of the NMOS transistors M8 and M9 of the upper portion of the element line breaking unit 42 and the lower portion of the element line equalizing unit 48 are also turned on. At the same time, the lower part element line disconnection signal BISL is deactivated to the logic level LOW, so that the NMOS transistors M10 and M11 of the lower part element line breaking unit 46 and the upper part of the element line equalization unit 13 Il2594.doc V 5 > All NMOS transistors of 40 are turned off. Conversely, when the cell array CELL ARRAY1 is selected, the block selection signal 5 and bs_I become the logic level L〇w and the logic level HIGH, respectively. Therefore, the lower part line disconnection signal bisl maintains the logic level high. Therefore, all of the NMOS transistors of the NMOS transistors ΜI 0 and Μ11 of the lower portion of the lower line disconnecting unit 46 and the equalizing unit 4 of the upper portion are also turned "on the same time." The bit line off signal BISH is deasserted to a logic level LOW such that all of the NMOS transistors M8 and M9 of the upper 4-bit line break unit 42 and the lower portion of the line equalization unit 48 are turned off. As described above, the memory device can be normally operated even when the bit line disconnection signal is used to control the bit line equalization unit. That is, no additional circuitry is required to generate the bit line equalization signal β. According to the present invention, the bit line control circuit can be simplified, thereby reducing the memory chip area. The present application contains the subject matter related to Korean Patent Application Nos. 2005-90956 and 2005-133985, which are filed on Sep. 29, 2005, and December 29, 2005, respectively. The full text of the case is incorporated herein by reference. Although the present invention has been described in terms of certain preferred embodiments, those skilled in the art will readily appreciate that various changes and modifications can be made without departing from the scope of the invention as defined in the following claims. . BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit circle of a dram core having a common bit line sense amplifier mechanism;
Ii2594.doc ⑶7361 圖2為用於產生位元線斷開訊號及位元線等化訊號之習 知位元線控制電路之方塊圖； 圖3為根據本發明之一實施例之dram核心的電路圖； 圖4為用於產生圖3中之上部位元線斷開訊號及下部位元 線斷開訊號之位元線控制電路的電路圖；及 圖5A至5C展示圖3之位元線等化器之電路圖。 【主要元件符號說明】 40 42 44 46 48 100 110 120 200 210 上部位元線等化單元 上部位元線斷開單元 行選擇單元 下部位元線斷開單元 下部位元線等化單元 區塊控制器 位元線斷開訊號產生器 位元線等化訊號產生器 區塊控制器 位元線斷開訊號產生器 I12594.doc -15· 、、匕/Ii2594.doc (3)7361 FIG. 2 is a block diagram of a conventional bit line control circuit for generating a bit line disconnection signal and a bit line equalization signal; FIG. 3 is a circuit diagram of a dram core according to an embodiment of the present invention; 4 is a circuit diagram of a bit line control circuit for generating a top line disconnection signal and a lower part element line disconnection signal in FIG. 3; and FIGS. 5A to 5C are diagrams showing the bit line equalizer of FIG. Circuit diagram. [Main component symbol description] 40 42 44 46 48 100 110 120 200 210 Upper part element line equalization unit upper part element line disconnection unit row selection unit lower part element line disconnection unit lower part element line equalization unit block control Transmitter bit line disconnection signal generator bit line equalization signal generator block controller bit line disconnection signal generator I12594.doc -15·, 匕/