CN1941193B - Semiconductor memory device and driving method thereof - Google Patents
Semiconductor memory device and driving method thereof Download PDFInfo
- Publication number
- CN1941193B CN1941193B CN2006101592187A CN200610159218A CN1941193B CN 1941193 B CN1941193 B CN 1941193B CN 2006101592187 A CN2006101592187 A CN 2006101592187A CN 200610159218 A CN200610159218 A CN 200610159218A CN 1941193 B CN1941193 B CN 1941193B
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- bit line
- signal
- nmos pass
- cut
- pass transistor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
A semiconductor memory device has a shared bit line sense amplifier. The semiconductor memory device includes: a bit line sense amplifier for amplifying data applied on bit line pair; an upper bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of an upper cell array in response to an upper bit line disconnection signal; a lower bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of a lower cell array in response to a lower bit line disconnection signal; an upper bit line equalization unit for equalizing the bit line pair of the upper cell array in response to the lower bit line disconnection signal; and a lower bit line equalization unit for equalizing the bit line pair of the lower cell array in response to the upper bit line disconnection signal.
Description
Technical field
The present invention relates to a kind of semiconductor storage; And more particularly, the present invention relates to a kind of semiconductor storage and driving method thereof with share bit lines sensor amplifier mechanism.
Background technology
In comprising most of semiconductor storages of DRAM, bit line sense amplifier is used to read the faint data-signal that puts on bit line.Semiconductor storage has nucleus, wherein is arranged with a plurality of storage unit.In this nucleus, repeatedly form memory cell array and bit line sense amplifier array on column direction.That is, form memory cell array below reaching above the bit line sense amplifier.Propose a kind of efficient of maximizing bit line sense amplifier and reduce the share bit lines sensor amplifier mechanism of chip area.In this share bit lines sensor amplifier mechanism, by top and the single bit line sense amplifier of the common use of bottom memory cell array.
Fig. 1 is the circuit diagram with DRAM core of share bit lines sensor amplifier mechanism.
Referring to Fig. 1, bit line sense amplifier comprises being connected in and draws pressure-wire RTO and bit line to two PMOS transistors between BL and the BLB, and is connected in actuation voltage line SB and bit line to two nmos pass transistors between BL and the BLB.
Bit line sense amplifier system is shared by upper cell array CELL ARRAY0 and lower unit array CELL ARRAY1.Bit line switching units, bit line equalization unit, bit-line pre-charge unit and column selection unit cell arrangement are between bit line sense amplifier and memory cell array.
In specific words, nmos pass transistor M0 to M4 is placed between bit line sense amplifier and cell array 0 block.Nmos pass transistor M1 and M2 make upper bit line be connected with bit line sense amplifier/disconnect BLU and BLBU in response to upper bit line cut-off signal BISH.Nmos pass transistor M3 and M4 are precharged to bit-line pre-charge voltage VBLP (be generally Vdd/2) with bit line to BL and BLB in response to bit line equalizing signal BLEQ.Nmos pass transistor M0 makes upper bit line to BLU and BLBU equilibrium in response to bit line equalizing signal BLEQ.
Similarly, nmos pass transistor M5 to M7 and two nmos pass transistors are placed between bit line sense amplifier and the cell array CELL ARRAY1.Nmos pass transistor M5 and M6 make lower bit line be connected with bit line sense amplifier/disconnect BLD and BLBD in response to lower bit line cut-off signal BISL.Nmos pass transistor M7 makes lower bit line to BLD and BLBD equilibrium in response to bit line equalizing signal BLEQ.Two nmos pass transistors are connected to sector data bus to SIO and SIOB with bit line to BL and BLB selectivity in response to array selecting signal CY.
Fig. 2 is the block diagram that is used to produce the conventional bit line control circuit of bit line cut-off signal BISH and BISL and bit line equalizing signal BLEQ.
Referring to Fig. 2, the conventional bit line control circuit comprises block controller 100, bit line cut-off signal generator 110, and bit line equalizing signal generator 120.Block controller 100 reception area block address signal AX select signal BS_0 and BS_1 to produce corresponding to the block of memory cell array.Bit line cut-off signal generator 110 is selected signal BS_0 and BS_1 and is produced bit line cut-off signal BISH and BISL in response to block.Bit line equalizing signal generator 120 is selected signal BS_0 and BS_1 and is produced bit line equalizing signal BLEQ in response to block.Block controller 100 comprises corresponding to a plurality of blocks of memory cell array selects signal generator.
Once more referring to Fig. 1, conducting nmos pass transistor M0 to M7 in pre-charge state.When applying activation command (active command) and selected cell array 0 block, block selects signal BS_0 and BS_1 to become logic level HIGH (height) and logic level LOW (low) respectively.
Select in the combination of signal BS_0 and BS_1 at block, upper bit line cut-off signal BISH keeps logic level HIGH, so that nmos pass transistor M1 and M2 conducting, and lower bit line cut-off signal BISL is logic level LOW by deactivation, so that nmos pass transistor N5 and M6 end.
When block selected signal BS_0 to be activated as logic level HIGH, bit line equalizing signal BLEQ was logic level LOW by deactivation, so that nmos pass transistor M0, M3, M4 and M7 end.
As illustrated in fig. 2, must provide bit line cut-off signal generator 110 and bit line equalizing signal generator 120 respectively.Because independently signal wire must be provided, so need many metal wires.As indicated above, with the array format bit line sense amplifier, and provide many bit line sense amplifier arrays.Therefore, increased chip area owing to bit line control circuit and metal wire.
Summary of the invention
Therefore, purpose of the present invention is for providing a kind of semiconductor storage and driving method thereof with share bit lines sensor amplifier mechanism, thereby can prevent that the chip area that is caused by bit line control circuit and metal wire from increasing.
According to an aspect of the present invention, provide a kind of semiconductor storage, it comprises: bit line sense amplifier, and it is used for to putting on bit line last data being amplified; The upper bit line switching units, it is used in response to the upper bit line cut-off signal this bit line sense amplifier being disconnected to last selectivity from the bit line of upper cell array; The lower bit line switching units, it is used in response to the lower bit line cut-off signal this bit line sense amplifier being disconnected to last selectivity from the bit line of lower unit array; The upper bit line balanced unit, it is used for making in response to this lower bit line cut-off signal this bit line of this upper cell array to equilibrium; And the lower bit line balanced unit, it is used for making in response to this upper bit line cut-off signal this bit line of this lower unit array to equilibrium.
According to a further aspect in the invention, provide a kind of method that drives semiconductor storage, it comprises: to putting on bit line last data are amplified; In response to the upper bit line cut-off signal bit line sense amplifier is disconnected to last selectivity from the bit line of upper cell array; In response to the lower bit line cut-off signal this bit line sense amplifier is disconnected to last selectivity from the bit line of lower unit array; This bit line that makes this upper cell array in response to this lower bit line cut-off signal is to equilibrium; And make this bit line of this lower unit array to equilibrium in response to this upper bit line cut-off signal.
Description of drawings
By with reference to the accompanying drawings the preferred embodiments of the present invention being described, above-mentioned and other aspects of the present invention and feature will become apparent, wherein:
Fig. 1 is the circuit diagram with DRAM core of share bit lines sensor amplifier mechanism;
Fig. 2 is the block diagram that is used to produce the conventional bit line control circuit of bit line cut-off signal and bit line equalizing signal;
Fig. 3 is the circuit diagram according to the DRAM core of one embodiment of the invention;
Fig. 4 is the circuit diagram that is used for producing the bit line control circuit of the upper bit line cut-off signal of Fig. 3 and lower bit line cut-off signal; And
Fig. 5 A to 5C shows the circuit diagram of the bit line equalization device of Fig. 3.
Embodiment
After this, describe semiconductor storage and driving method thereof with reference to the accompanying drawings in detail with share bit lines sensor amplifier mechanism according to illustrative examples of the present invention.
Fig. 3 is the circuit diagram according to the DRAM core of one embodiment of the invention.
Referring to Fig. 3, DRAM comprises bit line sense amplifier, upper bit line switching units 42, lower bit line switching units 46, upper bit line balanced unit 40, and lower bit line balanced unit 48.Bit line sense amplifier amplifies last data putting on the bit line that is connected to upper cell array CELL ARRAY0 or lower unit array CELL ARRAY1.Upper bit line switching units 42 makes bit line sense amplifier from the bit line of cell array CELL ARRAY0 BLU and BLBU be gone up the selectivity disconnection in response to upper bit line cut-off signal BISH.Lower bit line switching units 46 makes bit line sense amplifier from the bit line of cell array CELL ARRAY1 BLD and BLBD be gone up the selectivity disconnection in response to lower bit line cut-off signal BISL.Upper bit line balanced unit 40 makes the bit line of cell array CELL ARRAY0 to BLU and BLBU equilibrium in response to lower bit line cut-off signal BISL.Lower bit line balanced unit 48 makes the bit line of cell array CELLARRAY1 to BLD and BLBD equilibrium in response to upper bit line cut-off signal BISH.
Upper bit line switching units 42 comprises nmos pass transistor M8 and the M9 with the grid that receives upper bit line cut-off signal BISH, and makes upper bit line be connected with bit line sense amplifier/disconnect BLU and BLBU.
In addition, lower bit line switching units 46 comprises nmos pass transistor M10 and the M11 with the grid that receives lower bit line cut-off signal BISL, and makes lower bit line be connected with bit line sense amplifier/disconnect BLD and BLBD.
Bit line sense amplifier comprises being connected in and draws pressure-wire (RTO line) and bit line to two PMOS transistors between BL and the BLB, and is connected in actuation voltage line SB and bit line to two nmos pass transistors between BL and the BLB.Column selection unit 44 comprises two nmos pass transistors with the grid that receives array selecting signal CY, and bit line is connected SIO and SIOB selectivity with the sector data bus BL and BLB.
Fig. 4 is the circuit diagram that is used for producing the bit line control circuit of the upper bit line cut-off signal of Fig. 3 and lower bit line cut-off signal.
Referring to Fig. 4, bit line control circuit comprises block controller 200 and bit line cut-off signal generator 210.Block controller 200 reception area block address signal AX select signal BS_0 and BS_1 to produce corresponding to the block of memory cell array.Bit line cut-off signal generator 210 is selected signal BS_0 and BS_1 and is produced bit line cut-off signal BISH and BISL in response to block.
Compare with the prior art shown in Fig. 1, bit line control circuit of the present invention does not comprise bit line equalizing signal generator 120.Reason is that bit line equalization unit 40 and 48 is by bit line cut-off signal BISH and BISL control, rather than control by bit line equalizing signal BLEQ.
Bit line cut-off signal generator 210 comprises: upper bit line cut-off signal generator, and it is used for producing upper bit line cut-off signal BISH in response to lower region block selection signal BS_1; And lower bit line cut-off signal generator, it is used for producing lower bit line cut-off signal BISL in response to upper zone block selection signal BS_0.
Upper bit line cut-off signal generator comprises the inversion device INV1 that receives lower region block selection signal BS_1, and the level shifter LS1 of the activation level of the output signal of increase inversion device INV1, and lower bit line cut-off signal generator comprises the inversion device INV3 that is used to receive upper zone block selection signal BS_0, and is used to increase the level shifter LS2 of activation level of the output signal of inversion device INV3.
In level shifter LS1, two PMOS transistor MP1 and MP2 have the source electrode that is connected to high voltage end VPP, and cross connection grid and drain electrode together.Nmos pass transistor MN1 have the drain electrode that is connected to PMOS transistor MP1 drain electrode, be connected to the source electrode of input end N1, and receive the grid of supply voltage VDD.Nmos pass transistor MN2 have the drain electrode that is connected to PMOS transistor MP2 drain electrode, be connected to the source electrode of earth terminal VSS, and be connected to the grid of input end N1.Inversion device INV2 is connected to the drain electrode of PMOS transistor MP2.
Use known circuits to make up level shifter LS1 and LS2.The reason of using level shifter LS1 and LS2 to produce bit line cut-off signal BISH and BISL is: consider the loss of threshold voltage, drive bit line with the high voltage VPP that is higher than supply voltage VDD and disconnect transistor.
Fig. 5 A to 5C shows the bit line equalization unit 40 of Fig. 3 and 48 circuit diagram respectively.
Referring to Fig. 5 A, bit line equalization unit 40 and 48 comprises: nmos pass transistor has the grid that receives bit line cut-off signal BIS, and is connected in bit line between BL and the BLB; And two nmos pass transistors, have the grid that receives bit line cut-off signal BIS, and be connected in bit-line pre-charge voltage VBLP (general VBPL=Vdd/2) and bit line between BL and the BLB.
Referring to Fig. 5 B, bit line equalization unit 40 and 48 comprises two nmos pass transistors, has the grid that receives bit line cut-off signal BIS, and is connected in bit-line pre-charge voltage VBLP (being generally Vdd/2) and bit line between BL and the BLB.
Referring to Fig. 5 C, bit line equalization unit 40 and 48 comprises a MOS transistor, has the grid that receives bit line cut-off signal BIS, and is connected in bit line between BL and the BLB.
In Fig. 5 A and 5B, bit-line pre-charge voltage VBLP be applied to upper bit line balanced unit 40 and lower bit line balanced unit 48 the two.On the contrary, in Fig. 5 (C), bit-line pre-charge voltage VBLP is applied in upper bit line balanced unit 40 and the lower bit line balanced unit 48.
Because be in logic level HIGH at pre-charge state middle and upper part bit line cut-off signal BISH and lower bit line cut-off signal BISL, so nmos pass transistor M8 to M11 is switched on.Bit line equalization unit 40 and all nmos pass transistors of 48 also are switched on.
When applying activation command and selected cell array CELL ARRAY0, block selects signal BS_0 and BS_1 to become logic level HIGH and logic level LOW respectively.Select in the combination of signal BS_0 and BS_1 at block, upper bit line cut-off signal BISH keeps logic level HIGH.Therefore, all nmos pass transistors of the nmos pass transistor M8 of upper bit line switching units 42 and M9 and lower bit line balanced unit 48 also are switched on.Simultaneously, lower bit line cut-off signal BISL is logic level LOW by deactivation, so that all nmos pass transistors of the nmos pass transistor M10 of lower bit line switching units 46 and M11 and upper bit line balanced unit 40 are cut off.
On the contrary, when selecting cell array CELL ARRAY1, block selects signal BS_0 and BS_1 to become logic level LOW and logic level HIGH respectively.Therefore, lower bit line cut-off signal BISL keeps logic level HIGH.Therefore, the also conducting of all nmos pass transistors of the nmos pass transistor M10 of lower bit line switching units 46 and M11 and upper bit line balanced unit 40.Simultaneously, upper bit line cut-off signal BISH is logic level LOW by deactivation, so that all nmos pass transistors of the nmos pass transistor M8 of upper bit line switching units 42 and M9 and lower bit line balanced unit 48 end.
As indicated above, even using the bit line cut-off signal to control under the situation of bit line balanced unit, but also normal running memory storage.That is, do not need additional circuit to produce bit line equalizing signal.
According to the present invention, can simplify bit line control circuit, thereby reduce the storage chip area.
The application's case contains and korean patent application case 2005-90956 number and 2005-133985 number relevant purport in the application of Korean Patent office on September 29th, 2005 and on Dec 29th, 2005 respectively, and the full text of these patent application cases is incorporated herein by reference.
Though described the present invention about some preferred embodiment, it will be appreciated by those skilled in the art that, under situation about not deviating from, can make various changes and modification by the defined scope of the present invention of appended claims.
Claims (11)
1. semiconductor storage, it comprises:
Bit line sense amplifier is used for to putting on bit line last data being amplified;
The upper bit line switching units is used in response to the upper bit line cut-off signal bit line sense amplifier being disconnected to last selectivity from the bit line of upper cell array;
The lower bit line switching units is used in response to the lower bit line cut-off signal bit line sense amplifier being disconnected to last selectivity from the bit line of lower unit array;
The upper bit line balanced unit is used for making in response to the lower bit line cut-off signal bit line of upper cell array to equilibrium;
The lower bit line balanced unit is used for making in response to the upper bit line cut-off signal bit line of lower unit array to equilibrium;
Lower bit line cut-off signal generator is used for producing this lower bit line cut-off signal in response to selecting signal with corresponding first block of this upper cell array; And
Upper bit line cut-off signal generator is used for producing this upper bit line cut-off signal in response to selecting signal with corresponding second block of this lower unit array,
Wherein this bit line sense amplifier, this upper bit line switching units, this lower bit line switching units, this upper bit line balanced unit and this lower bit line balanced unit are arranged in the cellar area.
2. semiconductor storage according to claim 1 also comprises the column selection unit, and described column selection unit is used for making in response to array selecting signal described bit line pair with the sector data bus selectivity to be connected.
3. semiconductor storage according to claim 1, wherein, this upper bit line switching units comprises first and second nmos pass transistor, this first and this second nmos pass transistor have the grid that receives this upper bit line cut-off signal, and make this bit line of this upper cell array pair be connected/disconnect with this bit line sense amplifier.
4. semiconductor storage according to claim 3, wherein, this lower bit line switching units comprises the 3rd and the 4th nmos pass transistor, the the 3rd and the 4th nmos pass transistor has the grid that receives this lower bit line cut-off signal, and makes this bit line of this lower unit array pair be connected/disconnect with this bit line sense amplifier.
5. semiconductor storage according to claim 1, wherein, this lower bit line cut-off signal generator comprises:
First inversion device, it is used to make this first block to select the signal counter-rotating; And
First level shifter, it is used to increase the activation level of the output signal of this first inversion device.
6. semiconductor storage according to claim 5, wherein, this upper bit line cut-off signal generator comprises:
Second inversion device, it is used to make this second block to select the signal counter-rotating; And
Second level shifter, it is used to increase the activation level of the output signal of this second inversion device.
7. semiconductor storage according to claim 6, wherein, this first and this second level shifter in each comprise:
First and second PMOS transistor has the source electrode and cross connection grid and the drain electrode together that are connected to high voltage end VPP;
First nmos pass transistor, it has the drain electrode that is connected to a PMOS transistor drain, the source electrode that is connected to input end, and receives the grid of supply voltage;
Second nmos pass transistor, it has the drain electrode that is connected to the 2nd PMOS transistor drain, the source electrode that is connected to earth terminal, and is connected to the grid of this input end; And
The 3rd inversion device, it is connected to the 2nd PMOS transistor drain.
8. semiconductor storage according to claim 1, wherein, this upper bit line balanced unit comprises first nmos pass transistor, and this first nmos pass transistor has the grid that receives this lower bit line cut-off signal, and it is right to be connected to this bit line of this upper cell array.
9. semiconductor storage according to claim 1, wherein, this lower bit line balanced unit comprises first nmos pass transistor, and this first nmos pass transistor has the grid that receives this upper bit line cut-off signal, and it is right to be connected to this bit line of this lower unit array.
10. semiconductor storage according to claim 1, wherein, this top/this lower bit line balanced unit comprises first and second nmos pass transistor, this first and this second nmos pass transistor have the grid that receives this bottom/upper bit line cut-off signal, and this bit line that is connected in bit-line pre-charge voltage and this top/this lower unit array between.
11. semiconductor storage according to claim 1, wherein, this top/this lower bit line balanced unit comprises:
First nmos pass transistor, it has the grid that receives this bottom/upper bit line cut-off signal, and this bit line that is connected in this top/this lower unit array between; And
Second and third nmos pass transistor, it has the grid that receives this bottom/upper bit line cut-off signal, and this bit line that is connected in bit-line pre-charge voltage and this top/this lower unit array between.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20050090956 | 2005-09-29 | ||
| KR90956/05 | 2005-09-29 | ||
| KR1020050133985A KR100668512B1 (en) | 2005-09-29 | 2005-12-29 | Semiconductor memory device having shared bit line sense amplifier scheme and driving method thereof |
| KR133985/05 | 2005-12-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1941193A CN1941193A (en) | 2007-04-04 |
| CN1941193B true CN1941193B (en) | 2010-05-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101592187A Expired - Fee Related CN1941193B (en) | 2005-09-29 | 2006-09-22 | Semiconductor memory device and driving method thereof |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR100668512B1 (en) |
| CN (1) | CN1941193B (en) |
| TW (1) | TWI337361B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101198252B1 (en) | 2010-08-31 | 2012-11-07 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
| CN107452418A (en) * | 2016-06-01 | 2017-12-08 | 华邦电子股份有限公司 | Semiconductor memory system |
| CN114155896B (en) * | 2020-09-04 | 2024-03-29 | 长鑫存储技术有限公司 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4701937A (en) * | 1985-05-13 | 1987-10-20 | Industrial Technology Research Institute Republic Of China | Signal storage and replay system |
| CN1108788A (en) * | 1993-09-10 | 1995-09-20 | 株式会社东芝 | Storage device for semiconductor |
| US6104653A (en) * | 1999-02-13 | 2000-08-15 | Integrated Device Technology, Inc. | Equilibration circuit and method using a pulsed equilibrate signal and a level equilibrate signal |
| US6333869B1 (en) * | 2000-07-06 | 2001-12-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with readily changeable memory capacity |
| US6661714B2 (en) * | 2001-06-30 | 2003-12-09 | Samsung Electronics Co., Ltd. | Integrated circuit memory devices having sense amplifiers therein that receive nominal and boosted supply voltages when active and methods of operating same |
-
2005
- 2005-12-29 KR KR1020050133985A patent/KR100668512B1/en not_active IP Right Cessation
-
2006
- 2006-06-30 TW TW095123944A patent/TWI337361B/en not_active IP Right Cessation
- 2006-09-22 CN CN2006101592187A patent/CN1941193B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4701937A (en) * | 1985-05-13 | 1987-10-20 | Industrial Technology Research Institute Republic Of China | Signal storage and replay system |
| CN1108788A (en) * | 1993-09-10 | 1995-09-20 | 株式会社东芝 | Storage device for semiconductor |
| US6104653A (en) * | 1999-02-13 | 2000-08-15 | Integrated Device Technology, Inc. | Equilibration circuit and method using a pulsed equilibrate signal and a level equilibrate signal |
| US6333869B1 (en) * | 2000-07-06 | 2001-12-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with readily changeable memory capacity |
| US6661714B2 (en) * | 2001-06-30 | 2003-12-09 | Samsung Electronics Co., Ltd. | Integrated circuit memory devices having sense amplifiers therein that receive nominal and boosted supply voltages when active and methods of operating same |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI337361B (en) | 2011-02-11 |
| TW200713306A (en) | 2007-04-01 |
| KR100668512B1 (en) | 2007-01-12 |
| CN1941193A (en) | 2007-04-04 |
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