1336526 P950164 22006twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明枝關於-種半導體元件崎作方法，且 是有關於一種用於非揮發記憶體之多位準記憶胞 (multi-level cell，MLC)的操作方法。 【先前技術】 在各種記憶體產品中，具有可進行多次資料之存入、 讀取、抹除等動作’且具有存入的資料在斷電後也不會消 失之優點的非揮發性s己憶體，已成為個人電腦和電子設備 所廣泛採用的一種記憶體元件。 & 一典型的非揮發性記憶體僅能夠儲存「〇」和「丨」兩種 資料狀態，而為一種單記憶胞單位元(i bit/cell)儲存的記憶 ，。在璜取記憶體的資料時，會將閘極電壓設於， 田Vread大於5己憶體的b界電壓(threshold voltage，Vt)時， $有電流流經記憶體的源極與汲極，則判定此狀態為i ; 田Vread小於記憶體的臨界電壓時，沒有電流流經記憶體 的源極與汲極，則判定此狀態為〇。 〜 “ 近年來，P现著向禮、度的記憶體元件的發展，非揮發性 =憶體的每-記憶胞能夠儲存超過一位元，即所謂的多位 二己憶體元件。此種記憶體每單一記憶胞具有二位元以上 斜二料儲存’如此可於相同的晶片面積下增加其資 料Z的选度。為了於每-記憶胞内儲存二位元以上的資 胞可被程式化為22階，即4階。在此，4階 界麵分簡應出⑻、(h、1G、n的4_存狀態。 5 1336526 P950164 22006twf.doc/n1336526 P950164 22006twf.doc/n IX. Description of the invention: [Technical field of the invention] The present invention relates to a semiconductor device, and relates to a multi-level memory cell for non-volatile memory (multi -level cell, MLC) operation method. [Prior Art] Among various memory products, there are non-volatile s which can perform the operations of storing, reading, erasing, etc., multiple times of data, and having the advantage that the stored data does not disappear after power-off. It has become a memory component widely used in personal computers and electronic devices. & A typical non-volatile memory can only store two data states, "〇" and "丨", and is a memory stored in a single memory unit (i bit/cell). When extracting the data of the memory, the gate voltage is set to be. When the Vread is greater than the threshold voltage (Vt) of the 5th memory, the current flows through the source and the drain of the memory. Then, it is determined that this state is i; when the field Vread is smaller than the threshold voltage of the memory, no current flows through the source and the drain of the memory, and the state is determined to be 〇. ~ "In recent years, P is now developing the memory components of ritual and degree. Non-volatile = memory cells can store more than one bit per cell, so-called multi-bit two-remembered components. The memory has two bits or more of oblique storage for each single memory cell. This can increase the selection of the data Z under the same wafer area. In order to store more than two bits per memory, the program can be programmed. It is turned into 22 orders, that is, 4th order. Here, the 4th-order interface is divided into (4), (h, 1G, n, 4_ state. 5 1336526 P950164 22006twf.doc/n
然而’多位準記憶體元件的每一記憶胞在進行程式化 ，，無法精確地控制注入之電子的數量，因此各個儲存狀 態之記憶胞臨界電壓分佈曲線甚廣，而容易在讀取時發生 誤判。而且，由於記憶胞的程式化操作通常是以程式化時 間長短來控制臨界電壓，因此並不容易精確地到達目標^ 式化^^ 界電麼(target programming Vt)。 由於，上述之記憶胞操作的問題會影響元件效能，且 會造成元件的可靠度(reliability)降低。因此，如何改善此 問已成為業界積極發展的課題之一。 【發明内容】 有鑑於此，本發明的目的就是在提供—種多位準記憔 月匕的操作方法，能夠有效改善先前技術之問題，以提高元 件效能However, each memory cell of a multi-level memory device is programmed to accurately control the amount of electrons injected. Therefore, the memory cell threshold voltage distribution curve of each storage state is very wide, and it is easy to occur during reading. Misjudgment. Moreover, since the stylized operation of the memory cell usually controls the threshold voltage in terms of the length of the stylized time, it is not easy to accurately reach the target programming Vt. Since the above-mentioned problem of memory cell operation affects component performance, the reliability of the component is lowered. Therefore, how to improve this question has become one of the topics actively developed by the industry. SUMMARY OF THE INVENTION In view of the above, the object of the present invention is to provide a multi-position operation method capable of effectively improving the problems of the prior art to improve the component performance.
^ 本發明提出一種多位準記憶胞的操作方法。此多位準 2憶胞包括基底、控制閘極、位於基底與控制閘極之間的 1荷儲存層，以及位於基底中的二源成極區。此操作方 :⑻操作多位準記憶胞，至多鱗記憶胞的—臨界 书姿大於預先程式化臨界電壓；以及⑻操作多位準記恨 臉’至多位準記憶胞_界電壓大於目標程式化臨界^ 胞 壓 於預先程式化臨界電壓 依照本發明的實施例所述之多位準記憶胞的操作方 作接ί迷之步驟⑷的操作為，程式化操作。其中，此程式 注•顧道熱電子(CHE)注入法，電子 入去或雙邊偏壓(DSB)電子注入法來進行。 6 1336526 P950164 22006twf.doc/n 依‘日、?、本發明的實施例所述之多位準記憶胞的操作方 法，上述之步驟(C)的操作為一軟抹除操作。其中，此軟抹 除操作可例如是，利用帶對帶熱電洞(BTBHH)注入法、FN 電子排除法或雙邊偏壓電洞注入法來進行。 、 依照本發明的實施例所述之多位準記憶胞的操作方 法’在步驟(a)之後以及步驟(b)之前，更包括進行(c)進行一 第^驗證步驟，若步驟(a)之臨界電壓小於預先程式化臨界 ，壓則重複步驟(a)。上述之步驟(c)的第一驗證步驟例如 是進行一讀取操作，由多位準記憶胞的讀取電壓，判斷 步驟(a)之臨界電壓是否大於預先程式化臨界電壓。 依照本發明的實施例所述之多位準記憶胞的操作方 心Ϊ步驟⑼之後’更包括：（d)進行—第二驗證步驟，若 二()之臨界㈣大於預先程式化臨界電壓則重複步驟 複牛Iff驟⑻之臨界電壓小於目標程式化臨界電壓則重 二，(a)〜(d)。上述之步驟(d)的第二驗證步驟例如是， 作’由多位準記憶胞的讀取電壓，判斷步驟⑼ ==是否大於目標程式化臨界電壓、小於預先:式 =本^的實施例所述之多位準記 奈米荷儲存射例如是浮置閘極、電荷補^ = 積體電ΐ@❹‘胃胞作储存資料的 电格此積體電路包括：半導體基底 ^ 陣列、偏墨調整狀態器以及電路系統。复夕，己憶胞 /、甲，多位準記憶 7 P950164 22006twf.doc/n 胞陣列減至半導:ft基底。偏壓調整狀態器可用以操作陣 列的多位準記憶胞，至多位準記憶胞的臨界電壓大於預先 程式化臨界電壓。電m祕轉㈣乡鱗記憶胞， 而電路系統適用於在多個特定持續時間其中之一對^特定 ^續時間雛電壓至-個或更多個多位準記憶胞，其中在 這些特找續時間其巾之對麟定持續時間内具有可儲存 在多位準記憶胞上的資料值其中之對應資料值。而且，電 路系、”先至：>、包括與陣列竊接之行解碼器與列解碼器，以及 與行2碼器耦接之感測放大器/資料輸入結構。其中，感測 放大器/資料輸入結構用以操作陣列的多位準記憶胞，至多 位準記憶胞的該臨界電壓大於目標程式化臨界電壓、小於 預先程式化臨界電壓。 、 依照本發明的實施例所述之使用多位準記憶胞作儲 存資料的積體電路，上述行解碼器與列解碼器是用以讀取 陣列的多位準記憶胞的電壓。 次依照本發明的實施例所述之使用多位準記憶胞作儲 存=料的積體電路，上述多位準記憶胞的電荷儲存層可例 如是浮置閘極、電荷補陷層或奈米晶粒層。 由於，本發明是先使記憶胞的臨界電壓大於預先程式 =臨界電壓，然後將記憶胞的臨界電壓操作在預先程式化 臨界電壓與目標程式化臨界電壓之間，如此可使記憶胞可 精峰地到達目標程式化臨界電壓(target programming Vt)。 而·^，本發明之方法可使各儲存狀態的記憶胞臨界電壓分 佈範圍變窄’從而降低讀取時誤判的可能性。 1336526 P950164 22006twf.doc/n 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉較佳實施例’並配合所附圖式，作詳細說 明如下。 【實施方式】 本發明之多位準記憶胞的操作方法所適用之記憶胞 中的電荷儲存層例如是浮置閘極、電荷補陷 (charge-trapping)層或奈米晶粒(nan〇_crystal)層。浮置問的 材質常為摻雜複晶矽，電荷補陷層的材質常為氮化矽，奈 米晶粒層則包括位在一絕緣層中的許多分離的導體材料^ 米晶粒。本實施例雖僅以使用電荷補陷層的記憶胞作說 明，但具此領域巾通常知識者應可*本實_之說明推 知’本發明亦適用於使用浮置閘極或奈米晶粒層來儲存資 料的非揮發性之多位準記憶胞。 =圖1，其為依照本發明之實施例所繪示的多位 ，己憶胞的示意圖。本實施例之記憶胞⑽包 底102,依序向上堆疊的底氧化層刚、作為 二 W層廳、頂氧化層⑽與控制閉極11〇，以及= 110兩側之基底102中的N型的源極區112愈』 區114。此外，以浮置閘極為電荷儲存層之 /、及極 ί!10Γ106'108 ==間介電層而得者;以奈米晶粒 ;= 己憶胞的一例，則是將106換成内含許 存層 氧化碎層而得者。 '、y、夕日日粒的 接下來’說明本發明之多位準記憶胞的操作方法。以 9 P950164 22006twf.d〇c/n 平此肊一位兀(2 blts/cell)儲存 位準記憶胞_的〇〇、0卜10、116^二!脉賴夕 古一 1 川11的4種儲存狀態，分別具 ,7 (pre-programming threshold th 以5 S才示程式化臨界電壓細⑽programming S 0 votage)’且每-儲存綠態_先程式化臨界電 [比目標程式化臨界電壓稍大，其二者差值約為〇1〜〇5 ，特。上述’多位準記憶胞巾的每—種儲存狀態之 式可如下所示。 咕參照圖2 ’其為依照本發明之實補崎示的多位 準記憶胞的㈣方法流糊。首先，使記⑽的臨界電壓 (vt)大於預先程式化臨界電壓(步驟2〇2)。在步驟2〇2中， 可對記憶胞進行-程式化(program)操作，直至記 界電壓大於預先程式化臨界電壓。 ⑽ 接著，請繼續參照圖2，在步驟202之後，可進行第 「驗證步驟(步驟204)。上述，第一驗證步驟例如是，利用 進行一讀取操作，並由記憶胞的讀取電壓，來判斷步驟 的臨界電壓是否大於預先程式化臨界電壓。在步驟2〇4 中，若記憶胞的臨界電壓大於預先程式化臨界電壓，則繼 續下一步驟；相反地，若記憶胞的臨界電壓小於弁 化臨界電壓，則重複步驟202。 隨後，使記憶胞的臨界電壓大於目標程式化臨界電 壓、小於預先程式化臨界電壓(步驟206)。在步驟2〇6中， 可對記憶胞進行一軟抹除(soft-erasing)操作，直至記憶胞的 臨界電壓大於目標程式化臨界電壓、小於預先程式化臨界 P950164 22006twf.doc/n 電壓。值传注意的是’在步驟206中可使臨界電壓往下修 正’而收斂到接近目標程式化臨界電壓。 然後’清繼續參照圖2 ’在步驟206之後，可進行第 二驗證步驟(步驟208)。上述，第二驗證步驟例如是，利用 進行一讀取操作，並由記憶胞的讀取電壓，來判斷步驟2 〇 6 之臨界電壓是否介於預先程式化臨界電壓與目標程式化臨 界電壓之間。在步驟208中，若記憶胞的臨界電壓介於預 先辁式化臨界電壓與目標程式化臨界電壓之間，則即可完 成此操作（步驟210)。相反地，若記憶胞的臨界電壓大於^ 先程式化臨界，難複步驟綱；而若記憶胞的臨界 電壓小於目標程式化臨界電壓，則重複步驟2⑽〜2〇8。 特別要說明的是，本發明之操作方法為，先使記憶胞 的臨界電壓大於程式化臨界電壓，然後再將記憶胞的 &界電壓_在介於預絲式化臨界霞與目桿程臨 ^電壓1，如此可使鋪歧為射㈣達目標程式化 =電壓，、而且’本發明之方法亦可使各儲存狀態的記憶 _界電壓分佈範圍變窄，從而降低讀取時誤判的可能性。 列舉圖3A與圖3B之實施例詳細說明本發明之 細作方法中的程式化操作以及敕抹除操作。 2關从，其_本實_之多位準記憶胞的操 乍方法中的㈣化步驟，其是利用雙邊偏壓(dQubie - ias，DSB)電子注人法來進行^此程式化步驟包括 ’在基 顏2上施加0V ’在源極區112、沒極區ιΐ4上施加高於 0V的源極電塵Vs、沒極電麗Vd(=Vs)，且在控制間極ιι〇 1336526 P950164 22006twf.d〇c/n 亡=於〇v的閘極電壓Vg。其中，源極電壓Vs例如 電壓Vd例如是4〜6V，間極電壓W例如 源極電壓Vs、汲極電壓Vd之大小足以 =電 電· 可使電電上施加的陶壓㈣ 操作::之4 ’其繪示本發明之多位準記憶胞的 在 旱°己匕1具有對應4個位準的4個儲 ==儲存2位元的資料，其中位準由高至低:: 弟=儲存態例如分別對應〇〇、W、i〇、u之資料值第 先二的平行虛線係對應記憶胞中的儲存狀態之預 電昼大於預先程式化臨界電壓。 胞的:方、^^ 3B ’其繪示本實補之多位準記憶 入法二3抹除步驟’其是利用雙邊偏壓電洞注 在包括，在基底102上施加〇v， 沒極電壓且1 上施加高於GV的源極電壓％、 )在控制閘極110上施加低於或等;^ 電壓々。其中，源極電壓Vs例如是4〜6V ί 極電壓％ ，閘極電壓％例如是_5〜〇v。源 ”之大小足以在基底1G2中產_ g則ΊΓ使電洞注入電荷儲存層中。 12 P950164 22〇〇6twf.doc/] 操作=之繪示r明之多位準記憶胞的 而可儲n 祕有觀4値料4個儲存狀態， 儲70的貧料’其中位準由高至低之第一至第四 ff態例如分別對應GG、n 11之資料值。另外，圖 儲存線（—）、（…）是分別對應記憶胞中的 2狀態之預先程式化臨界電壓與目標程式化臨界電壓。 臨二日可軟抹除至臨界電壓介於預先程式化 標程=臨=式化臨界電壓之間’而收敛至到接近目 cornel：外^在本發明之操作方法中，可利用通道熱電子 帶航i 行步驟術之程式化操作，以及利用帶對 帶熱電洞(㈣冊)注入法進行_ 206之軟抹除摔作。 摔T其是綠示本實施例之多位準記憶胞的 Ϊ作方法巾的程式化步驟，其是利㈣絲電子注入法來 進行。此程式化操作例如是，在基底1〇2上施加〇ν，在源 :施力口 〇V，在沒極區114上施加高於0V的汲極 電愚Vd，其例如是4〜6V左右，且在控制閘極ιι〇上施 加向於ον的閘極電虔Vg，其例如是8〜12v左右，以所 產生的電子由源極區112注入電荷儲存層中。另外，許表 照圖6B’其是緣示本實施例之多位準記憶胞的操作方^ 的軟抹除步驟，其是利用帶對帶熱電洞注入法來進行。此 軟抹除操作例如是，在基底搬上施加〇v，在源極區n2 上施加ον，在沒極區114上施加高㈣v較極電愿別， 13 1336526 P950164 22006twf.d〇c/n 其例如是4〜6V左太，B + “ 的閘極電壓Vg，JL例如a '㈣極11G上施加低於〇V 雜極區⑽生的電 儲存層之記之’對以浮置閘極為電荷 202之鋥切利用别電子注入法進行步驟 之軟抹除操作以及利用抓電子排除法進行步驟挪^ The present invention proposes a method of operating a multi-level memory cell. The multi-level memory cell includes a substrate, a control gate, a 1-load storage layer between the substrate and the control gate, and a two-source formation region in the substrate. The operator: (8) operating a multi-level memory cell, the maximum critical book memory is greater than the pre-programmed threshold voltage; and (8) operating the multi-bit memory hate face to the multi-level memory cell boundary voltage is greater than the target stylization threshold The operation of the step (4) of the operation of the multi-level memory cell according to the embodiment of the present invention is a stylized operation. Among them, this program is required to be carried out by means of a hot electron (CHE) injection method, an electron in or double side bias (DSB) electron injection method. 6 1336526 P950164 22006twf.doc/n According to the operation method of the multi-level memory cell described in the embodiment of the present invention, the operation of the above step (C) is a soft erase operation. Here, the soft erase operation can be performed, for example, by a belt-to-belt thermal hole (BTBHH) injection method, an FN electron removal method, or a bilateral bias hole injection method. The method for operating a multi-level memory cell according to an embodiment of the present invention, after step (a) and before step (b), further comprises performing (c) performing a verification step, if step (a) The threshold voltage is less than the pre-programmed threshold, and the pressure is repeated in step (a). The first verification step of the above step (c) is, for example, performing a read operation for judging whether the threshold voltage of the step (a) is greater than the pre-programmed threshold voltage by the read voltage of the plurality of bit memory cells. The operation of the multi-level memory cell according to the embodiment of the present invention after the step (9) further includes: (d) performing a second verification step, if the threshold (4) of the second () is greater than the pre-programmed threshold voltage Repeating the steps of the complex cow Iff (8) The threshold voltage is less than the target stylized threshold voltage and then weighs two, (a) ~ (d). The second verification step of the above step (d) is, for example, an embodiment in which the read voltage of the multi-level memory cell is judged whether the step (9) == is greater than the target stylized threshold voltage, and less than the previous formula: The multi-bit register nano-load storage device is, for example, a floating gate, a charge-complementing body, an integrated body, and a gas-filled cell. The integrated circuit includes: a semiconductor substrate, an array, and a partial Ink adjustment stater and circuitry. On the eve, reminiscent of cells /, A, multiple quasi-memory 7 P950164 22006twf.doc / n cell array reduced to semi-conductive: ft substrate. The bias adjustment stater can be used to operate the array of multi-level memory cells, with the threshold voltage of the most-level memory cells being greater than the pre-programmed threshold voltage. The electric m secret turns (4) the township scale memory cell, and the circuit system is adapted to use one of a plurality of specific durations to determine the voltage to one or more multi-level memory cells, among which The continuation time has a corresponding data value of the data value that can be stored on the multi-level memory cell for the duration of the lining. Moreover, the circuit system, "first come:", includes a row decoder and column decoder that is spliced with the array, and a sense amplifier/data input structure coupled to the line coder. Among them, the sense amplifier/data The input structure is configured to operate the multi-level memory cells of the array, and the threshold voltage of the plurality of level memory cells is greater than the target programmed threshold voltage and less than the pre-programmed threshold voltage. The multi-level is used according to an embodiment of the present invention. The memory cell is an integrated circuit for storing data, and the row decoder and the column decoder are for reading the voltage of the multi-level memory cell of the array. The multi-level memory cell is used according to the embodiment of the present invention. The charge storage layer of the multi-level memory cell may be, for example, a floating gate, a charge trap layer or a nano-grain layer. Since the present invention first makes the threshold voltage of the memory cell larger than Pre-program = threshold voltage, and then operate the threshold voltage of the memory cell between the pre-programmed threshold voltage and the target programmed threshold voltage, so that the memory cell can reach the target stylized The target voltage (target programming Vt). However, the method of the present invention can narrow the range of the memory cell threshold voltage in each storage state, thereby reducing the possibility of misjudgment during reading. 1336526 P950164 22006twf.doc/n The above and other objects, features, and advantages of the present invention will become more apparent from the <RTIgt The charge storage layer in the memory cell to which the method of operation is applied is, for example, a floating gate, a charge-trapping layer or a nano-crystal layer. The material of the floating method is often doped. The material of the charge trap layer is usually tantalum nitride, and the nano grain layer includes a plurality of separated conductor materials in an insulating layer. The memory cells of the layer are described, but those who have the knowledge of this field should be able to use the description of the present invention. The invention is also applicable to the non-volatile use of floating gate or nano-grain layer to store data. Level memory cell = Figure 1, its A schematic diagram of a plurality of bits, a memory cell, in accordance with an embodiment of the present invention. The memory cell (10) of the present embodiment includes a bottom oxide layer that is sequentially stacked upward, and a double W layer chamber and a top oxide layer (10). And the control of the closed-pole 11〇, and the N-type source region 112 in the substrate 102 on both sides of the 110----------------------------------------------------------------------- = between the dielectric layer; in the case of nanocrystalline grains; = one of the cells, it is replaced by 106 with the inclusion of a layer of oxidized fragments. ', y, the next day of the sun 'Describe the operation method of the multi-level memory cell of the present invention. 9 P950164 22006twf.d〇c/n is equal to one 兀 (2 blts/cell) storing the level memory cell _ 〇〇, 0 卜 10, 116^二! The four storage states of the pulse Laiyuegu 1 Sichuan 3, respectively, 7 (pre-programming threshold th shows the programmed voltage threshold (5) programming S 0 votage) and each storage green state _ First stylized critical power [slightly larger than the target stylized threshold voltage, the difference between the two is about 〇1~〇5, special. The above-mentioned storage state of the multi-level memory cell can be as follows. Referring to Fig. 2', it is a (four) method flow paste of a multi-level memory cell according to the present invention. First, the threshold voltage (vt) of the note (10) is made larger than the pre-programmed threshold voltage (step 2〇2). In step 2〇2, the memory cell can be programmed to operate until the threshold voltage is greater than the pre-programmed threshold voltage. (10) Next, please continue to refer to FIG. 2. After step 202, a "verification step (step 204) may be performed. For example, the first verification step is performed by performing a read operation and reading voltage by the memory cell, To determine whether the threshold voltage of the step is greater than the pre-programmed threshold voltage. In step 2〇4, if the threshold voltage of the memory cell is greater than the pre-programmed threshold voltage, proceed to the next step; conversely, if the threshold voltage of the memory cell is less than After the threshold voltage is ramped up, step 202 is repeated. Subsequently, the threshold voltage of the memory cell is greater than the target programmed threshold voltage and less than the pre-programmed threshold voltage (step 206). In step 2〇6, the memory cell can be softened. Soft-erasing operation until the threshold voltage of the memory cell is greater than the target stylized threshold voltage and less than the pre-programmed critical P950164 22006twf.doc/n voltage. The value is noted that 'the threshold voltage can be made in step 206. The next correction 'converges to near the target stylized threshold voltage. Then 'clear continues with reference to Figure 2' after step 206, a second verification step can be performed (step Step 208). The second verification step is, for example, determining whether the threshold voltage of step 2 〇6 is between the pre-programmed threshold voltage and the target stylization by performing a read operation and reading voltage of the memory cell. Between the threshold voltages, in step 208, if the threshold voltage of the memory cell is between the pre-pushed threshold voltage and the target programmed threshold voltage, then the operation can be completed (step 210). Conversely, if the memory cell The threshold voltage is greater than the first stylized threshold, and the step of the step is difficult; if the threshold voltage of the memory cell is less than the target stylized threshold voltage, steps 2(10) to 2〇8 are repeated. In particular, the method of operation of the present invention is First, the threshold voltage of the memory cell is greater than the stylized threshold voltage, and then the voltage & boundary voltage of the memory cell is between the pre-filamentization critical wave and the target path, and the voltage is 1 (4) reaching the target stylization = voltage, and the method of the present invention can also narrow the memory_boundary voltage distribution range of each storage state, thereby reducing the possibility of misjudgment during reading. 3A and 3B are listed. The embodiment details the stylization operation and the erasing operation in the detailed method of the present invention. 2) The (four) step in the operation method of the multi-level memory cell of the present invention is to use the bilateral bias Pressing (dQubie - ias, DSB) electronic injection method ^This stylization step includes 'applying 0V on base 2' to apply source electric dust Vs higher than 0V on source region 112 and immersion region ιΐ4极无电丽Vd(=Vs), and in the control room ιι〇1336526 P950164 22006twf.d〇c/n 死 = 闸V gate voltage Vg, wherein the source voltage Vs such as voltage Vd is, for example, 4 ~6V, the inter-electrode voltage W, for example, the source voltage Vs, the drain voltage Vd is large enough to be = electric power, the ceramic pressure applied on the electric power (4) Operation: 4', which shows the multi-level memory cell of the present invention In the drought, 匕1 has 4 storages corresponding to 4 levels == storage of 2 bits of data, where the level is from high to low:: brother = storage state, for example, respectively, W, W, i〇, u The first parallel line of the data value corresponds to the pre-characterized threshold voltage of the storage state in the memory cell. Cell: square, ^^ 3B 'It shows the multi-level memory method of the real complement 2 3 erasing step' which is to use the bilateral bias hole injection in the inclusion, apply 〇v on the substrate 102, no pole A voltage and a source voltage % higher than GV are applied to the voltage, and a lower voltage or lower voltage is applied to the control gate 110. The source voltage Vs is, for example, 4 to 6 V ί pole voltage %, and the gate voltage % is, for example, _5 to 〇v. The size of the source is sufficient to produce _ g in the substrate 1G2, so that the hole is injected into the charge storage layer. 12 P950164 22〇〇6twf.doc/] Operation = the color of the quasi-memory cell can be stored There are 4 storage states of 4 materials, and the storage of 70 poor materials 'the first to fourth ff states from high to low, for example, respectively correspond to the data values of GG and n 11. In addition, the map storage line (-) , (...) are the pre-programmed threshold voltage and the target stylized threshold voltage corresponding to the 2 states in the memory cell respectively. The second step can be soft erased to the threshold voltage between the pre-programmed calibration range = Pro = normalized threshold voltage Between the two, in the operation method of the present invention, the stylized operation of the channel hot electrons can be utilized, and the hot hole ((4) volume) is used. Performing a soft erase of _ 206. It is a stylized step of greening the multi-level memory cell of the present embodiment, which is performed by the electron injection method. For example, 〇ν is applied to the substrate 1〇2, at the source: force 〇V, in no A gate electrode Vd higher than 0 V is applied to the region 114, which is, for example, about 4 to 6 V, and a gate electrode Vg to ον is applied to the control gate ιι, which is, for example, about 8 to 12 volts. The generated electrons are injected into the charge storage layer from the source region 112. In addition, FIG. 6B is a soft erase step of the operation of the multi-level memory cell of the present embodiment, which is a use of the tape. This is performed by a hot hole injection method in which, for example, 〇v is applied to the substrate, ον is applied to the source region n2, and a high (four)v is applied to the non-polar region 114. 1336526 P950164 22006twf.d〇c/n It is, for example, 4~6V left too, B + "gate voltage Vg, JL, for example, a '(4) pole 11G is applied with an electrical storage layer lower than the 〇V impurity region (10) Remember the 'soft erase operation using the electron injection method for the extreme charge 202 of the floating gate and the step of using the electronic elimination method
7A’其是繪示本實施例之多鱗記憶胞的 ㈣方法中的程式化步驟，其是利用FN電子注入法來進 行。此程式化操作例如是，在基底1〇2上施力口 〇v，在= 區112上施加0V，在汲極區114上施加〇v，且在控制閘 極110上施加高於0V的閘極電壓Vg，其例如是i4〜2〇v 左右，引發FN穿隧效應，致使電子注入電荷儲存層（浮置 閘極）中。另外，請參照圖7B，其是繪示本實施例之多位7A' is a stylized step in the method of (4) showing the multi-scale memory cell of the present embodiment, which is carried out by FN electron injection. This stylized operation is, for example, applying a force 〇v on the substrate 1〇2, applying 0V to the = area 112, applying 〇v to the drain region 114, and applying a gate higher than 0V to the control gate 110. The pole voltage Vg, which is, for example, about i4 to 2 〇v, induces a FN tunneling effect, causing electrons to be injected into the charge storage layer (floating gate). In addition, please refer to FIG. 7B, which illustrates multiple bits of the embodiment.
準5己憶胞的操作方法中的軟抹除步驟，其是利用FN電子 排除法來進行。此軟抹除操作例如是，在基底1〇2上施加 0V，在源極區112上施加〇v，在沒極區I!#上施加〇v， 且在控制閘極110上施加低於〇V的閘極電壓Vg，其例如 是-20〜-14V左右，引發FN穿隧效應，致使電子由電荷儲 存層（浮置閘極)注入基底102中。 圖8所繪示為本發明之實施例的多位準記憶胞積體電 路之簡化方塊圖。 請參照圖8，積體電路850包括位於半導體基底上之 多位準記憶胞陣列800。另外，積體電路850還包括列解 P950164 22006twf.doc/n =80:與行解碼$ 8〇3。其中’列解碼器謝是與多數 =兀線’耗合’並沿著記憶_ 8⑻中之制而設置。 订解碼副3找多數條位元線8G4 #合，並沿著記憶陣 歹田 1 =中之縱行而設置。列解碼器8〇1與行解碼器8〇3是 =取陣列_的多位準記憶胞的電壓。位址訊號則經 ，匯&排805提供給行解碼g 8〇3及列解石馬器。另外， 如n8G6巾的感應放大轉人資料結_經由匯流排 r山f至行解碼請3。㈣是由積體電路㈣上的輸入 ，出痒或其他内部/外部資料來源，經由資料輸入線811， _中的㈣輸入結構；而資料也可由方塊_ 放大器經由資料輸出線815，輸出至積體電路上 入珲或其他内私外部資料終端。偏壓調整狀態 二:疋用以控制偏壓奴量，以提供偏壓值継，以抹 寫入驗證電壓，同時負責寫人、抹除與讀取，以增加 而且，偏壓調整狀態器809可用以操作陣列8〇〇的 二胞’至f位準記憶胞的臨界電壓大於預先程式 入社禮ίϋ亦即疋進行程式化操作。感測放大器/資料輸 入、，，。構_用以操作_ _的多位準記憶胞，至多位準 壓大於目標程式化臨界電遂、小於預先程 式化私界電壓，亦即是進行軟抹除操作。其中，使 記憶胞陣列_進行程式化操作可利用CHE注入法、FN 電子注人糾DSBtBi人絲進行；使乡 列網進行軟抹除操作可利用BTMH*入法羊fnU；= 除法或DSB電洞注入法來進行。 15 1336526 P950164 22006twf.doc/n 由上述可知，本發明之操作綠可使記憶胞可精確地 ^達目標程式化臨界電壓。而且，本發明之方法可使各儲 =態的記憶胞臨界電壓分佈範圍變窄，從而降低讀取時 诱列的可能性。 雖然本發明已以較佳實施例揭露如上 =明丄任何熟習此技藝者，在不脫離本發= ，圍當視後附之申請專利範_界定者為準。狀㈣ 【圖式簡單說明】 示意=為依照本發明之實施例解示的多位準記憶胞的 圖2為依照本發明之實施例所緣 操作方法流程圖。 7议早心隐胞的 圖3A與林發0狀—實施狀乡 的操作方法中的程式化步驟與軟抹除步驟。'^己憶胞 圖4綠示本發明之多位準記憶胞的操作 v驟期間’記憶胞的臨界電壓隨時間的變化。壬式化 圖5_本發明之多位準滅胞的操 步驟期間’記憶胞的臨界電壓隨時_變化/之軟抹除 圖6 A與圖6 B繪示本發明之另一實施例之 的操作方法巾的程式姆驟與軟雜步驟。’此憶 ，7A與圖7B繪示本發明之又一實施例之 的操作方法巾的料化步驟與軟絲步驟。、己憶 圖8崎示為本發明之實施例的多位準記憶跑積體電 1336526 P950164 22006twf.doc/n 路之簡化方塊圖。 【主要元件符號說明】 100 :記憶胞 102 :基底 104 :底氧化層 106 :氮化矽層 108 :頂氧化層 $ 110:控制閘極 112 .源極區 114 ·>及極區 202、204、206、208、210 :步驟 Vd :汲極電壓 Vg :閘極電壓 Vs :源極電壓 17The soft erase step in the method of operation of the quasi-remembered cell is carried out by FN electron exclusion. This soft erase operation is, for example, applying 0V to the substrate 1〇2, applying 〇v to the source region 112, applying 〇v to the gate region I!#, and applying a lower voltage on the control gate 110. The gate voltage Vg of V, which is, for example, about -20 to -14 V, induces a FN tunneling effect, causing electrons to be injected into the substrate 102 from the charge storage layer (floating gate). Figure 8 is a simplified block diagram of a multi-level memory cell circuit in accordance with an embodiment of the present invention. Referring to Figure 8, integrated circuit 850 includes a plurality of level memory cell arrays 800 on a semiconductor substrate. In addition, the integrated circuit 850 also includes a column solution P950164 22006twf.doc/n = 80: and row decoding $8〇3. Where the 'column decoder is depleted with the majority = 兀 line' and is set along the memory _ 8 (8). Set the decoding sub 3 to find the majority of the bit line 8G4 #合, and set along the memory array 歹田 1 = the vertical line. The column decoder 8〇1 and the row decoder 8〇3 are = the voltage of the multi-level memory cell of the array_. The address signal is then supplied to the bank to decode g 8〇3 and the column stone device. In addition, such as the induction amplification of the n8G6 towel to the data node _ via the bus bar r mountain f to the line decoding please 3. (4) It is input from the integrated circuit (4), itching or other internal/external data sources, via the input input structure of the data input line 811, _ (4); and the data can also be output from the block _ amplifier via the data output line 815 to the product. On the body circuit, or other internal and external data terminals. The bias adjustment state 2: 疋 is used to control the bias value to provide a bias value 継 to erase the verification voltage, and is responsible for writing, erasing and reading to increase and, the bias adjustment state 809 The threshold voltage that can be used to operate the two cells 'to the f-level memory cell of the array 8 大于 is greater than the pre-programmed ritual, that is, the program operation. Sense Amplifier / Data Input,,,. The multi-level memory cell used to operate _ _, the multi-level quasi-voltage is greater than the target stylized threshold, and less than the pre-programmed private voltage, that is, the soft erase operation. Among them, the memory cell array _ can be programmed by CHE injection method, FN electronic injection of DSBtBi human silk; to make the rural network soft erase operation can use BTMH* into the sheep fnU; = division or DSB Hole injection method is used. 15 1336526 P950164 22006twf.doc/n As can be seen from the above, the operational green of the present invention allows the memory cell to accurately reach the target stylized threshold voltage. Moreover, the method of the present invention can narrow the range of the memory cell threshold voltage distribution of each of the stored states, thereby reducing the likelihood of trapping during reading. Although the present invention has been disclosed in the above preferred embodiments, it is to be understood that any person skilled in the art will be able to do so without departing from the scope of the invention. Figure 4 is a schematic diagram of a multi-level memory cell illustrated in accordance with an embodiment of the present invention. Figure 2 is a flow chart of a method of operation in accordance with an embodiment of the present invention. 7 Discussion of early heart cryptic cells Figure 3A and Linfa 0--the stylization steps and soft erase steps in the operation method of the implementation. Fig. 4 shows the operation of the multi-level memory cell of the present invention. The critical voltage of the memory cell changes with time.壬 化 5 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆The method of operation method is a step and a soft step. 7A and FIG. 7B illustrate the materialization step and the soft filament step of the operation method towel according to still another embodiment of the present invention. FIG. 8 is a simplified block diagram of a multi-level memory galvanic body 1336526 P950164 22006 twf.doc/n road according to an embodiment of the present invention. [Main component symbol description] 100: memory cell 102: substrate 104: bottom oxide layer 106: tantalum nitride layer 108: top oxide layer $110: control gate 112. source region 114 · > and polar regions 202, 204 , 206, 208, 210: Step Vd: drain voltage Vg: gate voltage Vs: source voltage 17