TWI334273B - Signal detection circuit with deglitch and method thereof - Google Patents

Description

1334273 « P2006-034-TW-A 22681twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a signal detection circuit with a function of de-noising noise, and in particular A signal detection circuit that can detect a signal jam of a differential signal and can go to a surge noise. [Prior Art]

In the serial link signal transmission and reception mechanism, the receiving end often sets a signal detector, which can detect the differential input signal received by the receiving end to determine whether the input signal is required. Whether the amplitude corresponds to a specific preset signal specification. This signal detector will judge based on the reference voltage. Sometimes the received input signal will be higher than the reference voltage. For this reason, the signal detector preferably has a rectifying function. In addition, when the signal is turned, the differential signal will be smaller than the reference voltage in a very short time, which will cause glitch in the judgment of the signal pinch. In addition, noise can also cause glitch noise. Referring to FIG. 1 , the display of the conventional low voltage differential signal detector is shown in FIG. 1 . The signal detector 1 includes: a subtractor 11 and a test voltage generator 13 , and samplers 14 and 15 , clock generator 16, or 琏 闸 y, and pulse expander (pulsestmeh (4) . Fu Lao ΐ state 11 and 12 will input signal 1N and reference voltage VREF (by the sample ^ ^ ^ production correction minus) and; The reference line clock generated by the sampler 14^15 pulse generator 16 is taken, and the output signals of the subtractors 11 and 12 are sampled, and 5 1334273 2268ltwf.d〇c/n

P2006-034-TW-A sends the sampling result to or logic gate 17. The samplers 14 and 15 amplify the rounding signals of the subtractions 11 and 12. The clock generator 16 randomly generates a low frequency reference clock. Therefore, the sampling points of the samplers 14 and 15 are random. The pulse expander 18 expands the pulse width of the output signal of the OR gate 17 to obtain the output signal OUT. Performing pulse expansion will facilitate the processing of the second stage circuit. In this conventional circuit, the samplers 14, 15, and or the logic gate 17 can achieve the purpose of full-wave rectification. However, the samplers 14 and 15 must have high gain to improve the common mode noise rejection capability of the S circuit. In addition, this conventional circuit does not have the ability to remove noise. Therefore, there is a need for a signal detecting circuit capable of detecting a differential signal, which can improve the disadvantages of the prior art and provide other advantages. SUMMARY OF THE INVENTION The present invention provides a signal detection circuit that can detect whether a differential input signal is smaller than a size to reflect a signal pinch condition of an input signal, and the signal detection circuit of the present invention has a debounce Wave noise function, better common mode noise resistance, and good judgment accuracy. An example of the present invention provides a signal detecting circuit for detecting a 夹 号 pinch condition of a differential input 彳 5. The signal detection circuit comprises: a reference voltage generator, generating a reference voltage, a common mode voltage of the reference voltage to track a common mode voltage of the input signal; an instant signal judging circuit, instantaneous full-wave rectification and amplifying a difference between the input signal and the reference voltage The instant signal judging circuit judges whether the input signal is greater than the reference voltage; wherein, the instant signal judging circuit comprises: a dual input differential comparator and a mutually exclusive or logic gate, and the two input differential comparison 6

< S P20〇6'°34-TW-A 2268 ltwf.doc/n = combination with mutual exclusion or logic gate Comparable differential input signal with reference power =, ' and de-surge noise circuit, coupled The instant signal judging circuit uses over-sampling and logic processing to remove noise. The hopping noise circuit includes an analog part and a digital part. The analog portion of the large-wave noise circuit converts the output signal of the real-time signal judging circuit, the line sampling and/or the amplification, and the digital portion of the glitch noise circuit converts the analog-like sampling result into a digital output signal. This digital output signal represents whether the input signal is desired or not, that is, the signal of the input signal. Another example of the present invention provides a signal detecting method for detecting a differential input signal. The method comprises the steps of: generating a reference voltage, the common mode voltage of the voltage chasing a common mode voltage of the input signal; inverting the input signal to generate an inverted signal of the input signal; comparing the input signal with the reference voltage to generate a first comparison As a result, the inverted signal of the input signal is compared with the reference voltage, /ί to generate a second comparison result; the first and second comparison results are mutually exclusive or logically operated to generate a first mutually exclusive or logical operation result; Sampling and/or amplifying the result of a mutually exclusive or logical operation; and sampling, the conversion of the residual wheel is stunned, and the digital input di signal represents whether the input signal is required or not, that is, the pinch of the input signal . Still another example of the present invention provides a signal detecting method for detecting a wheel-signal signal out-of-synchronization condition and providing a corresponding output signal, the signal level of the wheeled signal reflecting a signal pinch condition of the input signal. The method includes: detecting whether the round-in signal exceeds a predetermined reference range, and providing - comparing (4) to represent the result of the comparison; and _ smelling the signal 1332427 P2006-034-TW-A 22681twf.doc/n sampling and The logic operation is performed according to the sampling values at different times to filter out sampling errors sampled to the signal polarity inversion interlacing point (Cr〇SS p〇int), and the correctness of the pinch signal rotation is increased. The above-described features and advantages of the present invention will become more apparent from the following description. [Embodiment] FIG. 2 shows a signal detecting circuit 'which can detect a signal pinch of an input signal IN and is reflected on an output signal OUT, according to an embodiment of the present invention. The signal detecting circuit of the present invention has the function of de-surging noise, better common mode noise resistance, avoiding judgment errors, and eliminating the need for high-cost high-gain samplers. As shown in FIG. 2, the signal detecting circuit 20 includes a reference voltage generator 21, an instant signal judging circuit 22, and a de-bounce noise circuit 23. which is

The Ms number judgment circuit 22 includes an inverter 221, comparators 222 and 223, and a mutually exclusive or logic gate 224. Comparators 222 and 223 can form a dual input differential comparator. Further, the reference voltage generator 21 generates a reference voltage VREF (which is also a differential signal) based on the input signal IN. The input signal 〖^^ is a differential signal, which includes the signal IN_P and the signal IN_N. The reference voltage VREF is also a differential signal 'which includes reference voltages VREF_P and VREF_N. The common mode voltage of the reference voltage Vref will follow the common mode voltage of the input signal IN. Referring to Fig. 3', an example of the reference voltage generator 21 is shown. As shown in Fig. 1332273 P2006-034-TW-A 22681twf.doc/n 3 'This reference voltage generator 21 includes: a transistor, a 308, resistors 303, 304, 309 and 310; a current source 3〇5, 3〇6 and 31丄; and amplifier 3G7. The connection relationship of these components can be seen in Fig. 3 and will not be described in detail herein. The resistors 303 and 3〇4 preferably have the same resistance value (matching each other); similarly, the resistors 309 and 310 preferably have the same resistance value (matching each other). The transistors 301 and 302, and the resistors 3〇3 and 3〇4 can form a level shifter that slightly pulls the voltage level of the low voltage input signal IN (eg, close to ον) ( For example, pull up to about 15V). Amplifier 307 preferably has a high gain value. It can be seen from Fig. 3 that the reference voltages VREFJP and VREF_N can be approximated as follows: VREF_P~N1+I*R (1) VREF_N~N1-I*R (2) where N1 represents the node voltage and R is the resistance of 309 and 310. The resistance value, I is the current flowing through the resistors 309 and 310. The instant signal judging circuit 22 can perform full-wave rectification and amplification of the signal in real time, and judge whether the input signal IN is greater than the reference voltage VREF. The instant signal judging circuit 22 has a function of detecting a signal squelch. Please refer to Figure 2 again. The inverter 221 inverts the input signal IN to the inverted signal INJBAR. Comparator 222 compares input signal IN with reference voltage VREF. Comparator 223 compares inverted signal INJBAR with reference voltage VREF °. Referring to Figure 4, comparator 222 of the differential architecture is shown. Comparator 222 includes current sources 401 and 402, transistors 403-406, and resistors 407 and 408, as shown in Fig. 4 1 334 273 P2006-034-TW-A 22681 twf.doc/n. The signals c〇M_OUT~P and (:01^_0111'_>1 are the comparison results of the comparator 222. The connection relationship of these elements can be known by referring to Fig. 4, which will not be described in detail. Of course, the architecture of the comparator 223 It can be similar or identical to comparator 222.

The exclusive or logic gate 224 receives the outputs of comparators 222 and 223 and performs a mutually exclusive or logical operation. In this embodiment, the exclusive or logic gate 224 is, for example, a symmetric differential analog architecture. The symmetric differential analogy has a better anti-common noise capability than the mutual exclusion or logic gate 224 than the asymmetric differential architecture. Please refer to FIG. 5, which shows the architecture of symmetric differential analogy or inter-logic 224. As shown in FIG. 5, the exclusive or logic gate 224 includes a current source 501, transistors 502-507, and resistors 508 and 509. The connection relationship of these elements can be referred to Fig. 5 and will not be described in detail herein.

In FIG. 5, reference symbols VAN and VAb represent an input apostrophe (such as the output signal of comparator 222); reference symbol VBN and representative input signal (such as output signal _ of comparator 223) XOR_OUTJP X0R—〇UT_N is a mutually exclusive or logical two-out signal. Whan compares 222/223 with mutual exclusion or logic gate 224 to provide full-wave production and amplification effect. Improve the accuracy of detection. Also go to the glitch noise circuit 23 to use multiple sampling and logic processing to the purpose of de-spur pure. Please refer to Figure 6Α#6Β, respectively

丄JJ4Z/J P2006-034-TW-A 22681twf.d〇c/n Two examples of the surge noise circuit 23. Going to the spur noise circuit] includes analogous injuries and digital parts. The glancing noise circuit is amplified and entered into the Yao sample, which can also be called the sampling part. The number (4) side of the new noise circuit 23 is switched to the result of the recording to reflect the signal loss of the differential input signal IN.

Referring to FIG. 6A, the de-surge noise circuit 23 includes: a buffer 6〇1, a reverse-phase 6〇2, a latch 6 (BA and 6 coffee, and a logic close 6〇4, and or a gate 605). The connection relationship of these components can be known from _6a, which is not described in detail here. The nuclear power, the sway axis circuit 23 analogy portion includes: a buffer 601 'inverter 602, and a latch 6 〇 3a And 6〇3B; the digital portion of the de-synchronization noise path 23 includes: and logic gate 6 () 4, and or logic gate 605. The buffer 601 can output the exclusive or logic gate 224 output signal XOR-OUT Further step-by-step amplification. Inverting $6〇2 inverts the amplified signal XOR_OUT into the signal x〇R_〇UT_BAR.

The output signal of the buffer 601 is input to the reset terminal CLR of the lockers 6〇3A and 603B for resetting the latches. When the input signal is greater than the reference voltage and the difference between the two is greater than a predetermined value, the latches are reset. The k number XOR_OUT_BAR is input to the data terminal D of the latches 603A and 603B. The sampling clock SP_CK is input to the control terminals of the latches 6〇3A and 603B. The latches 603A and 603B can sample the signal X〇R_OUT_BAR according to the trigger of the sampling clock SP_CK. In the example of FIG. 6A, 'to increase the sampling positive greenness' is preferably performed at least twice during one week of the input signal IN 11 < S ) 1334273 P2006-034-TW-A 22681twf.doc/n Sampling, that is, over-sampling; that is, the sampling clock SP_CK has a frequency of at least twice the input signal IN. The sampling results of the latches 603A and 603B are input to the AND gate 604. Or the logic gate 605 receives the output signal of the logic gate 6〇4 and outputs the output signal OUT of the signal detection circuit. Referring to Figure 6B', the glitch noise circuit 23 includes an inverter 612, latches 613A, 613B and 613C' and logic gates 614A, 614B and 614C, and or a logic gate 615. The connection relationship of these elements can be known from Fig. 6B and will not be described in detail herein. In this example, the analog portion of the glitch noise circuit 23 includes an inverter 612, and latches 613A, 613B, and 613C. The digital portion of the glitch noise circuit 23 includes: and a logic gate 614A. , 614B and 614C, and or logic gate 615. The operation of the inverter and latch of Figure 6B is similar to the inverter and latch of Figure 6A and will not be repeated here. However, in the example of Fig. 6B, the signal XORJDUT does not need to be a reset signal as a latch. In the example of FIG. 6B, in order to increase the sampling accuracy, it is preferable to perform sampling at least three times in one cycle of the input signal IN; that is, the sampling clock S]p-CK has a frequency of at least the input signal IN. three times. — The inputs of logic gates 614A, 614B, and 614C receive the output signals of one of the two latches. For example, and logic gate 614a receives the output signals of latches 613a and 613C; and logic gate 614B receives the output signals of latches and 613Β; and logic gate 6MC receives the output signals of latches 6ΐ3Β. And the turn-off signals of the logic gates 614A, 614B, and 614c 12 1334273 P2006-034-TW-A 22681twf.doc/n are all input to the OR gate 615. When the signal is sampled, it may be sampled to the signal transition point. If it is processed, the output money OUT may be the noise of the signal. In addition, small noises that occasionally appear during transmission may cause glitch on the output signal. Fig. 7α and Fig. 7B show a schematic diagram of how the embodiment removes glitch noise. In the figure from ^ map

In W, the arrow t represents the lion's material and the dotted line represents the reference voltage VREF. Figure 7Α shows a schematic diagram of sampling of the input signal under normal transfer. When the = number X 〇 R_ 〇 UT - said sampling, it may just sample the signal transition point 'causing part of the sampling result to be logical" 。, and logic operation can eliminate the burst generated at the signal transition point Wave noise. As seen from Figure 7A, when the input signal IN is under normal transmission, the output signal qUt is 0^, which is not affected by the position of the sampling point, and will not be affected by the input.

Figure 7B shows how the actual implementation eliminates the small = noise that occurs during the transmission process. Even if the signal is not transmitted, there may still be a big friend noise during the transmission. If the magnitude of some glitch noises just exceeds the reference voltage and is paid, the QR logic operation can be added (4), except to avoid the error production. Figure 7B shows * 'When there is no signal transmission in the input ΙΝ 』OUT should be “1”; in addition, even if there is sudden glitch in the transmission process, the turn-out signal will remain “1”. In this embodiment, the sampling portion can have a small differential gain, and a high differential gain is not required as in the prior art. In addition, the comparator is mutually exclusive

13 1334273 P2006-034-TW-A 22681twfdoc/n 3 s = The sampling part (analog part) of the glitch noise circuit is a specific circuit. The low __ output from the comparator can be sampled into a digital logic I by analogy differential amplification so that the difference can be avoided. This recording circuit can effectively avoid the interference of common mode noise.

From another perspective, the present embodiment can measure the signal pinch of the input signal, and the age of the recorded signal QUT will reflect the money of the input signal IN. First, whether the side wheel man signal m exceeds the preset reference and provides a result. The __ result is sampled, and logical operations are performed according to the sample values at different times to adjust the signal margin of the output signal OUT. In this way, the sampling error that occurs when the signal polarity is reversed to the cross point can be filtered out, and the output of the number is correct. 5 This only example of the architecture is suitable for a variety of high-speed serial connection in the universal serial bus (USB) system. Encounter, first or

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art will be able to make a few changes and modifications within the spirit and scope of the invention. The scope of the invention is therefore defined by the scope of the appended claims. f [Simple diagram of a month] Figure 1 shows the architecture of a conventional low-voltage differential signal detector. 2 shows a low voltage differential signal prediction according to an embodiment of the present invention. 14 1334273 P2006-034-TW-A 22681 twfdoc/n Circuit FIG. 3 shows an example of a reference voltage generator according to the present embodiment. Fig. 4 shows an example of a differential comparator according to the present embodiment. Fig. 5 shows an example of a symmetrical differential repulsion or a logic gate according to the present embodiment. 6A and 6B show two examples of the de-splash noise circuit according to the present embodiment, respectively. % Fig. 7A and Fig. 7B are diagrams showing how the embodiment removes glitch noise. [Main component symbol description] 10 : Signal detector 11 ' 12 : Subtractor 13 : Reference voltage generator 10 17 18 20 21 22 23 14 ' 15 : Sampler clock generator or logic gate pulse expander signal detection Circuit reference voltage generator instant signal judging circuit to glitch noise circuit 221: inverter 222, 223: comparator

15 1334273 P2006-034-TW-A 22681twf.doc/n 224: Mutually exclusive or logic gates 301, 302, 308: transistors 303, 304, 309, 310: resistors '305, 306, 311: current source. 307: Amplifiers 401, 402: Current sources 403 to 406: Transistors 407, 408: Resistor® 501: Current sources 502 to 507: Transistors 508, 509: Resistor 601: Buffer 602: Inverters 603A, 603B: Latch 604: and logic gate 605: or logic gate • 612: inverter 613A, 613B, 613C: latch 614A, 614B, 614C: and logic gate 615: or logic gate 16

Claims (1)

1334273 P2006-034-TW-A 22681twf.doc/n X. Patent application scope: Main \ A signal price measurement circuit for _ an input signal signal is cool, the human signal is - differential signal, The signal_circuit includes: a reference voltage generator, generating a reference voltage according to the input signal, the reference voltage is a differential signal, and the common mode voltage of the reference voltage is tracking the common mode voltage of the input signal; a circuit that instantaneously rectifies and amplifies a difference between the input signal and the reference f, the instant signal determining circuit determines whether the input signal is greater than the reference voltage, and the instant signal determining circuit comprises: a dual input differential comparator and a mutual exclusion or logic gate for comparing the input signal with the reference voltage; and a de-surge noise circuit coupled to the instant signal determination circuit, the de-surge noise circuit utilizing oversampling and logic processing Going to the glitch noise circuit, the hopping noise circuit includes an analog portion and a digital portion, and the analog portion of the glitch noise circuit determines the instant signal One of the output signals of the circuit is sampled and/or amplified, and the digital portion of the de-splash noise circuit converts the analog portion of the sampled result into a digital output signal of the signal detection circuit to reflect the round-in signal The signal pinch situation. 2. The signal detecting circuit of claim 1, wherein the instant signal determining circuit further comprises: a first inverter that inverts the input signal to generate an inverted signal of the input signal. 3. The signal detecting circuit of claim 2, wherein the dual input differential comparator of the instant signal determining circuit comprises: 17 1334273 P2006-034-TW-A 22681twf.doc/n A first comparator having: a first input receiving the input signal; a second input receiving the reference voltage; and an output; a second comparator having: a first input receiving the inverted signal of the input signal; a second input receiving the reference voltage; and an output; wherein the first and second comparators are It is a differential analog amplifier. 4. The signal detecting circuit of claim 3, wherein the mutual repulsion or logic gate of the instant 判断 § judgement circuit has a first input terminal coupled to the first comparator The output end; a second input end coupled to the output end of the second comparator; and an output end outputting the output signal of the instant signal judging circuit; wherein the mutual exclusion or logic gate is a symmetry Sex differential analog logic gate. ▲ 5. The signal system as described in item 利 范围 , , , , , , , , , , , , 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该The electric output " output 5 tiger, and an output; the input end of the wheel, connected to the buffer of the device: having: - data terminal 'reduced to the second reverse phase _ connected to two receiving a sampling clock; - resetting the end, the end of the round of the attack; and an output; and the 'with: - data end, secret to the second inverting end, a control end, receiving the sampling clock; Reset terminal, 18 / f · % 1334273 P2006-034-TW-A 22681twf.doc / n Lightly connected to the wheel of the buffer; and an output. 6. The signal detecting circuit of claim 5, wherein the digital portion of the de-splash noise circuit comprises: a first and a logic gate having: a first input coupled to The output end of the first latch; a second input coupled to the output of the second latch; and an output; and the first or logic gate having: an input Coupled to the first and The Logic Gate rotates the n- and ώ terminals to output the digital output signal of the signal. The signal detecting circuit of claim 5, wherein the sampling clock has a frequency at least twice or more than the input signal. 8. The signal detecting circuit of claim 1, wherein the analog component of the surge noise circuit comprises: a second mesh, having: an input terminal, receiving the instant signal determining circuit to find Output signal; and - output; The locker of the device has: a data terminal connected to the third inverting terminal; a terminal 'control terminal' receiving-sampling clock; and an output terminal and an output-fifth latching device having a device The output terminal is coupled to the third inverting terminal. 'Receive the sampling clock; and - output 19 P2006-034-TW-A 2268ltwf.d〇c/n P2006-034-TW-A 2268ltwf.d〇c/n 9. As described in claim 8 Signal detection circuit, wherein -: the third and the logic gate, having: - the first input end, connected to the output end of the third latch; - the second input end, connected to the output end of the fourth check lock; And a round of the output; the fourth and the logic gate have: a first input end, lightly connected to the output end of the fourth latch; and a second input end coupled to the fifth latch And a output end; and an output end; and a first wheel-in end coupled to the first second input end, lightly connected to the fifth latch a second or logic gate having: a first input coupled to the output of the second and logic gates; a second input coupled to the output of the third and logic gates; The three-input terminal is connected to the output end of the fourth and logic gates; and an output terminal outputs the digital output signal of the signal detecting circuit. 10. The signal detecting circuit of claim 8, wherein the sampling clock has a frequency of at least three times greater than the input signal. 11. A signal detection method for detecting a signal pinch condition of an input signal, wherein the input signal is a differential signal, and the signal detecting method comprises: generating a reference voltage according to the input signal, the reference voltage The common mode voltage traces the common mode voltage of the input signal; inverts the input signal to generate an inverted signal of the input signal; compares the input signal with the reference voltage to generate a brother-one comparison knot 1334273 P2006-034- TW-A 22681twf.doc/n; comparing the inverted signal of the input signal with the reference voltage to generate a second comparison result; performing a mutually exclusive or logical operation on the first and second comparison results to Generating a first mutually exclusive or logical operation result; sampling and/or amplifying the first mutually exclusive or logical operation result; and, The sampled result is converted to a digital output signal that is used to represent whether the input signal is desired to reflect the pinch condition of the input signal. °, 12. The signal detecting method according to claim 5, wherein the step of comparing the input signal with the reference voltage comprises: comparing the input signal with the reference power by using a differential analog amplifier 13. The signal detecting method of claim 5, wherein the step of comparing the inverted signal of the input signal with the reference voltage comprises: comparing the input signal with a differential analog amplifier Inverted number and the reference voltage. U 14. The signal detection method of claim 11, wherein the step of performing the mutual exclusion or logic operation comprises: using a logical operation symmetry differential analog repulsion or a logic gate to perform the Mutual exclusion or 15. The signal detection method described in the scope of claim 5, which samples the first mutually exclusive or logical operation result in 21 1 11334273 P2006-034-TW-A 22681twf.doc/n And/or the step of amplifying comprises: amplifying and inverting the first mutually exclusive or logical operation result to generate a second mutually exclusive or logical operation result; according to the - sampling clock' of the second mutually exclusive or logical operation result Performing a first oversampling; and performing a second oversampling on the second mutually exclusive or logical operation result according to the sampling clock. 16. For the credit measurement method described in item 15 (4), the step of applying the sampling result to the button output signal includes: performing - and logical operation on the first and second oversampling results A logical operation to obtain the digital output signal. 17. In the signal detection method described in item 15 of the sf patent (4), the sampling clock is at least twice as large as the input money. - the __ method described in item u, the result of which is sampled and/or amplified to invert the first mutually exclusive or logical operation result, to produce or logically operate the result; and; The heterogeneous two-check-out operation result is performed according to the sampling clock, the second mutually exclusive-fourth oversampling; the money μ~ fruit is ordered according to the sampling clock 'the second mutually exclusive or _ operation Result twenty two