CN101320981B - Signal detection circuit with surge noise removing function and method thereof - Google Patents
Signal detection circuit with surge noise removing function and method thereof Download PDFInfo
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- CN101320981B CN101320981B CN2007101065944A CN200710106594A CN101320981B CN 101320981 B CN101320981 B CN 101320981B CN 2007101065944 A CN2007101065944 A CN 2007101065944A CN 200710106594 A CN200710106594 A CN 200710106594A CN 101320981 B CN101320981 B CN 101320981B
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Abstract
A signal detecting circuit is used for detecting whether the differential input signal amplitude is smaller than the standard size to generate a digitalized output signal to reflect the signal clamping condition of the input signal. The signal detecting circuit comprises a reference voltage generator for generating the reference voltage, the common mode voltage of which searches the common mode voltage of the input signal; a real-time signal judging circuit for real-time amplifying the difference between the input signal and the reference voltage; and a surge and noise removing circuit, for sampling and/or amplifying the output signal on the judging circuit of the real-time signal, and converting the sampling result into the digitalized output signal.
Description
Technical field
The present invention relates to a kind of signal deteching circuit, particularly relate to a kind of signal folder that detects differential wave (differential signal) and end the signal deteching circuit that situation again can surge noise removing with surge noise removing (deglitch) function.
Background technology
Link in the signal transmitting and receiving mechanism of (seriallink) at list type; receiving terminal regular meeting is provided with a signal detector; whether it can detect the received differential input signal of institute's receiving terminal, be required to judge this input signal, and whether its amplitude conforms with specific default signal specification.This signal detector can be judged according to reference voltage.
Sometimes, the input signal that is received can be higher than reference voltage.For this reason, signal detector can have the function of better rectification.In addition, when the signal transition, differential wave can the utmost point in the short time less than reference voltage, surge noise (glitch) appears in the judgement that so will cause signal folder to end.In addition, noise also may cause surge noise.
Please refer to Fig. 1, it shows the Organization Chart of known Low Voltage Differential Signal detector.As shown in Figure 1, this signal detector 10 comprises: subtracter 11 and 12, reference voltage generator 13, sampler 14 and 15, clock generator 16, or gate 17, and pulse stretcher (pulsest retcher) 18.
Subtracter 11 and 12 subtracts each other input signal IN and reference voltage VREF (being produced by reference voltage generator 13), and subtraction result is inputed to sampler 14 and 15.According to the reference clock that clock generator 16 is produced, the sampler 14 and the 15 pairs of subtracters 11 and 12 output signal are taken a sample, and sampling result is delivered to or gate 17.The output signal of sampler 14 and 15 scalable these subtracters 11 and 12.Clock generator 16 can produce the frequency reference clock at random.So sampler 14 and 15 sampling point are at random.
Pulse stretcher 18 is incited somebody to action or the output signal of gate 17 is carried out the pulse duration expansion, to obtain output signal OUT.Carry out pulse expansion and will help the signal processing of late-class circuit.In this known circuit, sampler 14,15, and or gate 17 can reach the purpose of full-wave rectification.
Yet sampler 14 and 15 must have high-gain, could improve common-mode noise opposing (common mode noise rejection) ability of this known circuit.In addition, this known circuit does not possess the denoising ability.
Therefore, need a kind of signal deteching circuit that detects differential wave, it can improve the shortcoming of known technology, and other advantage can also be provided.
Summary of the invention
The invention provides a kind of signal deteching circuit, it can detect differential input signal and whether end (Squelch) situation less than the specification size with the signal folder of reflected input signal, and signal deteching circuit of the present invention has surge noise removing function, better common-mode noise resistivity, good judgement accuracy.
Example of the present invention provides a kind of signal deteching circuit, and the signal folder that is used to detect differential input signal ends situation.Signal deteching circuit comprises: reference voltage generator, produce reference voltage, and the common-mode voltage dynamic real-time of reference voltage chases after the lock input common-mode; The live signal decision circuitry, the difference between full-wave rectification in real time and amplification input signal and reference voltage, the live signal decision circuitry judges that whether input signal is greater than reference voltage; Wherein, the live signal decision circuitry comprises: a dual input differential comparator and an exclusive or logic gate, and the combination of dual input differential comparator and exclusive or logic gate can poor moving input signal and reference voltage; And the surge noise removing circuit, be coupled to this surge noise removing circuit of live signal decision circuitry and utilize based on the oversampling (over-sampling) of input signal and logical process with surge noise removing.This surge noise removing circuit comprises simulation part and numeral part, the simulation of surge noise removing circuit is partly taken a sample to the output signal of live signal decision circuitry and/or is amplified, and the numeral of surge noise removing circuit partly will be simulated sampling result partly and convert digital output signal to.This digital output signal can represent whether input signal is required, and just the signal of input signal folder ends situation.
Another example of the present invention provides a kind of signal detecting method, is used to detect a differential input signal.The method comprises the following steps: to produce reference voltage, and the common-mode voltage of reference voltage is pursued input common-mode; Rp input signal is to produce the inversion signal of input signal; Comparator input signal and reference voltage are to produce first comparative result; The inversion signal of comparator input signal and reference voltage are to produce second comparative result; First and second comparative result is carried out the XOR computing, to produce the first XOR operation result; The first XOR operation result is taken a sample and/or amplified; And convert sampling result to digital output signal, and digital output signal represents whether this input signal is required, and just the folder of input signal ends situation.
Another example of the present invention provides a kind of signal detecting method, and the signal that detects an input signal presss from both sides the output signal of ending situation and a correspondence being provided, and the signal level of this output signal reflects that the signal folder of this input signal ends situation.This method comprises: detect this input signal and whether surmount a default term of reference, and provide a comparison signal with representative result relatively; And this comparison signal carried out oversampling and carry out logical operation according to the sampling value of different time, be sampled to the missampling of signal polarity inversion cross-point (Cross point) with filtering, increase the correctness that folder ends signal output.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows the Organization Chart of known Low Voltage Differential Signal detector.
Fig. 2 shows Low Voltage Differential Signal testing circuit according to an embodiment of the invention
Fig. 3 shows the example according to the reference voltage generator of present embodiment.
Fig. 4 shows the example according to the differential comparator of present embodiment.
Fig. 5 shows the example according to the differential exclusive or logic gate of symmetry of present embodiment.
Fig. 6 A and 6B show two kinds of examples according to the surge noise removing circuit of present embodiment respectively.
Fig. 7 A and Fig. 7 B show how present embodiment removes the schematic diagram of surge noise.
The reference numeral explanation
10: signal detector
11,12: subtracter
13: reference voltage generator
14,15: sampler
16: clock generator
17: or gate
18: pulse stretcher
20: signal deteching circuit
21: reference voltage generator
22: the live signal decision circuitry
23: the surge noise removing circuit
221: inverter
222,223: comparator
224: exclusive or logic gate
301,302,308: transistor
303,304,309,310: resistance
305,306,311: current source
307: amplifier
401,402: current source
403～406: transistor
407,408: resistance
501: current source
502～507: transistor
508,509: resistance
601: buffer
602: inverter
603A, 603B: latch
604: with gate
605: or gate
612: inverter
613A, 613B, 613C: latch
614A, 614B, 614C: with gate
615: or gate
Embodiment
Please refer to Fig. 2, it shows signal deteching circuit according to an embodiment of the invention, and its signal folder that can detect input signal IN ends (Squelch) situation and is reflected in output signal OUT.Signal deteching circuit of the present invention has surge noise removing function, better common-mode noise resistivity, avoids error in judgement, also need not utilize expensive high-gain sampler.
As shown in Figure 2, this signal deteching circuit 20 comprises: reference voltage generator 21, live signal decision circuitry 22 and surge noise removing circuit 23.Live signal decision circuitry 22 comprises: inverter 221, comparator 222 and 223, and exclusive or logic gate 224. Comparator 222 and 223 can form a dual input differential comparator.
Reference voltage generator 21 can produce reference voltage VREF (it also is differential wave) according to input signal IN.Input signal IN is a differential wave, and it comprises signal IN_P and signal IN_N.Reference voltage VREF also is a differential wave, and it comprises reference voltage VREF_P and VREF_N.The common-mode voltage of reference voltage VREF will be pursued the common-mode voltage of input signal IN.
Please refer to Fig. 3, it shows an example of reference voltage generator 21.As shown in Figure 3, this reference voltage generator 21 comprises: transistor 301,302 and 308; Resistance 303,304,309 and 310; Current source 305,306 and 311; And amplifier 307.The annexation of these assemblies can be found out by Fig. 3, not be described in detail in this. Resistance 303 and 304 preferably has same resistance value (matching each other); Similarly, resistance 309 and 310 best tool same resistance values (matching each other).
As seen from Figure 3, can to distinguish approximate representation as follows for reference voltage VREF_P and VREF_N:
VREF_P≈N1+I*R(1)
VREF_N≈N1-I*R(2)
Wherein, N1 representation node voltage, R are the resistance value of resistance 309 and 310, and I is the electric current of resistance 309 and 310 of flowing through.
Live signal decision circuitry 22 can be carried out full-wave rectification to signal in real time and be amplified, and judges that whether input signal IN is greater than reference voltage VREF.Live signal decision circuitry 22 also has the function that detection signal folder ends (squelch).
Please refer again to Fig. 2.Inverter 221 is inverted into inversion signal IN_BAR with input signal IN.Comparator 222 comparator input signal IN and reference voltage VREF.Comparator 223 is inversion signal IN_BAR and reference voltage VREF relatively.
Please refer to Fig. 4, it shows the comparator 222 of differential architecture.As shown in Figure 4, comparator 222 comprises: current source 401 and 402, transistor 403～406, and resistance 407 and 408.Signal COM_OUT_P and COM_OUT_N are the comparative result of comparator 222.The annexation of these assemblies can be learnt with reference to figure 4, not describe in detail in this.Certainly, the framework of comparator 223 can be similar to or be same as comparator 222.
Exclusive or logic gate 224 receives the output of comparator 222 and 223, and carries out the XOR computing.In the present embodiment, exclusive or logic gate 224 is such as being symmetric differential analog architectures.Compared with asymmetrical differential architecture, symmetric differential simulation exclusive or logic gate 224 has better anti-common-mode noise ability.
Please refer to Fig. 5, it shows the framework of symmetric differential simulation exclusive or logic gate 224.As shown in Figure 5, exclusive or logic gate 224 comprises: current source 501, transistor 502～507, and resistance 508 and 509.The annexation of these assemblies can be learnt with reference to figure 5, not describe in detail in this.
In Fig. 5, reference symbol VAN and VAP represent some input signals (such as the output signal that is comparator 222); Reference symbol VBN and VBP represent another input signal (such as the output signal that is comparator 223); XOR_OUT_P and XOR_OUT_N then are the output signals of exclusive or logic gate 224.
Surge noise removing circuit 23 utilizes repeatedly sampling and logical process, to reach the purpose of surge noise removing.Please refer to Fig. 6 A and 6B, it shows two kinds of examples of surge noise removing circuit 23 respectively.Surge noise removing circuit 23 comprises simulation part and numeral part.The simulation of surge noise removing circuit 23 partly can be amplified signal and take a sample, and also can be described as sampling partly.The numeral of surge noise removing circuit 23 partly then converts sampling result to digital logic signal OUT, ends situation with the signal folder that reflects differential input signal IN.
Please refer to Fig. 6 A, surge noise removing circuit 23 comprises: buffer 601, and inverter 602, latch 603A and 603B, with gate 604, and or gate 605.The annexation of these assemblies can be learnt by Fig. 6 A, not describe in detail in this.In this example, the simulation of surge noise removing circuit 23 partly comprises: buffer 601, inverter 602, and latch 603A and 603B; The numeral of surge noise removing circuit 23 partly comprises: with gate 604, and or gate 605.
Buffer 601 can further amplify the output signal XOR_OUT of exclusive or logic gate 224.Inverter 602 will be inverted into signal XOR_OUT_BAR through amplifying signal XOR_OUT.
The output signal of buffer 601 inputs to the replacement end CLR of latch 603A and 603B, to be used to these latchs of resetting.When input signal greater than reference voltage and this difference between the two during greater than a set value, these latchs will be reset.
Signal XOR_OUT_BAR inputs to the data terminal D of latch 603A and 603B.Sampling clock SP_CK inputs to the control end of latch 603A and 603B.According to the triggering of sampling clock SP_CK, latch 603A and 603B can take a sample to signal XOR_OUT_BAR.In the example of Fig. 6 A,, preferably in the one-period of input signal IN, can carry out at least 2 times sampling, just oversampling (over-sampling) for increasing the sampling correctness; That is the frequency of sampling clock SP_CK is at least 2 times of input signal IN.
The sampling result of latch 603A and 603B inputs to and gate 604.Or gate 605 receives and the output signal of gate 604, and exports the output signal OUT of this signal deteching circuit.
Please refer to Fig. 6 B, surge noise removing circuit 23 comprises: inverter 612, and latch 613A, 613B and 613C, with gate 614A, 614B and 614C, and or gate 615.The annexation of these assemblies can be learnt by Fig. 6 B, not describe in detail in this.In this example, the simulation of surge noise removing circuit 23 partly comprises: inverter 612, and latch 613A, 613B and 613C; The numeral of surge noise removing circuit 23 partly comprises: with gate 614A, 614B and 614C, and or gate 615.
The inverter of Fig. 6 B and the class of operation of latch are similar to inverter and the latch of Fig. 6 A, no longer repeat in this.But, in the example of Fig. 6 B, signal XOR_OUT does not need the reset signal as latch.In the example of Fig. 6 B,, preferably in the one-period of input signal IN, can carry out at least 3 times sampling for increasing the sampling correctness; That is the frequency of sampling clock SP_CK is at least three times of input signal IN.
Receive the output signal of certain two latch with the input of gate 614A, 614B and 614C.Such as, with the output signal of gate 614A reception latch 613A and 613C; Output signal with gate 614B reception latch 613A and 613B; Output signal with gate 614C reception latch 613B and 613C.All input to or gate 615 with the output signal of gate 614A, 614B and 614C.
May be sampled to the signal state switching points during sample of signal,, then may have surge noise among the output signal OUT, influence the interpretation that the signal folder ends if do not handled.In addition, the little noise (noise) that occurs once in a while in the transmission course also may cause output signal to have surge noise (glitch).Fig. 7 A and Fig. 7 B show how present embodiment removes the schematic diagram of surge noise.In Fig. 7 A and Fig. 7 B, arrow ↑ represent sampling point, solid line to represent input signal IN and dotted line is represented reference voltage VREF.
Fig. 7 A shows the sampling schematic diagram of input signal under normal transmission.When signal XOR_OUT_BAR is taken a sample, may just be sampled to the signal state switching points, causing sampling result partly is logical one.The AND logical operation can be eliminated the surge noise that is produced in the signal state switching points.Find out from Fig. 7 A figure, when input signal IN under normal transmission, output signal OUT should be maintained " 0 ", is not subjected to the position influence of sampling point, also can not be subjected to the influence of input signal transition.
Fig. 7 B shows how present embodiment eliminates the little surge noise that transmission course occurs once in a while.Even at transmission signals not, transmission course still has and surge noise may occur.If the size of some surge noise is just above reference voltage and be sampled to again, can be eliminated by the OR logical operation, produce to avoid error.Find out that from Fig. 7 B figure when not having the signal transmission among the input signal IN, output signal OUT should be " 1 "; Even transmission course has surge noise suddenly in addition, output signal also can remain " 1 ".
In the present embodiment, sampling partly can have less differential gain, need as known technology not to need high differential gain.In addition, comparator, the sampling of exclusive or logic gate and surge noise removing circuit partly (simulation part) is all the differential analog circuit with gain.The low voltage signal that comparator is exported can be after simulating differential amplification, sampled one-tenth digital logic signal.So can avoid the generation of error in judgement.These differential analog circuits can effectively be avoided the interference of common-mode noise.
From another point of view, the signal folder that present embodiment can detect input signal IN ends situation, and the signal folder of the signal level of output signal OUT meeting reflected input signal IN ends situation.At first, detect input signal IN and whether surmount the preset reference scope, and comparative result is provided.This comparative result is taken a sample, and carry out logical operation to adjust the signal level of output signal OUT according to the sampling value of different time.So, the missampling that is taken place when can filtering being sampled to signal polarity inversion cross-point (Cross point) increases the correctness that folder ends signal output.
The framework of present embodiment is suitable for various high speed list type attachment system, or in USB (USB) system.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (22)
1. signal deteching circuit, the signal folder that is used to detect an input signal ends situation, and this input signal is a differential wave, and this signal deteching circuit comprises:
One reference voltage generator produces a reference voltage according to this input signal, and this reference voltage is a differential wave, and the common-mode voltage dynamic real-time of this reference voltage chases after this input common-mode of lock;
One live signal decision circuitry, full-wave rectification in real time and amplify this input signal and this reference voltage between difference, this live signal decision circuitry judges that whether this input signal is greater than this reference voltage, this live signal decision circuitry comprises: a dual input differential comparator and an exclusive or logic gate are used for relatively this input signal and this reference voltage; And
One surge noise removing circuit, be coupled to this live signal decision circuitry, this surge noise removing circuit utilizes based on the oversampling of this input signal and logical process with surge noise removing, this surge noise removing circuit comprises that a simulation is partly partly digital with one, this simulation of this surge noise removing circuit is partly taken a sample to an output signal of this live signal decision circuitry and/or is amplified, and the digital output signal that the sampling result that this numeral part of this surge noise removing circuit will be simulated part converts this signal deteching circuit to ends situation with the signal folder that reflects this input signal.
2. signal deteching circuit as claimed in claim 1, wherein this live signal decision circuitry also comprises:
One first inverter, anti-phase this input signal is to produce an inversion signal of this input signal.
3. signal deteching circuit as claimed in claim 2, wherein this dual input differential comparator of this live signal decision circuitry comprises:
One first comparator has: a first input end receives this input signal; One second input receives this reference voltage; An and output; And
One second comparator has: a first input end receives this inversion signal of this input signal; One second input receives this reference voltage; An and output;
Wherein this first and second comparator is all differential analogue amplifier.
4. signal deteching circuit as claimed in claim 3, wherein this exclusive or logic gate of this live signal decision circuitry has:
One first input end is coupled to this output of this first comparator; One second input is coupled to this output of this second comparator; And an output, export this output signal of this live signal decision circuitry;
Wherein this exclusive or logic gate is the differential analog logic door of a symmetry.
5. signal deteching circuit as claimed in claim 1, wherein this simulation of this surge noise removing circuit partly comprises:
One buffer has: an input receives this output signal of this live signal decision circuitry; An and output;
One second inverter has: an input is coupled to this output of this buffer; An and output;
One first latch has: a data terminal is coupled to this output of this second inverter; One control end receives a sampling clock; One resets holds, and is coupled to this output of this buffer; An and output; And
One second latch has: a data terminal is coupled to this output of this second inverter; One control end receives this sampling clock; One resets holds, and is coupled to this output of this buffer; An and output.
6. signal deteching circuit as claimed in claim 5, wherein this numeral of this surge noise removing circuit partly comprises:
One first and gate, have: a first input end is coupled to this output of this first latch; One second input is coupled to this output of this second latch; An and output; And
One first or gate, have: an input, be coupled to this first with this output of gate; And an output, export this digital output signal of this signal deteching circuit.
7. signal deteching circuit as claimed in claim 5, wherein the frequency of this sampling clock is at least more than the twice of this input signal.
8. signal deteching circuit as claimed in claim 1, wherein this simulation of this surge noise removing circuit partly comprises:
One the 3rd inverter has: an input receives this output signal of this live signal decision circuitry; An and output;
One the 3rd latch has: a data terminal is coupled to this output of the 3rd inverter; One control end receives a sampling clock; An and output; And
One quad latch has: a data terminal is coupled to this output of the 3rd inverter; One control end receives this sampling clock; An and output; And
One the 5th latch has: a data terminal is coupled to this output of the 3rd inverter; One control end receives this sampling clock; An and output.
9. signal deteching circuit as claimed in claim 8, wherein this numeral of this surge noise removing circuit partly comprises:
One second and gate, have: a first input end is coupled to this output of the 3rd latch; One second input is coupled to this output of the 5th latch; An and output;
One the 3rd and gate, have: a first input end is coupled to this output of the 3rd latch; One second input is coupled to this output of this quad latch; An and output;
One the 4th and gate, have: a first input end is coupled to this output of this quad latch; One second input is coupled to this output of the 5th latch; An and output; And
One second or gate, have: a first input end, be coupled to this second with this output of gate; One second input, be coupled to the 3rd with this output of gate; One the 3rd input, be coupled to the 4th with this output of gate; And an output, export this digital output signal of this signal deteching circuit.
10. signal deteching circuit as claimed in claim 8, wherein the frequency of this sampling clock is at least more than three times of this input signal.
11. a signal detecting method, the signal folder that is used to detect an input signal ends situation, and this input signal is a differential wave, and this signal detecting method comprises:
Produce a reference voltage according to this input signal, the common-mode voltage of this reference voltage is pursued this input common-mode;
Anti-phase this input signal is to produce an inversion signal of this input signal;
Relatively this input signal and this reference voltage are to produce one first comparative result;
Relatively this inversion signal of this input signal and this reference voltage are to produce one second comparative result;
This first and second comparative result is carried out an XOR computing, to produce one first XOR operation result;
This first XOR operation result is taken a sample and/or amplified; And
Convert this sampling result to a digital output signal, this digital output signal is used to represent whether this input signal is that required the folder with the signal that reflects this input signal ended situation.
12. signal detecting method as claimed in claim 11, wherein, relatively this step of this input signal and this reference voltage comprises:
Utilize a differential analogue amplifier to come relatively this input signal and this reference voltage.
13. signal detecting method as claimed in claim 11, wherein, relatively this step of this inversion signal of this input signal and this reference voltage comprises:
Utilize a differential analogue amplifier to come relatively this inversion signal and this reference voltage of this input signal.
14. signal detecting method as claimed in claim 11, wherein, this step of carrying out this XOR computing comprises:
Utilize the differential simulation exclusive or logic gate of a symmetry to carry out this XOR computing.
15. signal detecting method as claimed in claim 11 is wherein taken a sample to this first XOR operation result and/or this step of amplifying comprises:
Amplify and anti-phase this first XOR operation result, to produce one second XOR operation result;
According to a sampling clock, this second XOR operation result is carried out one first oversampling; And
According to this sampling clock, this second XOR operation result is carried out one second oversampling.
16. signal detecting method as claimed in claim 15, this step that wherein this sampling result is converted to this digital output signal comprises:
To this first and second oversampling result carry out one with logical operation and one or logical operation, to obtain this digital output signal.
17. signal detecting method as claimed in claim 15, wherein the frequency of this sampling clock is at least more than the twice of this input signal.
18. signal detecting method as claimed in claim 11 wherein, is taken a sample and/or this step of amplifying comprises to this first XOR operation result:
Anti-phase this first XOR operation result is to produce one second XOR operation result; And;
According to a sampling clock, this second XOR operation result is carried out one the 3rd oversampling;
According to this sampling clock, this second XOR operation result is carried out one the 4th oversampling; And
According to this sampling clock, this second XOR operation result is carried out one the 5th oversampling.
19. signal detecting method as claimed in claim 18, this step that wherein this sampling result is converted to this digital output signal comprises:
To the 3rd, the 4th and the 5th oversampling result carry out one with logical operation and one or logical operation, to obtain this digital output signal.
20. signal detecting method as claimed in claim 18, wherein the frequency of this sampling clock is at least more than three times of this input signal.
21. a signal detecting method, the signal that detects an input signal presss from both sides the output signal of ending situation and a correspondence being provided, and the signal level of this output signal reflects that the signal folder of this input signal ends situation, and this method comprises:
Detect this input signal and whether surmount a default term of reference, and provide a comparison signal with representative result relatively; And
This comparison signal is carried out oversampling and carry out logical operation according to the sampling value of different time being sampled to the missampling of signal polarity inversion cross-point with the signal level of adjusting this output signal with filtering, increase the correctness that folder ends signal output.
22. as the method for claim 21, wherein, when this comparison signal was carried out oversampling, its sampling frequency was more than three times of this input signal clock.
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| CN2007101065944A CN101320981B (en) | 2007-06-06 | 2007-06-06 | Signal detection circuit with surge noise removing function and method thereof |
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| CN111239476B (en) * | 2018-11-29 | 2022-11-22 | 瑞昱半导体股份有限公司 | Signal detector and signal detection method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5856750A (en) * | 1996-02-28 | 1999-01-05 | Nec Corporation | Interface circuit having receiving side circuit for controlling logical threshold values |
| CN1386349A (en) * | 2000-07-25 | 2002-12-18 | 皇家菲利浦电子有限公司 | 5-unit receiver utilizing common mode insensitive differential offset comparator |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5856750A (en) * | 1996-02-28 | 1999-01-05 | Nec Corporation | Interface circuit having receiving side circuit for controlling logical threshold values |
| CN1386349A (en) * | 2000-07-25 | 2002-12-18 | 皇家菲利浦电子有限公司 | 5-unit receiver utilizing common mode insensitive differential offset comparator |
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