KR100865335B1 - Circuit and method of converting an analog signal into a digital signal - Google Patents

Abstract

A digital signal restoring circuit and a digital signal restoring method are provided to offer a clock signal for controlling a range that an analog signal is converted into a digital signal in a desired restoration range, thereby restoring and outputting only a digital signal in a desired range. A digital signal restoring circuit(100) includes a clock signal generator(110), an ADC(Analog to Digital Converter) unit(120), and a sampling unit(130). The clock signal generator provides a clock signal(SIG3) based on an input signal(Vin), and first and second threshold values(VDD/2+Va,VDD/2-Va). The ADC unit provides a first digital signal(SIG4) based on a reference value(VDD/2) corresponding to an average value of the first and second threshold values and the input signal. The sampling unit is synchronized with the clock signal to sample the first digital signal to output a second digital signal(SIG5).

Description

Digital signal recovery circuit and digital signal recovery method {Circuit and method of converting an analog signal into a digital signal}

1 is a circuit diagram illustrating a digital signal recovery circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating an operation of the digital signal recovery circuit of FIG. 1.

3 is a circuit diagram illustrating an example of comparators included in the digital signal recovery circuit of FIG. 1.

4 is a block diagram illustrating an RFID reader according to an embodiment of the present invention.

The present invention relates to wireless communications, and more particularly, to a radio frequency identification (RFID) reader.

In wireless communications, the restoration of analog signals to digital signals is one of the roles of the receiver. To this end, a receiver for converting an analog signal to digital is required at the front end of a receiver. An analog-to-digital converter (ADC) is generally used. When the ADC included in the receiver converts an analog signal into a multi-bit digital signal, the receiver processes various digital signals such as filtering, frequency offset elimination and DC offset elimination based on the converted digital signal. For example, a UHF RFID reader receives a modulated signal within a range of 910 to 914 MHz for data of up to 640 kbps, demodulates the received signal into a digital signal, and processes the digital signal. At this time, since the RFID reader does not require a complicated digital signal processing process, the process of converting an analog signal to digital becomes relatively important.

RFID readers must be able to recognize signals from RFID tags in a range of several centimeters to several meters. As the distance between the RFID tag and the RFID reader increases, the magnitude of the signal received by the reader becomes inversely proportional to the square of the distance. Thus, the magnitude of the signal ranges from tens of mVs to hundreds of mVs, and RFID readers need an ADC that can convert signals in the range of tens of mVs to hundreds of mVs into digital signals. In addition, even when there is no input signal in the RFID reader, various kinds of noises such as electromagnetic interference (EMI), substrate noise, and simultaneous switching noise (SSN) may occur. Signals such as noise are needed for the ADC so that it is not seen as an input signal.

In general, the comparator functions to convert analog signals into digital signals. The comparator outputs a logic high when the input signal is larger than a certain reference voltage and a logic low when the comparator is smaller. However, a typical comparator works for all small signals, such as noise, which is not suitable for ADCs because of the high glitches and sometimes incorrect outputs.

Accordingly, there is a need for a digital signal recovery circuit that restores a small signal such as a noise or a signal outside the recognition distance, that is, a digital signal for a wrong input, and a digital signal for a large input signal in a predetermined range.

An object of the present invention for solving the above problems is to provide a digital signal recovery circuit that outputs a default signal for a signal coming in below a certain size and restores a digital signal for a signal having a desired size range.

Another object of the present invention is to provide a digital signal recovery method using the digital signal recovery circuit.

Still another object of the present invention is to provide an RFID reader including the digital signal recovery circuit.

A digital signal recovery circuit according to an embodiment of the present invention for achieving the above object includes a clock signal generator, an analog-to-digital converter, and a sampling unit. The clock signal generator provides a clock signal based on an input signal and first and second threshold values. The analog-to-digital converter provides a first digital signal based on a reference value corresponding to an average value of the first and second thresholds and the input signal. The sampling unit samples the first digital signal in synchronization with the clock signal and outputs a second digital signal.

The clock signal generator may include a first comparator, a second comparator, and a logic circuit. The first comparator compares the input signal with the first threshold and has a logic low level when the value of the input signal is less than the first threshold, and the value of the input signal is greater than the first threshold. Provide a first comparison signal having a logic high level. The second comparator compares the input signal with the second threshold and has a logic high level when the value of the input signal is less than the second threshold, and the value of the input signal is greater than the second threshold. Provide a second comparison signal having a logic low level. The logic circuit has a logic low level when the value of the input signal is between the first threshold value and the second threshold value range based on the first comparison signal and the second comparison signal, the input signal And provides a clock signal having a logic high level when a value of is outside the first threshold value and the second threshold value range.

The analog-to-digital converter is configured to compare the input signal with the reference value and have a logic low level when the value of the input signal is less than the reference value and have a logic high level when the value of the input signal is greater than the reference value. One may comprise a third comparator for providing a digital signal.

The sampling unit may be configured as a flip-flop. The flip-flop samples the first digital signal in synchronization with the rising edge of the clock signal and outputs the second digital signal. The flip-flop outputs a default signal when the clock signal maintains one of a logic low level and a logic high level. The sampling unit may further include a Schmitt trigger for removing noise of the second digital signal.

In the digital signal recovery method according to an embodiment of the present invention for achieving the above object, a clock signal is provided based on the input signal and the first and second threshold values. A first digital signal is provided based on a reference value corresponding to the average of the first and second thresholds and the input signal. A second digital signal is provided by sampling the first digital signal in synchronization with the clock signal.

To provide the clock signal, the first comparison signal is provided by comparing the input signal with the first threshold. The first comparison signal has a logic low level when the value of the input signal is less than the first threshold and has a logic high level when the value of the input signal is greater than the first threshold. The second comparison signal is provided by comparing the input signal with the second threshold. The second comparison signal has a logic high level when the value of the input signal is less than the second threshold and has a logic low level when the value of the input signal is greater than the second threshold. The clock signal may be provided based on the first comparison signal and the second comparison signal. The clock signal has a logic low level when the value of the input signal is between the first and second threshold ranges, and the value of the input signal is within the first and second threshold ranges It has a logic high level when it is outside.

The input signal and the reference value may be compared to provide the first digital signal. The first digital signal has a logic low level when the value of the input signal is less than the reference value and has a logic high level when the value of the input signal is greater than the reference value.

When the clock signal transitions between a logic low level and a logic high level, the second digital signal is provided by sampling the first digital signal in synchronization with the rising edge of the clock signal. On the other hand, if the clock signal maintains one of a logic low level and a logic high level, a default signal is provided.

In order to provide the second digital signal, noise of the second digital signal can be removed.

RFID reader according to an embodiment of the present invention for achieving the above object includes an analog processor, an analog-to-digital converter, and a digital processor. The analog processor demodulates the first analog RFID signal received from Athena and outputs a second analog RFID signal. The analog-digital converter converts the second analog RFID signal into a digital RFID signal. The digital processing unit processes the digital RFID signal. The analog-digital converter includes a clock signal generation module, an analog-digital conversion module, and a sampling module. The clock signal generation module provides a clock signal based on the second analog RFID signal and first and second thresholds. The analog-to-digital conversion module provides a first digital signal based on a reference value corresponding to the average value of the first and second thresholds and the second analog RFID signal. The sampling module samples the first digital signal in synchronization with the clock signal and outputs a digital RFID signal.

The clock signal generation module may include a first comparator, a second comparator, and a logic module. The first comparator compares the second analog RFID signal with the first threshold value and has a logic low level when the value of the second analog RFID signal is less than the first threshold value. Provide a first comparison signal having a logic high level when the value is greater than the first threshold. The second comparator compares the second analog RFID signal with the second threshold value and has a logic high level when the value of the second analog RFID signal is less than the second threshold value. Provide a second comparison signal having a logic low level when the value is greater than the second threshold. The logic circuit has a logic low level when a value of the second analog RFID signal is between the first threshold value and the second threshold value range based on the first comparison signal and the second comparison signal, And provide a clock signal having a logic high level when the value of the second analog RFID signal is outside the first threshold and second threshold ranges.

The analog-to-digital conversion module compares the second analog RFID signal with the reference value and has a logic low level when the value of the second analog RFID signal is smaller than the reference value, wherein the value of the second analog RFID signal is the reference value. And a third comparator that provides the first digital signal having a logic high level when greater.

The sampling module may be configured as a flip-flop. The flip-flop samples the first digital signal in synchronization with the rising edge of the clock signal and outputs the digital RFID signal. The flip-flop outputs a default signal when the clock signal maintains one of a logic low level and a logic high level. In addition, the sampling module may further include a Schmitt trigger for removing noise of the digital RFID signal.

Accordingly, the digital signal restoration circuit and the digital signal restoration method according to an embodiment of the present invention may output a default signal for a signal coming in below a predetermined size and restore a digital signal for a signal having a desired range of magnitude.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

1 is a circuit diagram illustrating a digital signal recovery circuit according to an embodiment of the present invention.

Referring to FIG. 1, a digital signal recovery circuit 100 according to an embodiment of the present invention includes a clock signal generator 110, an analog-digital converter 120, and a sampling unit 130.

The clock signal generator 110 converts an analog signal of a range to be restored into a digital signal based on the input signal Vin and the first and second threshold values Vdd / 2 + Va and Vdd / 2-Va. It provides a clock signal (SIG3) for controlling the range for. The analog-digital conversion unit 120 based on the reference value VDD / 2 and the input signal Vin corresponding to the average value of the first and second thresholds Vdd / 2 + Va and Vdd / 2-Va. The first digital signal SIG4 is provided. The analog-digital converter 120 converts an analog signal into a digital signal and provides the same. The sampling unit 130 outputs the second digital signal SIG5 by sampling the first digital signal SIG4 in synchronization with the clock signal SIG3. The sampling unit 130 outputs the second digital signal SIG5 by sampling only a signal having a desired range among the first digital signals SIG4 in response to the clock signal SIG3.

The clock signal generator 110 receives an input signal Vin and first and second threshold values Vdd / 2 + Va and Vdd / 2-Va that designate a range to be restored, and between the threshold ranges. Outputs a logic low value for the input signal and outputs a logic high value for the input signal outside the thresholds. The first and second thresholds Vdd / 2 + Va and Vdd / 2-Va may be set externally. The clock signal generator 110 may include a first comparator 111, a second comparator 112, and a logic circuit 113. The first comparator 111 includes a positive terminal to which an input signal Vin is applied and a negative terminal to which a first threshold value Vdd / 2 + Va is applied. The second comparator 112 includes a negative terminal to which the input signal Vin is applied and a positive terminal to which the second threshold value Vdd / 2-Va is applied. The first comparator 111 outputs a logic low value when the input signal Vin is less than the first threshold value Vdd / 2 + Va, and the second comparator 112 outputs the input signal Vin at the second threshold value. If it is larger than the value (Vdd / 2-Va), the logic low value can be output. The logic circuit 113 may be formed of an AND gate. The OR gate 113 has a second threshold when the outputs of the first and second comparators 111 and 112 are both at a logic low state, that is, the input signal Vin is less than the first threshold Vdd / 2 + Va and at the same time a second threshold. When the value is greater than the value (Vdd / 2-Va), the logic low value is output.

The analog-digital converter 120 may include a third comparator 121. The third comparator 121 includes a positive terminal to which the input signal Vin is applied and a negative terminal to which the reference value Vdd / 2 is applied. The third comparator 121 outputs a logic high value when the input signal Vin is greater than the reference value Vdd / 2, and outputs a logic low value when the input signal Vin is greater than the reference value Vdd / 2, thereby outputting an analog input signal Vin. A first digital signal SIG4 having two logic states is converted. The reference value Vdd / 2 may be an average value of the input signal Vin or an average value of the first and second threshold values Vdd / 2 + Va and Vdd / 2-Va.

The sampling unit 130 may be configured as a flip-flop 131. The flip-flop 131 receives the first digital signal SIG4 converted by the analog-to-digital converter 120 and responds to the clock signal SIG3 generated by the clock signal generator 110. Sample only. If the input signal Vin exists between the first and second threshold values Vdd / 2 + Va, Vdd / 2-Va, that is, the first and second threshold values Vdd / 2 + Va, Vdd When a signal having a small magnitude between / 2-Va) is input, the clock signal SIG3 maintains a logic low value and no transition occurs. In addition, when a DC signal having an input signal Vin outside the first and second threshold values is input, the clock signal maintains a logic high value and no transition occurs. In this case, the flip-flop 131 maintains one of a logic low level and a logic high level regardless of the logic level of the first digital signal SIG4. Output the default signal. On the other hand, the input signal Vin is between the first and second threshold values Vdd / 2 + Va and Vdd / 2-Va and the first and second threshold values Vdd / 2 + Va and Vdd / 2-Va. If a periodic signal is out of the range, i.e., if an analog signal having a magnitude greater than the first and second threshold values (Vdd / 2 + Va, Vdd / 2-Va) is input, the clock signal is logic high. A transition from a logic low state or a logic low state to a logic high state occurs. The sampling unit 130 may sample an output signal of the analog-to-digital converter 120 in synchronization with a rising edge of the clock signal SIG3.

The sampling unit 130 may further include one or more Schmitt triggers 132. The Schmitt trigger 132 may remove noise of the flip-flop 131 output signal.

FIG. 2 is a timing diagram illustrating an operation of the digital signal recovery circuit of FIG. 1.

1 and 2, the overall operation of the digital signal recovery circuit 100 of FIG. 1 will be described.

For example, the first comparator 111 receives an input signal Vin and a first threshold value Vdd / 2 + Va and outputs a first comparison signal SIG1. The first comparator 111 outputs a logic high value when the value of the input signal Vin input to the positive terminal is greater than the first threshold value Vdd / 2 + Va input to the negative terminal and the input signal. When the value of Vin is smaller than the first threshold value Vdd / 2 + Va, a logic low value is output. The second comparator 112 receives an input signal Vin and a second threshold value Vdd / 2-Va and outputs a second comparison signal SIG2. The second comparator 112 outputs a logic low value when the value of the input signal Vin input to the negative terminal is greater than the value of the second threshold value Vdd / 2-Va input to the positive terminal, and when the value is small. Output a logic high value. The OR gate 113 outputs a clock signal SIG3 by performing an AND operation on the output signals SIG1 and SIG2 of the first comparator 111 and the second comparator 112. The OR gate 113 outputs a logic high value when any of the states of the signals SIG1 and SIG2 is logic high, and outputs a logic low value when the signals SIG1 and SIG2 are logic low at the same time. The third comparator 121 receives the input signal Vin and the reference value Vdd / 2 and outputs the first digital signal SIG4. The first digital signal SIG4 corresponds to the output signal of the conventional analog-to-digital conversion circuit. The third comparator 121 outputs a logic high value when the value of the input signal Vin input to the positive terminal is greater than the reference value Vdd / 2 input to the negative terminal, and outputs a logic low value when the value is small. . The flip-flop 131 samples the first digital signal SIG4 and outputs the second digital signal SIG5 in synchronization with the rising edge of the clock signal SIG3. The second digital signal SIG5 is output in a form in which the first digital signal SIG4 is delayed. At this time, when the clock signal SIG3 maintains the logic high state or the logic low state, the default signal is output as the second digital signal SIG5.

3 illustrates an example of a circuit configuration of comparators included in the digital signal recovery circuit of FIG. 1.

Referring to FIG. 3, the terminals INP and INN represent the positive and negative terminals of the comparators shown in FIG. 1. In addition, the terminal Q represents the output terminal of the comparators shown in FIG. 1. Although not shown in FIG. 1, a bias voltage and a clock signal necessary for the operation of the comparator may be applied to the bias terminals VBP and VBN and the clock terminal CLK illustrated in FIG. 3, and the inverted output terminal Q_bar may be a terminal. Can be substituted for (Q). The comparator having the structure of FIG. 3 may be used for the comparators 111, 112, and 113 of FIG. 1. In addition, other comparators having the same function may be used as the comparators 111, 112, and 113 of FIG. 1. The configuration and operation of the comparator as shown in FIG. 3 is well known to those skilled in the art, and a description thereof will be omitted.

4 is a schematic block diagram illustrating an RFID reader 300 according to an embodiment of the present invention.

Referring to FIG. 4, the RFID reader 300 includes an analog processor 310, an analog-digital converter 320, and a digital processor 330. The analog processor 310 amplifies the first analog RFID signal received from the antenna 305 using a low noise amplifier (LNA), demodulates it, and outputs a second analog RFID signal. The analog-to-digital converter 320 converts the second analog RFID signal into a digital RFID signal and outputs it. The analog to digital converter 320 may include a clock signal generation module 322, an analog-to-digital conversion module 324, and a sampling module 326. The clock signal generation module 322, the analog-digital conversion module 324, and the sampling module 326 of FIG. 4 may include the clock signal generation unit 110, the analog-digital conversion unit 120, and the sampling unit of FIG. 1. The same function as 130. That is, it converts the analog signal of the range to be restored into a digital signal. The digital processor 330 receives the restored digital signal, performs digital signal processing, and extracts ID information from the first analog RFID signal.

Therefore, the RFID reader 300 including the analog-to-digital converter 320 for converting an analog signal of a range to be restored into a digital signal has a function of reading ID information for a signal coming over a predetermined size. For signals coming in below a certain size, such as noise, the analog or digital converter 320 recognizes abnormal operation such as noise and does not generate an output.

As described above, the digital signal recovery circuit, the digital signal recovery method, and the RFID reader according to an embodiment of the present invention provide a clock signal for controlling a range for converting an analog signal of a range to be restored into a digital signal. Only digital signals in the range are recovered and output. Accordingly, a signal coming in below a predetermined size, such as a noise signal or a signal outside the recognition distance, may not be restored, and an input signal within a desired recognition distance may be restored to a digital signal.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

Claims (17)

A clock signal generator configured to provide a clock signal based on the input signal and the first and second threshold values; An analog-to-digital converter configured to provide a first digital signal based on a reference value corresponding to the average value of the first and second thresholds and the input signal; And And a sampling unit configured to output the second digital signal by sampling the first digital signal in synchronization with the clock signal. The clock signal generator of claim 1, wherein the clock signal generator Comparing the input signal with the first threshold to have a logic low level when the value of the input signal is less than the first threshold, and to set a logic high level when the value of the input signal is greater than the first threshold. A first comparator having a first comparison signal having a first comparison signal; Comparing the input signal with the second threshold to have a logic high level when the value of the input signal is less than the second threshold, and to reduce the logic low level when the value of the input signal is greater than the second threshold. A second comparator having a second comparison signal having a second comparison signal; And Have a logic low level when a value of the input signal is between the first threshold value and the second threshold range based on the first comparison signal and the second comparison signal, wherein the value of the input signal is And a logic gate for providing the clock signal having a logic high level when outside of a first threshold and a second threshold range. 2. The logic circuit of claim 1, wherein the analog-to-digital converter has a logic low level when the value of the input signal is smaller than the reference value by comparing the input signal with the reference value, and when the value of the input signal is greater than the reference value. And a third comparator for providing said first digital signal having a high level. The digital signal recovery circuit of claim 1, wherein the sampling unit comprises a flip-flop. The digital signal recovery circuit of claim 4, wherein the flip-flop outputs the second digital signal by sampling the first digital signal in synchronization with a rising edge of the clock signal. The method of claim 5, wherein the flip-flop is configured to maintain one of a logic low level and a logic high level regardless of a logic level of the first digital signal when the clock signal maintains one of a logic low level and a logic high level. And a default signal output circuit. The digital signal recovery circuit of claim 1, wherein the sampling unit further comprises a Schmitt trigger for removing noise of the second digital signal. Providing a clock signal based on the input signal and the first and second threshold values; Providing a first digital signal based on a reference value corresponding to the average of the first and second thresholds and the input signal; And Sampling the first digital signal in synchronization with the clock signal and outputting a second digital signal. The method of claim 8, wherein providing the clock signal Comparing the input signal with the first threshold to have a logic low level when the value of the input signal is less than the first threshold, and to set a logic high level when the value of the input signal is greater than the first threshold. Providing a first comparison signal having a branch; Comparing the input signal with the second threshold to have a logic high level when the value of the input signal is less than the second threshold, and to reduce the logic low level when the value of the input signal is greater than the second threshold. Providing a second comparison signal having a second comparison signal; And Have a logic low level when a value of the input signal is between the first threshold value and the second threshold range based on the first comparison signal and the second comparison signal, wherein the value of the input signal is Providing the clock signal having a logic high level when outside of a first threshold and a second threshold range. The method of claim 8, wherein the providing of the first digital signal has a logic low level when the value of the input signal is smaller than the reference value by comparing the input signal with the reference value, wherein the value of the input signal is the reference value. Providing the first digital signal having a logic high level when greater. 9. The method of claim 8, wherein providing the second digital signal is Sampling the first digital signal and outputting the second digital signal in synchronization with a rising edge of a clock signal when the clock signal transitions between a logic low level and a logic high level; And Outputting a default signal that maintains either a logic low level or a logic high level regardless of the logic level of the first digital signal when the clock signal maintains one of a logic low level and a logic high level. Characterized in that the digital signal recovery method. The method of claim 11, And removing the noise of the second digital signal. An analog processor for demodulating the first analog RFID signal received from the antenna and outputting a second analog RFID signal; An analog-to-digital converter converting the second analog RFID signal into a digital RFID signal; And It includes a digital processing unit for processing the digital RFID signal, The analog-digital converter A clock signal generation module for providing a clock signal based on the second analog RFID signal and first and second threshold values; An analog-digital conversion module configured to provide a first digital signal based on a reference value corresponding to the average value of the first and second threshold values and the second analog RFID signal; And And a sampling module configured to output the digital RFID signal by sampling the first digital signal in synchronization with the clock signal. The method of claim 13, wherein the clock signal generation module The second analog RFID signal is compared with the first threshold value to have a logic low level when the value of the second analog RFID signal is less than the first threshold value, and the value of the second analog RFID signal is equal to the first threshold value. A first comparator for providing a first comparison signal having a logic high level when greater than a threshold; Comparing the second analog RFID signal with the second threshold to have a logic high level when the value of the second analog RFID signal is less than the second threshold, and wherein the value of the second analog RFID signal is the second; A second comparator for providing a second comparison signal having a logic low level when greater than a threshold; And Have a logic low level when the second analog RFID signal is between the first threshold and the second threshold range based on the first comparison signal and the second comparison signal, and the second analog RFID signal And a logic gate providing the clock signal having a logic high level when the value of is outside the first threshold and the second threshold ranges. The method of claim 13, wherein the analog-to-digital conversion module compares the second analog RFID signal with the reference value and has a logic low level when the value of the second analog RFID signal is smaller than the reference value. And a third comparator for providing said first digital signal having a logic high level when the value of said signal is greater than said reference value. The method of claim 13, wherein the sampling module is configured as a flip-flop, the flip-flop When the clock signal transitions between a logic low level and a logic high level, the first digital signal is sampled and output the digital RFID signal by synchronizing on the rising edge of the clock signal, and the clock signal is a logic low level and a logic high level. If you keep one of the levels And output a default signal that maintains either a logic low level or a logic high level regardless of the logic level of the first digital signal. The RFID reader of claim 13, wherein the sampling module further comprises a Schmitt trigger to remove noise of the digital RFID signal.

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